Photodiode based on color router and integrated pixel circuit

Abstract

The invention relates to a photodiode based on a color router and an integrated pixel circuit. In one embodiment, a plurality of pixels arranged in rows and columns of a pixel array are disposed in a semiconductor material. In some embodiments, each pixel includes a plurality of photodiodes and a color router covering the plurality of photodiodes. In some embodiments, the plurality of pixels are configured to receive incident light through the color router. In some embodiments, the integrated pixel circuit includes a plurality of pixel circuits, where each pixel circuit is associated with a corresponding pixel of the plurality of pixels. In some embodiments, the pixel circuit is disposed on the same horizontal plane as the plurality of photodiodes.

Description

Technical Field

[0001] The present disclosure relates generally to the design of image sensors, and in particular, to image sensors with improved illumination of photodiodes. Background Art

[0002] Image sensors have become ubiquitous. They are widely used in digital cameras, cell phones, surveillance cameras, and in medical, automotive, and other applications. The technology used to manufacture image sensors continues to advance rapidly. For example, the demand for higher image sensor resolution and lower power consumption has driven further miniaturization and integration of image sensors into digital devices.

[0003] Image sensors operate in response to image light from an external scene and incident on the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and responsively generate corresponding charges. The charge of an individual pixel can be measured as an output voltage of each photosensitive element. In general, the output voltage varies with the intensity and duration of the incident light. The output voltages of the individual photosensitive elements are used to generate a digital image (i.e., image data) representing the external scene.

[0004] In some applications, photodiodes are illuminated by incident light that passes through a combination of lenses and color filters, thus exposing individual photodiodes to light of a given color (wavelength), such as blue, green, or red. Based on the exposure of the photodiode to only a limited range of wavelengths, the properties of the photodiodes can be optimized so that, for example, the peak sensitivity of a given photodiode is within a target range of light wavelengths. However, lenses and color filters necessarily attenuate the incident light, thus limiting the dynamic range of the photodiode. Therefore, there is a need for systems and methods for improving the illumination and dynamic range of image sensors. Summary of the invention

[0005] In one aspect, the present disclosure provides an image sensor comprising: a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor substrate, wherein each pixel comprises a plurality of photodiodes; a color router covering the plurality of photodiodes, wherein the plurality of pixels are configured to receive incident light through the color router; and a plurality of pixel circuits, wherein each pixel circuit is associated with a corresponding pixel of the plurality of pixels, wherein the plurality of pixel circuits are configured on the same horizontal plane as the plurality of photodiodes.

[0006] On the other hand, the present disclosure provides a method of reading out charges of an image sensor, the image sensor comprising: a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor substrate, wherein each pixel comprises a plurality of photodiodes; a color router covering the plurality of photodiodes, wherein the plurality of pixels are configured to receive incident light through the color router; and a plurality of pixel circuits, wherein each pixel circuit is associated with a corresponding pixel of the plurality of pixels, wherein the plurality of pixel circuits are configured on the same horizontal plane as the plurality of photodiodes, the method comprising: transferring one or more charges from one or more photodiodes of the plurality of photodiodes to one or more transfer transistors of a plurality of transfer transistors, wherein each photodiode is coupled to a transfer transistor of the plurality of transfer transistors; transferring the one or more charges from each corresponding transfer transistor to a central transistor; transferring the one or more charges to a floating diffusion region; and reading out the one or more charges to generate an image. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0008] Figure 1 An imaging system according to an embodiment of the present disclosure is described.

[0009] Figure 2 is a schematic diagram of a conventional pixel circuit according to the present disclosure.

[0010] Figure 3 is a side view of a pixel with a color router according to an embodiment of the present disclosure.

[0011] Figure 4 is a top view of a photodiode and a pixel circuit according to an embodiment of the present disclosure.

[0012] Figure 5 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure.

[0013] Figures 6A to 6E is a process diagram of charge propagation according to an embodiment of the present disclosure.

[0014] Figure 7 is a top view of a pixel group according to an embodiment of the present disclosure.

[0015] Figure 8 is a top view of a group of photodiodes and pixel circuits according to an embodiment of the present disclosure.

[0016] Fig. 9 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure.

[0017] Figures 10A to 10D is a process diagram of charge propagation according to an embodiment of the present disclosure.

[0018] Fig.11 is a top view of a pixel group according to an embodiment of the present disclosure.

[0019] In the several views of the drawings, corresponding reference characters indicate corresponding components. It will be appreciated by those skilled in the art that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help facilitate understanding of the various embodiments of the present invention. In addition, common but well-known elements that are useful or required in commercially feasible embodiments are generally not depicted in order to facilitate unobstructed viewing of these various embodiments of the present invention. DETAILED DESCRIPTION

[0020] Image sensors are disclosed and, in particular, image sensors including color routers. In the following description, numerous specific details are set forth to provide a comprehensive understanding of the embodiments. However, those skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0021] Reference in this specification to "one example" or "one embodiment" means that a particular feature, structure, or characteristic described in conjunction with the example is included in at least one example of the present invention. Therefore, the phrases "in one example" or "in one embodiment" appearing in various places in this specification do not necessarily all refer to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0022] For ease of description, spatially relative terms such as "below," "beneath," "under," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is flipped, then the elements described as being "below" or "below" or "under" other elements or features will be oriented to be "above" the other elements or features. Thus, the exemplary terms "below" and "under" may encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein are interpreted accordingly. In addition, it should also be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers or one or more intervening layers may also be present.

[0023] It should be understood from the above that specific embodiments of the technology have been described herein for illustration, but various modifications may be made without departing from the present disclosure. In addition, although various advantages and features associated with the embodiments have been described above in the context of certain embodiments, other embodiments may also exhibit such advantages and / or features, and not all embodiments need to necessarily exhibit such advantages and / or features to fall within the scope of the technology. When describing a method, the method may include more, less or other steps. In addition, the steps may be performed in any suitable order. Therefore, the present disclosure may cover other embodiments that are not explicitly shown or described herein. In the context of the present disclosure, the terms "approximately", "approximately", etc. mean + / -5% of a specified value.

[0024] In this specification, several technical terms are used. These terms take their ordinary meaning in the art, unless explicitly defined herein or the context of their use clearly implies otherwise. It should be noted that in this document, element names and symbols are used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0025] In brief, embodiments of the present technology relate to photodiodes coupled to color routers. In some embodiments, color routers are used in place of microlenses and color filters. The color router may cover multiple photodiodes in a pixel or pixel group. In addition, disclosed herein is an architecture of pixels and pixel groups that allows the pixel circuitry to be on the same horizontal plane as the multiple photodiodes in each pixel or pixel group. In some embodiments, each pixel includes four quadrants, three of the four quadrants include photodiodes and the fourth quadrant includes pixel circuitry associated with the pixel. In some embodiments, four pixels are arranged in a pixel group such that the fourth quadrant of each pixel is aligned to form a connected pixel region. In some embodiments, this connected pixel region includes connected pixel circuitry, i.e., shared circuitry (e.g., lateral overflow integration capacitor (LOFIC)) for each photodiode in the pixel group.

[0026] Figure 1 An example imaging system 100 is illustrated in accordance with an embodiment of the present disclosure. Imaging system 100 includes a pixel array 102, control circuitry 104, readout circuitry 106 (also referred to as pixel circuitry), and function logic 110. In one example, pixel array 102 is a two-dimensional (2D) array of photodiodes or image sensor pixels 112 (e.g., pixels P1, P2, ..., Pn). As illustrated, the photodiodes are arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx). In operation, the photodiodes acquire image data of an external scene, which can then be used to render a 2D image of a person, place, object, etc. However, in other embodiments, the photodiodes may be arranged in configurations other than rows and columns.

[0027] In an embodiment, after each pixel 112 in the pixel array 102 acquires its image charge, the image data is read out by the readout circuitry 106 via the bit line 118 and then transferred to the function logic 110. In various embodiments, the readout circuitry 106 may include a signal amplifier, analog-to-digital (ADC) conversion circuitry, and data transmission circuitry. The function logic 110 may store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, etc.). In some embodiments, the control circuitry 104 and the function logic 110 may be combined into a single functional block to control the capture of images by the pixels 112 and the readout of the image data from the readout circuitry 106. For example, the function logic 110 may be a digital processor. In one embodiment, the readout circuitry 106 may read a row of image data at a time along the readout column lines (bit lines 118) or may use various other techniques to read the image data, such as serial readout at the same time or fully parallel readout of all pixels (not illustrated).

[0028] In one embodiment, control circuitry 104 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuitry 104 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal that is used to simultaneously enable all pixels within pixel array 102 to simultaneously capture their respective image data during a single data acquisition window. In another embodiment, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows. In another embodiment, image acquisition is synchronized with a lighting effect such as a flash.

[0029] In one embodiment, readout circuitry 106 includes an analog-to-digital converter (ADC) that converts analog image data received from pixel array 102 into a digital representation. The digital representation of the image data may be provided to function logic 110. In some embodiments, data transfer circuitry 108 may receive the digital representation of the image data from the ADC in parallel and may provide the image data to function logic 110 in series.

[0030] In various embodiments, the imaging system 100 may be incorporated into a digital camera, a cell phone, a laptop computer, or the like. Additionally, the imaging system 100 may be coupled to other hardware, such as a processor (general purpose or otherwise), a memory element, an output (USB port, a wireless transmitter, an HDMI port, etc.), a light / flash, an electrical input (a keyboard, a touch display, a track pad, a mouse, a microphone, etc.), and / or a display. The other hardware may transmit instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0031] Figure 2 2 is a schematic diagram of a conventional pixel 210 according to the present disclosure. Pixel 210 may be coupled to a bit line 218, such as a readout column that provides image data to a readout circuitry (e.g., readout circuitry 106). In operation, pixel 210 may receive control signals from control circuitry (e.g., control circuitry 104) to control the operation of various transistors of pixel 210. The control circuitry may control the transistors to operate in a desired sequence in a relative timing that ensures orderly readout of the image data.

[0032] The illustrated embodiment of pixel 210 includes a photodiode (PD) 211, a floating diffusion region (FD1) 213 having an intrinsic capacitor (FDC) 219, a transfer transistor 212, an optional double floating diffusion (DFD) transistor 216, an optional floating diffusion region (FD2) 217 ​​connected to an optional lateral overflow integration capacitor (LOFIC) 215, a reset (RST) transistor 214, a row select (RS) transistor 221, and a source follower (SF) transistor 220. A transfer (TX) transistor 212 (which may also be referred to as a transmission gate 212) is coupled between the photodiode PD 211 and the floating diffusion region FD1 213. The TX transistor 212 operates based on a TX control signal on its gate terminal. Although the floating diffusion region FD1 213 is depicted as being connected to the intrinsic capacitor FDC 219 connected to ground, the combination of FD1 213 and FDC 219 may also be collectively referred to as a floating diffusion region.

[0033] RST transistor 214 may be coupled to a reference voltage AVDD and may receive a reset control signal on its gate terminal. Additional capacitance LOFIC 215 may be coupled between a variable reference voltage VCAP and a floating diffusion node FD2 217. DFD transistor 216 may be coupled between FD1 213 and FD2 217 and further coupled to receive a DFD control signal on its gate terminal. In addition, a gate terminal of SF transistor 220 is coupled to floating diffusion node FD1 213. The source / drain terminal of the SF transistor is coupled between reference voltage AVDD and the RS transistor. RS transistor 221 may be coupled between bit line 218 and SF transistor 220.

[0034] In operation, transistor TX 212 receives a gate signal to enable charge to be transferred from PD 211 to floating diffusion FD1 213. In general, the amount of charge transferred depends on the exposure of PD 211 and the operation of pixel 210. Equivalent capacitor FDC 219 is illustrated as being coupled to ground.

[0035] In some embodiments, LOFIC 215 can increase the storage, e.g., capacitance, of floating diffusion FD2 217. For example, in response to high intensity illumination, photodiode PD 211 can generate more charge than floating diffusion FD1 213 can store. The additional charge can be stored by LOFIC 215. In some embodiments, reference voltage VCAP can be modulated between two or more voltage levels (e.g., a high voltage level "H" and a low voltage level "L"), thus adjusting how much charge is stored by LOFIC 215. In general, FDC 219 has a smaller capacitance than LOFIC 215. Therefore, floating diffusion FD1 213 is read in conjunction with a high conversion gain (HCG) portion of the data readout, while floating diffusion FD2 217 and floating diffusion 213 are read in conjunction with a low conversion gain (LCG) portion of the readout. The HCG and LCG readouts together constitute a dual conversion gain (DCG) data readout.

[0036] In some embodiments, the operation of the RST transistor 214 and the DFD transistor 216 can reset the floating diffusion region FD1 213 to a high voltage representing a dark state because the photogenerated electrons reduce a voltage proportional to the charge strength of the PD 211 when they are transferred to the floating diffusion region FD1 213. To reset the floating diffusion region FD1 213, both the RST transistor 214 and the DFD transistor 216 are enabled (turned on) by their respective gate signals. In other embodiments, the RST transistor 214 can be in a conductive state while the DFD transistor remains in an off state, thereby resetting the floating diffusion region FD2 217 but not resetting the floating diffusion region FD1 213.

[0037] During integration, the variable voltage VCAP coupled to the LOFIC 215 may be modulated between two or more voltage levels. In some embodiments, VCAP may be modulated between about 0.4V to about 1.8V depending on the value of AVDD. In other embodiments, other voltage levels may be implemented depending on the underlying semiconductor material. When the DFD 216 is enabled, the coupling of FD2 217 to FD1 213 may provide additional capacitance to store the charge generated by the PD 211. For example, when the TX 212 is enabled to transfer image charge to the floating diffusion region FD1 213, the DFD 216 may be enabled to couple the additional capacitance LOFIC 215 to the floating diffusion region FD1 213 to increase the full well capacity (FWC) of the floating diffusion region. In some embodiments, the variable voltage VCAP may be at different voltages depending on whether the TX transistor 212 is enabled or disabled.

[0038] Figure 33 is a side view of a pixel 210 with a color router 303 according to an embodiment of the present disclosure. The pixel 210 may include a plurality of photodiodes 211-B, 211-G, 211-R, and 211-GR formed in a semiconductor substrate 305. The color router 303 may cover the plurality of photodiodes 211-B, 211-G, 211-R, and 211-GR, such that the plurality of photodiodes receive incident light 301 through the color router 303. L represents a characteristic length. In some embodiments, the characteristic length L is one wavelength of the incident light.

[0039] The plurality of photodiodes 211-B, 211-G, 211-R, and 211-GR may be a blue photodiode 211-B, a green photodiode 211-G, a red photodiode 211-R, and a gray photodiode 211-GR. In some embodiments, the plurality of photodiodes 211-B, 211-G, 211-R, and 211-GR are configured to receive incident light 301 through a color router 303, as described herein. In some embodiments, each of the plurality of photodiodes 211-B, 211-G, 211-R, and 211-GR is configured to receive incident light 301 of a specific color, such as blue light, green light, red light, and gray light, respectively.

[0040] In some embodiments, a plurality of photodiodes 211-B, 211-G, 211-R, and 211-GR are formed in a semiconductor substrate 305. In some embodiments, the silicon wafer 305 is a semiconductor substrate formed of silicon, silicon germanium, silicon germanium alloys, germanium, silicon carbide alloys, indium gallium arsenide alloys, any other alloys formed from III-V compounds, other semiconductor materials or alloys, combinations thereof, substrates thereof, bulk substrates thereof, or wafers thereof. Although four photodiodes 211-B, 211-G, 211-R, and 211-GR are illustrated in the semiconductor substrate 305, it should be understood that a different number of photodiodes may be formed or embedded in the silicon wafer 305.

[0041] In some embodiments, color router 303 includes one or more high refractive index materials, such as TiO2, embedded in a low refractive index medium. In some embodiments, color router 303 includes one or more nanorods made of a high refractive index material embedded in a low refractive index medium. In some embodiments, the one or more nanorods have different sizes (i.e., diameters) that selectively slow down incident light 301 when it reaches multiple photodiodes 211-B, 211-G, 211-R, and 211-GR.

[0042] In operation, incident light 301 travels through the nanorods much slower than incident light 301 travels through the low refractive index medium and surrounding areas. The induced phase difference of incident light 301 rises and falls depending on the wavelength λ, thus allowing wavelength-dependent spatial separation. In some embodiments, this wavelength-dependent spatial separation is caused by constructive and / or destructive interference and diffraction phenomena when the incident light passes through the nanorods. The amount of phase delay for representative wavelengths of red, green, and blue can be determined by the size-sensitive effective refractive index of the nanorods (i.e., based on the corresponding diameters of the nanorods and the spatial distribution of the nanorods). Based on the acquired phase dispersion information, conditions can be designed to simultaneously meet the desired phase distribution of each wavelength under various conditions. In this way, the color router 303 can simultaneously separate the incident light 301 into red, green, and blue light and guide this separated light to each corresponding photodiode of the plurality of photodiodes 211-B, 211-G, 211-R, and 211-GR, such as Figure 3 . Thus, the color router 303 can allow for a higher efficiency of the photodiodes 211-R, 211-G, 211-B, 211-GR than a conventional combination of color filters and microlenses. By utilizing the color router 303, microlenses and / or color filters can be omitted from the image sensor, thus avoiding light intensity loss caused by the color filters.

[0043] Figure 4 2 is a top view of a pixel 210 including a plurality of photodiodes 211-B, 211-R, 211-G and a pixel circuit 230 according to an embodiment of the present disclosure. In some embodiments, the pixel 210 includes four quadrants Q1, Q2, Q3 and Q4. In some embodiments, the pixel 210 includes a group of photodiodes 211-R, 211-G, 211-B. Each photodiode of the photodiode group 211-R, 211-G, 211-B is located in the first quadrant Q1, the second quadrant Q2 and the third quadrant Q3, respectively. In some embodiments, the pixel 210 includes only a single red photodiode 211-R, a single green photodiode 211-G and a single blue photodiode 211-B. It should be understood that although in Figure 4 In the embodiment, the red photodiode 211-R is located in the first quadrant Q1, the green photodiode 211-G is located in the second quadrant Q2, and the blue photodiode 211-B is located in the third quadrant Q3, but each photodiode of the photodiode groups 211-R, 211-G, 211-B may be located in any quadrant Q1, Q2, Q3. In some embodiments, the photodiode groups 211-R, 211-G, 211-B may be Figure 3 In some embodiments, a color router (eg, color router 303) may cover photodiodes 211-R, 211-G, 211-B ( Figure 4 Because the color router allows the omission of color filters and microlenses, the pixel circuitry 230 can be located at the same level as the photodiodes 211-R, 211-G, 211-B (e.g. Figure 4 This is in contrast to the layout of conventional photodiodes and pixel circuits, where the photodiodes are distributed in one plane (closer to the color filters and microlenses) and the pixel circuits are distributed in another plane (farther away from the color filters and microlenses). In conventional technology, the plane of the photodiodes is configured between the plane of the pixel circuits on one side and the plane of the color filters and microlenses on the other side. In addition, because the color router improves the efficiency of the photodiode groups 211-R, 211-G, 211-B, only a single red photodiode 211-R, green photodiode 211-G, and blue photodiode 211-B may be included in the pixel 210, thereby creating space that can be used to place the readout circuit (pixel circuit), as further explained below.

[0044] In some embodiments, the pixel 210 includes a central transfer transistor (TX4) 212-4. In some embodiments, each photodiode of the photodiode group 211-R, 211-G, 211-B includes a respective transfer transistor (TX1) 212-1, (TX2) 212-2, (TX3) 212-3. In some embodiments, the central transfer transistor TX4 212-4 is adjacent to each transfer transistor TX1 212-1, TX2 212-2, TX3 212-3 of the first quadrant Q1, the second quadrant Q2, and the third quadrant Q3. In operation, each transfer transistor TX1 212-1, TX2 212-2, TX3 212-3 is enabled to transfer image charge from its respective photodiode 211-R, 211-G, 211-B to the central transfer transistor TX4 212-4, as described in detail in FIG. 6 .

[0045] In some embodiments, the pixel circuit 230 includes a floating diffusion region (FD) 213 having an intrinsic capacitor (FDC) 219 coupled to a reset transistor (RST) 214, a source follower (SF) transistor 220, a row select (RS) transistor 221, and a bit line BL (218), as described herein. In some embodiments, the pixel circuit 230 further includes a subsequent transfer transistor (TX5) 212-5 coupled to the floating diffusion region FD 213. In operation, the central transistor TX4 212-4 receives a gate signal to enable charge to be transferred from each photodiode 211-R, 211-G, 211-B to the subsequent transfer transistor TX5 212-5. Typically, the amount of charge transfer depends on the exposure of each of the photodiodes 211-R, 211-G, 211-B and the operation of the pixel 210. The subsequent transfer transistor TX5 212-5 receives charge from the central transistor TX4 212-4. In some embodiments, pixel circuit (readout circuit) 230 allows reading out from one photodiode of photodiode group 212-R, 212-G, 212-B, such as Figure 5 6. In some embodiments, pixel circuit 230 is configured to generate simultaneous readout from photodiode groups 212-R, 212-B, 212-G to generate a black and white image. Dashed line AA to AA' represents a cross section of the charge flow path from photodiode 211-B to floating diffusion region FD 213. This cross section is shown and further described with respect to FIG. 6.

[0046] Figure 5 2 is a schematic diagram of a pixel circuit 230 according to an embodiment of the present disclosure. The pixel circuit 230 is used to implement Figure 1 Each pixel 103 (eg Figure 4 Pixel circuit 230 may be implemented with a front or back illuminated pixel array.

[0047] The illustrated embodiment of the pixel circuit 230 includes a first photodiode (PD1) 211-1, a second photodiode (PD2) 211-2, and a third photodiode (PD3) 211-3. The photodiodes 211-1, 211-2, and 211-3 may correspond to Figure 4212-2, and the third photodiode PD3 is coupled to the third transfer transistor TX3 212-3. In one embodiment, the transfer transistors TX1 212-1, TX2 212-2, and TX3 212-3 are similar in size, which reduces the space required for the readout circuitry and increases the fill factor (defined as the ratio of the area occupied by the different components of the readout circuitry to the total available area in the fourth quadrant Q4). In some embodiments, each of the transfer transistors TX1 212-1, TX2 212-2, TX3 212-3 is coupled to a central transfer transistor TX4 212-4. In some embodiments, the central transfer transistor TX4 212-4 is coupled to a subsequent transfer transistor TX5 212-5, which is coupled to the floating diffusion region FD 213. Node S2 is configured between the central transfer transistor TX4 212-4 and the subsequent transfer transistor TX5 212-5.

[0048] In some embodiments, floating diffusion region FD 213 having intrinsic capacitor (FDC) 219 is coupled to reset transistor (RST) 214, source follower (SF) transistor 220, row select (RS) transistor 221, and bit line BL (218), as described herein.

[0049] In some embodiments, the pixel circuit 230 further includes a subsequent transfer transistor (TX5) 212-5 coupled to the FD 213. In operation, the read charge of each photodiode 211 of the first photodiode PD1 211-1, the second photodiode PD2 211-2, and the third photodiode PD3 211-3 can be read out by the pixel circuit 230. Specifically, the read charge of the first photodiode PD1 211-1 can be read out by the pixel circuit 230 by transferring the charge from the first photodiode PD 211-1 to the first transfer gate TX1 212-1, the center transfer transistor TX4 212-4, the subsequent transfer transistor 212-5, and the floating diffusion region FD 213. Similarly, the read charge of the second photodiode PD2 211-2 may be read out by the pixel circuit 230 by transferring the charge from the second photodiode PD2 211-2 to the second transfer gate TX 212-2, the center transfer gate TX4 212-4, the subsequent transfer gate 212-5, and the floating diffusion region FD 213. In addition, the read charge of the third photodiode PD2 211-3 may be read out by the pixel circuit 230 by transferring the charge from the third photodiode PD2 211-3 to the third transfer gate TX 212-3, the center transfer gate TX4 212-4, the subsequent transfer gate 212-5, and the floating diffusion region FD 213. In some embodiments, the accumulated charge may be simultaneously transferred from the first photodiode PD1 211-1, the second photodiode PD2 211-2, and the third photodiode PD3 211-3 to achieve a grayscale image.

[0050] Figures 6A to 6E is a process diagram of charge propagation according to an embodiment of the present disclosure. Figures 6A to 6E Indicates along Figure 4 Specifically, the line AA to AA' represents the cross section of the line AA to AA'. Figure 4 2 is a cross section of a photodiode 211-B in the third quadrant Q3 of a pixel 210. The cross section AA to AA' cuts through the photodiode 211-B, through the first transfer transistor TX1 212-1, to the central transfer transistor TX4 212-4, through the subsequent transfer transistor TX5 212-5 to the floating diffusion region FD 213. Figures 6A to 6E On the left side of each is the voltage in volts. Figures 6A to 6E As described in , the photodiode may include an insulator and multiple gates (transistors TX1, TX4, TX5) above the insulator. Figures 6A to 6E In, electronic - Flows between the photodiode and the corresponding transistor.

[0051] like Fig. 6AAs shown in the figure, the electrons e accumulated in the photodiode (PD1) - The gate voltage of each transistor (the first transfer transistor TX1, the central transfer transistor TX4, and the subsequent transfer transistor TX5) is zero (0V), so each transistor is set to an off state. Figure 6B In the embodiment, the gates of transistors TX1, TX4 and TX5 are set to a conducting state by a gate voltage VTX, thereby allowing photogenerated charges from photodiode PD1 (211-B) to flow into the wells of the first transfer transistor TX212-1, the central transfer transistor TX4 212-4 and the subsequent transfer transistor TX5 212-5 and accumulate.

[0052] exist Figure 6C In all the electrons e - After completing its transfer, the gate of the first transfer transistor TX1 212-1 is set to an off position by setting the gate voltage back to 0 V, and charge has now flowed from the well of the first transfer transistor TX1 212-1 to the wells of the center transfer transistor 212-4TX4 and the subsequent transfer transistors 212-5TX5. The gates of the center transfer transistor TX4 212-4 and the subsequent transfer transistors maintain the voltage VTX, thus keeping these gates in their on position. Fig.6D In , the charge transfer process continues. That is, after all electrons e' complete their transfer from the well of the central transfer transistor TX4 212-4, the gate of TX4 is set to the off position by setting the gate voltage back to 0V. At this point, charge is accumulated at the subsequent transfer transistor TX5. The subsequent transfer transistor maintains the gate voltage at VTX, thus keeping this transistor in the on state. Fig. 6E In all the electrons e - After completing its transfer to the floating diffusion region FD, the gate of the subsequent transfer transistor TX5 212-5 is set to the off position by setting the gate voltage back to 0 V. The charge is now accumulated in the floating diffusion region FD 213. As shown in FIG. Figure 5 As explained, the RST transistor is coupled to a reference voltage AVDD and is configured to receive a reset control signal on its gate terminal. Thus, the RST transistor can reset the floating diffusion region FD 213. When TX1 212-1, TX2 212-2, TX3 212-3, TX4 212-4, and TX5 212-5 are all turned on through their gate terminals, PD1, PD2, and PD3 are reset.

[0053] Figure 7 is a top view of a group of pixels 260 according to an embodiment of the present disclosure. In some embodiments, Figure 1The plurality of pixels 103 of the pixel array 102 are arranged to form a plurality of pixel groups, each pixel group 260 in the plurality of pixel groups includes a first pixel 210-i, a second pixel 210-ii, a third pixel 210-iii, and a fourth pixel 210-iv. In some embodiments, each pixel group 260 in the plurality of pixel groups is arranged as a 2×2 array of pixels 210-i, 210-ii, 210-iii, 210-iv. In some embodiments, each pixel 210-i, 210-ii, 210-iii, 210-iv is substantially similar in structure to the first pixel 210-i, the second pixel 210-ii, the third pixel 210-iii, and the fourth pixel 210-iv. Figure 4 The pixels 210 of FIG. 2 are the same. Therefore, each pixel 210-i, 210-ii, 210-iii, 210-iv is understood to have a first quadrant, a second quadrant, a third quadrant, and a fourth quadrant (i.e., Q1, Q2, Q3, Q4), wherein the first photodiode 211-R, the second photodiode 211-G, and the third photodiode 211-B are located in the first quadrant, the second quadrant, and the third quadrant. For simplicity and Figure 7 For easier reading, the readout circuits (pixel circuits) 230-i, 230-ii, 230-iii, and 230-iv are symbolically illustrated in this figure with rectangles. A person skilled in the art should understand that each pixel 210-i, 210-ii, 210-iii, and 210-iv requires one readout circuit 230. For simplicity and clarity of the figure, only the transfer transistors (e.g., Figure 5 212-1TX1, 212-2TX2, 212-3TX3), center transfer transistors (e.g. Figure 5 TX4 212-4 in), subsequent transfer transistors (e.g. Figure 5 TX5 212-5) and floating diffusion region FD (e.g. Figure 5 FD in ), but these transfer transistors also exist in other pixels and their readout circuits. In some embodiments, a color router (eg, color router 303) covers all photodiodes 211 in pixel group 260.

[0054] In some embodiments, each pixel 210-i, 210-ii, 210-iii, 210-iv in the pixel group 260 is arranged so that the fourth quadrant of each pixel is adjacent to the fourth quadrant of its neighboring pixel in the 2×2 pixel array. For example, the fourth quadrant of pixel 210-i is adjacent to the fourth quadrant of both pixels 210-ii and 210-iii. By arranging the pixels 210-i, 210-ii, 210-iii, 210-iv in this manner, a connected pixel region 700 is formed. The connected pixel region 700 allows the pixel circuitry 230-i, 230-ii, 230-iii, 230-iv to be located in the center of the pixel group 260. The connected pixel region 700 is configured to allow for larger or common circuit components. For example, in some embodiments, a large lateral overflow integration capacitor (LOFIC) 730 may be shared by all pixels in pixel group 260, as indicated by the dashed lines connecting each pixel 210-i, 210-ii, 210-iii, and 210-iv to the LOFIC 730 and described in more detail below. This sharing of the LOFIC 730 may result in further savings in chip area occupied by the readout circuitry. This allows for better utilization of space in the image sensor and integration of larger circuit components. In addition, the presence of the connected pixel region 700 may enable the pixels 210 and the pixel circuitry 230 to be placed in the same plane. One of ordinary skill in the art will appreciate that the plane of the pixel's photodiode and the plane of the pixel circuitry are typically offset vertically, i.e., the photodiode is above the circuitry when viewed from the light source side. In addition, in some embodiments, the connected pixel region 700 allows the connected pixel circuitry to include a larger source follower (SF) 220 located at the same horizontal plane as the photodiodes 211-R, 211-B, 211-G (e.g., Figure 7 A larger source follower SF can reduce the noise of the image sensor.

[0055] Figure 8 2 is a top view of a pixel 210 including a plurality of photodiodes 211-R, 211-B, 211-G and a pixel circuit 230 according to an embodiment of the present disclosure. In some embodiments, the pixel 210 includes four quadrants Q1, Q2, Q3 and Q4. In some embodiments, the pixel includes a group of photodiodes 211-R, 211-G, 211-B. Each photodiode of the photodiode group 211-R, 211-G, 211-B is located in the first quadrant Q1, the second quadrant Q2 and the third quadrant Q3, respectively. In some embodiments, the pixel 210 includes only a single red photodiode 211-R, a single green photodiode 211-G and a single blue photodiode 211-B. It should be understood that although in Figure 8In the embodiment, the red photodiode 211-R is located in the first quadrant Q1, the green photodiode 211-G is located in the second quadrant Q2, and the blue photodiode 211-B is located in the third quadrant Q3, but each photodiode of the photodiode groups 211-R, 211-G, and 211-B can be located in any quadrant Q1, Q2, and Q3. Therefore, the overall structure is simpler. In some embodiments, the photodiode groups 211-R, 211-G, and 211-B can be Figure 3 The photodiodes 211-R, 211-G, 211-B shown in FIG. The color router allows the conventional color filters and microlenses to be omitted. The pixel circuit system 230 can be located at the same level as the photodiodes 211-R, 211-G, 211-B (e.g. Figure 8 This is in contrast to the layout of conventional photodiodes and pixel circuits, where the photodiodes are distributed in one plane (or layer, closer to the color filters and microlenses) and the pixel circuits are distributed in another plane (further away from the color filters and microlenses). In conventional technology, the plane of the photodiodes is configured between the plane of the pixel circuits on one side and the plane of the color filters and microlenses on the other side. In addition, because the color router improves the efficiency of the photodiode groups 211-R, 211-G, 211-B, only a single red photodiode 211-R, green photodiode 211-G, and blue photodiode 211-B may be included in the pixel 210 (as opposed to two green photodiodes 211-G included in a conventional pixel), thereby creating space that can be used to place the readout circuitry (pixel circuitry), as further explained below.

[0056] In some embodiments, the pixel 210 includes a central transfer transistor (TX4) 212-4. In some embodiments, each of the photodiodes 211-R, 211-G, 211-B includes a respective transfer transistor (TX1) 212-1, (TX2) 212-2, (TX3) 212-3. In some embodiments, the central transfer transistor TX4 212-4 is adjacent to respective transfer transistors TX1 212-1, TX2 212-2, TX3 212-3 of the first quadrant Q1, the second quadrant Q2, and the third quadrant Q3. In operation, each transfer transistor TX1 212-1, TX2 212-2, TX3 212-3 is enabled to transfer image charge from its respective photodiode 211-R, 211-G, 211-B to the central transfer transistor TX4 212-4, as shown in FIG. Figures 10A to 10D Described in detail in.

[0057] In some equivalent embodiments, pixel circuit 230 includes floating diffusion region (FD) 213 having intrinsic capacitor (FDC) 219, reset transistor (RST) 214, source follower (SF) transistor 220, row select (RS) transistor 221, and bit line BL (218). In some embodiments, pixel circuit 230 does not include a subsequent transfer transistor (e.g. Figure 4 In such embodiments, the size of the floating diffusion region FD 213 is greater than Figure 4 Therefore, Figure 8 The larger floating diffusion area of ​​FD 213 is comparable Figure 4 The smaller floating diffusion region has a larger capacitance. The increased size of FD 213 is at least partially caused by the absence of the subsequent transfer transistor TX5. The presence of TX5 allows Figure 4 The FD 213 of the embodiment of the present invention is further scaled down to increase to a higher sensitivity with the minimum possible full well capacity. In some embodiments, it is desirable for the FD 213 to have a low capacitance so that it achieves a high conversion gain (HCG). In some embodiments, the pixel circuit (readout circuit) 230 allows reading from one photodiode of the photodiode group 212-R, 212-G, 212-B, such as Fig. 9 Detailed description and presentation in .

[0058] In some embodiments, pixel circuit 230 is configured to generate simultaneous readout from photodiode groups 212-R, 212-B, 212-G to generate a black and white image. Dashed line AA to AA' represents a cross section of the charge flow path from photodiode 211-B to floating diffusion region FD 213. This cross section is about Figures 10A to 10D Display and further description.

[0059] Fig. 9 2 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure. Figure 1 Each pixel 103 (eg Figure 8 Pixel circuit 230 may be implemented using a front or back illuminated pixel array.

[0060] The illustrated embodiment of the pixel circuit 230 includes a first photodiode (PD1) 211-1, a second photodiode (PD2) 211-2, and a third photodiode (PD3) 211-3. In some embodiments, the first photodiode PD1 211-1, the second photodiode PD2 211-2, and the third photodiode PD3 211-3 are coupled to respective transfer transistors (TX1 212-1, TX2 212-2, TX3 212-3). Specifically, the first photodiode PD1 211-1 is coupled to the first transfer transistor TX1 212-1, the second photodiode PD2 211-2 is coupled to the second transfer transistor TX2 212-2, and the third photodiode PD3 is coupled to the third transfer transistor TX3 212-3. In one embodiment, transfer transistors TX1 212-1, TX2 212-2, TX3 212-3 are similarly sized, which reduces space and increases fill factor (defined as the ratio of the area occupied by the different components of the readout circuitry to the total available area in the fourth quadrant Q4). In some embodiments, each of transfer transistors 212-1, 212-2, 212-3 is coupled to node S1, which is coupled to a center transfer transistor TX4 212-4. In some embodiments, center transfer transistor TX4 212-4 is further coupled to floating diffusion region FD 213. In some embodiments, floating diffusion region FD 213 is coupled to capacitor (FDC) 219, reset transistor (RST) 214, source follower (SF) transistor 220, row select (RS) transistor 221, and bit line BL (218), as described herein.

[0061] In operation, the read charge of each photodiode 211 of the first photodiode PD1 211-1, the second photodiode PD2 211-2, and the third photodiode PD3 211-3 may be read out by the pixel circuit 230. Specifically, the read charge of the first photodiode PD1 211-1 may be read out by the pixel circuit 230 by transferring the charge from the first photodiode PD 211-1 to the first transfer transistor TX1 212-1, the center transfer transistor TX4 212-4, the subsequent transfer gate 212-5, and the floating diffusion region FD 213. Similarly, the read charge of the second photodiode PD2 211-2 may be read out by the pixel circuit 230 by transferring the charge from the second photodiode PD2 211-2 to the second transfer transistor TX 212-2, the center transfer transistor TX4 212-4, and the floating diffusion region FD 213. In addition, the read charge of the third photodiode PD2 211-3 can be read out by the pixel circuit 230 by transferring the charge from the third photodiode PD2 211-3 to the third transfer transistor TX 212-3, the center transfer transistor TX4 212-4, and the floating diffusion region FD 213. In some embodiments, the charge can be transferred from the first photodiode PD1 211-1, the second photodiode PD2 211-2, and the third photodiode PD3 211-3 at the same time to achieve a black and white image.

[0062] Figures 10A to 10D is a process diagram of charge propagation according to an embodiment of the present disclosure. Figures 10A to 10D Indicates along Figure 8 Specifically, the line AA to AA' represents the cross section of the line AA to AA'. Figure 8 2 is a cross section of a photodiode 211-B in the third quadrant Q3 of the pixel 210. The cross section AA to AA' cuts through the photodiode 211-B, through the first transfer transistor TX1 212-1, to the center transfer transistor TX4 212-4, and to the reset transistor (RST) 214. Figures 10A to 10D On the left side of each is the voltage in volts. Figures 10A to 10D As described in , the photodiode may include an insulator and multiple gates (transistors TX1, TX5) above the insulator. Figures 10A to 10D In, electronic - Flows between the photodiode and the corresponding transistor.

[0063] like Fig. 10A As shown in the figure, the electrons e accumulated in the photodiode (PD1) -The gate voltage of each transistor (the first transfer transistor TX1 and the central transfer transistor TX4) is zero (0V), so each transistor is set to an off state. Fig. 10B In the embodiment, the gates of transistors TX2 and TX4 are set to an on state by gate voltage VTX, thereby allowing photogenerated charges from photodiode PD1 (211-B) to flow into the wells of first transfer transistor TX 212-1 and center transfer transistor TX 212-4 and accumulate.

[0064] exist Fig. 10C In all the electrons e - After completing its transfer, the gate of the first transfer transistor TX1 212-1 is set to the off position by setting the gate voltage back to 0V, and the photogenerated charge has now flowed from the well of TX1 212-1 to the well of the center transfer transistor TX4 212-4. The gate of the center transfer transistor 212-4TX4 is maintained at the voltage VTX, thus keeping its gate in its on position. Fig. 10D The charge transfer process continues. That is, in all electrons e - After completing its transfer from the well of the center transfer transistor TX4 212-4, the gate of the center transfer transistor TX4 212-4 is set to the off position by setting the gate voltage back to 0 V. The charge is now accumulated in the floating diffusion region 213. As shown in FIG. Figure 8 As explained, the RST transistor is coupled to a reference voltage AVDD and is configured to receive a reset control signal on its gate terminal. Thus, the RST transistor can reset the floating diffusion region FD 213. When TX1 212-1, TX2 212-2, TX3 212-3, and TX4 212-4 are all turned on through their gate terminals, PD1, PD2, and PD3 are reset.

[0065] Fig.11 is a top view of a group of pixels 1160 according to an embodiment of the present disclosure. In some embodiments, Figure 1 The plurality of pixels 103 of the pixel array 102 are arranged to form a plurality of pixel groups, each pixel group 1160 in the plurality of pixel groups includes a first pixel 210-i, a second pixel 210-ii, a third pixel 210-iii, and a fourth pixel 210-iv. In some embodiments, each pixel group 1160 in the plurality of pixel groups is arranged in a 2×2 array. In some embodiments, each pixel 210-i, 210-ii, 210-iii, 210-iv is substantially similar in structure to the first pixel 210-i, the second pixel 210-ii, the third pixel 210-iii, and the fourth pixel 210-iv. Figure 8The pixels 210 of the same pixel group 1160. Therefore, each pixel 210-i, 210-ii, 210-iii, 210-iv is understood to have a first quadrant, a second quadrant, a third quadrant, and a fourth quadrant (i.e., Q1, Q2, Q3, Q4), wherein the first photodiode 211-R, the second photodiode 211-G, and the third photodiode 211-B are located in the first quadrant, the second quadrant, and the third quadrant, respectively. In some embodiments, a color router (e.g., color router 303) covers all photodiodes 211 in pixel group 1160. For simplicity and ease of use, Fig.11 For easier reading, the readout circuits (pixel circuits) 230-i, 230-ii, 230-iii, and 230-iv are symbolically illustrated in this figure with rectangles. A person skilled in the art should understand that each pixel 230-i, 230-ii, 230-iii, and 230-iv requires one readout circuit 230. For simplicity and clarity of the diagram, only the transfer transistors (e.g., Figure 8 212-1TX1, 212-2TX2, 212-3TX3), center transfer transistors (e.g. Figure 8 TX4 212-4) and floating diffusion region FD (e.g. Figure 8 FD 213 in ), but these transfer transistors are also present in other pixels and their readout circuits.

[0066] In some embodiments, each pixel 210-i, 210-ii, 210-iii, 210-iv in pixel group 260 is arranged so that the fourth quadrant of each pixel is adjacent to the fourth quadrants of two adjacent pixels in the 2×2 pixel array. For example, the fourth quadrant of pixel 210-i is adjacent to the fourth quadrants of both pixels 210-ii and 210-iii. By arranging pixels 210-i, 210-ii, 210-iii, 210-iv in this manner, a connected pixel region 1100 is formed. The connected pixel region 1100 allows the pixel circuitry 230-i, 230-ii, 230-iii, 230-iv to be located in the center of the pixel group 1160. The connected pixel region 1100 is configured to allow larger circuit components of the pixel circuitry 230-i, 230-ii, 230-iii, 230-iv to share space and be used for shared pixel circuitry, such as lateral overflow integrated capacitors (LOFICs) 1130, as described herein. For example, a large lateral overflow integration capacitor (LOFIC) may be shared by all pixels in pixel group 1160, as indicated by the dashed lines connecting each pixel 210-i, 210-ii, 210-iii, and 210-iv to LOFIC 1130 and described in more detail below. This sharing of LOFIC 1130 may result in further savings in die area required for readout circuitry. In some embodiments, connecting pixel region 1100 allows pixel circuitry 230-i, 230-ii, 230-iii, 230-iv to include a large source follower (SF) located on the same horizontal plane as photodiodes 211-R, 211-B, 211-G. Larger source followers SF may reduce noise of the image sensor.

[0067] Many embodiments of the above-described techniques may take the form of computer or controller executable instructions, including routines executed by a programmable computer or controller. Those skilled in the relevant art will appreciate that the techniques may be practiced on computer / controller systems other than those shown and described above. The techniques may be embodied in a special-purpose computer, an application-specific integrated circuit (ASIC), a controller, or a data processor that is specially programmed, configured, or constructed to execute one or more of the above-described computer-executable instructions. Of course, any logic or algorithm described herein may be implemented in software or hardware or a combination of software and hardware.

[0068] The above description of the illustrated examples of the present invention (including what is described in the Abstract) is not intended to be exhaustive or to limit the present invention to the precise forms disclosed. Although specific examples of the present invention are described herein for illustration, those skilled in the relevant art will recognize that various modifications may be made within the scope of the present invention.

[0069] These modifications can be made to the invention in light of the above detailed description. The terms used in the appended claims should not be interpreted as limiting the invention to the specific examples disclosed in the specification. Rather, the scope of the present invention is determined entirely by the appended claims, which will be interpreted in accordance with established principles of claim interpretation.

Claims

1. An image sensor, comprising: a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor substrate, wherein each pixel comprises a plurality of photodiodes; a color router covering the plurality of photodiodes, wherein the plurality of pixels are configured to receive incident light through the color router; and A plurality of pixel circuits, wherein each pixel circuit is associated with a corresponding pixel of the plurality of pixels, wherein the plurality of pixel circuits are arranged on the same horizontal plane as the plurality of photodiodes.

2. The image sensor of claim 1, wherein each pixel comprises a group of photodiodes, the group of photodiodes including only one each of a blue photodiode, a red photodiode, and a green photodiode.

3. The image sensor of claim 2 , wherein each pixel comprises a first quadrant, a second quadrant, a third quadrant, and a fourth quadrant, wherein each photodiode in the group of photodiodes is configured in one of the first quadrant, the second quadrant, or the third quadrant of the pixel, and wherein the pixel circuit associated with the pixel is configured in the fourth quadrant of the pixel.

4. The image sensor of claim 3, wherein the pixel circuit comprises at least a central transfer transistor, a floating diffusion region, a reset transistor, a source follower transistor, and a row select transistor.

5. The image sensor of claim 4, wherein the pixel circuit further comprises a subsequent transfer transistor coupled to the central transfer transistor and the floating diffusion region.

6. The image sensor of claim 3, wherein the first, second, and third quadrants of the pixel each include a transfer transistor.

7. The image sensor of claim 6 , wherein the pixel further comprises a center transfer transistor adjacent to each transfer transistor of the first quadrant, the second quadrant, and the third quadrant, wherein each transfer transistor of the first quadrant, the second quadrant, and the third quadrant is coupled to the center transfer transistor, and wherein each transfer transistor is configured to transfer charge from a corresponding photodiode of the first quadrant, the second quadrant, and the third quadrant to the center transfer transistor.

8. The image sensor of claim 7, wherein the fourth quadrant further comprises a subsequent transfer transistor coupled to the center transfer transistor, wherein the center transfer transistor is configured to transfer charge to the subsequent transfer transistor.

9. The image sensor of claim 8, wherein a floating diffusion region is coupled to the subsequent transfer transistor and is configured to receive the charge from the subsequent transfer transistor.

10. The image sensor of claim 7, wherein the fourth quadrant further comprises a floating diffusion region coupled to the center transfer transistor and configured to receive the charge from the center transfer transistor.

11. The image sensor of claim 6 , wherein the plurality of pixels are arranged into a plurality of pixel groups, each of the plurality of pixel groups comprising a first pixel, a second pixel, a third pixel, and a fourth pixel, wherein each of the plurality of pixel groups is arranged into a 2×2 array, and wherein each pixel in the pixel group is arranged such that the fourth quadrant of each pixel is adjacent to the fourth quadrant of each adjacent pixel in the 2×2 array, thereby forming a connected pixel region.

12. The image sensor of claim 11, wherein each pixel group of the connected pixel region includes connected pixel circuitry associated with a photodiode of a given pixel.

13. The image sensor of claim 12, wherein each connected pixel circuit further comprises a lateral overflow integration capacitor.

14. The image sensor of claim 12, wherein each connected pixel circuit shares a common lateral overflow integration capacitor.

15. A method for reading a readout charge of an image sensor, the image sensor comprising: a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor substrate, wherein each pixel comprises a plurality of photodiodes, a color router covering the plurality of photodiodes, wherein the plurality of pixels are configured to receive incident light through the color router, and a plurality of pixel circuits, wherein each pixel circuit is associated with a corresponding pixel of the plurality of pixels, wherein the plurality of pixel circuits are arranged on the same horizontal plane as the plurality of photodiodes, The method comprises: transferring one or more charges from one or more photodiodes of the plurality of photodiodes to one or more transfer transistors of a plurality of transfer transistors, wherein each photodiode is coupled to a transfer transistor of the plurality of transfer transistors; transferring the one or more charges from each respective transfer transistor to a central transistor; transferring the one or more charges to a floating diffusion region; and The one or more charges are read out to produce an image.

16. The method of claim 15, wherein each pixel comprises a group of photodiodes, the group of photodiodes including only one each of a blue photodiode, a red photodiode, and a green photodiode.

17. The method according to claim 16, wherein the method further comprises: Transferring charge from the red photodiode, the green photodiode, and the blue photodiode simultaneously; and The charges are read out simultaneously to produce a black and white image.

18. The method of claim 16, wherein each pixel comprises a first quadrant, a second quadrant, a third quadrant, and a fourth quadrant, wherein each photodiode in the group of photodiodes is configured in one of the first quadrant, the second quadrant, or the third quadrant of the pixel, and wherein the pixel circuit associated with the pixel is configured in the fourth quadrant of the pixel.

19. The method of claim 18, wherein the pixel circuit comprises at least a central transfer transistor, a floating diffusion region, a reset transistor, a source follower transistor, and a row select transistor.

20. The method of claim 19, wherein the pixel circuit further comprises a subsequent transfer transistor coupled to the central transfer transistor and the floating diffusion region.

21. The method of claim 18, wherein the fourth quadrant further comprises a subsequent transfer transistor coupled to the center transfer transistor, wherein the method further comprises: The one or more charges are transferred from the central transfer transistor to the subsequent transfer transistor prior to transferring the one or more charges to the floating diffusion region.

22. The method of claim 18, wherein the fourth quadrant further comprises a floating diffusion region coupled to the center transfer transistor and configured to receive the charge from the center transfer transistor.

23. The method of claim 15, wherein the plurality of pixels are arranged into a plurality of pixel groups, each of the plurality of pixel groups comprising a first pixel, a second pixel, a third pixel, and a fourth pixel, wherein each of the plurality of pixel groups is arranged into a 2×2 array, and wherein each pixel in the pixel group is arranged such that the fourth quadrant of each pixel is adjacent to the fourth quadrant of each adjacent pixel in the 2×2 array, thereby forming a connected pixel region.

24. The method of claim 23, wherein each pixel of the connected pixel region includes connected pixel circuitry associated with a photodiode of a given pixel.

25. The method of claim 24, wherein each connected pixel circuit further comprises a lateral overflow integrating capacitor.

26. The method of claim 24, wherein each connected pixel circuit shares a common lateral overflow integrating capacitor.

Images