Preparation method and equipment of photodiode chip and photodiode chip

Abstract

The invention provides a photodiode chip preparation method and device and a photodiode chip, and the method comprises the steps: carrying out the etching of a current epitaxial wafer, forming a trench window, enabling a second region where the trench window is located to be located outside a first region, and enabling the second region to surround the first region, a groove window penetrates through the P ohmic contact layer, the diffusion window layer, the intrinsic absorption layer and the N-type material contact layer, and the groove window is located on the InP substrate layer; growing an anti-reflection film on the current surface layer; etching the P ohmic contact area to obtain a P window, and leading out a P electrode at the P window; growing a metal reflecting film on the groove window and the edge extension area of the groove window; and manufacturing an N electrode on the back surface of the InP substrate layer to form a photodiode chip. According to the technical scheme, the responsivity of incident light with the wavelength of 1310 nm can be improved, the quantum efficiency reaches 98% or above, the responsivity of incident light with the wavelength of 300-755 nm is reduced, the quantum efficiency is smaller than 2%, and the special requirement of an optical detection sensing chip is met.

Description

[Technical field]

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method and device for preparing a photodiode chip and a photodiode chip. [Background technology]

[0002] Photodiode chips are widely used photosensitive devices in electronic circuits. They have a large PN junction area and generate current when receiving incident light as a photosensitive surface. The greater the intensity of the incident light, the greater the reverse current generated. In other words, the principle is to achieve the conversion of optical signals into electrical signals by bringing about changes in the current of the photodiode chip through changes in the incident light.

[0003] At present, the photodiode chips on the market can effectively respond to incident light with a wavelength of 1310nm. However, in the actual environment, there is also low-wavelength visible light of 300-755nm. This visible light acts as noise and also causes the photodiode chip to respond, affecting the working performance of the photodiode chip and having a negative impact on the circuit where the photodiode chip is located and even the entire product.

[0004] Therefore, how to reduce the negative impact of low-wavelength visible light on photodiode chips has become a technical problem that needs to be solved urgently. [Summary of the invention]

[0005] The embodiments of the present application provide a method and device for preparing a photodiode chip and a photodiode chip, aiming to solve the technical problem in the related art that low-wavelength visible light affects the normal operation of the photodiode chip.

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a photodiode chip, which is used to make an epitaxial wafer into a photodiode chip, wherein the epitaxial wafer includes a P ohmic contact layer, a diffusion window layer, an intrinsic absorption layer, an N-type material contact layer and an InP substrate layer from the surface layer to the bottom layer, and the method includes:

[0007] Etching a P ohmic contact region in the P ohmic contact layer;

[0008] growing a diffusion barrier film on the current surface;

[0009] A diffusion hole is formed in the diffusion window layer, and the first region where the diffusion hole is located accommodates the location of the P ohmic contact region;

[0010] Performing Zn diffusion treatment to form a highly doped P+-INP diffusion zone in the first region, wherein the diffusion zone is distributed from the diffusion window layer to the intrinsic absorption layer;

[0011] Etching the current epitaxial wafer to form a groove window, wherein the second region where the groove window is located is located outside the first region and surrounds the first region, the groove window penetrates the P ohmic contact layer, the diffusion window layer, the intrinsic absorption layer and the N-type material contact layer, and the groove window is located in the InP substrate layer;

[0012] growing an anti-reflection film on the current surface;

[0013] Etching the P ohmic contact area to obtain a P window, and leading out a P electrode at the P window;

[0014] Growing a metal reflective film on the groove window and the edge extension area of ​​the groove window;

[0015] An N electrode is fabricated on the back side of the InP substrate layer to form a photodiode chip.

[0016] In one embodiment of the present application, optionally, the method further includes:

[0017] The metal reflective film is grown on at least one side wall of the epitaxial wafer.

[0018] In one embodiment of the present application, optionally, the metal reflective film is a combination material of Ti, Pt, and Au, the thickness of Ti in the metal reflective film is greater than or equal to 30nm and less than or equal to 100nm; the thickness of Pt in the metal reflective film is greater than or equal to 30nm and less than or equal to 100nm; the thickness of Au in the metal reflective film is greater than or equal to 3000nm and less than or equal to 15000nm.

[0019] In one embodiment of the present application, optionally, before manufacturing the N electrode on the back side of the InP substrate layer, the method further includes:

[0020] Performing a thickness reduction process on the InP substrate layer;

[0021] In the process of arranging the N electrode on the outer surface of the InP substrate layer, the process further includes:

[0022] The composite material of Ti, Pt and Au is sputtered or evaporated on the back of the thinned InP substrate layer to form an N electrode layer having the composite material of Ti, Pt and Au.

[0023] In one embodiment of the present application, optionally, the thickness of Ti in the N-electrode layer is greater than or equal to 50 nm and less than or equal to 100 nm; the thickness of Pt in the N-electrode layer is greater than or equal to 50 nm and less than or equal to 100 nm; the thickness of Au in the N-electrode layer is greater than or equal to 100 nm and less than or equal to 200 nm.

[0024] In one embodiment of the present application, optionally, the thickness of the epitaxial wafer after thickness reduction is greater than or equal to 110 μm and less than or equal to 160 μm.

[0025] In one embodiment of the present application, optionally, the P-ohmic contact area is a P-ohmic contact ring; the first area where the diffusion hole is located accommodates the P-ohmic contact ring; and the groove window is a closed circular groove or a closed polygonal groove surrounding the first area.

[0026] In one embodiment of the present application, optionally, the P ohmic contact area is a P ohmic contact block; the first area where the diffusion hole is located accommodates the P ohmic contact block; while etching the P ohmic contact area, it also includes: etching a portion of the diffusion area adjacent to the P ohmic contact block, wherein the entire area subjected to the etching process is a P window, and the shape of the P window is block-shaped; the third area where the P electrode is located covers the position of the P window, and the third area is non-surroundingly adjacent to the fourth area covered by the photosensitive surface of the photodiode chip; the groove window is an unclosed arc groove or an unclosed polygonal groove surrounding the first area, and the unclosed position of the unclosed arc or the unclosed polygon is covered by the third area.

[0027] In a second aspect, an embodiment of the present application provides a photodiode chip, characterized in that it is prepared by the method for preparing a photodiode chip according to any one of the first aspects above, and the photodiode chip comprises:

[0028] A diffusion window layer is provided with a diffusion hole, wherein a first region where the diffusion hole is located has a diffusion region with a high doping P+-INP;

[0029] A groove window is located in a second area outside the first area, surrounding the first area, wherein the groove window penetrates the P ohmic contact layer, the diffusion window layer, the intrinsic absorption layer and the N-type material contact layer, and the bottom of the groove window is a surface groove of the InP substrate layer;

[0030] A diffusion barrier film covering the area outside the diffusion hole and the groove window in the surface layer of the diffusion window layer;

[0031] An intrinsic absorption layer is located in a lower layer adjacent to the diffusion window layer, and the diffusion region diffuses to an upper region of the intrinsic absorption layer;

[0032] An N-type material contact layer, located in a lower layer adjacent to the intrinsic absorption layer;

[0033] An InP substrate layer, located in a lower layer adjacent to the N-type material contact layer;

[0034] P ohmic contact region, located above the first region;

[0035] an anti-reflection film covering the diffusion barrier film, a position other than the P-ohmic contact region in the first region, and a surface of the groove window;

[0036] A P electrode connected to the P ohmic contact region through a P window;

[0037] A metal reflective film, an anti-reflective film covering the surface of the groove window, and an anti-reflective film covering the edge extension area of ​​the groove window;

[0038] The N electrode is arranged on the back side of the InP substrate layer.

[0039] In a third aspect, an embodiment of the present application provides a device for preparing a photodiode chip, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the first aspect above.

[0040] The above technical solution aims at the technical problem that low-wavelength visible light affects the normal operation of photodiode chips in related technologies. By adding groove windows and metal reflective films, the influence of low-wavelength visible light on the operation of photodiode chips can be effectively reduced, and the responsiveness of incident light with a wavelength of 1310nm can be improved, so that the quantum efficiency reaches more than 98%, and the responsiveness of incident light with a wavelength of 300-755nm can be reduced, so that the quantum efficiency is less than 2%, so as to meet the special needs of light detection sensor chips. As a result, the reliability of the photodiode chip is improved, and the overall performance of the circuit and even the product in which the photodiode chip is located is improved.

Brief Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A flow chart showing a method for preparing a photodiode chip according to an embodiment of the present application is shown;

[0043] Figure 2 shows a cross-sectional view of an epitaxial wafer according to an embodiment of the present application;

[0044] Figure 3 shows a cross-sectional view of a photodiode chip according to an embodiment of the present application;

[0045] Figure 4 A cross-sectional view of a photodiode chip according to another embodiment of the present application is shown. [Specific implementation method]

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] Figure 1 A flow chart of a method for preparing a photodiode chip according to an embodiment of the present application is shown.

[0048] like Figure 1 As shown, a method for preparing a photodiode chip according to an embodiment of the present application includes:

[0049] Step 102: etching a P-ohmic contact region in the P-ohmic contact layer.

[0050] Step 104, growing a diffusion barrier film on the current surface layer.

[0051] It should be noted that the preparation method described in this application is used to process the epitaxial wafer into a photodiode chip, such as Figure 2 As shown, the epitaxial wafer includes a P ohmic contact layer, a diffusion window layer, an intrinsic absorption layer, an N-type material contact layer and an InP substrate layer in sequence from the surface layer to the bottom layer.

[0052] Optionally, the thickness of the P ohmic contact layer is greater than or equal to 0.05 μm and less than or equal to 0.2 μm.

[0053] Optionally, the thickness of the diffusion window layer is greater than or equal to 3 μm and less than or equal to 5 μm.

[0054] Optionally, the thickness of the intrinsic absorption layer is greater than or equal to 3 μm and less than or equal to 5 μm.

[0055] Optionally, the N-type material contact layer is N-type with high concentration doping (>2E+18cm -3 ) InP material, with a thickness greater than or equal to 0.3 μm and less than or equal to 1.5 μm.

[0056] Optionally, the InP substrate layer is a 2-4 inch InP conductive substrate sheet.

[0057] Specifically, first, a P ohmic contact area is etched in the P ohmic contact layer for ohmic contact, and then a diffusion barrier film is set. The diffusion barrier film is used to protect the area outside the diffusion hole on the surface of the chip substrate during the subsequent setting of the diffusion hole.

[0058] In a possible design, a SiO2 barrier film, a SiNx barrier film or a SiNx / SiO2 composite barrier film with a thickness greater than or equal to 100 nm and less than or equal to 1000 nm is grown on the current surface layer as a diffusion barrier film. Of course, the thickness of the diffusion barrier film can be any value that meets actual needs, and is not limited to the above value range.

[0059] Step 106: forming a diffusion hole in the diffusion window layer, wherein the first region where the diffusion hole is located accommodates the location of the P ohmic contact region.

[0060] When diffusion is performed, the entire P ohmic contact area is contained within the diffusion hole.

[0061] Step 108 , performing Zn diffusion treatment to form a highly doped P+-INP diffusion zone in the first region, wherein the diffusion zone is distributed from the diffusion window layer to the intrinsic absorption layer.

[0062] In a possible design, the diffusion region diffuses into the intrinsic absorption layer to a depth greater than or equal to 0.05 μm and less than or equal to 0.5 μm.

[0063] Step 110, etching the current epitaxial wafer to form a groove window, wherein the second area where the groove window is located is located outside the first area and surrounds the first area, and the groove window penetrates the P ohmic contact layer, the diffusion window layer, the intrinsic absorption layer and the N-type material contact layer, and the bottom of the groove window is recessed into the InP substrate layer.

[0064] The etching method in the etching process includes wet etching or dry RIE etching until the N-type material contact layer is etched through and finally falls on the InP substrate layer.

[0065] Step 112, growing an anti-reflection film on the current surface layer.

[0066] The anti-reflection film includes a SiNx single-layer film or a SiNx / SiO2 composite film, has a thickness greater than or equal to 170nm and less than or equal to 210nm, and has a reflectivity of less than 2.5% for incident light with a wavelength of 1310nm.

[0067] Step 114, etching the P ohmic contact area to obtain a P window, and leading out a P electrode at the P window.

[0068] That is, the anti-reflection film in the P ohmic contact area is etched cleanly through photolithography and RIE etching so as to lead out the P electrode, wherein the P electrode can be formed by photolithography.

[0069] Step 116, growing a metal reflective film on the groove window and the edge extension area of ​​the groove window.

[0070] Optionally, the metal reflective film is a combination of Ti, Pt and Au.

[0071] Optionally, the thickness of Ti in the metal reflective film is greater than or equal to 30 nm and less than or equal to 100 nm.

[0072] Optionally, the thickness of Pt in the metal reflective film is greater than or equal to 30 nm and less than or equal to 100 nm.

[0073] Optionally, the thickness of Au in the metal reflective film is greater than or equal to 3000 nm and less than or equal to 15000 nm.

[0074] Step 118, making an N electrode on the back side of the InP substrate layer to form a photodiode chip.

[0075] Thus, the low-wavelength visible light on the surface of the photodiode chip can be isolated by the metal reflective film. At the same time, by setting the groove window, the P-ohmic contact layer, the diffusion window layer, the intrinsic absorption layer, and the N-type material contact layer can be isolated from the first part on the outside of the groove window and the second part on the inside of the groove window, respectively, to prevent free electrons generated by the low-wavelength visible light in the first part on the outside from entering the second part on the inside, thereby reducing the impact of the low-wavelength visible light on the actual working effect of the photodiode chip.

[0076] Optionally, the low-wavelength visible light refers to incident light with a wavelength of 300-755 nm. Of course, the low-wavelength visible light can also be light of any wavelength that has a negative impact on the photodiode chip.

[0077] The above technical solution can effectively reduce the influence of low-wavelength visible light on the operation of the photodiode chip by adding a groove window and a metal reflective film, improve the responsiveness of the incident light with a wavelength of 1310nm, and make the quantum efficiency reach more than 98%, and reduce the responsiveness of the incident light with a wavelength of 300-755nm, so that the quantum efficiency is less than 2%, so as to meet the special needs of the light detection sensor chip. In this way, the reliability of the photodiode chip is improved, and the overall performance of the circuit and even the product in which the photodiode chip is located is improved.

[0078] Optionally, the photodiode chip described in the context embodiments includes but is not limited to a low-speed chip, an MPD backlight monitoring diode chip or a sensor diode chip, etc. In another possible design, the photodiode chip is a PIN photodiode chip, an APD photodiode chip or an MPD photodiode chip.

[0079] Figure 3 A cross-sectional view of a photodiode chip according to an embodiment of the present application is shown.

[0080] like Figure 3 As shown, the photodiode chip according to one embodiment of the present application includes: a diffusion window layer, a groove window, a diffusion barrier film, an intrinsic absorption layer, an N-type material contact layer, an InP substrate layer, a P ohmic contact area, an anti-reflection film, a metal reflective film, a P electrode and an N electrode.

[0081] The diffusion window layer is provided with a diffusion hole, and the first region where the diffusion hole is located has a diffusion region of high doping P+-INP. The intrinsic absorption layer is located in the adjacent lower layer of the diffusion window layer, the diffusion region diffuses to the upper region of the intrinsic absorption layer, the N-type material contact layer is located in the adjacent lower layer of the intrinsic absorption layer, and the InP substrate layer is located in the adjacent lower layer of the N-type material contact layer.

[0082] The groove window is located in the second area outside the first area, surrounding the first area, and the groove window penetrates the P ohmic contact layer, the diffusion window layer, the intrinsic absorption layer and the N-type material contact layer, and the bottom of the groove window is the surface groove of the InP substrate layer. The diffusion barrier film covers the area outside the diffusion hole and the groove window in the surface layer of the diffusion window layer, and the P ohmic contact area is located above the first area. The metal reflection film covers the anti-reflection film on the surface of the groove window and the anti-reflection film covering the edge extension area of ​​the groove window.

[0083] The anti-reflection film covers the diffusion barrier film, a location other than the P-ohmic contact region in the first region, and a surface of the groove window.

[0084] The P electrode is connected to the P ohmic contact region through a P window, and the N electrode is arranged on the outer surface of the InP substrate layer.

[0085] The photodiode chip has all the technical effects described in any of the above embodiments, which will not be repeated here.

[0086] Figure 4 A cross-sectional view of a photodiode chip according to another embodiment of the present application is shown.

[0087] like Figure 4As shown, the metal reflective film is grown on at least one side wall of the epitaxial wafer, thereby blocking the short-wavelength visible light received by the side wall of the epitaxial wafer, reducing the minority carriers generated by the side wall being irradiated by the short-wavelength visible light, and further reducing the negative impact of the short-wavelength visible light on the photodiode chip.

[0088] Optionally, the metal reflective film is grown on a side wall of the epitaxial wafer to reduce minority carriers generated by the side wall being irradiated by short-wavelength visible light.

[0089] Optionally, the metal reflective film is grown on all side walls of the epitaxial wafer to reduce minority carriers generated when all side walls of the epitaxial wafer are irradiated with short-wavelength visible light.

[0090] In addition, based on any of the above embodiments, before the N electrode is formed on the back side of the InP substrate layer, the InP substrate layer may be thinned. In the process of arranging the N electrode on the outer surface of the InP substrate layer, the back side of the InP substrate layer after the thickness is thinned is sputtered or evaporated with a combination of Ti, Pt, and Au to form an N electrode layer with a combination of Ti, Pt, and Au.

[0091] Therefore, the function of isolating low-wavelength visible light can be added to the back side of the photodiode chip, thereby reducing the negative impact of low-wavelength visible light on the photodiode chip in all directions.

[0092] In one possible design, the thickness of Ti in the N-electrode layer is greater than or equal to 50 nm and less than or equal to 100 nm; the thickness of Pt in the N-electrode layer is greater than or equal to 50 nm and less than or equal to 100 nm; the thickness of Au in the N-electrode layer is greater than or equal to 100 nm and less than or equal to 200 nm.

[0093] In a possible design, the thickness of the epitaxial wafer after the thickness reduction is greater than or equal to 110 μm and less than or equal to 160 μm.

[0094] It should be noted that any numerical parameter and any numerical range parameter described in the embodiments of the present application are examples. In actual production scenarios, these parameters of the photodiode chip can be arbitrarily set and adjusted based on actual product requirements, and are not limited to the examples given in this application.

[0095] In a possible design, the P-ohmic contact area is a P-ohmic contact ring, the first area where the diffusion hole is located accommodates the P-ohmic contact ring, and the groove window is a closed circular groove or a closed polygonal groove surrounding the first area.

[0096] In another possible design, the P ohmic contact area is a P ohmic contact block, and the first area where the diffusion hole is located accommodates the P ohmic contact block; while etching the P ohmic contact area, it also includes: etching a portion of the diffusion area adjacent to the P ohmic contact block, wherein the entire area subjected to the etching process is a P window, and the shape of the P window is block-shaped; the third area where the P electrode is located covers the position where the P window is located, and the third area is non-surroundingly adjacent to the fourth area covered by the photosensitive surface of the photodiode chip; the groove window is an unclosed arc groove or an unclosed polygonal groove surrounding the first area, and the unclosed position of the unclosed arc or the unclosed polygon is covered by the third area.

[0097] Specifically, the P ohmic contact layer can be etched into a P ohmic contact block of a specified length and a specified width, wherein the specified length is greater than or equal to 2 μm and less than or equal to 7 μm, and the specified width is greater than or equal to 2 μm and less than or equal to 7 μm. Of course, the length and width of the P ohmic contact block can be arbitrarily set values ​​based on the use requirements of the photodiode, and are not limited to the above value range.

[0098] On this basis, the area of ​​the P ohm contact block is much smaller than the area of ​​the general P ohm contact ring. Accordingly, only a smaller P window needs to be etched at the location of the P ohm contact block. Thus, more area is released to the photosensitive surface of the photodiode chip, improving the light coupling efficiency of the photodiode chip. At the same time, when the area of ​​the photosensitive surface is constant, the chip size of the photodiode chip can be reduced in reverse, so that more chips can be produced from the same size of epitaxial wafer, thereby reducing chip costs and improving the market competitiveness of products.

[0099] In summary, the technical solution of the present application covers the entire surface area of ​​the photodiode chip except the photosensitive surface area with a metal reflective film. Furthermore, the side walls around the chip can also be covered with a metal reflective film at the same time, and the minority carriers caused by short-wavelength visible light are isolated through the groove window or through the groove window and the chip side wall. A @1310nm AR anti-reflection film is also grown in the photosensitive surface area to control the reflectivity within 2.5%. A high response of more than 0.9A / W can be obtained for 1310nm wavelength visible light, and visible light with a wavelength of 300-755nm can be effectively isolated.

[0100] In addition, in one embodiment, the present application provides a device for preparing a photodiode chip, which can be a server, including a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the photodiode chip preparation device is used to provide computing and control capabilities. The memory of the photodiode chip preparation device includes non-volatile and / or volatile storage media and internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The network interface of the photodiode chip preparation device is used to communicate with an external client through a network connection. When the computer program is executed by the processor, the preparation method described in any of the above embodiments can be implemented.

[0101] In one embodiment, the present application also provides a device for preparing a photodiode chip, which can be a client, including a processor, a memory, a network interface, a display screen, and an input device connected through a system bus. Among them, the processor of the device for preparing the photodiode chip is used to provide computing and control capabilities. The memory of the device for preparing the photodiode chip includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the device for preparing the photodiode chip is used to communicate with an external server through a network connection. When the computer program is executed by the processor, the preparation method described in any of the above embodiments can be implemented.

[0102] In addition, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to control a photodiode chip manufacturing device to perform the following steps:

[0103] Etching a P ohmic contact region in the P ohmic contact layer;

[0104] growing a diffusion barrier film on the current surface;

[0105] A diffusion hole is formed in the diffusion window layer, and the first region where the diffusion hole is located accommodates the location of the P ohmic contact region;

[0106] Performing Zn diffusion treatment to form a highly doped P+-INP diffusion zone in the first region, wherein the diffusion zone is distributed from the diffusion window layer to the intrinsic absorption layer;

[0107] Etching the current epitaxial wafer to form a groove window, wherein the second region where the groove window is located is located outside the first region and surrounds the first region, the groove window penetrates the P ohmic contact layer, the diffusion window layer, the intrinsic absorption layer and the N-type material contact layer, and the bottom of the groove window is recessed into the InP substrate layer;

[0108] growing an anti-reflection film on the current surface;

[0109] Etching the P ohmic contact area to obtain a P window, and leading out a P electrode at the P window;

[0110] Growing a metal reflective film on the groove window and the edge extension area of ​​the groove window;

[0111] An N electrode is fabricated on the back side of the InP substrate layer to form a photodiode chip.

[0112] It should be noted that the above functions or steps that can be implemented by the computer-readable storage medium or computer device can refer to the relevant description in the aforementioned method embodiment. In order to avoid repetition, they will not be described one by one here.

[0113] The above describes in detail the technical solution of the present application in conjunction with the accompanying drawings. The technical solution of the present application can effectively reduce the influence of low-wavelength visible light on the operation of the photodiode chip by adding a groove window and a metal reflective film, improve the responsiveness of incident light with a wavelength of 1310nm, and make the quantum efficiency reach more than 98%, and reduce the responsiveness of incident light with a wavelength of 300-755nm, so that the quantum efficiency is less than 2%, so as to meet the special needs of light detection sensor chips. As a result, the reliability of the photodiode chip is improved, and the overall performance of the circuit and even the product in which the photodiode chip is located is improved.

[0114] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0115] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0116] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A method for preparing a photodiode chip, characterized in that: The method is used to manufacture an epitaxial wafer into a photodiode chip, wherein the epitaxial wafer includes a P ohmic contact layer, a diffusion window layer, an intrinsic absorption layer, an N-type material contact layer and an InP substrate layer in order from the surface layer to the bottom layer, and the method includes: Etching a P ohmic contact region in the P ohmic contact layer; growing a diffusion barrier film on the current surface; A diffusion hole is formed in the diffusion window layer, and the first region where the diffusion hole is located accommodates the location of the P ohmic contact region; Performing Zn diffusion treatment to form a highly doped P+-INP diffusion zone in the first region, wherein the diffusion zone is distributed from the diffusion window layer to the intrinsic absorption layer; Etching the current epitaxial wafer to form a groove window, wherein the second region where the groove window is located is located outside the first region and surrounds the first region, the groove window penetrates the P ohmic contact layer, the diffusion window layer, the intrinsic absorption layer and the N-type material contact layer, and the groove window is located in the InP substrate layer; growing an anti-reflection film on the current surface; Etching the P ohmic contact area to obtain a P window, and leading out a P electrode at the P window; Growing a metal reflective film on the groove window and the edge extension area of ​​the groove window; An N electrode is fabricated on the back side of the InP substrate layer to form a photodiode chip.

2. The method according to claim 1, characterized in that Also includes: The metal reflective film is grown on at least one side wall of the epitaxial wafer.

3. The method according to claim 1 or 2, characterized in that: The metal reflective film is a composite material of Ti, Pt and Au. The thickness of Ti in the metal reflective film is greater than or equal to 30 nm and less than or equal to 100 nm; The thickness of Pt in the metal reflective film is greater than or equal to 30 nm and less than or equal to 100 nm; The thickness of Au in the metal reflective film is greater than or equal to 3000 nm and less than or equal to 15000 nm.

4. The method according to claim 1, characterized in that: Before forming the N electrode on the back side of the InP substrate layer, the method further comprises: Performing a thickness reduction process on the InP substrate layer; In the process of manufacturing the N electrode on the back side of the InP substrate layer, the process also includes: The composite material of Ti, Pt and Au is sputtered or evaporated on the back of the thinned InP substrate layer to form an N electrode layer having the composite material of Ti, Pt and Au.

5. The method according to claim 4, characterized in that The thickness of Ti in the N electrode layer is greater than or equal to 50 nm and less than or equal to 100 nm; The thickness of Pt in the N-electrode layer is greater than or equal to 50 nm and less than or equal to 100 nm; The thickness of Au in the N-electrode layer is greater than or equal to 100 nm and less than or equal to 200 nm.

6. The method according to claim 4, characterized in that The thickness of the epitaxial wafer after the thickness reduction is greater than or equal to 110 μm and less than or equal to 160 μm.

7. The method according to claim 1, characterized in that The P ohmic contact area is a P ohmic contact ring, The first region where the diffusion hole is located accommodates the P ohmic contact ring; The groove window is a closed circular groove or a closed polygonal groove surrounding the first area.

8. The method according to claim 1, characterized in that The P ohmic contact area is a P ohmic contact block, The first area where the diffusion hole is located accommodates the P ohmic contact block; While the P ohmic contact region is being etched, the method further comprises: Etching a portion of the diffusion area adjacent to the P ohmic contact block, wherein the entire area subjected to the etching process is a P window, and the shape of the P window is a block; The third area where the P electrode is located covers the location of the P window, and the third area is non-circumferentially adjacent to the fourth area covered by the photosensitive surface of the photodiode chip; The groove window is an unclosed arc groove or an unclosed polygon groove surrounding the first area, and the unclosed position of the unclosed arc or the unclosed polygon is covered by the third area.

9. A photodiode chip, characterized in that: The photodiode chip is prepared by the method for preparing a photodiode chip according to any one of claims 1 to 8, wherein the photodiode chip comprises: A diffusion window layer is provided with a diffusion hole, wherein a first region where the diffusion hole is located has a diffusion region with a high doping P+-INP; A groove window is located in a second area outside the first area, surrounding the first area, wherein the groove window penetrates the P ohmic contact layer, the diffusion window layer, the intrinsic absorption layer and the N-type material contact layer, and the bottom of the groove window is a surface groove of the InP substrate layer; A diffusion barrier film covering the area outside the diffusion hole and the groove window in the surface layer of the diffusion window layer; An intrinsic absorption layer is located in a lower layer adjacent to the diffusion window layer, and the diffusion region diffuses to an upper region of the intrinsic absorption layer; An N-type material contact layer, located in a lower layer adjacent to the intrinsic absorption layer; An InP substrate layer, located in a lower layer adjacent to the N-type material contact layer; P ohmic contact region, located above the first region; an anti-reflection film covering the diffusion barrier film, a position other than the P-ohmic contact region in the first region, and a surface of the groove window; A P electrode connected to the P ohmic contact region through a P window; A metal reflective film, an anti-reflective film covering the surface of the groove window, and an anti-reflective film covering the edge extension area of ​​the groove window; The N electrode is arranged on the back side of the InP substrate layer.

10. A device for preparing a photodiode chip, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

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