Apparatus and method for read data preprocessing using neural network

Abstract

A memory includes: a read / write amplifier configured to retrieve read data from a memory array; and a neural network-based preprocessing circuit configured to receive a read data signal according to the read data. A neural network of the pre-processing circuit is configured to pre-process the read data signal based on characteristics of a read data transmission path to provide a modified read data signal. The memory further includes an output driver configured to transmit the modified read data signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of filing U.S. Provisional Application No. 63 / 501,072, filed May 9, 2023. This application is incorporated herein by reference in its entirety for all purposes. Background Art

[0003] Digital systems such as memory devices continue to operate at higher and higher speeds. Due to channel loss or filtering by capacitance as frequency increases, various signal lines carrying digital signals may exhibit low pass filter (LPF) characteristics. In addition, process and temperature variations may also affect the speed at which the circuit system can operate. Therefore, the maximum data rate supported by the channel becomes limited. Existing solutions to compensate for the channel data rate limitations may include various equalization techniques, which include added complex circuit systems that may not effectively increase the channel data rate in many cases. A conventional method for equalization includes modifying the signal line to reduce the capacitance of the signal line, or modifying the signal to reduce the effect of capacitance on it, for example, by inserting a repeater or inverter on the signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a schematic diagram of a semiconductor device according to various embodiments.

[0005] Figure 2 A schematic block diagram illustrates a system for pre-processing a read data signal in a memory device according to various embodiments.

[0006] Figure 3 A schematic block diagram illustrating a neural network based system for pre-processing a read data signal in a memory device according to various embodiments.

[0007] Figure 4 is a block diagram illustrating a processing unit arranged in a computing system according to various embodiments.

[0008] Figure 5 is a flow chart illustrating a method for training a neural network to pre-process a read data signal at a memory according to various embodiments.

[0009] Figure 6 is a flow chart illustrating a method for pre-processing a read data signal at a memory using a neural network according to various embodiments. DETAILED DESCRIPTION

[0010] The present disclosure describes examples of apparatus and methods for preprocessing a read data signal used to transmit read data during a read operation using a machine learning model trained based on channel characteristics of a semiconductor device. In some examples, the machine learning model may include a neural network. Preprocessing may include modifying the shape of the transmission signal so that the properties of the signal line (e.g., capacitance, circuit switching speed, etc.) cause the transmission signal to be received and stored at the memory cell array in a desired shape. Preprocessing may include pre-emphasis or de-emphasis of the signal shape. Pre-emphasis refers to increasing the amplitude of a digital signal by providing an overshoot filtered by the capacitive effect of the signal line at each bit transition. De-emphasis refers to a complementary process of reducing the amplitude of a digital signal, wherein a full rail-to-rail swing between a high power supply voltage (VDDQ, VDD) and a low power supply voltage (VSSQ, VSS) is provided at each bit transition.

[0011] One conventional way to implement de-emphasis / pre-emphasis is to use delay chains to sequentially turn on or off branches of the pull-up and / or pull-down circuits of a voltage driver. This causes dynamic changes in the driver output impedance, which can degrade signal integrity. In addition, de-emphasis / pre-emphasis is typically asymmetric, emphasizing the pull-up from VSSQ or the pull-down from VDDQ. Using a trained machine learning model (e.g., such as a neural network) can mitigate the negative effects of these conventional approaches.

[0012] The following detailed description describes several exemplary embodiments in more detail to enable those skilled in the art to practice such embodiments. The described examples are provided for illustrative purposes only and are not intended to limit the scope of the present invention. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art that other embodiments of the present invention may be practiced without some of these specific details.

[0013] Figure 1 1 is a schematic diagram of a semiconductor device 100 according to various embodiments. The semiconductor device 100 includes a memory die. The memory die may include an address / command input circuit 105, an address decoder 110, a command decoder 115, a clock input circuit 120, an internal clock generator 130, a timing generator 135, a row decoder 140, a column decoder 145, a memory array 150, a read / write amplifier 155, a pre-processing control circuit 125, an I / O circuit 160, a ZQ calibration circuit 165, and a voltage generator 170.

[0014] In some embodiments, the semiconductor device 100 may include, but is not limited to, a DRAM device such as a DDR3 or DDR4 device integrated into a single semiconductor chip. The die may be mounted on an external substrate, such as a memory module substrate, a motherboard, etc. The semiconductor device 100 may further include a memory array 150. The memory array 150 includes a plurality of memory banks, each memory bank including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by a row decoder 140, and the selection of the bit lines BL is performed by a column decoder 145. The sense amplifier (SA) is positioned for its corresponding bit line BL and connected to at least one corresponding local I / O line, which in turn is coupled to a corresponding one of at least two main I / O line pairs via a transfer gate (TG) acting as a switch.

[0015] The semiconductor device 100 may employ a plurality of external terminals including address and command terminals coupled to a command / address bus (C / A), clock terminals CK and / CK, data terminals DQ, DQS and DM, power terminals VDD, VSS, VDDQ and VSSQ, and a ZQ calibration terminal (ZQ).

[0016] The address signal and the memory bank address signal can be supplied from the outside to the command / address terminal. The address signal and the memory bank address signal supplied to the address terminal are transmitted to the address decoder 110 via the address / command input circuit 105. The address decoder 110 receives the address signal, and supplies the decoded row address signal to the row decoder 140 and the decoded column address signal to the column decoder 145. The address decoder 110 also receives the memory bank address signal, and supplies the memory bank address signal to the row decoder 140 and the column decoder 145.

[0017] The command / address terminal may be further supplied with a command signal from the outside, for example, from a memory controller. The command signal may be provided to a command decoder 115 via the C / A bus via the address / command input circuit 105. The command decoder 115 decodes the command signal to generate various internal commands including a row command signal for selecting a word line and a column command signal for selecting a bit line, for example, a read command or a write command.

[0018] Therefore, when a read command is issued and the row address and column address are supplied in time with the read command, read data is read from the memory cell specified by these row address and column address in the memory array 150. The read data DQ is output to the outside from the data terminals DQ, DQS, and DM via the read / write amplifier 155 and the input / output circuit 160. Similarly, when a read command is issued and the row address and column address are supplied in time with this command, and then the read data is supplied to the data terminals DQ, DQS, and DM, the read data is received by the data receiver in the input / output circuit 160, and is supplied to the memory array 150 via the input / output circuit 160 and the read / write amplifier 155 and is written in the memory cell specified by the row address and column address.

[0019] When the read / write amplifier 155 outputs the read data DQ from the memory array 150, the data has not yet undergone preprocessing. Therefore, the read data may be provided by the read / write amplifier 155 to the preprocessing control circuit 125, and the preprocessing control circuit 125 may then preprocess the read data DQ signal. The preprocessing may be controlled according to a control signal including a preprocessing control signal. When the read data DQ is received at the read / write amplifier 155, the read data DQ will generally be passed to the input / output circuit 160 for external transmission via a data bus. However, in order to increase the channel data rate for transmitting the read data, the read data signal may be processed by a machine learning model (e.g., a neural network) of the preprocessing control circuit 125 trained based on the channel characteristics of the semiconductor device to modify the shape of the read data signal so that the properties of the read data channel (e.g., capacitance, circuit switching speed, etc.) cause the transmitted read data signal to be received at the target device in a desired shape. The read data channel may include an output driver of the input / output circuit 160 and / or a data bus transmission channel. Pre-processing may include pre-emphasis or de-emphasis for signal shaping.

[0020] A machine learning model implemented using a neural network may be trained to set coefficients applied to the read data signal to compensate for the channel characteristics of the read data channel and the corresponding circuit system. For example, using the following equation:

[0021] y i (k) = x i (k)+f i (k)

[0022] where y i (k) is the actual voltage at the i-th cell and its k-level (total K-level), x i (k) is the target voltage at the i-th cell and its k-level, and f i (k) is the shifted voltage caused by programming noise, inter-cell interference and leakage. In order to train the neural network, the codeword xi (k)(i=1,,....L) are programmed, and then the actual voltage y can be measured i (k). The neural network may be trained during training by adjusting the coefficients used by the neural network to modify the write data signal using the preprocessing control signal. During training, the input of the neural network may be y i (k)(KxL), and the target output can be x i (k). The actual voltage y i (k) and the target output x i (k) is compared. During training, the input of the neural network can be used to determine the fusion difference estimate f i (k)y i (k)(KxL)(e.g., the target input x of the neural network i (k) minus the output equals f i (k)). The coefficients can be modified until the target output x is met. i (k) and the fused difference and coefficients may be stored in the coefficient data memory. During a read operation, the neural network of the pre-processing control circuit 125 may receive a read data signal x from the memory array 150. i (k), and the neural network can use the stored coefficients to modify x i (k) to provide a new programming voltage (eg, it should be x i (k)-f i (k), or equal to the input of the neural network minus f i (k)). Therefore, due to the channel characteristics after the read data signal is transmitted to the driver of the input / output circuit 160, the resulting voltage of the read data signal is x i (k).

[0023] Turning to explain the external terminals included in the semiconductor device 100, the clock terminals CK and / CK are respectively supplied with an external clock signal and a complementary external clock signal. The external clock signal (including the complementary external clock signal) can be supplied to the clock input circuit 120. The clock input circuit 120 can receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK is supplied to the internal clock generator 130, and thus a phase-controlled internal clock signal LCLK is generated based on the received internal clock signal ICLK and the clock enable signal CKE from the address / command input circuit 105. Although not limited to this, the DLL circuit can be used as the internal clock generator 130. The phase-controlled internal clock signal LCLK is supplied to the input / output circuit 160 and used as a timing signal for determining the output timing of the read data. The internal clock signal ICLK is also supplied to the timing generator 135, and thus various internal clock signals can be generated.

[0024] The power supply terminals are supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 generates various internal potentials VPP, VOD, VARY, VPERI, etc. and a reference potential ZQVREF based on the power supply potentials VDD and VSS. The internal potential VPP is mainly used in the row decoder 140, the internal potentials VOD and VARY are mainly used in the sense amplifier included in the memory array 150, and the internal potential VPERI is used in many other circuit blocks. The reference potential ZQVREF is used in the ZQ calibration circuit 165.

[0025] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. These power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 160. The power supply potentials VDDQ and VSSQ are the same potentials as the power supply potentials VDD and VSS, respectively. However, the dedicated power supply potentials VDDQ and VSSQ are used for the input / output circuit 160 so that the power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0026] The calibration terminal ZQ is connected to the ZQ calibration circuit 165. When activated by the ZQ calibration command signal (ZQ_com), the ZQ calibration circuit 165 performs a calibration operation with reference to the impedance of RZQ and the reference potential ZQVREF. The impedance code ZQCODE obtained by the calibration operation is supplied to the input / output circuit 160, and thus specifies the impedance of the output buffer (not shown) included in the input / output circuit 160.

[0027] Figure 2 A schematic block diagram of a system 200 for preprocessing a read data signal in a memory device according to various embodiments is illustrated. The system 200 may include a memory controller 205 coupled to a system memory 215. The memory controller 205 may include a preprocessing control logic 210. The system memory 215 may include a preprocessing control circuit 220 configured to receive a preprocessing control signal from the preprocessing control logic 210. The preprocessing control circuit 220 may be further configured to receive data (DQ) from a memory array 230. The DQ may include digital data that will be equalized by the preprocessing control circuit 220 and then output externally to, for example, the memory controller 205 via an output driver 225. The preprocessing control circuit 220 may be coupled to the output driver 225. In some embodiments, the output driver 225 may include, but is not limited to, a push-pull voltage driver. The output driver 225 may then be configured to output the equalized digital signal to the memory controller 205.

[0028] In some examples, the pre-processing time used to modify the shape of the read data DQ may be controlled via external control signals, such as those generated by the pre-processing control logic 210. This may include adjustments to the pre-processing time, as well as pre-processing amplitude adjustment amounts. The memory controller 205 may include an external controller, such as a processor, to control the pre-processing operations.

[0029] In some embodiments, the memory controller 205 may optionally include a training circuit 235. The training circuit 235 may be configured to train a machine learning model (e.g., a neural network) of the pre-processing control circuit 220 based on, but not limited to, data eye optimization, reference voltage (amplitude) calibration, and read data training to pre-process the read data signal before providing it to the output driver 225. In some embodiments, the training circuit 235 may also be optionally connected to the pre-processing control logic 210. Thus, in some embodiments, the pre-processing control signal may be adjusted to adjust the coefficients of the machine learning model based on input from the training circuit 235, for example, in data eye optimization. In further embodiments, data eye optimization may include first identifying a pre-processing amplitude adjustment direction (e.g., de-emphasis or pre-emphasis) and providing the magnitude of the best data eye for a given channel (e.g., but not limited to, a data path for the data output of the output driver 225). To perform the training, the cells in the codeword may be programmed and then the actual voltage may be measured. During training, the input to the machine learning model may be the expected output and the target output may be the read data signal. The training circuit 235 may compare the actual voltage to the target output to determine a fused difference estimate (e.g., the target input minus the output of the machine learning model). The training circuit 235 may modify the coefficients of the neural network until the target output is met, and the fused difference and coefficients may be stored in a coefficient data memory.

[0030] Figure 3 A schematic block diagram illustrating a system 300 for preprocessing a read data signal in a memory device according to various embodiments. The system 300 may include a preprocessing control circuit 310 based on a machine learning model, a read / write amplifier 320, and a memory array 330. The memory array 330 may be configured to provide read data to the read / write amplifier 320, which in turn may provide the read data signal to the preprocessing control circuit 310 based on the machine learning model. The machine learning model (e.g., a neural network) of the preprocessing control circuit 310 may be configured to preprocess the read data signal using stored coefficients before providing the read data signal to an output driver (not shown).

[0031] In some examples, the pre-processing time used to modify the shape of the read data DQ can be controlled via an external control signal. This can include adjustments to the pre-processing time, as well as pre-processing amplitude adjustments by changing coefficients applied to the read data signal by the machine learning model.

[0032] Figure 4 4 is a block diagram illustrating a processing unit 405 arranged in a computing system 400 according to various embodiments. The system 400 may include Figure 1 The semiconductor device 100, Figure 2 System 200, Figure 3 The processing unit 405 may be configured to implement a neural network to implement a machine learning model, such as a neural network trained based on channel characteristics of a memory device to pre-process a read data signal.

[0033] The processing unit 405 may receive input data (e.g., X_1 / 2 / N(n)) 410a-c from a computing system, such as a host computing device. In some examples, the input data 410a-c may be read data associated with a read operation at a memory. The processing unit 405 may include multiplication units / accumulation units 412a-c, 416a-c and memory lookup units 414a-c, 418a-c, which, when mixed with coefficient data retrieved from the memory 430, may generate output data (e.g., Y_1 / 2 / N(n)) 420a-c. In some examples, the output data 420a-c may be used as input data for another processing stage or as output data, such as one or more channel characteristics associated with a channel within a memory. In other words, processing unit 405 may include one or more stages of a neural network such that processing unit 405 receives input data 410a-c including data associated with a read operation and generates output data 420a-c including one or more channels through which the read operations 410a-c are performed.

[0034] When one or more processing units 405 are implemented, a computer-readable medium at an electronic device may execute corresponding control instructions to perform operations through executable pre-processing control instructions 415 within the processing unit 405. For example, the control instructions provide instructions to the processing unit 405, which, when executed by the electronic device, cause the processing unit 405 to configure the multiplication units 412a-c to multiply the input data 410a-c with the coefficient data, and to configure the accumulation units 416a-c to accumulate the processing results to generate the output data 420a-c.

[0035] The multiplication units / accumulation units 412a-c, 416a-c multiply two operands from the input data 410a-c to generate a multiplication process result, which is accumulated by the accumulation unit portion of the multiplication units / accumulation units 412a-c, 416a-c. The multiplication process results are added by the multiplication units / accumulation units 412a-c, 416a-c to update the process results stored in the accumulation unit portion, thereby accumulating the multiplication process results. For example, the multiplication units / accumulation units 412a-c, 416a-c can perform a multiply-accumulate operation such that two operands M and N are multiplied and then added to P to generate a new version of P, which is stored in its corresponding multiplication unit / accumulation unit. The memory lookup units 414a-c, 418a-c retrieve coefficient data stored in the memory 430. For example, the memory lookup unit can be a table lookup to retrieve a specific coefficient. The output of the memory lookup unit 414a-c, 418a-c is provided to the multiplication unit / accumulation unit 412a-c, 416a-c, which can be used as a multiplication operand in the multiplication unit portion of the multiplication unit / accumulation unit 412a-c, 416a-c. Using such a circuit system arrangement, output data (e.g., Y_1 / 2 / N(n)) 420a-c can be generated from input data (e.g., X_1 / 2 / N(n)) 410a-c.

[0036] In some examples, coefficient data, for example from memory 430 , may be mixed with input data X_1 / 2 / N(n) 410 a - c to generate output data Y_1 / 2 / N(n) 420 a - c .

[0037] As described above, the memory lookup units 414a-c, 418a-c retrieve coefficients to mix with the input data. Thus, the input data may be manipulated with the multiply / accumulate unit to provide output data by using a set of coefficients stored in memory associated with the characteristics of the read data channel at the memory. The resulting mapped data may be manipulated by additional multiply / accumulate units using additional sets of coefficients stored in memory associated with the characteristics of the channel. The set of coefficients multiplied at each stage of the processing unit 405 may represent or provide an estimate of the processing of the input data in specially designed hardware (e.g., an FPGA).

[0038] Furthermore, it can be shown that in some examples, system 400 can approximate any nonlinear mapping with arbitrarily small errors, and the mapping of system 400 is determined by coefficients. For example, if such coefficient data is specified, any mapping and processing between input data X_1 / 2 / N(n) 410a-c and output data Y_1 / 2 / N(n) 420a-c can be implemented by system 400. Such relationships as derived from the circuit system arrangement depicted in system 400 can be used to train entities of computing system 400 to generate coefficient data. For example, entities of computing system 400 can compare input data with output data to generate coefficient data.

[0039] In an example of system 400, processing unit 405 mixes coefficient data with input data X_1 / 2 / N(n) 410a-c using memory lookup units 414a-c, 418a-c. In some examples, memory lookup units 414a-c, 418a-c may be referred to as table lookup units. Coefficient data may be associated with a mapping relationship of input data X_1 / 2 / N(n) 410a-c to output data Y_1 / 2 / N(n) 420a-c. For example, coefficient data may represent a nonlinear mapping of input data X_1 / 2 / N(n) 410a-c to output data Y_1 / 2 / N(n) 420a-c. In some examples, the nonlinear mapping of coefficient data may represent a Gaussian function, a piecewise linear function, a sigmoid function, a thin plate spline function, a multiquadratic function, a cubic approximation, an inverse multiquadratic function, or a combination thereof. In some examples, some or all of the memory lookup units 414a-c, 418a-c may be deactivated. For example, one or more of the memory lookup units 414a-c, 418a-c may operate as a gain unit with unity gain. In this case, instructions (e.g., executable instructions 415) may be executed to facilitate selecting a unity gain processing mode for some or all of the memory lookup units 414a-c, 418a-c.

[0040] Each of the multiplication units / accumulation units 412a-c, 416a-c may include multiple multipliers, multiple accumulation units, or / and / or multiple adders. Any of the multiplication units / accumulation units 412a-c, 416a-c may be implemented using an arithmetic logic unit (ALU). In some examples, any of the multiplication units / accumulation units 412a-c, 416a-c may include one multiplier and one adder, each of which performs multiple multiplications and multiple additions, respectively. The input-output relationship of the multiplication / accumulation units 412, 416 may be expressed as:

[0041]

[0042] where "I" represents the number of multiplications performed in the unit, C iare coefficients accessible from a memory such as memory 430, and B in (i) represents a factor from the input data X_1 / 2 / N(n) 410a-c or from the output of the multiplication unit / accumulation unit 412a-c, 416a-c. In the example, the output B of the set of multiplication units / accumulation units out Equal to coefficient data C i Multiply by the output B of another set of multiplication / accumulation units in The sum of (i). in (i) It can also be input data so that the output B of the set of multiplication units / accumulation units is out Equal to coefficient data C i Multiplies the sum of the input data.

[0043] Figure 5 is a flow chart illustrating a method 500 for training a machine learning model to pre-process a read data signal at a memory according to various embodiments. The method 500 may be performed, for example, using Figure 1 At least a portion of the semiconductor device 100 (eg, the pre-processing control circuit 125) and / or Figure 2 at least a portion of the system 200 (e.g., the training circuit 235, the pre-processing control circuit 220, and / or the pre-processing control logic 210), Figure 3 A preprocessing circuit 310 based on a machine learning model, and / or Figure 4 The processing unit 405 is executed.

[0044] The method 500 includes generating, at 502 , a read data training data set based on characteristics of a read data transfer channel of the memory, wherein the training data set includes a correlation between read data for the channel and the characteristics of the read data transfer channel.

[0045] The method 500 further includes training a machine learning model of a read data preprocessing circuit of the memory to determine channel characteristics of a read data transmission channel based on the read data for the read data transmission channel using the read data training data set at 504. In some examples, the read data training data set is associated with a codeword of the memory. In some examples, the method 500 further includes applying the trained machine learning model to determine characteristics of the read data transmission channel based on the read data, and modifying one or more coefficient values ​​of the machine learning model associated with the read data channel based on the determined channel characteristics.

[0046] In some examples, method 500 further includes generating a write data training dataset using the read data, testing the trained neural network using the read data training dataset, and retraining the trained machine learning model using a different training dataset when the trained machine learning model does not exceed a threshold accuracy level.

[0047] Figure 6 6 is a flow chart illustrating a method 600 for preprocessing a read data signal at a memory using a machine learning model according to various embodiments. The method 500 may be performed, for example, using Figure 1 At least a portion of the semiconductor device 100 (eg, the pre-processing control circuit 125) and / or Figure 2 at least a portion of the system 200 (e.g., the pre-processing control circuit 220 and / or the pre-processing control logic 210), Figure 3 A preprocessing circuit 310 based on a machine learning model, and / or Figure 4 The processing unit 405 is executed. In some examples, the machine learning model may include a neural network.

[0048] The method 600 includes, at 602 , retrieving read data from a memory array of a memory.

[0049] The method 600 further includes preprocessing a read data signal corresponding to the read data based on a characteristic of the read data transmission path via a machine learning model of a preprocessing circuit of the memory to provide a modified read data signal at 604. In some examples, the method 600 further includes modifying the read data signal based on one or more coefficient values ​​selected based on the characteristic of the read data transmission path. In some examples, the method 600 may further include determining the one or more coefficient values ​​by writing test write data to the memory array and reading back the test write data during training of the machine learning model. In some examples, the method 600 further includes increasing the amplitude of the read data signal via the machine learning model and causing the amplitude of the read data signal to provide a modified read data signal. In some examples, the method 600 further includes reducing the amplitude of the read data signal via the machine learning model to provide a modified read data signal. In some examples, the characteristic of the read data transmission path includes a capacitance of a signal line of the read data transmission path, a process variation of a circuit component of the memory array, or any combination thereof.

[0050] The method 600 further includes transmitting the read data based on the modified read data signal via an output driver of the memory at 606 .

[0051] Although certain features and aspects have been described with respect to exemplary embodiments, it will be appreciated by those skilled in the art that various modifications and additions may be made to the embodiments discussed without departing from the scope of the invention. Although the above-described embodiments mention specific features, the scope of the invention also includes embodiments with different combinations of features and embodiments that do not include all of the above-described features. For example, the methods and processes described herein may be implemented using hardware components, software components, and / or any combination thereof. In addition, although the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may be implemented in any suitable hardware, firmware, and / or software configuration. Similarly, although certain functionality is attributed to certain system components, unless the context otherwise specifies, this functionality may be distributed among various other system components according to several embodiments.

[0052] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, individual procedures may be reordered, added, and / or omitted according to various embodiments. The processes described with respect to a method or process may be incorporated into other described methods or processes; similarly, hardware components described according to a specific structural architecture and / or with respect to a system may be organized and / or incorporated into other described systems in place of the structural architecture. Therefore, although various embodiments with or without certain features are described for ease of description, the various components and / or features described herein with respect to specific embodiments may be combined, replaced, added, and / or subtracted among other described embodiments. Therefore, although several exemplary embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A device comprising: a read / write amplifier configured to retrieve read data from the memory array; a pre-processing circuit configured to receive a read data signal based on the read data, wherein a machine learning model of the pre-processing circuit trained based on characteristics of a read data transmission path is configured to pre-process the read data signal based on the characteristics of the read data transmission path to provide a modified read data signal; as well as An output driver is configured to transmit the modified read data signal.

2. The apparatus of claim 1 , wherein the machine learning model comprises a neural network configured to modify the read data signal based on one or more coefficient values ​​selected based on the characteristics of the read data transmission path.

3. The apparatus of claim 2, wherein the one or more coefficient values ​​are determined during training of the neural network by writing test write data to the memory array and reading the test write data back out.

4. The apparatus of claim 2, wherein the neural network comprises a multiplication and accumulation unit configured to combine the read data signal with the one or more coefficient values.

5. The apparatus of claim 1, wherein the machine learning model is configured to cause an amplitude of the read data signal to be adjusted to provide the modified read data signal.

6. The apparatus of claim 1, wherein the machine learning model is configured to increase an amplitude of the read data signal to provide the modified read data signal.

7. The apparatus of claim 1, wherein the machine learning model is configured to reduce an amplitude of the read data signal to provide the modified read data signal.

8. The apparatus of claim 1, wherein the characteristic of the read data transfer path comprises a capacitance of a signal line of the read data transfer path.

9. The apparatus of claim 1, wherein the characteristics of the read data path include process variations of circuit components of the output driver.

10. A method comprising: generating a read data training data set based on characteristics of a read data transfer channel of a memory, wherein the training data set comprises a correlation between the read data for the channel and the characteristics of the read data transfer channel; as well as The read data training data set is used to train a machine learning model of a read data pre-processing circuit of a memory to determine a channel characteristic of the read data transfer channel based on the read data for the read data transfer channel. The method of claim 10 , wherein the read data training data set is associated with a codeword of the memory.

12. The method according to claim 10, further comprising: applying the trained machine learning model to determine the characteristics of the read data transmission channel based on the read data; as well as One or more coefficient values ​​of the machine learning model associated with the read data channel are modified based on the determined channel characteristics.

13. The method according to claim 10, further comprising: Using the read data to generate a read data training data set; Testing the trained machine learning model using the read data training dataset; as well as When the trained neural network does not exceed a threshold accuracy level, the trained machine learning model is retrained using a different training data set.

14. A method comprising: Retrieving read data from a memory array of a memory; preprocessing a read data signal corresponding to the read data based on the characteristics of the read data transfer path to provide a modified read data signal via a machine learning model of a preprocessing circuit of the memory trained based on the characteristics of the read data transfer path; as well as The read data is transmitted via an output driver of the memory based on the modified read data signal.

15. The method of claim 14, further comprising modifying the read data signal based on one or more coefficient values ​​selected based on the characteristics of the read data transfer path.

16. The method of claim 15, further comprising determining the one or more coefficient values ​​during training of the machine learning model by writing test write data to the memory array and reading back the test write data.

17. The method of claim 14, further comprising increasing an amplitude of the read data signal via the machine learning model and causing the amplitude of the read data signal to provide the modified read data signal.

18. The method of claim 14, further comprising reducing an amplitude of the read data signal via the machine learning model to provide the modified read data signal.

19. The method of claim 14, wherein the characteristic of the read data transfer path comprises a capacitance of a signal line of the read data transfer path.

20. The method of claim 14, wherein the characteristics of the read data transfer path include process variations of circuit components of the memory array.

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