Semiconductor device and power conversion device using same

Abstract

The invention provides a semiconductor device capable of suppressing a location where an avalanche is generated by forming an electric field concentration layer (7) and suppressing the flow of carriers caused by the avalanche to a region where a switching element main body is present. The first body layer (5a) and the second body layer (5b) are separated from each other by generating an avalanche in a certain region of the second body layer (5b) by means of the electric field concentration layer (7) and having a floating layer (8) between the first body layer (5a) in which the switching element body is present and the second body layer (5b) in which the avalanche is generated. The flow of carriers caused by avalanche to the first body layer (5a) in which the switching element body exists can be suppressed.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a power conversion device using the same. Background Art

[0002] As power modules become more densely populated, switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are required to operate at higher current densities and withstand wider RBSOAs (Reverse Bias Safe Operating Areas) than ever before.

[0003] For example, in Patent Document 1 Figure 1 And in paragraph 0029, it is recorded that "by forming an n electric field concentration layer 115 having a higher carrier concentration than the n barrier layer 114 in the second region, current concentration is generated in the second region where the parasitic thyristor does not exist, and the current flowing through the first region where the parasitic thyristor exists is reduced" and "the second region and the first region are separated by a groove, so that latching of the first region due to current concentration in the second region can be suppressed", and in paragraph 0024 of Patent Document 1, it is recorded that "by dispersing the current at the time of shutdown, the heat generated by latching is reduced, and an IGBT with a wider RBSOA can be provided."

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2016-184712 Summary of the invention

[0007] Problems to be solved by the invention

[0008] However, in Patent Document 1, although the first region and the second region are separated by the trench, they are adjacent to each other. Therefore, part of the avalanche current generated in the n electric field concentration layer 115 flows to the first region (region where the switching element main body exists) where the parasitic thyristor exists, and the parasitic thyristor may latch up, which has a problem that latch-up cannot be completely prevented.

[0009] In addition, in the case of MOSFET instead of IGBT, the p collector layer on the back side becomes an n+ layer, so there is no pnpn parasitic thyristor in the area where the switching element body exists, but there is an npn parasitic transistor in the area where the switching element body exists. Therefore, when an avalanche current is generated, there is a problem that the npn parasitic transistor is turned on.

[0010] The problem to be solved by the present invention is to provide a semiconductor device and a power conversion device using the same that can suppress the location where avalanche occurs by forming an electric field concentration layer and suppress the flow of carriers caused by avalanche to the region where a switching element main body exists.

[0011] Solutions to Solve Problems

[0012] In order to solve the above-mentioned problems, the first semiconductor device of the present invention, for example, has: a drift layer of a first conductivity type; a first main layer of a second conductivity type, which is formed on the surface of the above-mentioned drift layer; a surface-side electrode layer of the first conductivity type, which is formed on the surface of the above-mentioned first main layer; a surface-side main electrode, which is connected to the above-mentioned first main layer and the above-mentioned surface-side electrode layer; a first trench, which is formed in contact with the above-mentioned first main layer and the above-mentioned surface-side electrode layer; a gate electrode, which is formed inside the above-mentioned first trench; and a gate insulating film, which is formed inside the above-mentioned first trench between the above-mentioned first main layer and the above-mentioned gate electrode, and between the above-mentioned surface-side electrode layer and the above-mentioned gate electrode, the above-mentioned semiconductor The device is characterized in that it comprises: a second main layer of the second conductivity type, which is formed on the surface of the above-mentioned drift layer, without the above-mentioned surface side electrode layer, and is connected to the above-mentioned surface side main electrode; a second groove, which is formed in contact with the above-mentioned second main layer; a virtual electrode, which is formed inside the above-mentioned second groove and is formed to have the same potential as the above-mentioned surface side main electrode; an insulating film, which is formed inside the above-mentioned second groove between the above-mentioned second main layer and the above-mentioned virtual electrode; an electric field concentration layer of the first conductivity type, which is formed at the bottom of the above-mentioned second main layer and has a higher impurity concentration than the above-mentioned drift layer; and a floating layer of the second conductivity type, which is formed between the above-mentioned first groove and the above-mentioned second groove and is formed to be electrically floating.

[0013] In addition, in order to solve the above-mentioned problems, the second semiconductor device of the present invention, for example, comprises: a drift layer of a first conductivity type; a first main body layer of a second conductivity type, which is formed on the surface of the above-mentioned drift layer; a surface-side electrode layer of a first conductivity type, which is formed on the surface of the above-mentioned first main body layer; a surface-side main electrode, which is connected to the above-mentioned first main body layer and the above-mentioned surface-side electrode layer; a groove, which is formed in contact with the above-mentioned first main body layer and the above-mentioned surface-side electrode layer; a gate electrode, which is formed on the side wall of the above-mentioned first main body layer side inside the above-mentioned groove; and a gate insulating film, which is formed inside the above-mentioned groove between the above-mentioned first main body layer and the above-mentioned gate electrode, and between the above-mentioned surface-side electrode layer and the above-mentioned gate electrode. The above-mentioned semiconductor device is characterized in that it comprises: a second main body layer of a second conductivity type, which is in contact with the above-mentioned groove, and is in contact with the above-mentioned first main layer. The side opposite to the main layer is formed on the surface of the drift layer, the surface side electrode layer is not formed, and is connected to the surface side main electrode; a virtual electrode is formed on the side wall of the second main layer side inside the groove and is formed at the same potential as the surface side main electrode; a first insulating film is formed inside the groove between the second main layer and the virtual electrode; an electric field concentration layer of the first conductivity type is formed at the bottom of the second main layer and has a higher impurity concentration than the drift layer; a field plate is formed inside the groove and is formed at the same potential as the surface side main electrode; a second insulating film is formed inside the groove between the field plate and the drift layer; and a third insulating film is formed inside the groove between the field plate and the gate electrode, and between the field plate and the virtual electrode.

[0014] Furthermore, the power conversion device of the present invention is characterized by using, for example, the first semiconductor device or the second semiconductor device of the present invention as a switching element.

[0015] Effects of the Invention

[0016] According to the present invention, an electric field concentration layer is used to generate an avalanche in a certain area of ​​the second main layer, and a floating layer is provided between the first main layer where the switching element main body exists and the second main layer where the avalanche occurs, or a wide groove with a field plate is formed inside, so that the first main layer and the second main layer are separated from each other, thereby being able to suppress the carrier flow caused by the avalanche to the first main layer where the switching element main body exists. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1 is a cross-sectional view illustrating the semiconductor device of Example 1.

[0018] Figure 2 This is a cross-sectional view illustrating the semiconductor device of Example 2.

[0019] Figure 3This is a cross-sectional view illustrating the semiconductor device of Example 3.

[0020] Figure 4 This is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment.

[0021] Figure 5 This is a cross-sectional view illustrating the semiconductor device of Example 5.

[0022] Figure 6 This is a cross-sectional view illustrating the semiconductor device of Example 6. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In each of the drawings and embodiments, the same or similar components are denoted by the same reference numerals, and repeated descriptions are omitted.

[0024] Example 1

[0025] Figure 1 1 is a cross-sectional view illustrating the semiconductor device of Example 1.

[0026] Figure 1 This is an example of application to a trench IGBT. In addition, it is not limited to IGBT, and can also be applied to MOSFET as described later.

[0027] The semiconductor device of the first embodiment has, in the unit cell 9, for example: a first conductivity type (in Figure 1 The drift layer 10 of the second conductivity type (in Figure 1 The present invention comprises a first main layer 5a (of p-type in the embodiment) formed on the surface of the drift layer 10; an emitter layer 6 (surface side electrode layer) of a first conductive type formed on the surface of the first main layer 5a; an emitter electrode 2 (surface side main electrode) connected to the first main layer 5a and the emitter layer 6; a first trench 20a formed in contact with the first main layer 5a and the emitter layer 6; a gate electrode 3 formed inside the first trench 20a; and a gate insulating film 21a formed inside the first trench 20a between the first main layer 5a and the gate electrode 3, and between the emitter layer 6 and the gate electrode 3.

[0028] In addition, the semiconductor device of Example 1 has, for example: a first conductive type buffer layer 11, which is formed on the back side of the drift layer 10 (the side opposite to the first main layer 5a); a second conductive type collector layer 12 (back side electrode layer), which is formed on the back side of the buffer layer 11; and a collector electrode 1 (back side main electrode), which is formed on the back side of the collector layer 12.

[0029] And, thereby, the switch element main body is constituted.

[0030] Here, the impurity concentration of the drift layer 10 is low (n-), and the impurity concentration of the emitter layer 6 is high (n+). Figure 1 In the description, the first conductivity type is set to n-type and the second conductivity type is set to p-type as an example, but the first conductivity type may be set to p-type and the second conductivity type may be set to n-type. In this case, the carriers are electrons instead of holes (positive holes).

[0031] exist Figure 1 In the description, IGBT is used as an example, but in the case of MOSFET, it is sufficient to replace the emitter layer 6 as the surface side electrode layer with the source layer, replace the emitter electrode 2 as the surface side main electrode with the source electrode, and replace the collector electrode 1 as the back side main electrode with the drain electrode. In addition, in the case of MOSFET, the collector layer 12 of the second conductivity type as the back side electrode layer is replaced with the drain layer of the first conductivity type. The impurity concentration of the drain layer is a high concentration (n+).

[0032] In addition, the semiconductor device of embodiment 1 has, for example, in the unit cell 9: a second conductive type second main layer 5b, which is formed on the surface of the drift layer 10, without forming an emitter layer 6 and connected to the emitter electrode 2; a second trench 20b, which is formed in contact with the second main layer 5b; a virtual electrode 4, which is formed inside the second trench 20b and is formed at the same potential as the emitter electrode 2; an insulating film 21b, which is formed inside the second trench 20b between the second main layer 5b and the virtual electrode 4; and a first conductive type electric field concentration layer 7, which is formed at the bottom of the second main layer 5b and has a higher impurity concentration than the drift layer 10.

[0033] The electric field concentration layer 7 is formed at the bottom of the second main body layer 5b, so that the avalanche voltage at this location is lower than that at other parts. When the IGBT is turned off, when an avalanche occurs, it is generated at this location. Holes, which are a large number of carriers generated by the avalanche, flow through the second main body layer 5b and pass through the emitter electrode 2. Since the emitter layer 6 of the first conductivity type is not formed in the second main body layer 5b, there is no pnpn parasitic thyristor in the second main body layer 5b, and latching of the parasitic thyristor will not occur.

[0034] Here, if the first body layer 5 a of the switching element body having the first conductivity type emitter layer 6 is located nearby, carriers caused by avalanche also flow to the first body layer 5 a , and latch-up of the parasitic thyristor may occur.

[0035] Therefore, the semiconductor device of the first embodiment has a structure including a second conductivity type floating layer 8 formed between the first trench 20a and the second trench 20b and electrically floating in the unit cell 9. The floating layer 8 is insulated from the emitter electrode 2 by the insulating film 22 for electrical floating.

[0036] The floating layer 8 separates the first main body layer 5a and the second main body layer 5b from each other, and can suppress the flow of carriers caused by avalanche to the first main body layer 5a where the switch element main body exists. As a result, latching of the parasitic thyristor can also be suppressed. In addition, the reduction in RBSOA tolerance due to latching of the parasitic thyristor can also be suppressed. In addition, in the case of MOSFET, since an npn parasitic transistor exists instead of a parasitic thyristor, the parasitic transistor can be suppressed from turning on.

[0037] In addition, the floating layer 8 is electrically floating and is not connected to the emitter electrode 2, so when the IGBT is turned on, holes do not pass through the emitter electrode 2 via the floating layer 8. If holes pass through the emitter electrode 2 from a certain area of ​​the floating layer 8 when the IGBT is turned on, the hole density will decrease, the IE (Injection Enhancement) effect will be weakened, and the conductivity modulation will become insufficient, which will cause problems such as the turn-on voltage becoming higher. However, since the floating layer 8 is electrically floating and is not connected to the emitter electrode 2, such problems will not occur.

[0038] As described above, according to Example 1, an avalanche is generated in a certain area of ​​the second main layer 5b by utilizing the electric field concentration layer 7, and a floating layer 8 is provided between the first main layer 5a where the switching element main body exists and the second main layer 5b where the avalanche is generated, so that the first main layer 5a and the second main layer 5b are separated from each other, and the carrier flow caused by the avalanche to the first main layer 5a where the switching element main body exists can be suppressed.

[0039] Example 2

[0040] Embodiment 2 is a modified example of Embodiment 1. The description will focus on the differences from Embodiment 1, and any duplicate description will be omitted.

[0041] Figure 2 This is a cross-sectional view illustrating the semiconductor device of Example 2.

[0042] Figure 2 This is an example of application to an IGBT of a so-called side gate structure. In addition, as in the first embodiment, it is not limited to IGBTs, and can also be applied to MOSFETs. In addition, the conductivity type can also be reversed.

[0043] The semiconductor device of the second embodiment includes, for example, a first conductive type drift layer 10, a second conductive type first main layer 5a formed on the surface of the drift layer 10, a first conductive type emitter layer 6 (surface side electrode layer) formed on the surface of the first main layer 5a, an emitter electrode 2 (surface side main electrode) connected to the first main layer 5a and the emitter layer 6, a trench 20c formed in contact with the first main layer 5a and the emitter layer 6, a gate electrode 13 formed on the side wall of the first main layer 5a inside the trench 20c, and a gate insulating film 23a formed between the first main layer 5a and the gate electrode 13, and between the emitter layer 6 and the gate electrode 13 inside the trench 20c. The structure of the back side is the same as that of the first embodiment, so the description is omitted. Thus, a switching element body of the so-called side gate structure is formed.

[0044] In addition, the semiconductor device of the second embodiment includes, in the unit cell 9, for example: a second conductive type second body layer 5b, which is in contact with the trench 20c, is formed on the surface of the drift layer 10 on the side opposite to the first body layer 5a, has no emitter layer 6 formed thereon, and is connected to the emitter electrode 2; a dummy electrode 14, which is formed on the side wall of the second body layer 5b side inside the trench 20c and is formed at the same potential as the emitter electrode 2; a first insulating film 23b, which is formed inside the trench 20c between the second body layer 5b and the dummy electrode 14; and a first conductive type electric field concentration layer 7, which is formed at the bottom of the second body layer 5b and has a higher impurity concentration than the drift layer 10. Since the effect of the electric field concentration layer 7 is the same as that of the first embodiment, the description thereof is omitted.

[0045] Furthermore, the semiconductor device of the second embodiment has, in the unit cell 9, for example, a field plate 15 formed inside the trench 20c and formed at the same potential as the emitter electrode 2; a second insulating film 23c formed inside the trench 20c between the field plate 15 and the drift layer 10; and a third insulating film 24a formed inside the trench 20c between the field plate 15 and the gate electrode 13, and between the field plate 15 and the dummy electrode 14. In addition, the third insulating film 24a represents a portion of the insulating film 24 formed inside the trench 20c.

[0046] In the second embodiment, the following structure is adopted: instead of the floating layer 8 of the first embodiment, a wide groove 20c having a field plate 15 formed therein is provided. Thus, as in the first embodiment, the first main body layer 5a and the second main body layer 5b are separated from each other, and it is possible to suppress the flow of carriers caused by avalanche to the first main body layer 5a where the switch element main body exists.

[0047] The field plate 15 is set to the same potential as the emitter electrode 2 because otherwise, the electric field concentrates under the dummy electrode 14 , destroying the first insulating film 23 b and causing carriers to flow to the dummy electrode 14 .

[0048] Furthermore, since the field plate 15 is surrounded by the second insulating film 23c and the third insulating film 24a, holes do not pass through the emitter electrode 2 via the field plate 15 when the IGBT is turned on. Therefore, the problem of high on-voltage is avoided as in the first embodiment.

[0049] The other effects are the same as those of the first embodiment or the side gate structure, and thus description thereof is omitted.

[0050] Example 3

[0051] Embodiment 3 is a modified example of Embodiment 1. The description will be centered around differences from Embodiment 1, and duplicate descriptions will be omitted. Embodiment 3 can also be applied to Embodiment 2.

[0052] Figure 3 This is a cross-sectional view illustrating the semiconductor device of Example 3.

[0053] The third embodiment is different from the first embodiment in that the width Wb of the second main body layer 5b is larger than the width Wa of the first main body layer 5a. The other aspects are the same as the first embodiment.

[0054] By increasing the width Wb, the area of ​​the pn junction between the second main body layer 5b and the drift layer 10 or between the second main body layer 5b and the electric field concentration layer 7 can be increased, so that the avalanche voltage can be lowered compared to the case of the width Wa, and avalanche can be reliably generated at a certain location in the second main body layer 5b. However, if the width Wb is too wide, the avalanche voltage is too low, resulting in a decrease in the overall withstand voltage, so it is desirable to set it in consideration of the balance with the overall withstand voltage.

[0055] The other effects are the same as those of the first embodiment, and thus their description is omitted.

[0056] Example 4

[0057] Embodiment 4 is a modified example of Embodiment 1. The description will be centered around differences from Embodiment 1, and duplicate descriptions will be omitted. In addition, Embodiment 4 can also be applied to Embodiment 2 or Embodiment 3.

[0058] Figure 4 This is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment.

[0059] The fourth embodiment is different from the first embodiment in that an electric field concentration layer 7 is also provided at the bottom of the first body layer 5a and the avalanche voltage in the second body layer 5b is lower than that in the first body layer 5a.

[0060] According to the fourth embodiment, in the RBSOA action when the IGBT is turned off, a negative voltage is applied between the gate and the emitter, so the electric field is dispersed to the pn junction composed of the first main body layer 5a and the electric field concentration layer 7 and the bottom of the first groove 20a. As a result, the avalanche voltage of the first main body layer 5a becomes higher. Therefore, the avalanche voltage in the second main body layer 5b is smaller than the avalanche voltage in the first main body layer 5a, and an avalanche can be generated on the side where the second main body layer 5b is located. In addition, the same is true for the case applied to the second embodiment, the electric field is dispersed to the pn junction composed of the first main body layer 5a and the electric field concentration layer 7 and the bottom of the groove 20c, and the avalanche voltage of the first main body layer 5a becomes higher, so an avalanche can be generated on the side where the second main body layer 5b is located.

[0061] In the fourth embodiment, the electric field concentration layer 7 formed at the bottom of the first main body layer 5a can block the hole penetration path in the first main body layer 5a, thereby preventing the IE (Injection Enhancement) effect from being weakened and preventing the on-voltage from being increased when the IGBT is turned on.

[0062] The other effects are the same as those of the first embodiment, and thus their description is omitted.

[0063] Example 5

[0064] Embodiment 5 is a modified example of Embodiment 4. The description will be centered around differences from Embodiment 4, and duplicate descriptions will be omitted. Embodiment 5 can also be applied to any of Embodiments 1 to 3.

[0065] Figure 5 This is a cross-sectional view illustrating the semiconductor device of Example 5.

[0066] The fifth embodiment is different from the fourth embodiment in that the impurity concentration (n+) of the electric field concentration layer 7 formed at the bottom of the second main body layer 5b is higher than the impurity concentration (n) of the electric field concentration layer 7 formed at the bottom of the first main body layer 5a. The other aspects are the same as the fourth embodiment.

[0067] According to Example 5, the avalanche voltage of the pn junction formed by the second body layer 5 b and the high-concentration electric field concentration layer 7 is lower than that of the pn junction formed by the first body layer 5 a and the electric field concentration layer 7 , so avalanche can be reliably generated in the second body layer 5 b .

[0068] The other effects are the same as those of Embodiment 4, and thus their description is omitted.

[0069] Example 6

[0070] Embodiment 6 is a modified example of Embodiment 4. The description will be centered around the differences from Embodiment 4, and duplicate descriptions will be omitted. Embodiment 6 can also be applied to any of Embodiments 1 to 3 and 5.

[0071] Figure 6 This is a cross-sectional view illustrating the semiconductor device of Example 6.

[0072] In Example 6, the difference from Example 4 is that the bottom (depth Db) of the electric field concentration layer 7 formed at the bottom of the second main body layer 5b is formed deeper than the bottom (depth Da) of the electric field concentration layer 7 formed at the bottom of the first main body layer 5a. Other than that, it is the same as Example 4.

[0073] According to Example 6, when the depth Db of the electric field concentration layer 7 of the second body layer 5 b is formed deeper, the avalanche voltage is reduced, and thus avalanche can be reliably generated in the second body layer 5 b .

[0074] The other effects are the same as those of Embodiment 4, and thus their description is omitted.

[0075] Example 7

[0076] Embodiment 7 is an embodiment of a power conversion device.

[0077] A power conversion device can be configured by using the semiconductor device of any one of Embodiments 1 to 6 as a switching element. Since the structure of the power conversion device is a general structure, the description thereof will be omitted.

[0078] Although the embodiments of the present invention have been described above, the present invention is not limited to the structures described in the embodiments, and various changes can be made within the scope of the technical concept of the present invention. In addition, part or all of the structures described in the embodiments can also be combined and applied.

[0079] Explanation of symbols

[0080] 1—collector electrode (back side main electrode), 2—emitter electrode (surface side main electrode), 3—gate electrode, 4—virtual electrode, 5a—first main layer, 5b—second main layer, 6—emitter layer (surface side electrode layer), 7—electric field concentration layer, 8—floating layer, 9—unit cell, 10—drift layer, 11—buffer layer, 12—collector layer (back side electrode layer), 13—gate electrode, 14—virtual electrode, 15—field plate, 20a—first trench, 20b—second trench, 20c—trench, 21a—gate insulating film, 21b—insulating film, 22—insulating film, 23a—gate insulating film, 23b—first insulating film, 23c—second insulating film, 24—insulating film, 24a—third insulating film.

Claims

1. A semiconductor device comprising: a drift layer of a first conductivity type; A first main layer of a second conductivity type formed on a surface of the drift layer; A first conductive type surface-side electrode layer formed on the surface of the first bulk layer; A surface-side main electrode connected to the first main body layer and the surface-side electrode layer; A first groove formed in contact with the first main body layer and the surface-side electrode layer; A gate electrode formed inside the first trench; as well as a gate insulating film formed inside the first trench between the first body layer and the gate electrode and between the surface-side electrode layer and the gate electrode, The semiconductor device is characterized by comprising: A second conductive type second main body layer formed on the surface of the drift layer, without forming the surface side electrode layer, and connected to the surface side main electrode; A second groove is formed in contact with the second main body layer; a dummy electrode formed inside the second groove and having the same potential as the surface-side main electrode; an insulating film formed inside the second trench between the second main body layer and the dummy electrode; An electric field concentration layer of the first conductivity type, formed at the bottom of the second main layer, having a higher impurity concentration than the drift layer; as well as The floating layer of the second conductivity type is formed between the first trench and the second trench and is electrically floating.

2. A semiconductor device comprising: a drift layer of a first conductivity type; A first main layer of a second conductivity type formed on a surface of the drift layer; A first conductive type surface-side electrode layer formed on the surface of the first bulk layer; A surface-side main electrode connected to the first main body layer and the surface-side electrode layer; A groove formed in contact with the first main body layer and the surface-side electrode layer; a gate electrode formed on a side wall of the trench on the first body layer side; as well as a gate insulating film formed inside the trench between the first body layer and the gate electrode and between the surface-side electrode layer and the gate electrode, The semiconductor device is characterized by having: A second conductive type second main body layer, which is in contact with the trench, is formed on the surface of the drift layer on the side opposite to the first main body layer, has no surface-side electrode layer formed thereon, and is connected to the surface-side main electrode; a dummy electrode formed on a side wall of the groove on the second main body layer side and having the same potential as the surface-side main electrode; a first insulating film formed inside the trench between the second main body layer and the dummy electrode; An electric field concentration layer of the first conductivity type, formed at the bottom of the second main layer, having a higher impurity concentration than the drift layer; A field plate formed inside the trench and having the same potential as the surface-side main electrode; a second insulating film formed inside the trench between the field plate and the drift layer; as well as A third insulating film is formed inside the trench between the field plate and the gate electrode and between the field plate and the dummy electrode.

3. The semiconductor device according to claim 1 or 2, characterized in that: The second main body layer has a width greater than that of the first main body layer.

4. The semiconductor device according to claim 1 or 2, characterized in that: The electric field concentration layer is also provided at the bottom of the first main layer. An avalanche voltage in the second body layer is smaller than an avalanche voltage in the first body layer.

5. The semiconductor device according to claim 4, wherein: The electric field concentration layer formed at the bottom of the second body layer has an impurity concentration higher than that of the electric field concentration layer formed at the bottom of the first body layer.

6. The semiconductor device according to claim 4, wherein: The bottom of the electric field concentration layer formed at the bottom of the second body layer is formed deeper than the bottom of the electric field concentration layer formed at the bottom of the first body layer.

7. The semiconductor device according to claim 1 or 2, characterized in that: The surface-side electrode layer is an emitter layer, and the surface-side main electrode is an emitter electrode.

8. The semiconductor device according to claim 1 or 2, characterized in that: The surface-side electrode layer is a source layer, and the surface-side main electrode is a source electrode.

9. A power conversion device, characterized in that: The semiconductor device according to claim 1 or 2 is used as a switching element.

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