Test circuit of radio frequency control chip and test method thereof

Abstract

The invention provides a test circuit of a radio frequency control chip and a test method thereof. The test circuit comprises a radio frequency signal transmitting circuit and a digital signal processing circuit. The digital signal processing circuit is used for inputting a control signal to the radio frequency signal transmitting circuit and providing a clock signal for a radio frequency control chip to be tested, and the clock signal and the control signal are synchronous signals; the radio frequency signal transmitting circuit is used for generating a radio frequency carrier signal according to the control signal, shaping the radio frequency carrier signal and transmitting a test signal to the radio frequency control chip to be tested so as to test the radio frequency control chip to be tested; and the digital signal processing circuit is also used for receiving a processing signal output by the radio frequency control chip to be tested, sampling and analyzing the processing signal, and determining a test result of the radio frequency control chip to be tested. According to the invention, automatic testing can be realized, and the radio frequency control chips with defects can be rapidly and accurately screened out.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit automated testing, and in particular to a test circuit and a test method for a radio frequency control chip. Background Art

[0002] RF control chips are mainly used in wireless communications, radar, navigation, radio and television, etc. They have the characteristics of high frequency, low power consumption, high sensitivity, etc., and can be applied in the fields of Internet of Things, Internet of Vehicles, industrial control and security monitoring, smart home, health care, etc. With the surge in demand for RF control chips, how to quickly and accurately screen out defective RF control chips is a difficult point in screening tests. Summary of the invention

[0003] The present application provides an improved test circuit and test method for a radio frequency control chip.

[0004] The present application provides a test circuit for a radio frequency control chip, comprising: a radio frequency signal transmitting circuit and a digital signal processing circuit, wherein the radio frequency signal transmitting circuit is electrically connected to a radio frequency control chip to be tested, and the digital signal processing circuit is electrically connected to the radio frequency signal transmitting circuit and the radio frequency control chip to be tested; wherein the digital signal processing circuit is used to input a control signal to the radio frequency signal transmitting circuit, and to provide a clock signal to the radio frequency control chip to be tested, and the clock signal and the control signal are synchronization signals; the radio frequency signal transmitting circuit is used to generate a radio frequency carrier signal according to the control signal, to shape the radio frequency carrier signal, and to transmit a test signal to the radio frequency control chip to be tested, so as to test the radio frequency control chip to be tested; the test signal is used to test the radio frequency control chip to be tested after passing through the radio frequency control chip to be tested, so that the radio frequency control chip to be tested outputs a processing signal to the digital signal processing circuit; the digital signal processing circuit is also used to sample and analyze the processing signal output by the radio frequency control chip to be tested, and to determine the test result of the radio frequency control chip to be tested.

[0005] Preferably, the control signal includes a square wave signal having a frequency of at least 13.56 MHz or an integer multiple thereof; the digital signal processing circuit is used to input a square wave signal having a frequency of at least 13.56 MHz or an integer multiple thereof into the RF signal transmitting circuit, and is used to form a carrier envelope by changing the input level of the square wave signal to modulate the RF carrier signal output by the RF signal transmitting circuit so that the RF carrier signal meets the format requirements of the communication test.

[0006] Preferably, the control signal comprises a digital signal with the same frequency and opposite phase; the test signal comprises a differential sinusoidal signal with the same frequency and opposite phase; and the processing signal comprises a differential digital signal with the same frequency and opposite phase.

[0007] Preferably, the RF control chip to be tested includes at least one transceiver mode and / or at least one transceiver rate; the test circuit is used to test the at least one transceiver mode and / or the at least one transceiver rate of the RF control chip to be tested.

[0008] Preferably, the test circuit further includes a radio frequency power supply circuit electrically connected to the radio frequency signal transmitting circuit, and the radio frequency power supply circuit is used to supply power to the radio frequency signal transmitting circuit.

[0009] Preferably, the test circuit further includes a chip power supply circuit electrically connected to the RF control chip to be tested, and the chip power supply circuit is used to supply power to the RF control chip.

[0010] The present application also provides a test method for a radio frequency control chip, using a test circuit as described in any one of the above embodiments; the test method includes:

[0011] The digital signal processing circuit inputs a control signal to the radio frequency signal transmitting circuit, and provides a clock signal to the radio frequency control chip to be tested, wherein the clock signal and the control signal are synchronous signals;

[0012] The RF signal transmitting circuit generates a RF carrier signal according to the control signal, shapes the RF carrier signal, and transmits a test signal to the RF control chip to be tested, so as to test the RF control chip to be tested; and

[0013] The digital signal processing circuit samples and analyzes the processing signal output by the radio frequency control chip to be tested, and determines the test result of the radio frequency control chip to be tested.

[0014] Preferably, the control signal comprises a square wave signal having a frequency of at least 13.56 MHz or an integer multiple thereof; the digital signal processing circuit inputting the control signal to the radio frequency signal transmitting circuit comprises:

[0015] The digital signal processing circuit inputs a square wave signal with a frequency of at least 13.56 MHz or an integer multiple thereof to the RF signal transmitting circuit, and forms a carrier envelope by changing the input level of the square wave signal to modulate the RF carrier signal output by the RF signal transmitting circuit so that the RF carrier signal meets the format requirements of the communication test.

[0016] Preferably, the control signal comprises a digital signal with the same frequency and opposite phase; the test signal comprises a differential sinusoidal signal with the same frequency and opposite phase; and the processing signal comprises a differential digital signal with the same frequency and opposite phase.

[0017] Preferably, the RF control chip to be tested includes at least one transceiver mode and / or at least one transceiver rate; the digital signal processing circuit samples and analyzes the processed signal output by the RF control chip to be tested to determine the test result of the RF control chip to be tested, including:

[0018] The digital signal processing circuit samples and analyzes different processing signals of the at least one transceiver mode and / or the at least one transceiver rate of the radio frequency control chip to be tested, and determines a test result of the radio frequency control chip to be tested.

[0019] The test circuit and test method of the radio frequency control chip of the embodiment of the present application. The test circuit includes a radio frequency signal transmitting circuit and a digital signal processing circuit, the radio frequency signal transmitting circuit is electrically connected to the radio frequency control chip to be tested, and the digital signal processing circuit is electrically connected to the radio frequency signal transmitting circuit and the radio frequency control chip to be tested. Among them, the digital signal processing circuit inputs a control signal to the radio frequency signal transmitting circuit and provides a clock signal to the radio frequency control chip to be tested, the radio frequency signal transmitting circuit generates a radio frequency carrier signal according to the control signal, shapes the radio frequency carrier signal, and transmits a test signal to the radio frequency control chip to be tested to test the radio frequency control chip to be tested, the test signal passes through the radio frequency control chip to be tested, and then outputs a processing signal to the digital signal processing circuit, the digital signal processing circuit receives the processing signal output by the radio frequency control chip to be tested, samples and analyzes the processing signal, and determines the test result of the radio frequency control chip to be tested. Such a setting can realize automated testing, quickly and accurately screen out defective radio frequency control chips, and the test efficiency is high and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Shown is a principle block diagram of an embodiment of a test circuit of a radio frequency control chip of the present application.

[0021] Figure 2 Shown Figure 1 A principle block diagram of another embodiment of a test circuit for a radio frequency control chip is shown.

[0022] Figure 3 Shown is a flow chart of an embodiment of a method for testing a radio frequency control chip of the present application. DETAILED DESCRIPTION

[0023] The test circuit and test method of the radio frequency control chip of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features of the following embodiments and implementations can be combined with each other.

[0024] Figure 1 FIG. 1 is a schematic block diagram of an embodiment of a test circuit 1 of a radio frequency control chip of the present application. Figure 1 As shown, the test circuit 1 of the RF control chip 2 is used to detect defects of the RF control chip 2 to be tested. The RF control chip 2 may include a near field communication control chip, but is not limited thereto. The test circuit 1 includes a RF signal transmitting circuit 11 and a digital signal processing circuit 12. The RF signal transmitting circuit 11 is electrically connected to the RF control chip 2 to be tested, and the digital signal processing circuit 12 is electrically connected to the RF signal transmitting circuit 11 and the RF control chip 2 to be tested. Among them, the digital signal processing circuit 12 is used to input a control signal to the RF signal transmitting circuit 11, and to provide a clock signal to the RF control chip 2 to be tested, and the clock signal and the control signal are synchronization signals. The RF signal transmitting circuit 11 is used to generate a RF carrier signal according to the control signal, shape the RF carrier signal, and transmit a test signal to the RF control chip 2 to be tested, so as to test the RF control chip 2 to be tested. After the test signal passes through the RF control chip 2 to be tested, the RF control chip 2 to be tested is tested, so that the RF control chip 2 to be tested outputs a processing signal to the digital signal processing circuit 12. The digital signal processing circuit 12 is also used to sample and analyze the processing signal output by the RF control chip 2 to be tested, and determine the test result of the RF control chip 2 to be tested.

[0025] Specifically, the digital signal processing circuit 12 includes a first output terminal DriverP, a second output terminal DriverN, a first sampling terminal Compare1, a second sampling terminal Compare2 and a clock signal transmitting terminal OTHER. The RF signal transmitting circuit 11 includes a first input terminal DINP, a second input terminal DINN, a first transmitting terminal RXP0 and a second transmitting terminal RXN0. The RF control chip 2 to be tested includes a first receiving terminal RXP1, a second receiving terminal RXN1, a first transmitting terminal TXP, a second transmitting terminal TXN and a clock signal terminal CLK.

[0026] The digital signal processing circuit 12 is electrically connected to the first input terminal DINP and the second input terminal DINN of the radio frequency signal transmitting circuit 11 through the first output terminal DriverP and the second output terminal DriverN. The digital signal processing circuit 12 inputs a control signal to the first input terminal DINP and the second input terminal DINN of the radio frequency signal transmitting circuit 11 through the first output terminal DriverP and the second output terminal DriverN. The digital signal processing circuit 12 is electrically connected to the clock signal terminal CLK of the radio frequency control chip 2 to be tested through the clock signal transmitting terminal OTHER, and the digital signal processing circuit 12 provides a clock signal to the clock signal terminal CLK of the radio frequency control chip 2 to be tested through the clock signal transmitting terminal OTHER. The clock signal and the control signal are synchronous signals. Such a setting ensures that all signals received by the radio frequency control chip 2 to be tested are of the same frequency and phase, thereby avoiding clock and phase deviations when the radio frequency control chip 2 to be tested is processing radio frequency signals.

[0027] The RF signal transmitting circuit 11 is electrically connected to the first receiving terminal RXP1 and the second receiving terminal RXN1 of the RF control chip 2 to be tested via the first transmitting terminal RXP0 and the second transmitting terminal RXN0. The RF signal transmitting circuit 11 is used to generate a RF carrier signal according to the received control signal, and transmit a test signal to the first receiving terminal RXP1 and the second receiving terminal RXN1 of the RF control chip 2 to be tested via the first transmitting terminal RXP0 and the second transmitting terminal RXN0, so as to test the RF control chip 2 to be tested.

[0028] The RF control chip 2 to be tested is electrically connected to the first sampling terminal Compare1 and the second sampling terminal Compare2 of the digital signal processing circuit 12 through the first transmitting terminal TXP and the second transmitting terminal TXN. After the test signal passes through the RF control chip 2 to be tested, the processing signal is output to the first sampling terminal Compare1 and the second sampling terminal Compare2 of the digital signal processing circuit 12 through the first transmitting terminal TXP and the second transmitting terminal TXN. The digital signal processing circuit 12 receives the processing signal output by the RF control chip 2 to be tested through the first sampling terminal Compare1 and the second sampling terminal Compare2, samples and analyzes the processing signal, and determines the test result of the RF control chip 2 to be tested. The test result of the RF control chip 2 to be tested is used to determine whether the RF control chip 2 is defective, thereby determining the quality of the RF control chip 2. With such a configuration, the test circuit 1 of the present application can realize automated testing, quickly and accurately screen out defective RF control chips, and has high test efficiency and low cost.

[0029] exist Figure 1In the embodiment shown, the control signal includes a digital signal with the same frequency and opposite phase. The test signal includes a differential sinusoidal signal with the same frequency and opposite phase. The processing signal includes a differential digital signal with the same frequency and opposite phase. Such an arrangement is conducive to signal detection.

[0030] exist Figure 1 In the embodiment shown, the control signal includes a square wave signal having a frequency of at least 13.56 MHz or an integer multiple thereof. The digital signal processing circuit 12 is used to input a square wave signal having a frequency of at least 13.56 MHz or an integer multiple thereof to the RF signal transmitting circuit 11, and is used to form a carrier envelope by changing the input level of the square wave signal to modulate the RF carrier signal output by the RF signal transmitting circuit 11 so that the RF carrier signal meets the format requirements of the communication test requirements. In this way, the communication test requirements are met.

[0031] In this embodiment, the digital signal processing circuit 12 inputs digital signals with the same frequency and opposite phases to the first input terminal DINP and the second input terminal DINN of the RF signal transmitting circuit 11 through the first output terminal DriverP and the second output terminal DriverN. The digital signal processing circuit 12 provides a square wave signal with a frequency of 13.56 MHz or an integer multiple thereof to the RF signal transmitting circuit 11, which is used to control the RF carrier signal of the test rate output by the RF signal transmitting circuit 11. The digital signal processing circuit 12 forms a carrier envelope by changing the input level of the input port, and modulates the output signal of the RF signal transmitting circuit 11, so that the RF carrier signal output by the RF signal transmitting circuit 11 meets the format requirements of the communication test requirements. The digital signal processing circuit 12 is electrically connected to the clock signal terminal CLK of the RF control chip 2 to be tested through the clock signal transmitting terminal OTHER, and the digital signal processing circuit 12 provides a clock signal to the clock signal terminal CLK of the RF control chip 2 to be tested through the clock signal transmitting terminal OTHER. The clock signal and the digital signal with the same frequency but opposite phase are synchronous signals. This setting ensures that all signals received by the RF control chip 2 to be tested have the same frequency and phase, avoiding clock and phase deviation when the RF control chip 2 to be tested processes RF signals.

[0032] The RF signal transmitting circuit 11 generates an RF carrier signal according to the received digital signal with the same frequency and opposite phase, and transmits a differential sinusoidal signal with the same frequency and opposite phase to the first receiving terminal RXP1 and the second receiving terminal RXN1 of the RF control chip 2 to be tested through the first transmitting terminal RXP0 and the second transmitting terminal RXN0, so as to test the RF control chip 2 to be tested.

[0033] After the differential sinusoidal signal with the same frequency and opposite phase passes through the RF control chip 2 to be tested, the differential digital signal with the same frequency and opposite phase is output to the first sampling terminal Compare1 and the second sampling terminal Compare2 of the digital signal processing circuit 12 through the first transmitting terminal TXP and the second transmitting terminal TXN. The digital signal processing circuit 12 receives the differential digital signal with the same frequency and opposite phase output by the RF control chip 2 to be tested through the first sampling terminal Compare1 and the second sampling terminal Compare2, samples the differential digital signal with the same frequency and opposite phase, and analyzes the sampling result using an algorithm that meets the communication test requirements, judges the quality of the RF control chip 2 to be tested by the analysis result, and completes the screening test of the RF control chip 2.

[0034] Such an arrangement can realize an automated test on the RF control chip 2 to be tested, and quickly and accurately screen out defective RF control chips to meet communication test requirements, with high test efficiency and low cost.

[0035] exist Figure 1 In the illustrated embodiment, the RF control chip 2 to be tested includes at least one transceiver mode and / or at least one transceiver rate. In some embodiments, at least one transceiver mode of the RF control chip 2 to be tested includes TypeA card mode, TypeA card reader mode, TypeB card mode, TypeB card reader mode, TypeF card mode, TypeF card reader mode, and the above transceiver modes all meet the communication test requirements. In some embodiments, at least one transceiver rate of the RF control chip 2 to be tested includes 106kbps, 212kbps, and 424kbps transceiver rates, and the above transceiver rates all meet the communication test requirements. The test circuit 1 is used to test at least one transceiver mode and / or at least one transceiver rate of the RF control chip 2 to be tested. In some embodiments, the test circuit 1 is used to traverse the test of one or more transceiver modes of the RF control chip 2 to be tested in sequence. In some embodiments, the test circuit 1 is used to traverse the test of one or more transceiver rates of the RF control chip 2 to be tested in sequence. In this way, the communication test requirements are met.

[0036] Figure 2 Shown Figure 1 The schematic diagram of another embodiment of the test circuit 1 of the radio frequency control chip is shown. Figure 2 The embodiment shown is Figure 1 The embodiment shown is similar, the main difference is that the test circuit 1 also includes a radio frequency power supply circuit 13, which is electrically connected to the radio frequency signal transmitting circuit 11, and the radio frequency power supply circuit 13 is used to supply power to the radio frequency signal transmitting circuit 11. Figure 2In the illustrated embodiment, the RF signal transmitting circuit 11 further includes a positive power supply electrode +8V and a negative power supply electrode -8V. The RF power supply circuit 13 includes a first power supply terminal 131 and a second power supply terminal 132. The RF power supply circuit 13 is electrically connected to the positive power supply electrode +8V of the RF signal transmitting circuit 11 through the first power supply terminal 131, and is electrically connected to the negative power supply electrode -8V of the RF signal transmitting circuit 11 through the second power supply terminal 132. The RF power supply circuit 13 provides a continuous and stable ±8V power supply to the positive power supply electrode +8V and the negative power supply electrode -8V of the RF signal transmitting circuit 11 through the first power supply terminal 131 and the second power supply terminal 132, so that the RF signal transmitting circuit 11 can operate stably and reliably.

[0037] exist Figure 2 In the illustrated embodiment, the test circuit 1 further includes a chip power supply circuit 14, which is electrically connected to the RF control chip 2 to be tested, and the chip power supply circuit 14 is used to supply power to the RF control chip 2. In this way, by setting the chip power supply circuit 14, a stable power supply is provided to the RF control chip 2 to be tested, so that the RF control chip 2 to be tested can be stably tested, stably and reliably.

[0038] Figure 3 FIG. 2 is a flow chart of an embodiment of a method for testing a radio frequency control chip 2 of the present application. Figure 1 and Figure 3 As shown, the test method of the RF control chip 2 adopts the above Figure 1 to Figure 2 The test circuit 1 shown in the embodiment. The test method includes steps S1 to S3. Among them,

[0039] Step S1: The digital signal processing circuit 12 inputs a control signal to the RF signal transmitting circuit 11 and provides a clock signal to the RF control chip 2 to be tested. The clock signal and the control signal are synchronous signals. Figure 1 As shown, the digital signal processing circuit 12 is electrically connected to the first input terminal DINP and the second input terminal DINN of the RF signal transmitting circuit 11 through the first output terminal DriverP and the second output terminal DriverN. The digital signal processing circuit 12 inputs a control signal to the first input terminal DINP and the second input terminal DINN of the RF signal transmitting circuit 11 through the first output terminal DriverP and the second output terminal DriverN. The digital signal processing circuit 12 is electrically connected to the clock signal terminal CLK of the RF control chip 2 to be tested through the clock signal transmitting terminal OTHER, and the digital signal processing circuit 12 provides a clock signal to the clock signal terminal CLK of the RF control chip 2 to be tested through the clock signal transmitting terminal OTHER. The clock signal and the control signal are synchronous signals. Such a setting ensures that all signals received by the RF control chip 2 to be tested are of the same frequency and phase, thereby avoiding clock and phase deviations when the RF control chip 2 to be tested is processing RF signals.

[0040] Step S2: The RF signal transmitting circuit 11 generates a RF carrier signal according to the control signal, shapes the RF carrier signal, and transmits a test signal to the RF control chip 2 to be tested, so as to test the RF control chip 2 to be tested. Figure 1 As shown, the RF signal transmitting circuit 11 is electrically connected to the first receiving terminal RXP1 and the second receiving terminal RXN1 of the RF control chip 2 to be tested via the first transmitting terminal RXP0 and the second transmitting terminal RXN0. The RF signal transmitting circuit 11 is used to generate a RF carrier signal according to the received control signal, and transmit a test signal to the first receiving terminal RXP1 and the second receiving terminal RXN1 of the RF control chip 2 to be tested via the first transmitting terminal RXP0 and the second transmitting terminal RXN0, so as to test the RF control chip 2 to be tested.

[0041] The RF control chip 2 to be tested is electrically connected to the first sampling terminal Compare1 and the second sampling terminal Compare2 of the digital signal processing circuit 12 through the first transmitting terminal TXP and the second transmitting terminal TXN. After the test signal passes through the RF control chip 2 to be tested, the RF control chip 2 to be tested is tested, and the processing signal is output to the first sampling terminal Compare1 and the second sampling terminal Compare2 of the digital signal processing circuit 12 through the first transmitting terminal TXP and the second transmitting terminal TXN.

[0042] Step S3: The digital signal processing circuit 12 samples and analyzes the processed signal output by the RF control chip 2 to be tested, and determines the test result of the RF control chip 2 to be tested. Figure 1 As shown, the digital signal processing circuit 12 receives the processing signal output by the RF control chip 2 to be tested through the first sampling terminal Compare1 and the second sampling terminal Compare2, samples and analyzes the processing signal, and determines the test result of the RF control chip 2 to be tested. The test result of the RF control chip 2 to be tested is used to determine whether the RF control chip 2 is defective, thereby determining the quality of the RF control chip 2.

[0043] With such a configuration, the testing method of the present application can realize automated testing, quickly and accurately screen out defective RF control chips, and has high testing efficiency and low cost.

[0044] exist Figure 3 In the embodiment shown, the control signal includes a digital signal with the same frequency and opposite phase. The test signal includes a differential sinusoidal signal with the same frequency and opposite phase. The processing signal includes a differential digital signal with the same frequency and opposite phase. Such an arrangement is conducive to signal detection.

[0045] exist Figure 3In the illustrated embodiment, in some embodiments, the control signal includes a square wave signal having a frequency of at least 13.56 MHz or an integer multiple thereof. Step S1, the digital signal processing circuit 12 inputs a control signal to the RF signal transmitting circuit 11, including: the digital signal processing circuit 12 inputs a square wave signal having a frequency of at least 13.56 MHz or an integer multiple thereof to the RF signal transmitting circuit 11, and forms a carrier envelope by changing the input level of the square wave signal to modulate the RF carrier signal output by the RF signal transmitting circuit 11, so that the RF carrier signal meets the format requirements of the communication test requirements. In this way, the communication test requirements are met.

[0046] In some embodiments, before the digital signal processing circuit 12 inputs a control signal to the RF signal transmitting circuit 11 and is used to provide a clock signal to the RF control chip 2 to be tested, the test method further includes: downloading multiple test programs into the RF control chip 2 to be tested. In this way, different transceiver rates and transceiver modes of the RF control chip 2 to be tested are pre-stored to improve test efficiency.

[0047] In some embodiments, the RF control chip 2 to be tested includes at least one transceiver mode and / or at least one transceiver rate. In some embodiments, at least one transceiver mode of the RF control chip 2 to be tested includes TypeA card mode, TypeA card reader mode, TypeB card mode, TypeB card reader mode, TypeF card mode, TypeF card reader mode, and the above transceiver modes meet the communication test requirements. In some embodiments, at least one transceiver rate of the RF control chip 2 to be tested includes 106kbps, 212kbps, and 424kbps transceiver rates, and the above transceiver rates meet the communication test requirements.

[0048] Step S3, the digital signal processing circuit 12 samples and analyzes the processed signal output by the RF control chip 2 to be tested, and determines the test result of the RF control chip 2 to be tested, including: the digital signal processing circuit 12 samples and analyzes different processed signals of at least one transceiver mode and / or at least one transceiver rate of the RF control chip 2 to be tested, and determines the test result of the RF control chip 2 to be tested. Such a setting meets the communication test requirements.

[0049] Specifically, before the test is performed, the test program is first downloaded to the internal memory of the RF control chip 2 to be tested, and the above Figure 1 to Figure 2The hardware construction of the test circuit shown in the embodiment. When testing, the digital signal processing circuit 12 provides a control signal to the RF control chip 2 to be tested, which is used to control the test program to select different test items. The command control word is input to the RF control chip 2 to be tested, and the RF control chip 2 to be tested runs the internal test program, selects the test items, and completes the test parameter configuration. After the RF control chip 2 to be tested completes the test parameter configuration according to the internal program, it waits for the RF module to input a signal and controls the RF signal transmitting circuit 11 to start data transmission.

[0050] After the RF control chip 2 to be tested receives the input signal transmitted by the RF signal transmitting circuit 11, it runs the test program and outputs the test result, performs sampling through the digital signal processing circuit 12, and parses the data according to the communication test requirements through the digital signal processing circuit 12, and judges whether the RF control chip 2 to be tested meets the requirements according to the parsing results. According to the requirements of the communication test requirements, the test program respectively performs tests of Type A card mode, Type A card reader mode, Type B card mode, Type B card reader mode, Type F card mode, and Type F card reader mode.

[0051] The digital signal processing circuit 12 adjusts the input rate of the RF control chip to be tested by changing the output frequency of the RF signal transmitting circuit 11, and tests the 106kbps, 212kbps, and 424kbps rate transceiver tests that meet the communication test requirements, respectively, to complete the 26.48kbps Type V card mode test that meets the communication test requirements. After all tests are passed, the RF control chip 2 to be tested is marked as Pass, and other module tests are performed. If there is no data or data parsing error in one of the test ports, it is marked as Fail and thrown.

[0052] This application provides a screening test solution for detecting the RF control chip 2 to be tested, and builds the above Figure 1 to Figure 2 The test circuit 1 shown in the embodiment downloads a test program for the RF control chip 2 to be tested, adjusts the input envelope and carrier frequency according to different communication test requirements, and tests different transmission protocols and different transmission rates. In this way, automated testing is implemented, and defective RF control chips are quickly and accurately screened out to meet communication test requirements, with high test efficiency and low cost.

[0053] It should be understood that the present application is not limited to the contents described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A test circuit for a radio frequency control chip, characterized in that: include: A radio frequency signal transmitting circuit and a digital signal processing circuit, wherein the radio frequency signal transmitting circuit is electrically connected to a radio frequency control chip to be tested, and the digital signal processing circuit is electrically connected to the radio frequency signal transmitting circuit and the radio frequency control chip to be tested; wherein the digital signal processing circuit is used to input a control signal to the radio frequency signal transmitting circuit, and to provide a clock signal to the radio frequency control chip to be tested, and the clock signal and the control signal are synchronization signals; the radio frequency signal transmitting circuit is used to generate a radio frequency carrier signal according to the control signal, to shape the radio frequency carrier signal, and to transmit a test signal to the radio frequency control chip to be tested, so as to test the radio frequency control chip to be tested; the test signal is used to test the radio frequency control chip to be tested after passing through the radio frequency control chip to be tested, so that the radio frequency control chip to be tested outputs a processing signal to the digital signal processing circuit; the digital signal processing circuit is also used to receive a processing signal output by the radio frequency control chip to be tested, to sample and analyze the processing signal, and to determine a test result of the radio frequency control chip to be tested.

2. The test circuit according to claim 1, characterized in that: The control signal includes a square wave signal with a frequency of at least 13.56 MHz or an integer multiple thereof; the digital signal processing circuit is used to input a square wave signal with a frequency of at least 13.56 MHz or an integer multiple thereof to the RF signal transmitting circuit, and is used to form a carrier envelope by changing the input level of the square wave signal to modulate the RF carrier signal output by the RF signal transmitting circuit so that the RF carrier signal meets the format requirements of the communication test requirements.

3. The test circuit according to claim 1 or 2, characterized in that: The control signal comprises a digital signal with the same frequency and opposite phase; the test signal comprises a differential sinusoidal signal with the same frequency and opposite phase; and the processing signal comprises a differential digital signal with the same frequency and opposite phase.

4. The test circuit according to claim 1, characterized in that: The RF control chip to be tested includes at least one transceiver mode and / or at least one transceiver rate; the test circuit is used to test the at least one transceiver mode and / or the at least one transceiver rate of the RF control chip to be tested.

5. The test circuit according to claim 1, characterized in that: The test circuit also includes a radio frequency power supply circuit electrically connected to the radio frequency signal transmitting circuit, and the radio frequency power supply circuit is used to supply power to the radio frequency signal transmitting circuit.

6. The test circuit according to claim 1, characterized in that: The test circuit also includes a chip power supply circuit electrically connected to the radio frequency control chip to be tested, and the chip power supply circuit is used to supply power to the radio frequency control chip.

7. A method for testing a radio frequency control chip, characterized in that: Using the test circuit as described in any one of claims 1 to 6; the test method comprises: The digital signal processing circuit inputs a control signal to the radio frequency signal transmitting circuit, and provides a clock signal to the radio frequency control chip to be tested, wherein the clock signal and the control signal are synchronous signals; The RF signal transmitting circuit generates a RF carrier signal according to the control signal, shapes the RF carrier signal, and transmits a test signal to the RF control chip to be tested, so as to test the RF control chip to be tested; and The digital signal processing circuit samples and analyzes the processing signal output by the radio frequency control chip to be tested, and determines the test result of the radio frequency control chip to be tested.

8. The testing method according to claim 7, characterized in that: The control signal includes a square wave signal having a frequency of at least 13.56 MHz or an integer multiple thereof; the digital signal processing circuit inputs the control signal to the radio frequency signal transmitting circuit, including: The digital signal processing circuit inputs a square wave signal with a frequency of at least 13.56 MHz or an integer multiple thereof to the RF signal transmitting circuit, and forms a carrier envelope by changing the input level of the square wave signal to modulate the RF carrier signal output by the RF signal transmitting circuit so that the RF carrier signal meets the format requirements of the communication test.

9. The testing method according to claim 7, characterized in that: The control signal comprises a digital signal with the same frequency and opposite phase; the test signal comprises a differential sinusoidal signal with the same frequency and opposite phase; and the processing signal comprises a differential digital signal with the same frequency and opposite phase.

10. The testing method according to claim 7, characterized in that: The radio frequency control chip to be tested includes at least one transceiver mode and / or at least one transceiver rate; the digital signal processing circuit samples and analyzes the processed signal output by the radio frequency control chip to be tested to determine the test result of the radio frequency control chip to be tested, including: The digital signal processing circuit samples and analyzes different processing signals of the at least one transceiver mode and / or the at least one transceiver rate of the radio frequency control chip to be tested, and determines a test result of the radio frequency control chip to be tested.

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