Array substrate and display panel

Abstract

The embodiment of the present application discloses an array substrate and a display panel, comprising a plurality of pixel units arranged in an array, for each pixel unit, the array substrate comprises a driving circuit layer, a first passivation layer, a first electrode layer, a second passivation layer and a second electrode layer which are sequentially arranged on the surface of a substrate, the first electrode layer comprises a plurality of strip electrodes arranged in parallel at a preset distance, the second electrode layer is arranged in a flat plate shape covering the second passivation layer, the orthographic projection of the first electrode layer on the substrate is located in the orthographic projection of the second electrode layer on the substrate, the display medium is driven by the first electrode layer and the second electrode layer respectively, so as to control the pixel unit to emit light with different brightness and different viewing angles, thereby realizing compatible large viewing angle and high brightness display.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to array substrates and display panels. Background Technology

[0002] With the development of optoelectronic display technology and semiconductor manufacturing technology, Thin Film Transistor-Liquid Crystal Display (TFT-LCD) has become one of the mainstream display devices due to its advantages such as thinness, energy saving, and high display quality, as well as its mature and stable manufacturing process. TFT-LCD has several commonly used display modes, such as Vertical Alignment (VA) display, Horizontal Alignment (IPS) display, and Twisted Alignment (TN) display. Among them, the VA mode has better dark state performance and better contrast compared to other display modes, but its viewing angle is relatively poor. Currently, multi-domain display is often used to improve the viewing angle of VA displays, such as 4-domain and 8-domain. Among them, multi-domain display can make the cumulative effect of human eyes better and effectively solve the problem of color deviation. However, because the overall brightness of 4-domain and 8-domain panels is relatively low, they cannot be compatible with high-brightness displays. Summary of the Invention

[0003] In view of the shortcomings of the prior art, this application provides an array substrate and display panel that can effectively accommodate wide viewing angles and high brightness.

[0004] This application provides an array substrate, including a plurality of pixel units arranged in an array. For each pixel unit, the array substrate includes a driving circuit layer, a first passivation layer, a first electrode layer, a second passivation layer and a second electrode layer, which are sequentially stacked on the surface of a substrate. The first electrode layer includes a plurality of strip electrodes spaced at a predetermined distance and arranged in parallel with each other. The second electrode layer is a flat plate covering the second passivation layer. The orthographic projection of the first electrode layer on the substrate is located within the orthographic projection of the second electrode layer on the substrate.

[0005] Optionally, the pixel unit includes a first pixel area and a second pixel area, the first electrode layer includes a first main electrode and a first sub-electrode, the first main electrode is set corresponding to the first pixel area and is used to drive the first pixel area, the first sub-electrode is set corresponding to the second pixel area and is used to drive the second pixel area, and the second electrode layer is set corresponding to the first pixel area and the second pixel area and is used to drive the first pixel area and the second pixel area simultaneously.

[0006] Optionally, corresponding to the first pixel area, the driving circuit layer includes a first switch and a second switch, which are connected in series. The first switch is also electrically connected to the data input terminal and the first main electrode, respectively. The second switch is also electrically connected to the second electrode layer. The first main electrode receives data signals from the data input terminal through the first switch, and the second electrode layer receives data signals from the data input terminal through the first and second switches. Corresponding to the second pixel area, the driving circuit layer also includes a third switch and a fourth switch, which are connected in series. The third switch is also electrically connected to the data input terminal and the first sub-electrode, and the first sub-electrode receives data signals from the data input terminal through the third switch.

[0007] Optionally, the array substrate further includes multiple data lines and multiple scan lines. Pixel units are disposed at the intersection of the data lines and scan lines, and are electrically connected to the data lines and scan lines. Pixel units are used to receive scan signals from the scan lines and data signals from the data lines according to the scan signals. The control terminal of the first switch is electrically connected to the scan line, and the first conductive terminal of the first switch is electrically connected to the data line through a data input terminal. The second conductive terminal of the first switch is electrically connected to the first main electrode. The control terminal of the third switch is electrically connected to the scan line, the first conductive terminal of the third switch is electrically connected to the data line, and the second conductive terminal of the third switch is electrically connected to the first sub-electrode. The first and third switches are simultaneously turned on under the control of the scan signal to transmit data signals to the first main electrode and the first sub-electrode in the first electrode layer.

[0008] Optionally, the driving circuit layer further includes a voltage dividing capacitor. The control terminal of the second switch is electrically connected to the first control signal terminal, the first conductive terminal of the second switch is electrically connected to the second conductive terminal of the first switch, and the second conductive terminal of the second switch is electrically connected to the second electrode layer. The second switch is used to conduct under the control of the first control signal terminal to transmit data signals to the second electrode layer. The control terminal of the fourth switch is electrically connected to the second control signal terminal, the first conductive terminal of the fourth switch is electrically connected to the second conductive terminal of the third switch, and the second conductive terminal of the fourth switch is electrically connected to the voltage dividing capacitor. The fourth switch is used to conduct under the control of the second control signal terminal to transmit data signals to the voltage dividing capacitor.

[0009] Optionally, the fourth switch and the second switch are not turned on at the same time. When the second switch is turned on, the data signal is loaded and transmitted to the second electrode layer through the data input terminal. When the fourth switch is turned off, the first sub-electrode and the main electrode receive the same data signal and are loaded with the same voltage. When the fourth switch is turned on, the data signal loaded on the first sub-electrode is partially released through the fourth switch so that it is loaded with a different voltage than the first main electrode.

[0010] This application also provides a display panel, including a counter substrate, a display medium layer and the aforementioned array substrate. The array substrate and the counter substrate are arranged parallel to each other with a preset distance between them. The display medium layer is disposed between the array substrate and the counter substrate. The counter substrate includes a common electrode. The array substrate and the counter substrate are used to form an electric field to drive the display medium in the display medium layer to rotate and emit light. The second electrode layer does not simultaneously form an electric field with the common electrode to drive the display medium layer to perform image display.

[0011] Optionally, the first pixel region includes four first sub-pixel regions arranged in an array, and the second pixel region includes four second sub-pixel regions arranged in an array. The first main electrode is used to form different electric fields with the common electrode according to the data signal to drive the display media in the four first sub-pixel regions to rotate at different angles to emit four different brightness levels of light. The first secondary electrode forms different electric fields with the common electrode according to the received data signal to drive the display media in the four second sub-pixel regions to rotate at different angles to emit four different brightness levels of light. When the first main electrode and the first secondary electrode are applied to the same voltage, the four types of light emitted from the first pixel region have the same brightness as the four types of light emitted from the second pixel region. When the first main electrode and the first secondary electrode are applied to different voltages, the four types of light emitted from the first pixel region are different from the four types of light emitted from the second pixel region. The second electrode layer forms an electric field with the common electrode according to the received data signal to drive the display media in the first and second sub-pixel regions to rotate at the same angle to emit light of the same brightness.

[0012] Optionally, corresponding to the first pixel area, the driving circuit layer further includes a first pixel capacitor and a first storage capacitor. The first pixel capacitor and the first storage capacitor are formed by coupling between the first main electrode and the common electrode. The second conductive terminal of the first switching transistor is electrically connected to the first pixel capacitor and the first storage capacitor for transmitting data to the first pixel capacitor and the first storage capacitor.

[0013] Optionally, corresponding to the second pixel area, the driving circuit layer further includes a second pixel capacitor and a second storage capacitor. The second pixel capacitor and the second storage capacitor are formed by coupling between the first sub-electrode and the common electrode. The second conductive terminal of the third switch is electrically connected to the second pixel capacitor and the second storage capacitor for transmitting data to the second pixel capacitor and the second storage capacitor.

[0014] Optionally, when the first, second, and third switches are turned on and the fourth switch is turned off, the second electrode layer forms an electric field with the common electrode according to the data signal to drive the display medium to emit the same light, and the first pixel area and the second pixel area emit light with the same first brightness; when the first and third switches are turned on and the second and fourth switches are turned off, the first main electrode and the first sub-electrode are loaded with the same voltage, and the four types of light emitted from the first pixel area are consistent with the four types of light emitted from the second pixel area and have a second brightness, the first brightness being greater than the second brightness; when the first, third, and fourth switches are turned on and the second switch is turned off, the first sub-electrode releases part of the data signal through the voltage dividing capacitor, the first main electrode and the first sub-electrode are loaded with different voltages, and the four types of light emitted from the first pixel area are different from the four types of light emitted from the second pixel area.

[0015] Compared to the problems of existing technologies, this application sets up a first electrode layer and a second electrode layer so that the first electrode layer and the second electrode layer can drive the display medium to rotate at different times. Since the first electrode layer and the second electrode layer have different structures, the rotation angle of the corresponding display medium can be controlled. Therefore, the switching between the large viewing angle and the high brightness mode can be achieved by switching the first electrode layer and the second electrode layer, so that the display panel can be compatible with both high brightness and large viewing angle display modes. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a display device provided in the first embodiment of this application;

[0018] Figure 2 for Figure 1 A schematic diagram of the side structure of the central display panel;

[0019] Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the central display panel;

[0020] Figure 4 This is a schematic diagram of the cross-sectional structure of the corresponding pixel unit in the array substrate;

[0021] Figure 5 for Figure 4 A schematic diagram of the planar layout of the first electrode layer;

[0022] Figure 6 for Figure 4 Schematic diagram of the planar layout of the second electrode layer;

[0023] Figure 7 for Figure 3 A schematic diagram of the equivalent circuit of the driving circuit in a pixel unit.

[0024] Explanation of reference numerals in the attached drawings: Display device - 100, Display panel - 10, Power module - 20, Display area - 10a, Non-display area - 10b, Timing control circuit - 11, Data driving circuit - 12, Scan driving circuit - 13, Pixel unit - 30, Backlight module - 17, Common electrode - Vcom, Array substrate - 10c, Display dielectric layer - 10e, Opposing substrate - 10d, Clock signal - CLK, Horizontal synchronization signal - Hsyn, Vertical synchronization signal - Vsyn, Gate output control signal - Cg, Source output control signal - Cs, First direction - F1, Second direction - F2, m data lines - S1~Sm, n scan lines - G1~Gn, First pixel area - 31, Second pixel area - 32, First sub-pixel area - 311, Second sub-pixel area - 321, Slit - st, Substrate - 101, Driving circuit layer - 102, First passivation layer - 103, First electrode layer - 104. Second passivation layer - 105, second electrode layer - 106, first conductive layer - 1021, first insulating layer - 1022, active layer - 1023, second conductive layer - 1024, first gate - Gate1, second gate - Gate2, first sub-active layer - a1, second sub-active layer - a2, first source - s1, first drain - d1, second source - s2, second drain - d2, first via - H1, second via - H2, first main electrode - 1041, First sub-electrode - 1042, i-th scan line - Gi, j-th data line - Sj, First switch transistor - T1, Second switch transistor - T2, Third switch transistor - T3, Fourth switch transistor - T4, First pixel capacitor - Clc1, First storage capacitor - Cst1, First capacitor - C1, Second pixel capacitor - Clc2, Second storage capacitor - Cst2, First control signal terminal - K1, Second control signal terminal - K2, Second capacitor - C2. Detailed Implementation

[0025] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0026] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order.

[0028] Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding functions, operations, elements, etc., disclosed, but do not limit the inclusion of one or more other functions, operations, elements, etc. Additionally, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of this application, "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0030] Please see Figure 1 , Figure 1This is a schematic diagram of a display device according to the first embodiment of this application. The display device 100 includes a display panel 10 and a power module 20, which is disposed on the back of the display panel 10, i.e., the non-display surface of the display panel 10. The power module 20 is used to provide power voltage for the display panel 10 to display images. In this embodiment, the display device 100 can be a portable electronic device, such as a mobile phone or tablet computer.

[0031] Please see Figure 2 , Figure 2 for Figure 1 A schematic diagram of the side structure of the central display panel.

[0032] The display panel 10 includes an array substrate 10c and a counter substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the counter substrate 10d. A common electrode Vcom disposed on the array substrate 10c and the counter substrate 10d generates a corresponding electric field based on a data signal (Data), thereby driving the display medium in the display medium layer 10e to emit light of corresponding brightness to perform image display. The display medium can be liquid crystal molecules, miniLED, Micro-LED, OLED, etc., and this application does not limit its use.

[0033] Taking a liquid crystal display panel as an example, the display medium in the display medium layer 10e is liquid crystal molecules. The display panel 10 also includes a back light module 17 (BM), wherein the back light module 17 is used to provide light for display to the display medium layer 10e. The liquid crystal molecules deflect relative angles according to the data signal so as to emit the light transmitted by the back light module 17 to the opposing substrate to perform image display.

[0034] Please refer to the following: Figure 3 , Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the central display panel.

[0035] like Figure 3 As shown, the display panel 10 also includes a timing control circuit 11, a data driving circuit 12, and a scan driving circuit 13. The timing control circuit 11, the data driving circuit 12, and the scan driving circuit 13 are disposed in the non-display area 10b of the display panel 10.

[0036] The display area 10a of the display panel 10 has m data lines (Source lines) S1 to Sm and n scan lines (Gate lines) G1 to Gn arranged in a grid pattern. The m data lines S1 to Sm extend along a first direction F1, and the n scan lines G1 to Gn extend along a second direction F2. The first direction F1 and the second direction F2 are perpendicular to each other. Pixel units 30 are disposed at the intersections of the n scan lines G1 to Gn and the m data lines S1 to Sm.

[0037] The timing control circuit 11 receives an image signal Dv representing image information from an external signal source, obtains a clock signal CLK for synchronization, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn, and outputs a gate output control signal Cg for controlling the scan drive circuit 13, a source output control signal Cs for controlling the data drive circuit 12, and a data signal representing image information. In this embodiment, the timing control circuit 11 performs data adjustment processing on the original data signal to obtain a data signal, and then transmits the data signal to the data drive circuit 12.

[0038] m data lines S1 to Sm are connected to the data driving circuit 12 and are used to receive data signals provided by the data driving circuit 12, which are stored and transmitted in the form of grayscale values. n scan lines G1 to Gn are connected to the scan driving circuit 13 and are used by the self-scanning driving circuit 13 to receive scan signals.

[0039] Under the control of n scan lines G1 to Gn, the pixel unit 30 receives the grayscale data voltage of the corresponding data signal provided by m data lines S1 to Sm within a predetermined time period, and drives the display medium layer 10e to deflect at the corresponding angle, thereby emitting light of corresponding brightness according to the corresponding angle of deflection, so as to achieve image display by emitting light of corresponding brightness according to the image signal.

[0040] The scan drive circuit 13 receives the gate output control signal Cg from the timing control circuit 11 and outputs scan signals to n scan lines G1 to Gn. The data drive circuit 12 receives the source output control signal Cs from the timing control circuit 11 and outputs data signals to m data lines S1 to Sm for image display by the driving elements in each pixel unit 30 in the display area 10a. The data signals provided to the display panel 10 are analog grayscale voltages. The scan drive circuit 13 outputs scan signals to control the pixel unit 30 to receive the data signals output by the data drive circuit 12, thereby controlling the pixel unit 30 to display the corresponding image.

[0041] Please refer to the following: Figure 4 , Figure 5 and Figure 6 , Figure 4This is a schematic diagram of the cross-sectional structure of the corresponding pixel unit in the array substrate.

[0042] Figure 5 for Figure 4 A schematic diagram of the planar layout of the first electrode layer 104. Figure 6 for Figure 4 A schematic diagram of the planar layout of the second electrode layer 106.

[0043] like Figure 4 As shown, for each pixel unit 30, the array substrate 10c includes a substrate 101, a driving circuit layer 102, a first passivation layer 103, a first electrode layer 104, a second passivation layer 105, and a second electrode layer 106, which are stacked sequentially along the thickness direction. The first electrode layer 104 includes a plurality of strip electrodes spaced at a predetermined distance and arranged parallel to each other. The second electrode layer 106 is flat and covers the second passivation layer 105. The orthographic projection of the first electrode layer 104 on the substrate 101 is located within the orthographic projection of the second electrode layer 106 on the substrate 101, that is, the second electrode layer 106 covers the first electrode layer 104.

[0044] The driving circuit layer 102 includes a first conductive layer 1021, a first insulating layer 1022, an active layer 1023, and a second conductive layer 1024. The first conductive layer 1021 is stacked on the substrate 101 along the thickness direction and includes a first gate Gate1 and a second gate Gate2 disposed at a predetermined distance. The first insulating layer 1022 covers the first gate Gate1 and the second gate Gate2.

[0045] The active layer 1023 is stacked on the side of the first insulating layer 1022 away from the first conductive layer 1021, corresponding to the first pixel region 31. Figure 5 The active layer 1023 includes a first sub-active layer a1 and a second sub-active layer a2. The first sub-active layer a1 and the second sub-active layer a2 are separated by a preset distance. The projection of the first sub-active layer a1 on the substrate 101 along the thickness direction coincides with the first gate Gate1, and the projection of the second sub-active layer a2 on the substrate 101 along the thickness direction coincides with the second gate Gate2.

[0046] The second conductive layer 1024 is stacked on the side of the first insulating layer 1022 away from the first conductive layer 1021. The second conductive layer 1024 partially covers the active layer 1023. The second conductive layer 1024 includes a first source s1, a first drain d1, a second source s2, and a second drain d2. The first source s1 and the first drain d1 are respectively disposed on both sides of the first sub-active layer a1 and partially cover the first active layer a1. The second source s2 and the second drain d2 are respectively disposed on both sides of the second sub-insulating layer 104b and partially cover the second active layer a2. The first gate Gate1, the first source s1, the first drain d1, and the first active layer a1 constitute the first switch T1. The second gate Gate2, the second source s2, the second drain d2, and the second active layer a2 constitute the second switch T2. The first drain d1 is electrically connected to the second source s2.

[0047] A first passivation layer 103 is stacked on the side of the second conductive layer 1024 away from the first insulating layer 1022, and covers the active layer 1023 and the second conductive layer 1024. A first electrode layer 104 is stacked on the side of the first passivation layer 103 away from the second conductive layer 1024. The first passivation layer 103 includes a first via H1, and the first electrode layer 104 is electrically connected to the first drain electrode d1 through the first via H1.

[0048] The second passivation layer 105 is stacked on the side of the first electrode layer 104 away from the first passivation layer 103, and the second electrode layer 106 is stacked on the side of the second passivation layer 105 away from the first electrode layer 104. The first passivation layer 103 and the second passivation layer 105 are provided with a second through hole H2 at the position corresponding to the second drain d2. The second electrode layer 106 is electrically connected to the second drain d2 through the second through hole H2.

[0049] like Figure 5 and Figure 6 As shown, the pixel unit 30 includes a first pixel region 31 and a second pixel region 32 arranged adjacent to each other. The first pixel region 31 and the second pixel region 32 each include four sub-pixel regions, that is, the first pixel region 31 includes four first sub-pixel regions 311, and the second pixel region 32 includes four second sub-pixel regions 321. In other words, the first pixel region 31 and the second pixel region 32 constitute a pixel structure with a two-region eight-domain vertical alignment (VA) architecture. The first electrode layer 104 includes a first main electrode 1041 and a first sub-electrode 1042. The first main electrode 1041 is disposed corresponding to the first pixel region 31, and the first sub-electrode 1042 is disposed corresponding to the second pixel region 32. The first main electrode 1041 and the first sub-electrode 1042 are provided with multiple slits st arranged at intervals and parallel to each other. The second electrode layer 106 is flat and parallel to the first electrode layer 104 at a predetermined distance.

[0050] Corresponding to the first pixel area 31, the driving circuit layer 102 includes a first switch T1 and a second switch T2, which are connected in series. The first switch T1 is also electrically connected to the data input terminal (data line S) and the first main electrode 1041. The second switch T2 is also electrically connected to the second electrode layer 106. The first main electrode 1041 receives data signals from the data input terminal through the first switch T1, and the second electrode layer 106 receives data signals from the data input terminal through the first switch T1 and the second switch T2. Corresponding to the second pixel area 32, the driving circuit layer 102 also includes a third switch T3. Figure 7 ) and the fourth switch T4 ( Figure 7 The third switch T3 and the fourth switch T4 are connected in series. The third switch T3 is also electrically connected to the data input terminal and the first sub-electrode 1042. The first sub-electrode 1042 receives data signals from the data input terminal through the third switch T3.

[0051] When the first main electrode 1041 and the common electrode Vcom form an electric field to drive the first pixel area 31 to emit light, the liquid crystals in the four first sub-pixel areas 311 rotate at different angles to emit four different brightness levels of light. When the first secondary electrode 1042 and the common electrode Vcom form an electric field to drive the second pixel area 32 to emit light, the liquid crystals in the four second sub-pixel areas 321 rotate at different angles to emit four different brightness levels of light. The first main electrode 1041 and the first secondary electrode 1042 have the same structure, meaning that under the same voltage driving, the four rotation angles of the liquid crystals in the first pixel area 31 and the second pixel area 32 are the same, making the four types of light emitted from the first pixel area 31 and the second pixel area 32 consistent, thus forming a 4-domain pixel display. When an electric field is formed between the second electrode layer 106 and the common electrode Vcom to drive the pixel unit 30 to emit light, the first pixel area 31 and the second pixel area 32 simultaneously emit light of the same brightness to form a 1-domain pixel display.

[0052] Please see Figure 7 , Figure 7 for Figure 3 A schematic diagram of the equivalent circuit of the driving circuit in a pixel unit.

[0053] like Figure 7As shown, corresponding to the first pixel area 31, the driving circuit layer 102 includes a first switch transistor T1 and a second switch transistor T2. The control terminal of the first switch transistor T1 is electrically connected to the i-th scan line Gi, the first conductive terminal of the first switch transistor T1 is electrically connected to the j-th data line Sj, and the second conductive terminal of the first switch transistor T1 is electrically connected to the first main electrode 1041. The first main electrode 1041 and the common electrode Vcom are coupled to form a first pixel capacitor Clc1 and a first storage capacitor Cst1. Therefore, it is equivalent to the second conductive terminal of the first switch transistor T1 being electrically connected to the first pixel capacitor Clc1 and the first storage capacitor Cst1. Where 1≤i≤n, 1≤j≤m

[0054] The control terminal of the second switch transistor T2 is electrically connected to the first control signal terminal K1. The first conductive terminal of the second switch transistor T2 is electrically connected to the second conductive terminal of the first switch transistor T1. The second conductive terminal of the second switch transistor T2 is electrically connected to the second electrode layer 106. The second electrode layer 106 and the common electrode Vcom are coupled to form a first capacitor C1. Therefore, it is equivalent to being electrically connected to the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is electrically connected to the common electrode Vcom.

[0055] Corresponding to the second pixel area 32, the driving circuit layer 102 also includes a third switch T3 and a fourth switch T4. The control terminal of the third switch T3 is electrically connected to the i-th scan line Gi, the first conductive terminal of the third switch T3 is electrically connected to the j-th data line Sj, and the second conductive terminal of the third switch T3 is electrically connected to the first sub-electrode 1042. The first sub-electrode 1042 and the common electrode Vcom are coupled to form a second pixel capacitor Clc2 and a second storage capacitor Cst2. Therefore, it is equivalent to the second conductive terminal of the third switch T3 being electrically connected to the first terminal of the second pixel capacitor Clc2 and the first terminal of the second storage capacitor Cst2, the second terminal of the second pixel capacitor Clc2 being electrically connected to the common electrode Vcom, and the second terminal of the second storage capacitor Cst2 being electrically connected to the common electrode Vcom.

[0056] The control terminal of the fourth switch transistor T4 is electrically connected to the second control signal terminal K2. The first conductive terminal of the fourth switch transistor T4 is electrically connected to the second conductive terminal of the third switch transistor T3. The second conductive terminal of the fourth switch transistor T4 is electrically connected to the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is electrically connected to the common electrode Vcom. The second capacitor C2 is a voltage divider capacitor. When the fourth switch transistor T4 is turned on, part of the voltage transmitted to the first sub-electrode 1042 is released to the second capacitor C2.

[0057] The display panel 10 includes a first display mode, a second display mode, and a third display mode. When the display panel 10 executes the first display mode, the first switch T1, the second switch T2, and the third switch T3 are turned on, and the fourth switch T4 is turned off, which is used to transmit data signals to the second electrode layer 106. Since the second electrode layer 106 is a flat, flat surface, an electric field is formed between the second electrode layer 106 and the common electrode Vcom to control the liquid crystal molecules in the four sub-pixel areas of the first pixel area 31 and the second pixel area 32 to rotate at the same angle, thereby emitting light of the same brightness to achieve high brightness display, that is, to achieve 1-domain pixel display.

[0058] When the display panel 10 executes the second display mode, the first switch T1 and the third switch T3 are turned on, while the second switch T2 and the fourth switch T4 are turned off. Data signals are transmitted via the first switch T1 to the first main electrode 1041 and stored in the first pixel capacitor Clc1 and the first storage capacitor Cst1. This is used to control the four first sub-pixel areas 311 in the first pixel area 31 to emit four different brightness levels of light. Data signals are also transmitted via the third switch T3 to the first secondary electrode 1042 and stored in the second pixel capacitor Clc2 and the second storage capacitor Cst2. This is used to control the four second sub-pixels in the second pixel area 32. Region 321 emits four different types of light rays. The first pixel capacitor Clc1 and the second pixel capacitor Clc2 have the same capacitance value, and the first storage capacitor Cst1 and the second storage capacitor Cst2 have the same capacitance value. Therefore, the four different types of light rays emitted from the first pixel region 31 are consistent with the four different types of light rays emitted from the second pixel region 32. That is, each pixel unit 30 emits four different types of bright lines to achieve image display corresponding to the 4-domain pixel architecture. This ensures that when the user views the image from a wide viewing angle, the liquid crystal rotation angle is not in the same direction, resulting in a better cumulative effect for the human eye and thus solving the problem of color shift at wide viewing angles.

[0059] When the display panel 10 executes the third display mode, the first switch T1, the third switch T3, and the fourth switch T4 are turned on, and the second switch T2 is turned off. The data signal is transmitted to the first main electrode 1041 via the first switch T1 and stored in the first pixel capacitor Clc1 and the first storage capacitor Cst1. This is used to control the four first sub-pixel areas 311 in the first pixel area 31 to emit four different types of light. The data signal is also transmitted to the first secondary electrode 1042 via the third switch T3 and stored in the second pixel capacitor Clc2 and the second storage capacitor Cst2. This is used to control the four second sub-pixel areas 321 in the second pixel area 32 to emit four different types of light. The data signal is also transmitted to the fourth switch T4. Transmission from tube T4 is transmitted to the second capacitor C2. The second capacitor C2 is used to divide the voltage between the second pixel capacitor Clc2 and the second storage capacitor Cst2, so as to control that the charge stored in the second pixel capacitor Clc and the second storage capacitor Cst2 is less than the charge in the first pixel capacitor Clc1 and the first storage capacitor Cst1. This ensures that the four different brightness light rays emitted from the first pixel area 31 are different from the four different brightness light rays emitted from the second pixel area 32. That is, each pixel unit 30 emits eight different brightness light lines to achieve the image display corresponding to the 8-domain pixel architecture. This makes it so that when the user views at a wide viewing angle, the liquid crystal rotation angle is not in the same direction, resulting in a better cumulative effect for the human eye, thereby further solving the color shift problem at wide viewing angles.

[0060] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. An array substrate, characterized by, The array substrate comprises a plurality of pixel units arranged in an array, and for each pixel unit, the array substrate comprises a driving circuit layer, a first passivation layer, a first electrode layer, a second passivation layer and a second electrode layer which are sequentially arranged on the surface of a substrate, the first electrode layer comprises a plurality of strip electrodes, the second electrode layer is in the form of a flat plate and covers the second passivation layer, and the orthographic projection of the first electrode layer on the substrate is located within the orthographic projection of the second electrode layer on the substrate; The pixel unit comprises a first pixel region and a second pixel region, the first electrode layer comprises a first main electrode and a first auxiliary electrode, the first main electrode is arranged corresponding to the first pixel region and is used to form an electric field with a common electrode to drive the first pixel region, the first auxiliary electrode is arranged corresponding to the second pixel region and is used to form an electric field with the common electrode to drive the second pixel region, and the second electrode layer is arranged corresponding to the first pixel region and the second pixel region and is used to form an electric field with the common electrode to simultaneously drive the first pixel region and the second pixel region; For the first pixel region, the driving circuit layer comprises a first switch tube and a second switch tube, the first switch tube and the second switch tube are connected in series, the first switch tube is further electrically connected to a data input end and the first main electrode respectively, and the second switch tube is further electrically connected to the second electrode layer, so that the first main electrode receives a data signal from the data input end through the first switch tube, and the second electrode layer receives the data signal from the data input end through the first switch tube and the second switch tube; For the second pixel region, the driving circuit layer further comprises a third switch tube and a fourth switch tube, the third switch tube and the fourth switch tube are connected in series, the third switch tube is further electrically connected to the data input end and the first auxiliary electrode, and the first auxiliary electrode receives the data signal from the data input end through the third switch tube.

2. The array substrate of claim 1, wherein, The array substrate further comprises a plurality of data lines and a plurality of scan lines, the pixel unit is arranged at the intersection of the data line and the scan line, and the pixel unit is electrically connected to the data line and the scan line, used to receive a scan signal from the scan line and receive the data signal from the data line according to the scan signal; The control end of the first switch tube is electrically connected to the scan line, the first conductive end of the first switch tube is electrically connected to the data line through the data input end, and the second conductive end of the first switch tube is electrically connected to the first main electrode; the control end of the third switch tube is electrically connected to the scan line, the first conductive end of the third switch tube is electrically connected to the data line, and the second conductive end of the third switch tube is electrically connected to the first auxiliary electrode; and the first switch tube and the third switch tube are used to be turned on simultaneously under the control of the scan signal, so as to transmit the data signal to the first main electrode and the first auxiliary electrode in the first electrode layer.

3. The array substrate of claim 2, wherein, The driving circuit layer further comprises a voltage dividing capacitor, a control end of the second switch tube is electrically connected to a first control signal end, a first conductive end of the second switch tube is electrically connected to a second conductive end of the first switch tube, and a second conductive end of the second switch tube is electrically connected to the second electrode layer, and the second switch tube is used for conducting under the control of the first control signal end to transmit the data signal to the second electrode layer. The control end of the fourth switch tube is electrically connected to a second control signal end, the control end of the fourth switch tube is electrically connected to the second control signal end, a first conductive end of the fourth switch tube is electrically connected to a second conductive end of the third switch tube, and a second conductive end of the fourth switch tube is electrically connected to the voltage dividing capacitor, and the fourth switch tube is used for conducting under the control of the second control signal end to transmit the data signal to the voltage dividing capacitor.

4. The array substrate of claim 3, wherein, The fourth switch tube and the second switch tube are not simultaneously conducting, and if the second switch tube is conducting, the data signal is transmitted to the second electrode layer through the data input end; If the fourth switch tube is cut off, the first auxiliary electrode and the first main electrode receive the same data signal to be loaded to the same voltage, and if the fourth switch tube is conducting, the data signal loaded by the first auxiliary electrode is partially released through the fourth switch tube to be loaded to a different voltage from the first main electrode.

5. A display panel, characterized by, The display device comprises a counter substrate, a display medium layer and the array substrate as claimed in any one of claims 1-4, the array substrate and the counter substrate are arranged in parallel at a preset distance, the display medium layer is arranged between the array substrate and the counter substrate, the counter substrate comprises a common electrode, and the array substrate and the counter substrate are used for forming an electric field to drive display medium in the display medium layer to rotate to emit light rays, wherein the second electrode layer and the first electrode layer do not simultaneously form an electric field with the common electrode to drive the display medium layer to perform image display.

6. The display panel of claim 5, wherein, The first pixel area comprises four first sub-pixel areas arranged in an array, and the extending directions of the strip-shaped electrodes in different first sub-pixel areas are different, and the second pixel area comprises four second sub-pixel areas arranged in an array, and the extending directions of the strip-shaped electrodes in different second sub-pixel areas are different. The first main electrode is used for forming an electric field with the common electrode according to the data signal to drive the display medium in the four first sub-pixel areas to rotate respectively to emit light rays of four different brightnesses, and the first auxiliary electrode forms an electric field with the common electrode according to the received data signal to drive the display medium in the four second sub-pixel areas to rotate to emit light rays of four different brightnesses, wherein if the first main electrode and the first auxiliary electrode are loaded to the same voltage, the four light rays emitted by the first pixel area are consistent with the four light rays emitted by the second pixel area in brightness, and if the first main electrode and the first auxiliary electrode are loaded to different voltages, the four light rays emitted by the first pixel area are different from the four light rays emitted by the second pixel area. The second electrode layer forms an electric field with the common electrode according to the received data signal to drive the display medium in the first sub-pixel region and the second sub-pixel region to rotate the same angle to emit the same brightness of light.

7. The display panel of claim 6, wherein, Corresponding to the first pixel region, the driving circuit layer further comprises a first pixel capacitor and a first storage capacitor, the first pixel capacitor and the first storage capacitor are coupled between the first main electrode and the common electrode, and the second conductive end of the first switch tube is electrically connected to the first pixel capacitor and the first storage capacitor, for transmitting the data signal to the first pixel capacitor and the first storage capacitor.

8. The display panel of claim 7, wherein, Corresponding to the second pixel region, the driving circuit layer further comprises a second pixel capacitor and a second storage capacitor, the second pixel capacitor and the second storage capacitor are coupled between the first auxiliary electrode and the common electrode, and the second conductive end of the third switch tube is electrically connected to the second pixel capacitor and the second storage capacitor, for transmitting the data signal to the second pixel capacitor and the second storage capacitor.

9. The display panel of claim 8, wherein, when the first switch tube, the second switch tube and the third switch tube are turned on and the fourth switch tube is turned off, the second electrode layer drives the display medium to rotate the same angle according to the data signal and the common electrode, and the first pixel region and the second pixel region emit the same first brightness of light; when the first switch tube and the third switch tube are turned on and the second switch tube and the fourth switch tube are turned off, the first main electrode and the first auxiliary electrode are loaded to the same voltage, the four kinds of light emitted by the first pixel region are consistent with the four kinds of light emitted by the second pixel region and have a second brightness, and the first brightness is greater than the second brightness; when the first switch tube, the third switch tube and the fourth switch tube are turned on and the second switch tube is turned off, the first auxiliary electrode releases part of the data signal through the voltage dividing capacitor, the first main electrode and the first auxiliary electrode are loaded to different voltages, and the four kinds of light emitted by the first pixel region are different from the four kinds of light emitted by the second pixel region.

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