Memory system and method for controlling memory system

Abstract

The embodiment of the invention relates to a memory system and a control method of the memory system. The invention provides a memory system and a control method of the memory system, which can prevent data error due to wrong reading from being transmitted to a host. According to an embodiment, a controller manages a plurality of flags respectively corresponding to a plurality of physical addresses. In response to receiving a read instruction from a host, the controller acquires a physical address mapped to a logical address specified by the read instruction, and reads data from the non-volatile memory based on the acquired physical address. The controller determines whether to transmit the read data to the host on the basis of setting the current state of the flag corresponding to the acquired physical address to a first value indicating valid data or to a second value indicating invalid data.

Description

[0001] This application is based on Japanese Patent Application No. 2023-114619 (filing date: July 12, 2023) and claims the benefit of priority. This application incorporates all the contents of the basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to a memory system and a method for controlling the memory system. Background Art

[0003] As a memory system that has become widely popular in recent years, for example, a solid state drive (SSD) including a nonvolatile memory and a controller for controlling the nonvolatile memory is known.

[0004] The memory system is usually connected to an external host and can send and receive data to and from the host. For example, in an SSD, the controller receives specific instructions from the external host and executes the processing of writing the data received from the host to the non-volatile memory, or reading the data written to the non-volatile memory and sending it to the host.

[0005] In data transmission and reception of a memory system such as an SSD, when data written in a nonvolatile memory is read and sent to a host, a technology is required to prevent wrong data (wrong data) from being sent to the host due to erroneous reading. Summary of the invention

[0006] The problem to be solved by the embodiments of the present invention is to provide a memory system and a control method of the memory system that can prevent erroneous data caused by erroneous reading from being sent to a host.

[0007] According to an embodiment, a memory system can be connected to a host. The memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory. The controller uses a first management table to manage mapping information indicating mappings between a plurality of logical addresses used by the host to access the memory system and a plurality of physical addresses of the nonvolatile memory. The controller uses a second management table to manage a plurality of flags corresponding to the plurality of physical addresses. For each of the plurality of flags, a first value indicating that data stored in a storage location of the nonvolatile memory corresponding to the corresponding physical address is valid data or a second value indicating that data is invalid data is set. In response to receiving a write command specifying a first logical address from the host, the controller assigns a first physical address to the first logical address. The controller writes the first data associated with the write command to a first storage location of the nonvolatile memory corresponding to the first physical address. The controller sets the first flag corresponding to the first physical address to the first value. The controller sets the first flag to the second value in response to the first data being set as invalid data by updating or deleting the first data. The controller obtains from the first management table a physical address mapped to the first logical address when the read command is executed in response to the first data being set as invalid data by updating or deleting the first data. The controller reads data from the nonvolatile memory based on the obtained physical address. The controller determines whether to send the read data to the host based on whether the current state of the flag corresponding to the obtained physical address is set to the first value or the second value. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a block diagram showing a configuration example of an information processing system including a memory system according to an embodiment.

[0009] Figure 2 This is a block diagram showing a configuration example showing a relationship between a plurality of channels and a plurality of flash memory dies used in a memory system according to an embodiment.

[0010] Figure 3 This is a diagram showing an example of the configuration of a super block used in the memory system according to the embodiment.

[0011] Figure 4 This is a diagram showing a configuration example of a valid flag table used in a memory system according to an embodiment.

[0012] Figure 5 It is a diagram showing a configuration example related to control of writing data and reading data in a memory system according to an embodiment.

[0013] Figure 6 It is a diagram showing the flow of write processing in the memory system according to the embodiment.

[0014] Figure 7 It is a diagram showing the flow of invalidation processing of the memory system according to the embodiment.

[0015] Figure 8 It is a diagram showing the flow of a read process of the memory system according to the embodiment.

[0016] Fig. 9 This is a diagram showing the flow of garbage collection processing in the memory system according to the embodiment.

[0017] Fig.10 It is a diagram showing a first example of write data in the memory system according to the embodiment.

[0018] Fig.11 It is a diagram showing a first example of read data in the memory system according to the embodiment.

[0019] Fig.12 This is a flowchart showing a first example of the procedure of the write process of the memory system according to the embodiment.

[0020] Fig.13 This is a flowchart showing a first example of the procedure of the read processing of the memory system according to the embodiment.

[0021] Fig.14 It is a diagram showing a second example of write data in the memory system according to the embodiment.

[0022] Fig.15 It is a diagram showing a second example of read data in the memory system according to the embodiment.

[0023] Fig.16 This is a flowchart showing a second example of the procedure of the write process of the memory system according to the embodiment.

[0024] Fig.17 This is a flowchart showing a second example of the procedure of the read processing of the memory system according to the embodiment.

[0025] Fig.18 It is a diagram showing a third example of write data in the memory system according to the embodiment.

[0026] Fig.19 It is a diagram showing a third example of read data in the memory system according to the embodiment.

[0027] Fig. 20 This is a flowchart showing a third example of the procedure of the write process of the memory system according to the embodiment.

[0028] Fig.21This is a flowchart showing a third example of the procedure of the read processing of the memory system according to the embodiment.

[0029] Fig. 22 It is a diagram showing a fourth example of write data in the memory system according to the embodiment.

[0030] Fig.23 It is a diagram showing a fourth example of read data in the memory system according to the embodiment.

[0031] Fig.24 This is a flowchart showing a fourth example of the procedure of the write process of the memory system according to the embodiment.

[0032] Fig.25 This is a flowchart showing a fourth example of the procedure of the read processing of the memory system according to the embodiment. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments will be described with reference to the drawings.

[0034] Figure 1 1 is a block diagram showing a configuration example of an information processing system 1 including a memory system according to an embodiment. The information processing system 1 includes a host (host device) 2 and an SSD (Solid State Drive) 3 as a memory system.

[0035] The host 2 is, for example, an information processing device such as a personal computer, a server computer, or a mobile device. The host 2 is connected to the SSD 3 and can access the SSD 3. Specifically, the host 2 issues a write command for writing data to the SSD 3. In addition, the host 2 issues a read command for reading data to the SSD 3.

[0036] The SSD 3 is also called a memory device, and can write data to and read data from an internal non-volatile memory.

[0037] The communication between SSD3 and host 2 is performed via bus 7. Bus 7 is a transmission line connecting host 2 and SSD3. Bus 7 is, for example, PCI express TM (PCIe TM : Peripheral Component Interconnect Express (PCIe) bus. The PCIe bus is a full duplex transmission line. The full duplex transmission line includes two transmission lines: a transmission line for sending data and input / output (I / O) commands from the host 2 to the SSD 3, and a transmission line for sending data and responses from the SSD 3 to the host 2. The I / O command is issued from the host 2 to the SSD 3, including a write command for writing data to the non-volatile memory, or a read command for reading data from the non-volatile memory.

[0038] The logical interface connecting the host 2 and the SSD 3 can be, for example, NVM express TM (NVMe TM : Non-Volatile Memory Host Controller Interface Specification) specification. In an interface according to the NVMe specification, a pair of queues including at least one submission queue (SQ, Submission Queue) and a completion queue (CQ, Completion Queue) associated with the at least one submission queue (SQ) is used to communicate between the host 2 and the SSD 3. For example, the pair of queues is called a submission queue / completion queue pair (SQ / CQ pair).

[0039] Next, the configuration of the host computer 2 will be described.

[0040] The host 2 includes a processor 21 and a memory 22 . The processor 21 and the memory 22 are connected to each other via an internal bus 20 .

[0041] The processor 21 is, for example, a CPU (Central Processing Unit). The processor 21 executes software (host software) loaded from the SSD 3 or other memory devices connected to the host 2 to the memory 22. The host software includes, for example, an operating system, a file system, and an application program.

[0042] The memory 22 is, for example, a volatile memory. The memory 22 is also referred to as a main memory, a system memory, or a host memory. The memory 22 is, for example, a dynamic random access memory (DRAM). A portion of the storage area of ​​the memory 22 is used as a host write buffer. The host write buffer is a storage area that temporarily stores data to be written to the non-volatile memory of the SSD 3. Another portion of the storage area of ​​the memory 22 is used as a host read buffer. The host read buffer is a storage area that temporarily stores data that is read from the non-volatile memory of the SSD 3 and is to be sent (transmitted) to the host.

[0043] Next, the internal structure of SSD 3 is described. Here, it is assumed that the non-volatile memory included in SSD 3 is a NAND (Not and) type flash memory, but it can also be other flash memories, or other non-volatile memories such as MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), phase change memory, etc.

[0044] The SSD 3 includes a controller 4 and a NAND flash memory 5. The NAND flash memory 5 may be a 2D flash memory or a 3D flash memory. In addition, the SSD 3 may also include a random access memory, such as a volatile memory, that is, a dynamic random access memory (DRAM) 6.

[0045] The controller 4 is a memory controller. The controller 4 is, for example, a control circuit such as a System-on-a-Chip (SoC). The controller 4 is electrically connected to each of the NAND flash memory 5 and the DRAM 6. The controller 4 processes various instructions received from the host 2. When the controller 4 receives a write instruction, it executes a process of writing data to the NAND flash memory 5. When the controller 4 receives a read instruction, it executes a process of reading data from the NAND flash memory 5. Moreover, when the controller 4 receives a trim command, it executes a process of invalidating the data stored in the NAND flash memory 5. The trim command is an instruction requesting the SSD 3 to invalidate the data, which is also called a release instruction or an unmap instruction. The invalidated data is called invalid data that is not accessed by the host 2. On the other hand, the data that may be accessed by the host 2 before being invalidated is called valid data.

[0046] For example, a toggle interface or an open NAND flash interface (ONFI) is used as a physical interface connecting the controller 4 and the NAND flash memory 5. The functions of each part of the controller 4 can be implemented by dedicated hardware, a processor executing a program, or a combination of these dedicated hardware and processors.

[0047] The NAND flash memory 5 may include a plurality of bare chips. A bare chip is also called a flash memory bare chip, a memory bare chip, a memory chip, a flash memory chip, etc. In the following description, a bare chip is called a flash memory bare chip. Figure 1 , an example is shown in which the NAND flash memory 5 includes 32 flash memory chips #0 to #31.

[0048] Each of the multiple flash memory bare chips contained in the NAND flash memory 5 is composed of multiple blocks. Each of the multiple blocks is the minimum unit of data erasing action. Each of the multiple blocks is also called a memory block or a physical block. Each of the multiple blocks includes multiple pages. Each of the multiple blocks is a unit of data writing action and data reading action. A page includes a collection of storage cells connected to the same word line. A page is also called a physical page.

[0049] The DRAM 6 is a volatile memory, and a part of the storage area of ​​the DRAM 6 is used by the controller 4 for temporarily storing data written to the NAND flash memory 5 or temporarily storing data read from the NAND flash memory 5, for example.

[0050] Next, the internal structure of the controller 4 is described. The controller 4 includes components such as a host interface (host I / F) 41, a static RAM (SRAM, Static Random Access Memory) 42, a CPU 43, a check circuit 44, an error correction circuit 45, a NAND interface (NAND I / F) 46, and a DRAM interface (DRAM I / F) 47. These components are connected to each other via an internal bus 40.

[0051] The host interface 41 is a communication interface circuit that performs communication with the host 2. The host interface 41 is implemented by, for example, a PCIe controller.

[0052] The SRAM 42 is a volatile memory. The storage area of ​​the SRAM 42 is used, for example, as a work area of ​​the CPU 43. In addition, other storage areas of the SRAM 42 can be used as storage areas for temporarily storing data to be written to the NAND flash memory 5.

[0053] The CPU 43 is a processor. The CPU 43 loads a control program (firmware) stored in the NAND flash memory 5 or a ROM (Read-Only Memory) not shown in the figure into the SRAM 42. The CPU 43 performs various processes by executing the firmware. In addition, the firmware can also be loaded into the DRAM 6.

[0054] The CPU 43 manages the data stored in the NAND flash memory 5 and the blocks included in the NAND flash memory 5 as, for example, a flash translation layer (FTL). The management of the data stored in the NAND flash memory 5 includes, for example, the management of mapping information using a logical-to-physical address translation table (L2P table) 61. The L2P table 61 is a table that stores mapping information indicating the mapping between each of a plurality of logical addresses and each of a plurality of physical addresses. The details of the mapping information will be described below.

[0055] The data stored in the storage location indicated by the physical address mapped by the logical address among the data stored in the NAND flash memory 5 is valid data. On the other hand, the data stored in the storage location indicated by the physical address not mapped by any logical address is invalid data. That is to say, even if data is stored in the storage location corresponding to the physical address, if the physical address is not mapped with the logical address, it becomes invalid data. The CPU 43 manages the block storing at least one valid data as an active block. On the other hand, the CPU 43 manages the block not storing valid data as a free block.

[0056] Furthermore, management of each block of the NAND flash memory 5 includes bad block management, wear leveling (WL), garbage collection (GC), and the like.

[0057] The check circuit 44 is a circuit for checking whether the data (read data) read from the NAND flash memory 5 is correct data. In the check circuit 44, for example, in order to check whether the read data is correct data, that is, to confirm the integrity of the read data, a check code may be used. The check circuit 44 includes, for example, a check code generation circuit 441, a check code check circuit 442, a flag check circuit 443, a PBA check circuit 444, and an LBA check circuit 445. Part or all of the check code check circuit 442, the flag check circuit 443, the PBA check circuit 444, and the LBA check circuit 445 may operate as the data check circuit 44a.

[0058] The check code generation circuit 441 generates a check code using, for example, data to be written into the NAND flash memory 5. The check code is used to check whether the data is correct data, that is, a code to confirm the matching of the data. The check code is, for example, a cyclic redundancy code (CRC) or a hash value. The check code generation circuit 441 generates a check code using at least user data. User data is data associated with a write instruction received from the host 2. For example, two check codes generated from two identical data become mutually consistent values. In addition, two check codes generated from two different data become mutually different values. Therefore, the two data determined as the check codes used to generate two consistent values ​​are mutually identical data. In addition, the two data determined as the check codes used to generate two mutually different values ​​are mutually different data.

[0059] In this way, the check code generation circuit 441 generates a check code for confirming the matching of the user data. For example, when writing data, the user data and the check code generated from the user data are written as one data group to the storage location of the write destination in the NAND flash memory 5. In addition, when reading data, for example, the check code generation circuit 441 generates a check code to be compared with the check code read from the read target storage location of the NAND flash memory 5 together with the user data.

[0060] In addition, the check code generation circuit 441 can generate a check code not only using user data, but also using a logical address (e.g., a logical block address (LBA)), a physical address (e.g., a physical block address (PBA)), or a flag. That is, the check code generation circuit 441 can, for example, use all LBAs, PBAs, and flags with user data to generate a check code for confirming the matching of information including all LBAs, PBAs, and flags with user data. Alternatively, the check code generation circuit 441 can, for example, use any combination of LBAs, PBAs, and flags with user data to generate a check code for confirming the matching of information including any combination of LBAs, PBAs, and flags with user data. Here, the flag is a 1-bit data indicating whether the data stored in a storage location in the NAND flash memory 5 represented by a certain physical address is valid data or invalid data. The value of the flag is set to the first value when the data is valid data, and is set to the second value when the data is invalid data.

[0061] The data check circuit 44a determines whether the data read from the NAND flash memory 5 is consistent with the data of the check code generated by the check code generation circuit 441. In addition, here, the data is (1) user data and / or (2) check code data generated by any combination of LBA, PBA and flag in the check code generation circuit 441. When the two are consistent, it is determined that the two are the same data. When the two are inconsistent, it is determined that the two are not the same data.

[0062] The data check circuit 44 a may include, for example, all or part of the check code check circuit 442 , the flag check circuit 443 , the PBA check circuit 444 , and the LBA check circuit 445 .

[0063] The following describes the operation of each of the check code check circuit 442 and the check circuits 443, 444, and 445 that may be included in the data check circuit 44a.

[0064] The check code checking circuit 442 is a circuit for checking whether two check codes are consistent with each other. The check code checking circuit 442 compares the check code of the data read from the NAND flash memory 5 with the check code generated by the check code generating circuit 441. When the two check codes are consistent with each other, the check code checking circuit 442 determines that the data read from the NAND flash memory 5 is the same data, that is, correct data. In addition, when the two check codes are inconsistent with each other, the check code checking circuit 442 determines that the data read from the NAND flash memory 5 is not the same data, that is, wrong data.

[0065] The flag check circuit 443 is a circuit that determines whether the current state of the flag corresponding to the physical address mapped to the logical address of the read object when reading is executed is set to the first value. That is, the flag check circuit 443 refers to the value of the flag corresponding to the physical address mapped to the logical address specified by the read instruction received from the host 2 when reading is executed, and determines whether the value of the flag continues to maintain the first value. When the flag value is the first value, the flag check circuit 443 determines that the user data read from the NAND flash memory 5 is correct data. On the other hand, when the flag value does not maintain the first value, the flag check circuit 443 determines that the user data read from the NAND flash memory 5 is wrong data.

[0066] The PBA check circuit 444 is a circuit that checks whether two physical addresses (PBAs) are consistent with each other. The PBA check circuit 444 checks, for example, whether the PBA read from the NAND flash memory 5 is consistent with the latest PBA mapped to the LBA specified by the read instruction when the read is executed. When the two PBAs are consistent with each other, the PBA check circuit 444 determines that the data read from the NAND flash memory 5 is correct data. In addition, when the two PBAs are inconsistent with each other, the PBA check circuit 444 determines that the data read from the NAND flash memory 5 is erroneous data.

[0067] The LBA check circuit 445 is a circuit that checks whether two logical addresses (LBAs) are consistent with each other. For example, the LBA check circuit 445 checks whether the latest LBA specified by the read command is consistent with the LBA read from the NAND flash memory 5 together with the read data. If the two LBAs are consistent with each other, the LBA check circuit 445 determines that the data read from the NAND flash memory 5 is correct data. In addition, if the two LBAs are inconsistent with each other, the LBA check circuit 445 determines that the data read from the NAND flash memory 5 is erroneous data.

[0068] In the read processing performed in the present embodiment, when the read data is previous data (that is, old data) corresponding to the logical address specified by the read command received from the host 2, the read data is detected as erroneous data by the check circuit 44. That is, even if the read data is data corresponding to the same logical address as the logical address specified by the read command, but the read data is not the latest data (new data) corresponding to the logical address but previous data (old data), the read data is detected as erroneous data.

[0069] In the NAND flash memory 5, when data corresponding to a certain logical address is updated, the updated data (new data) is written to a storage location different from the storage location, rather than the storage location storing the previous data (old data). As a result, multiple generations of data corresponding to the same logical address may exist in the NAND flash memory 5. Therefore, if a part of the mapping information is erroneous due to data corruption in the L2P table 61, the previous data (old data) corresponding to a certain logical address may be read out from the NAND flash memory 5.

[0070] However, according to the present embodiment, when the previous data (old data) corresponding to a certain logical address is invalidated by writing the update data (new data) corresponding to the logical address, the flag corresponding to the physical address indicating the storage location storing the previous data (old data) is set to the second value indicating invalid data. The controller 4 obtains the latest physical address mapped to the logical address (logical address of the read object) specified by the read instruction received from the host 2 when the read instruction is executed from the L2P table 61, and reads data from the NAND flash memory based on the obtained physical address. When reading the data, it is determined whether the current state of the flag corresponding to the latest physical address obtained continues to maintain the state set to the first value. In this way, it can be determined whether the data read from the NAND flash memory 5 is correct data or erroneous data. Based on the determination result, the controller 4 determines whether to send the data read from the NAND flash memory 5 to the host 2. As a result, it is possible to prevent the previous data (old data) corresponding to the logical address of the read object or the data that has been invalidated by the sorting instruction from being sent to the host 2 due to erroneous reading.

[0071] As methods for determining whether the current state of the flag corresponding to the physical address mapped to the logical address of the read target when reading is executed continues to be set to the first value, there are the first method and the second method described below.

[0072] The first method is to refer to the flag itself corresponding to the physical address mapped to the logical address of the read object when the read is executed, and use the flag check circuit 443 to determine whether the value of the flag continues to maintain the first value (logical entity map flag value determination method ("1 / 0"). Hereinafter, it may also be referred to as the flag value determination method).

[0073] The second method is a method of using a check code written together with the user data when writing to the NAND flash memory 5 to confirm the matching of information including the user data and the flag having the first value (check code determination method ("match / mismatch")).

[0074] According to the second method, when user data is read out from a storage location represented by a physical address mapped to a logical address of a read object when a read instruction is executed, a check code is also read out together with the user data. In addition, a new check code for checking the matching of information including a flag corresponding to a physical address mapped to a logical address of a read object when the read instruction is executed and information of the read user data is generated using the flag and the read user data. When the value of the flag is set to the second value, the new check code is inconsistent with the read check code. Therefore, by determining whether the new check code is consistent with the read check code, it can be determined whether the current state of the flag corresponding to the physical address mapped to the logical address of the read object when the read instruction is executed continues to maintain the first value. Therefore, it is not necessary to determine the value by referring to the flag itself through the flag check circuit 443. That is, in the case of the second method, the check circuit 44 may not include the flag check circuit 443.

[0075] In addition, as described above, the physical address of the storage location storing the previous data (old data) corresponding to a certain logical address is different from the physical address of the storage location storing the latest data (new data) corresponding to the logical address. However, even if the content of the mapping information of the L2P table 61 is correct, in the case of an erroneous operation of the address decoder in the NAND flash memory 5, data may be erroneously read from the storage location storing the previous data (old data) corresponding to the logical address. In such a case, erroneous data due to erroneous reading may be sent to the host 2.

[0076] Thus, even in the case of erroneous reading caused by an erroneous operation generated in the NAND flash memory 5, it is necessary to prevent the erroneous data from being sent to the host 2. Therefore, the controller 4 may write the user data together with the additional information directly or indirectly determined by the physical address to which the user data is to be written into the NAND flash memory 5. As the additional information directly or indirectly determined by the physical address to which the user data is to be written, the physical address itself to which the user data is to be written may be used. Alternatively, a check code generated from the information including the user data and the physical address may be used as the additional information.

[0077] When reading data corresponding to the read object logical address specified by the read instruction from the NAND flash memory 5, the controller 4 obtains the latest physical address (read object physical address) mapped to the read object logical address when the read instruction is executed from the L2P table 61. Based on the obtained read object physical address, the controller 4 reads the user data together with the additional information from the NAND flash memory 5. The controller 4 determines whether the read additional information is consistent with the additional information directly or indirectly determined according to the read object physical address. In an instance where the physical address itself is used as additional information, the controller 4 determines whether the read additional information is consistent with the read object physical address. On the other hand, in an instance where a check code containing information of user data and physical address is used as additional information, the controller 4 first uses the read user data and the read object physical address to generate a check code. In addition, the controller 4 determines whether the read additional information is consistent with the generated check code.

[0078] In this way, by determining whether the additional information read out is consistent with the additional information determined directly or indirectly based on the physical address of the read object, it is possible to determine whether the user data read out from the NAND flash memory 5 is correct data read out from the physical address of the read object or erroneous data read out from another physical address different from the physical address of the read object. In this way, the controller 4 determines whether to send the user data read out from the NAND flash memory 5 to the host 2 based on whether the additional information read out from the NAND flash memory 5 is consistent with the additional information determined directly or indirectly based on the physical address of the read object. As a result, it is possible to prevent erroneous data such as the previous data corresponding to the logical address of the read object from being sent to the host 2.

[0079] As described above, the direct or indirect additional information may be, for example, the physical address (PBA) itself. In this case, the controller 4 writes the user data together with the PBA to which the user data is to be written (also referred to as the write destination PBA) into the NAND flash memory 5 .

[0080] Alternatively, as described above, the direct or indirect additional information may be, for example, a check code. In this case, the controller 4 first generates a check code for confirming the matching of information including user data and the write destination PBA, and writes the user data and the generated check code into the NAND flash memory 5.

[0081] When the additional information is the PBA itself (PBA additional information), the PBA check circuit 444 determines whether the user data read from the NAND flash memory 5 is correct data by comparing two PBAs. On the other hand, when the additional information is a check code (check code additional information), the check code check circuit 442 determines whether the data read from the NAND flash memory 5 is correct data by comparing two check codes. Therefore, in the above case, the PBA check circuit 444 does not need to compare the PBA itself, so the check circuit 44 does not need to include the PBA check circuit 444.

[0082] The error correction circuit 45 performs encoding processing when writing data to the NAND flash memory 5. In the encoding processing, the error correction circuit 45 adds an error correction code (ECC) as a redundant code to the data to be written to the NAND flash memory 5. When reading data from the NAND flash memory 5, the error correction circuit 45 performs decoding processing. In the decoding processing, the error correction circuit 45 uses the ECC added to the data read from the NAND flash memory 5 to perform error correction on the data.

[0083] The NAND interface 46 is a circuit for controlling the NAND flash memory 5. The NAND interface 46 is electrically connected to a plurality of flash memory dies included in the NAND flash memory 5.

[0084] Each flash memory die can operate independently. Therefore, the flash memory die functions as a unit that can operate in parallel. The NAND interface 46 includes, for example, NAND controllers 461-0, 461-1, ..., 461-7. The NAND controllers 461-0, 461-1, ..., 461-7 are connected to channels ch0, ch1, ..., ch7, respectively. Each of the NAND controllers 461-0, 461-1, ..., 461-7 is connected to one or more flash memory die via a corresponding channel. Figure 1In the example, a case where four flash memory dies are connected to each of channels ch0, ch1, ..., ch7 is illustrated. In the case, NAND controller 461-0 is connected to flash memory dies #0, #8, #16, and #24 via channel ch0. NAND controller 461-1 is connected to flash memory dies #1, #9, #17, and #25 via channel ch1. And NAND controller 461-7 is connected to flash memory dies #7, #15, #23, and #31 via channel ch7. Flash memory dies #0, #1, ..., #7 are processed as storage body BNK0 by controller 4. Flash memory dies #8, #9, ..., #15 are processed as storage body BNK1 by controller 4. Flash memory dies #16, #17, ..., #23 are processed as storage body BNK2 by controller 4. Flash memory dies #24, #25, ..., #31 are processed as storage body BNK3 by controller 4. A bank is a unit that allows multiple flash memory chips to operate in parallel by interleaving operations. Figure 2 The shown figure includes a plurality of blocks BLK1 to BLKx-1.

[0085] Figure 1 and Figure 2 In the configuration of the NAND flash memory 5 shown, the controller 4 can perform parallel access to the flash memory chips #0 to #31 by interleaving the memory bank with 8 channels. Therefore, the controller 4 can perform data writing or reading for a maximum of 32 flash memory chips in parallel.

[0086] In addition, each of the flash memory dies #0 to #31 may have a multi-plane structure having a plurality of planes. For example, when each of the flash memory dies #0 to #31 includes four planes, the controller 4 can execute data writing or reading for a maximum of 128 planes in parallel.

[0087] Each of the plurality of write-destination blocks may be one block (physical block), or may be a super block including a set of a plurality of physical blocks that can operate in parallel.

[0088] One super block is not limited thereto, and may include a total of 32 physical blocks selected one by one from the NAND flash memory dies #0 to #31. In addition, each of the NAND flash memory dies #0 to #31 may also have a multi-plane structure. For example, when each of the NAND flash memory dies #0 to #31 has a multi-plane structure including 4 planes, one super block may also include a total of 128 physical blocks selected one by one from the 128 planes corresponding to the NAND flash memory dies #0 to #31.

[0089] Figure 3An example is given of a super block (SB) that includes 32 physical blocks (here, physical block BLK2 of NAND flash memory chip #0, physical block BLK3 of NAND flash memory chip #1, physical block BLK7 of NAND flash memory chip #2, ..., physical block BLK4 in NAND flash memory chip #24, physical block BLK6 in NAND flash memory chip #25, ..., physical block BLK3 in NAND flash memory chip #31).

[0090] The super block (SB) includes the same number of super pages as the number of pages included in each of the 32 physical blocks. For example, page 0 of physical block BLK2 of NAND flash die #0, page 0 of physical block BLK3 of NAND flash die #1, page 0 of physical block BLK7 of NAND flash die #2, ..., page 0 of physical block BLK4 in NAND flash die #24, page 0 of physical block BLK6 in NAND flash die #25, ..., page 0 of physical block BLK3 in NAND flash die #31 can also be processed by the controller 4 as one of the 32 super pages in the super block (SB).

[0091] Alternatively, a configuration may be used in which one super block includes only one physical block. In this case, one super block is equivalent to one physical block.

[0092] Back to Figure 1 DRAM interface 47 is a circuit for controlling DRAM 6. DRAM interface 47 stores data in DRAM 6. In addition, DRAM interface 47 reads out data stored in DRAM 6.

[0093] Next, the structure of DRAM 6 will be described.

[0094] DRAM 6 includes a storage area for storing a logical-to-physical address translation table (L2P table) 61. DRAM 6 also includes a storage area for storing a valid flag table 62, a storage area for storing an active block list 63, and a storage area for storing a free block list 64.

[0095] The L2P table 61 is a table for storing mapping information. The mapping information is information that represents the mapping between each logical address and each physical address of the NAND flash memory 5 in units of a specified management size. The logical address is an address used by the host 2 for performing operations on the SSD 3. As a logical address, for example, a logical block address (LBA) is used. The physical address is an address that represents a storage location within the NAND flash memory 5. The physical address can be represented, for example, by a flash die address, a block address, a page address, an offset address within a page, and any combination of all or part of the above.

[0096] The valid flag table 62 is a table for managing multiple flags. The multiple flags correspond to each of the multiple physical addresses of the SSD 3 in a one-to-one relationship. Each of the multiple flags indicates whether the data stored in the storage location represented by the corresponding physical address is valid data or invalid data. That is, the controller 4 uses the valid flag table 62 to manage multiple flags that are respectively corresponding to the multiple physical addresses of the NAND flash memory 5. For each of the multiple flags, either a first value indicating that the data stored in the storage location of the NAND flash memory 5 corresponding to the corresponding physical address is valid data or a second value indicating that it is invalid data is set. For example, the first flag corresponding to the first physical address is set to the first value indicating valid data based on writing the data associated with the write instruction received from the host 2 to the first storage location represented by the first physical address. And, based on the update or deletion of the data stored in the first storage location, the data stored in the first storage location becomes invalid data, and the first flag is set to the second value corresponding to the invalid data. Here, updating the data stored in the first storage location means writing the updated data (new data) corresponding to the logical address of the data into the NAND flash memory 5. Furthermore, deleting the data stored in the first storage location means invalidating the data by a cleanup command.

[0097] The active block list 63 is a table for managing a list of blocks storing at least valid data, that is, active blocks.

[0098] The free block list 64 is a table that manages a list of blocks that do not store valid data, that is, free blocks.

[0099] Next, the functional configuration of the CPU 43 will be described. The CPU 43 includes a read processing unit 431 and a write processing unit 432 in addition to the components that function as the FTL.

[0100] A part or all of each of the read processing unit 431 and the write processing unit 432 may be realized by dedicated hardware of the controller 4 .

[0101] The read processing unit 431 performs a read process by processing each of the read commands received from the host 2. The read process includes the following processes: a process of converting a logical address specified by the read command into a physical address by referring to the L2P table 61; a process of reading data from a storage location in the NAND flash memory 5 indicated by the physical address; and a process of transferring the read data to the memory 22 of the host 2.

[0102] The write processing unit 432 performs write processing by processing each write command received from the host 2. The write processing includes the following processing: processing of loading (transferring) write data from the memory 22 of the host 2 to the SRAM 42 or DRAM 6; processing of writing the write data loaded to the SRAM 42 or DRAM 6 to the storage location in the NAND flash memory 5; and processing of updating the L2P table 61 to map the physical address indicating the storage location where the write data is written to the logical address specified by the write command.

[0103] The write processing unit 432 includes a flash PBA allocation unit 433 .

[0104] The flash PBA allocation unit 433 allocates a PBA indicating a storage location of the NAND flash memory 5 where data associated with the write command is to be written to the LBA specified by the write command. The PBA allocated to the LBA indicates a storage location that can be used to write update data (new data).

[0105] Next, the validity flag table 62 will be described. Figure 4 1 is a diagram showing a configuration example of the validity flag table 62 used in the memory system according to the embodiment.

[0106] The valid flag table 62 includes a plurality of valid flag table areas 62-1, ..., 62-n. The plurality of valid flag table areas 62-1, ..., 62-n correspond to one block BLK among the plurality of blocks BLK1, ..., BLK-n.

[0107] For example, the valid flag table area 62-1 corresponds to the block BLK1. The valid flag table area 62-1 includes a plurality of flags. The plurality of flags are also referred to as bitmap data. The bitmap data stored in the valid flag table area 62-1 includes the same number of bits (that is, flags) as the number of multiple physical addresses (PBAs) respectively representing the multiple storage locations contained in the block BLK1. Each of the multiple flags indicates whether the data stored in the storage location represented by the physical address corresponding to the flag is valid. The flag corresponding to the physical address representing the storage location where valid data is stored is set to the first value (for example, "1"). In addition, the flag corresponding to the physical address representing the storage location where invalid data is stored is set to the second value (for example, "0"). The following is an example of a case where the first value is "1" and the second value is "0".

[0108] Page P0 of block BLK1 includes, for example, four storage locations represented by four PBAs (PBAx, PBA(x+1), PBA(x+2), PBA(x+3)). Data D0, data D1, data D2, and data D3 are stored in the four storage locations. When each of data D0, data D2, and data D3 is valid data, and data D1 is invalid data, four flags corresponding to the four PBAs (PBAx, PBA(x+1), PBA(x+2), PBA(x+3)), that is, 4-bit bitmap data represents "1011".

[0109] Page P1 of block BLK1 includes, for example, four storage locations represented by four PBAs (PBA(x+4), PBA(x+5), PBA(x+6), PBA(x+7)). Data D4, data D5, data D6, and data D7 are stored in the four storage locations. When each of data D4, data D5, data D6, and data D7 is valid data, four flags corresponding to the four PBAs (PBA(x+4), PBA(x+5), PBA(x+6), PBA(x+7)), that is, 4-bit bitmap data represents "1111".

[0110] Page P2 of block BLK1 includes, for example, four storage locations represented by four PBAs (PBA (x+8), PBA (x+9), PBA (x+10), PBA (x+11)). Data D8, data D9, data D10, and data D11 are stored in the four storage locations. When each of data D8 and data D9 is valid data, and each of data D10 and data D11 is invalid data, the four flags corresponding to the four PBAs (PBA (x+8), PBA (x+9), PBA (x+10), PBA (x+11)), that is, the 4-bit bitmap data represents "1100".

[0111] Figure 5 It is a diagram showing a configuration example related to control of writing data and reading data in a memory system according to an embodiment.

[0112] In the data writing operation to the NAND flash memory 5, the memory system 3 writes the data to the storage location indicated by the write destination PBA output from the flash memory PBA allocation unit 433. The data includes the data output by the error correction circuit 45, that is, the data to be written to the NAND flash memory 5 and the ECC codeword (ECC frame). The data to be written to the NAND flash memory 5 includes, for example, user data, LBA and check code. In addition, the data to be written to the NAND flash memory 5 may also include PBA. User data is data associated with the write instruction received from the host 2. LBA is the write destination LBA to which the user data is to be written, that is, the LBA (request LBA) specified by the write instruction. PBA is the write destination PBA output from the flash memory PBA allocation unit 433 in accordance with the request LBA specified by the write instruction.

[0113] When reading data from the NAND flash memory 5 , the memory system 3 reads data (eg, user data, LBA, checksum, ECC) stored in the storage location indicated by the read target PBA recorded in the L2P table 61 , and sends the read data to the error correction circuit 45 .

[0114] In the check code generation circuit 441, when the SSD 3 receives a write command from the host 2, the check circuit 44 generates a check code (e.g., CRC) using, for example, data associated with the write command, a request LBA specified by the write command, a write destination PBA, and a flag having a value indicating valid data. Furthermore, the check circuit 44 outputs the data associated with the write command, the request LBA, and the generated CRC to the error correction circuit 45.

[0115] In the check code generation circuit 441, when the SSD 3 receives a read command from the host 2, the check circuit 44 generates a check code using, for example, the data read from the NAND flash memory 5, the request LBA (the read target LBA) specified by the read command, the read target PBA obtained from the L2P table 61, and the flag corresponding to the read target PBA. Here, the read target PBA is the PBA mapped to the read target LBA when the read command is executed. In addition, the check circuit 44 compares the check code generated in the check code generation circuit 441 with the check code read from the NAND flash memory 5. When the comparison results of the two check codes are consistent with each other, the check circuit 44 determines that the read data (user data) is correct data. The read data is sent to the host 2 via the host I / F 41. On the other hand, when the comparison results of the two check codes are inconsistent with each other, the check circuit 44 determines that the read data is erroneous data. In the above case, the error is notified to the host 2 via the host I / F 41.

[0116] The error correction circuit 45 performs encoding of data to be written to the NAND flash memory 5 or decoding of read data. The error correction circuit 45 receives the data, LBA, and check code from the check circuit 44 and generates ECC using the data, LBA, and check code. The error correction circuit 45 outputs the data, LBA, check code, and ECC to the NAND flash memory 5.

[0117] The error correction circuit 45 receives the data, LBA, check code and ECC read from the NAND flash memory 5 and performs error correction using the ECC. When the error correction is completed, the error correction circuit 45 outputs the data, LBA and check code to the check circuit 44.

[0118] The L2P table 61 manages the mapping between each LBA and each PBA corresponding to each LBA. When the SSD3 receives a write instruction or a sort instruction from the host 2, the controller 4 obtains the PBA (also called the final PBA) corresponding to the request LBA specified by the received instruction from the L2P table 61. The final PBA is the PBA mapped to the LBA specified by the write instruction or the sort instruction at the time when the write instruction or the sort instruction is received. The obtained final PBA is output to the valid flag table 62. When the SSD3 receives a read instruction from the host 2, the controller 4 obtains the PBA (read object PBA) corresponding to the request LBA specified by the received read instruction from the L2P table 61. The read object PBA is output to the NAND flash memory 5 and the valid flag table 62. In addition, in the write process or the GC process, the L2P table 61 is updated in a manner that maps the write destination PBA output from the flash memory PBA allocation unit 433 to the LBA specified by the write instruction.

[0119] The valid flag table 62 manages a plurality of flags corresponding to different PBAs. When the SSD3 receives a write command from the host 2, the flag of the valid flag table 62 corresponding to the final PBA recorded in the L2P table 61 is set to the second value. And, the flag corresponding to the write destination PBA output from the flash PBA allocation unit 433 is set to the first value. In addition, when the SSD3 receives a read command from the host 2, the controller 4 obtains the flag corresponding to the read object PBA recorded in the L2P table 61 from the valid flag table 62, and outputs the obtained flag to the inspection circuit 44. In addition, when the SSD3 performs GC processing, the controller 4 selects the PBA corresponding to the flag set to the first value from the plurality of PBAs of the GC copy source block, and outputs each of the selected PBAs as the GC copy source PBA to the flash PBA allocation unit 433. The flash PBA allocation unit 433 determines the GC copy destination PBA as the write destination PBA for each GC copy source PBA. If valid data stored in the storage location indicated by the GC copy source PBA is copied to the storage location indicated by the GC copy destination PBA, the flag corresponding to the GC copy source PBA is set to the second value and the flag corresponding to the GC copy destination PBA is set to the first value.

[0120] Next, the following Figure 5 More specifically, the memory system write process, invalidation process, read process, and garbage collection process are described using Figure 6 , Figure 7 , Figure 8 and Fig. 9 Explain in order.

[0121] Figure 6 Controller 4 of SSD 3 starts writing process in response to receiving a writing command from host 2 .

[0122] Here, as an example, a case where the check is performed by the second method (check code determination method) and the additional information is a check code (check code additional information) will be described below.

[0123] (1) The write destination LBA designated by the write command received from the host 2 is output to the L2P table 61 , the flash PBA allocation unit 433 , and the check circuit 44 .

[0124] (2) The controller 4 obtains the PBA mapped to the write destination LBA when the write command is executed from the L2P table 61 as the final PBA. The controller 4 sets the flag in the valid flag table 62 corresponding to the final PBA to the second value ( Figure 6 "Flag reset").

[0125] (3) The flash PBA allocation unit 433 of the controller 4 determines the storage location where the data associated with the received write command should be written, and allocates the write destination PBA indicating the storage location to the write destination LBA. The flash PBA allocation unit 433 outputs the write destination PBA to the NAND flash memory 5, the L2P table 61, and the valid flag table 62.

[0126] (4) Then, the flash PBA allocation unit 433 outputs the write destination PBA to the inspection circuit 44 .

[0127] (5) The check circuit 44 generates a check code using the data associated with the received write command, the flag having the first value, the write destination LBA, and the write destination PBA. The flag does not need to be a flag corresponding to a specific storage location, but is only a bit having the first value. The generated check code is, for example, CRC. The check circuit 44 outputs the data and the generated check code to the error correction circuit 45.

[0128] (6) The error correction circuit 45 generates an error correction code (ECC) using the data and the check code. The error correction circuit 45 outputs the data, the check code, and the ECC to the NAND flash memory 5 as data (ECC frame) to be written to the NAND flash memory 5. The NAND flash memory 5 writes the ECC frame to the storage location indicated by the write destination PBA.

[0129] (7) Then, the controller 4 updates the mapping information of the L2P table 61 in such a manner that the write destination PBA is mapped to the write destination LBA. In addition, the controller 4 sets the flag in the valid flag table 62 corresponding to the write destination PBA to the first value ( Figure 6 of the "flag group").

[0130] Figure 7 This is a diagram for explaining the flow of invalidation processing, focusing on a configuration example related to invalidation processing of a memory system. The controller 4 of the SSD 3 starts the invalidation processing in response to receiving a cleanup command from the host 2 .

[0131] (1) The LBA corresponding to the invalidation target data specified by the organize command received from the host 2 is output to the L2P table 61 .

[0132] (2) The controller 4 obtains the PBA mapped to the LBA corresponding to the invalidation target data when the sort instruction is executed from the L2P table 61 as the final PBA. The controller 4 sets the flag in the valid flag table 62 corresponding to the final PBA to the second value ( Figure 7 "Flag reset").

[0133] Figure 8This is a diagram for explaining the flow of the read process, focusing on a configuration example related to the read process of the memory system. The controller 4 of the SSD 3 executes the read process in response to receiving a read command from the host 2.

[0134] (1) The read target LBA specified by the read command is output to the L2P table 61 and the check circuit 44.

[0135] (2) The controller 4 obtains the PBA mapped to the read target LBA when the read instruction is executed from the L2P table 61 as the read target PBA. The controller 4 outputs the obtained read target PBA to the check circuit 44 and the valid flag table 62.

[0136] (3) The controller 4 acquires the flag corresponding to the read target PBA from the valid flag table 62. The controller 4 outputs the acquired flag to the inspection circuit 44.

[0137] (4) The controller 4 outputs the read target PBA to the NAND flash memory 5, and instructs the NAND flash memory 5 to read the data.

[0138] (5) The NAND flash memory 5 reads the data (EDD frame) stored in the storage location indicated by the read target PBA, and outputs it to the error correction circuit 45.

[0139] (6) The error correction circuit 45 decodes the ECC frame and generates data (user data and a check code) after error correction. The error correction circuit 45 outputs the generated data (user data and a check code) to the check circuit 44.

[0140] (7) The check circuit 44 generates a check code in the check code generation circuit 441 using the user data output from the error correction circuit 45, the flag obtained from the valid flag table 62, the read target LBA, and the read target PBA. The check circuit 44 compares the check code output from the error correction circuit 45 with the generated check code. When the two check codes are consistent with each other, the check circuit 44 determines that the correct user data is read and sends the read user output to the host 2. When the two check codes are inconsistent with each other, the check circuit 44 determines that erroneous data is read and performs error processing. In the error processing, the controller 4 does not send the read user data to the host 2, for example, notifies the host 2 of the error.

[0141] Fig. 9 Controller 4 of SSD 3 starts GC processing when the number of free blocks in SSD 3 is lower than a threshold value. When GC processing starts, an arbitrary block is selected from the set of blocks managed by active block list 63 as a copy source block. The selected block is, for example, a block having a low ratio of valid data in the stored data.

[0142] (1) The valid flag table 62 selects a PBA whose corresponding flag is the first value from among the PBAs corresponding to the storage locations included in the copy source block as the GC copy source PBA. The valid flag table 62 outputs the selected PBA to the flash PBA allocation unit 433 as the GC copy source PBA.

[0143] (2) The controller 4 outputs the GC copy source PBA as the read target PBA to the NAND flash memory 5, and instructs the NAND flash memory 5 to read the data.

[0144] (3) The NAND flash memory 5 reads data (ECC frame) from the read target PBA and outputs it to the error correction circuit 45 .

[0145] (4) The error correction circuit 45 decodes the ECC frame and generates data (user data and a check code) after error correction. The error correction circuit 45 outputs the generated data (user data and a check code) to the check circuit 44.

[0146] (5) The flash PBA allocation unit 433 allocates a physical address indicating a storage location where data read from the GC copy source PBA is to be written as a GC copy destination PBA. The flash PBA allocation unit 433 outputs the allocated GC copy destination PBA to the NAND flash memory 5 .

[0147] (6) The flash PBA allocation unit 433 outputs the allocated GC copy destination PBA to the inspection circuit 44 .

[0148] (7) The check circuit 44 generates a check code in the check code generation circuit 441 using the data (user data, that is, GC copy target data) read from the GC copy source PBA of the NAND flash memory 5, the flag having the first value, the GC copy target LBA, and the GC copy destination PBA. The check circuit 44 outputs the GC copy target data and the generated check code to the error correction circuit 45.

[0149] (8) The error correction circuit 45 generates an error correction code (ECC) using the GC copy target data and the check code. The error correction circuit 45 outputs the GC copy target data, the check code, and the ECC as write data (ECC frame) to the NAND flash memory 5. The NAND flash memory 5 writes the write data (ECC frame) to the storage location indicated by the GC copy destination PBA output by the flash PBA allocation unit 433.

[0150] (9) Furthermore, the controller 4 obtains the PBA mapped to the LBA corresponding to the GC copy target data when the copy operation is executed from the L2P table 61 as the final PBA. The controller 4 updates the mapping information of the L2P table 61 in such a way that the GC copy destination PBA is mapped to the LBA corresponding to the GC copy target data. Furthermore, the controller 4 sets the flag in the valid flag table 62 corresponding to the GC copy destination PBA to the first value ( Fig. 9 of the "flag group").

[0151] (10) The controller 4 sets the flag in the valid flag table 62 corresponding to the acquired final PBA to the second value ( Fig. 9 "Flag reset").

[0152] As described above, the writing process, invalidation process, reading process, and garbage collection process of the memory system are performed.

[0153] Next, various inspection methods of the memory system according to the present embodiment will be described below using specific examples.

[0154] (First method (logical entity map flag determination method (data·PBA and / or (and / or) LBA·flag)) and inspection of PBA additional information)

[0155] First, the case where read data is checked using (i) the physical address stored together with the data in the NAND flash memory 5 and (ii) the value of the valid flag managed by the valid flag table 62 is described. That is, the flag is checked using the first method (logical entity map flag determination method) and the additional information is the PBA itself (PBA additional information) is described.

[0156] First, writing data will be described. Fig.10 It is a diagram showing a first example of write data in the memory system according to the embodiment.

[0157] The write-related data is data associated with the data to be written to the NAND flash memory 5 and used in the write process. The write-related data includes, for example, user data, LBA, and PBA. The user data is data associated with the write command received from the host 2. The LBA is the request LBA (write destination LBA) specified by the write command. The PBA is the write destination PBA allocated to the write destination LBA by the flash memory PBA allocation unit 433. In addition, the write-related data only needs to include the user data and the PBA, and may not necessarily include the LBA.

[0158] The check code generation circuit 441 generates a check code using at least the user data. Alternatively, the check code generation circuit 441 may generate a check code using either the LBA or the PBA, or both the LBA and the PBA, in addition to the user data.

[0159] The error correction circuit 45 encodes the data group including the user data, LBA, PBA, and check code to generate an ECC frame, and writes the ECC frame including the user data, LBA, PBA, check code, and ECC into the same page of the NAND flash memory 5 .

[0160] Next, the data is read from the NAND flash memory 5. Fig.10 The case of writing data described in is explained below. Fig.11 It is a diagram showing a first example of read data in the memory system according to the embodiment.

[0161] The data read from the NAND flash memory 5 includes user data, LBA, PBA, check code, and ECC. The error correction circuit 45 performs error correction on the read data by performing a decoding process.

[0162] When error correction is completed, the error correction circuit 45 outputs user data, LBA, PBA, and a check code.

[0163] The flag check circuit 443 checks whether the flag value corresponding to the PBA mapped to the LBA specified by the read instruction when the read is executed continues to maintain the first value. If the flag is the first value, the flag check circuit 443 determines that correct data is read. If the flag is the second value, the flag check circuit 443 determines that erroneous data is read because part of the mapping information of the L2P table 61 is damaged.

[0164] The PBA check circuit 444 checks whether the PBA mapped to the LBA specified by the read instruction when the read is executed is consistent with the PBA output by the error correction circuit 45. If the two PBAs are consistent, the PBA check circuit 444 determines that correct data has been read. If the two PBAs are inconsistent, the PBA check circuit 444 determines that erroneous user data has been read due to an erroneous operation of the address decoder of the NAND flash memory 5.

[0165] The LBA check circuit 445 checks whether the LBA specified by the read command received from the host 2 is consistent with the LBA output by the error correction circuit 45. When the two LBAs are consistent, the LBA check circuit 445 determines that correct data has been read. When the two LBAs are inconsistent, the LBA check circuit 445 determines that erroneous data has been read because part of the mapping information of the L2P table 61 is damaged.

[0166] The check code generation circuit 441 generates a check code using at least the user data output by the error correction circuit 45. For example, it is assumed that when the data is written, in addition to the user data, one or both of the LBA or PBA are used to generate the check code. In the case, the check code generation circuit 441 generates a check code using, in addition to the user data output by the error correction circuit 45, one or both of the LBA specified by the read instruction or the PBA mapped to the LBA when the read is executed.

[0167] The check code checking circuit 442 checks whether the check code generated by the check code generating circuit 441 is consistent with the check code output by the error correction circuit 45. If the two check codes are inconsistent, the check code checking circuit 442 determines that erroneous data has been read. If the two check codes are consistent, the check code checking circuit 442 determines that correct data has been read.

[0168] When the parity check circuit 442 , the flag check circuit 443 , the PBA check circuit 444 , and the LBA check circuit 445 all determine that correct data has been read, the controller 4 transmits the read data (user data) to the host 2 .

[0169] When any one of the parity check circuit 442, the flag check circuit 443, the PBA check circuit 444, and the LBA check circuit 445 determines that erroneous data has been read, the controller 4 performs error processing. For example, the controller 4 notifies the host 2 of the error as error processing. In the above case, the controller 4 may also send a response indicating that the processing of the read command has failed as a completion response indicating that the read command has been completed to the host 2.

[0170] Furthermore, when only the PBA check circuit 444 determines that erroneous user data has been read, the controller 4 may again execute the process of reading data from the storage location in the NAND flash memory 5 indicated by the read target PBA as error processing. This is because, as the cause of the error detection by only the PBA check circuit 444, it is assumed that data is read from a storage location different from the storage location indicated by the read target PBA due to an erroneous operation of the address decoder in the NAND flash memory 5.

[0171] Next, the procedure of the write process will be described. Fig.12 This is a flowchart showing a first example of the procedure of the write process of the memory system according to the embodiment.

[0172] The controller 4 receives a write command from the host 2 in response to the SSD 3 (step S1001 ), and starts a write process.

[0173] The controller 4 determines whether the old data is associated with the write destination LBA specified by the write command received in S1001 (step S1002). If the PBA is mapped to the write destination LBA in the L2P table 61, the controller 4 determines that the old data is associated with the write destination LBA.

[0174] When the old data is associated with the write destination LBA (Yes in S1002 ), the controller 4 obtains the final PBA mapped to the write destination LBA from the L2P table 61 (step S1003 ).

[0175] The controller 4 resets the flag in the valid flag table 62 corresponding to the final PBA (step S1004). In step S1004, the flag in the valid flag table 62 corresponding to the final PBA is set to the second value.

[0176] When the old data is not associated with the write destination LBA (No in S1002 ), the controller 4 skips the processing of S1003 and S1004 .

[0177] The controller 4 allocates a new PBA to the write destination LBA (step S1005). The allocated PBA is a write destination PBA indicating a storage location where data associated with the write command should be written.

[0178] The controller 4 generates a check code in the check code generation circuit 441 using the data associated with the write command received in S1001 and the write destination LBA (step S1006). The check code is a code for confirming the matching of information including the data and the write destination LBA.

[0179] The controller 4 encodes the data, the write destination LBA, the write destination PBA and the check code to generate a code word (ECC frame) (step S1007).

[0180] The controller 4 writes the data, the write destination LBA, the write destination PBA, the check code, and the ECC to the storage position in the NAND flash memory 5 indicated by the write destination PBA (step S1008).

[0181] The controller 4 sets the flag corresponding to the write destination PBA in the valid flag table 62 (step S1009), and ends the write process. In step S1009, the controller 4 sets the flag corresponding to the write destination PBA to the first value.

[0182] in addition, Fig.12In the writing process shown, the case where data, a writing destination LBA, a writing destination PBA, and a check code are written to the NAND flash memory 5 is described. However, the controller 4 may not write the writing destination LBA to the NAND flash memory 5, but only write the data, the writing destination PBA, and the check code to the NAND flash memory 5. This is because the check code is generated using the data and the writing destination LBA.

[0183] Next, the sequence of the readout process will be described. Fig.13 This is a flowchart showing a first example of the procedure of the read processing of the memory system according to the embodiment.

[0184] The controller 4 receives a read command from the host 2 in response to the SSD 3 (step S1101 ), and starts a read process.

[0185] The controller 4 acquires the PBA corresponding to the LBA designated by the read command received in S1101 from the L2P table 61 (step S1102 ).

[0186] The controller 4 obtains the flag corresponding to the PBA obtained in S1102 from the valid flag table 62 (step S1103 ).

[0187] The controller 4 reads the read target data (here, user data, LBA, PBA, and check code) stored in the storage location indicated by the PBA acquired in S1102 from the NAND flash memory 5 (step S1104).

[0188] The controller 4 generates a check code in the check code generation circuit 441 using the user data included in the read target data read out in S1104 and the LBA specified by the read command received in S1101 (step S1105).

[0189] The controller 4 determines whether the check code generated in S1105 matches the check code included in the read target data read in S1104 (step S1106).

[0190] The controller 4 determines whether the PBA acquired from the L2P table 61 in S1102 and the PBA included in the read target data read in S1104 match each other (step S1107 ).

[0191] The controller 4 determines whether the flag acquired in S1103 is set to a value indicating validity (step S1108 ).

[0192] The determinations of S1106, S1107, and S1108 may be performed in any order.

[0193] When the check code generated in S1105 is consistent with the check code contained in the read object data read out in S1104 (Yes in S1106), the PBA obtained from the L2P table 61 in S1102 is consistent with the PBA contained in the read object data read out in S1104 (Yes in S1107), and the flag obtained in S1103 is set to indicate a valid value (Yes in S1108), the controller 4 sends the data (user data) contained in the read object data read out in S1104 to the host 2 (step S1109), and ends the read processing.

[0194] When the check code generated in S1105 is inconsistent with the check code contained in the read object data read out in S1104 (No in S1106), the PBA obtained from the L2P table 61 in S1102 is inconsistent with the PBA contained in the read object data read out in S1104 (No in S1107), or the flag obtained in S1103 is set to a value indicating an invalid value (No in S1108), the controller 4 performs error processing (step S1110) and ends the read processing.

[0195] In the above description, the case of checking all flags, PBAs, and check codes is described, but in the check using the first method (logical entity map flag determination method) and PBA (PBA additional information), the check using the check code (S1106) can be omitted. That is, in the check using the first method (logical entity map flag determination method) and PBA (PBA additional information), the controller 4 determines whether to send the data (user data) read from the NAND flash memory 5 to the host 2 based on whether the flag obtained in S1103 is set to a valid value and the PBA read from the NAND flash memory 5 is consistent with the latest PBA obtained from the L2P table 61.

[0196] (Second method (check code determination method (data·flag·PBA)) and check code additional information)

[0197] Next, a case where a check code is generated using at least data, a flag, and a physical address, and the check code is used to check the read data is described. That is, an example where the flag is checked using the second method (check code determination method) and the additional information is a check code (check code additional information) is described.

[0198] First, writing data will be described. Fig.14 It is a diagram showing a second example of write data in the memory system according to the embodiment.

[0199] The write-related data includes user data, LBA, PBA, and flag. User data is data associated with the write command received from the host 2. LBA is the request LBA (write destination LBA) specified by the write command. PBA is the write destination PBA allocated to the write destination LBA by the flash PBA allocation unit 433. The flag is a flag having a first value indicating valid data, that is, 1-bit data indicating "1", for example.

[0200] Here, the check code generation circuit 441 generates the check code using at least the user data, the PBA and the flag. In addition, the check code generation circuit 441 may also generate the check code using the LBA in addition to the user data, the PBA and the flag.

[0201] The error correction circuit 45 encodes the data group including the user data, LBA, and the check code to generate an ECC frame, and writes the ECC frame including the user data, LBA, the check code, and the ECC into the same page of the NAND flash memory 5 .

[0202] Next, the data is read from the NAND flash memory 5. Fig.14 The case of writing data described in is explained below. Fig.15 It is a diagram showing a second example of read data in the memory system according to the embodiment.

[0203] The data read from the NAND flash memory 5 includes user data, LBA, a check code, and ECC. The error correction circuit 45 performs error correction on the read data by performing a decoding process.

[0204] When error correction is completed, the error correction circuit 45 outputs the user data, LBA, and check code.

[0205] The check code generation circuit 441 generates a check code using the user data output by the error correction circuit 45, the PBA corresponding to the read target LBA in the L2P table 61, and the flag corresponding to the PBA in the valid flag table 62. Furthermore, when the check code is generated using the LBA in addition to the user data, the PBA, and the flag during data writing, the check code generation circuit 441 generates a check code using the read target LBA specified by the read command received from the host 2.

[0206] The check code checking circuit 442 checks whether the check code generated by the check code generating circuit 441 is consistent with the check code output by the error correction circuit 45. If the two check codes are inconsistent, the check code checking circuit 442 determines that erroneous user data has been read. If the two check codes are consistent, the check code checking circuit 442 determines that correct user data has been read.

[0207] When the check code check circuit 442 determines that correct user data has been read, the controller 4 transmits the read user data to the host 2 .

[0208] When the parity check circuit 442 determines that the user data has been read out incorrectly, the controller 4 executes an error process. For example, the controller 4 notifies the host 2 of the error as an error process.

[0209] Next, the procedure of the write process will be described. Fig.16 This is a flowchart showing a second example of the procedure of the write process of the memory system according to the embodiment.

[0210] The controller 4 receives a write command from the host 2 in response to the SSD 3 (step S1201 ), and starts a write process.

[0211] The controller 4 determines whether the old data is associated with the write destination LBA specified by the write command received in S1201 (step S1202). If the PBA is mapped to the write destination LBA in the L2P table 61, the controller 4 determines that the old data is associated with the write destination LBA.

[0212] When the old data is associated with the write destination LBA (Yes in S1202 ), the controller 4 obtains the final PBA mapped to the write destination LBA from the L2P table 61 (step S1203 ).

[0213] The controller 4 resets the flag in the valid flag table 62 corresponding to the final PBA (step S1204). In step S1204, the flag in the valid flag table 62 corresponding to the final PBA is set to the second value.

[0214] When the old data is not associated with the write destination LBA (No in S1202 ), the controller 4 skips the processing of S1203 and S1204 .

[0215] The controller 4 allocates a new PBA to the write destination LBA (step S1205). The allocated PBA is a write destination PBA indicating a storage location where data associated with the write command should be written.

[0216] The controller 4 generates a check code in the check code generation circuit 441 using the data associated with the write command received in S1201, the write destination LBA, the PBA allocated in S1205, and the flag set to indicate a valid value (step S1206). The check code is a code used to confirm the matching of information including data, write destination LBA, PBA, and flag.

[0217] The controller 4 encodes the data, the write destination LBA and the check code to generate a code word (ECC frame) (step S1207).

[0218] The controller 4 writes the data, the write destination LBA, the check code, and the ECC to the storage location in the NAND flash memory 5 indicated by the write destination PBA (step S1208).

[0219] The controller 4 sets the flag corresponding to the write destination PBA in the valid flag table 62 (step S1209), and ends the write process. In step S1209, the controller 4 sets the flag corresponding to the write destination PBA to the first value.

[0220] in addition, Fig.16 In the write process shown, the case where data, write destination LBA and check code are written to the NAND flash memory 5 is explained, but it is also possible to write only data and check code to the NAND flash memory 5 without writing the write destination LBA to the NAND flash memory 5.

[0221] Next, the sequence of the readout process will be described. Fig.17 This is a flowchart showing a second example of the procedure of the read processing of the memory system according to the embodiment.

[0222] The controller 4 receives a read command from the host 2 in response to the SSD 3 (step S1301 ), and starts a read process.

[0223] The controller 4 acquires the PBA corresponding to the LBA designated by the read command received in S1301 from the L2P table 61 (step S1302 ).

[0224] The controller 4 obtains the flag corresponding to the PBA obtained in S1302 from the valid flag table 62 (step S1303 ).

[0225] The controller 4 reads the read target data (here, data, LBA, and check code) stored in the storage position indicated by the PBA acquired in S1302 from the NAND flash memory 5 (step S1304).

[0226] The controller 4 generates a check code in the check code generation circuit 441 using the data included in the read target data read out in S1304, the LBA designated by the read command received in S1301, the PBA acquired in S1302, and the flag acquired in S1303 (step S1305).

[0227] The controller 4 determines whether the check code generated in S1305 matches the check code included in the read target data read in S1304 (step S1306).

[0228] When the check code generated in S1305 is consistent with the check code included in the read object data read in S1304 (Yes in S1306), the controller 4 sends the data (user data) included in the read object data read in S1304 to the host 2 (step S1307) to end the read processing.

[0229] When the check code generated in S1305 does not match the check code included in the read target data read in S1304 (No in S1306), the controller 4 executes error processing (step S1308) and ends the read processing.

[0230] (First method (logical entity diagram flag determination method) and inspection of check code additional information)

[0231] Next, a case where read data is checked using (i) a check code generated using data and a physical address and (ii) the value of a flag managed by the valid flag table 62 will be described. That is, an example where the flag is checked using the first method (logical entity graph flag determination method) and the additional information is a check code will be described.

[0232] First, writing data will be described. Fig.18 It is a diagram showing a third example of write data in the memory system according to the embodiment.

[0233] The write-related data includes, for example, user data, LBA, and PBA. User data is data associated with a write command received from the host 2. LBA is a request LBA (write destination LBA) specified by the write command. PBA is a write destination PBA allocated to the write destination LBA by the flash PBA allocation unit 433.

[0234] The check code generation circuit 441 generates a check code using at least the user data and the write destination PBA. In addition, the check code generation circuit 441 may further use the LBA to generate a check code in addition to the user data and the write destination PBA.

[0235] The error correction circuit 45 encodes the data group including the user data, LBA and the check code to generate an ECC frame, and writes the ECC frame including the user data, LBA, the check code and the ECC into the same page of the NAND flash memory 5 .

[0236] Next, the data is read from the NAND flash memory 5. Fig.18 The case of writing data described in is explained below. Fig.19 It is a diagram showing a third example of read data in the memory system according to the embodiment.

[0237] The data read from the NAND flash memory 5 includes user data, LBA, a check code, and ECC. The error correction circuit 45 performs error correction on the read data by performing a decoding process.

[0238] When error correction is completed, the error correction circuit 45 outputs the user data, LBA, and check code.

[0239] The check code generation circuit 441 generates a check code using the user data output by the error correction circuit 45 and the PBA corresponding to the read target LBA specified by the read command received from the host 2. In addition, when the LBA is used in addition to the user data and the PBA when writing the data, the check code generation circuit 441 generates a check code using the LBA specified by the read command received from the host 2 in addition to the user data output by the error correction circuit 45 and the PBA corresponding to the LBA specified by the read command received from the host 2.

[0240] The check code checking circuit 442 checks whether the check code generated by the check code generating circuit 441 is consistent with the check code output by the error correction circuit 45. If the two check codes are inconsistent, the check code checking circuit 442 determines that erroneous user data has been read. If the two check codes are consistent, the check code checking circuit 442 determines that correct user data has been read.

[0241] The flag check circuit 443 checks whether the value of the flag corresponding to the PBA corresponding to the read target LBA specified by the read command in the L2P table 61 is the first value. If the flag is the first value, the flag check circuit 443 determines that correct user data has been read. If the flag is the second value, the flag check circuit 443 determines that incorrect user data has been read.

[0242] When the check code check circuit 442 and the flag check circuit 443 determine that correct user data has been read, the controller 4 transmits the read user data to the host 2 .

[0243] When the parity check circuit 442 or the flag check circuit 443 determines that erroneous user data has been read, the controller 4 executes an error process. For example, the controller 4 notifies the host 2 of the error as an error process.

[0244] Furthermore, when the parity check circuit 442 determines that erroneous user data has been read, the controller 4 may again execute the process of reading data from the storage location in the NAND flash memory 5 indicated by the read target PBA as error processing. This is because, as the cause of the error detection by the parity check circuit 442, it is assumed that data is read from a storage location different from the storage location indicated by the read target PBA due to an erroneous operation of the address decoder in the NAND flash memory 5.

[0245] Next, the procedure of the write process will be described. Fig. 20 This is a flowchart showing a third example of the procedure of the write process of the memory system according to the embodiment.

[0246] The controller 4 receives a write command from the host 2 in response to the SSD 3 (step S1401 ), and starts a write process.

[0247] The controller 4 determines whether the old data is associated with the write destination LBA specified by the write command received in S1401 (step S1402). If the PBA is mapped to the write destination LBA in the L2P table 61, the controller 4 determines that the old data is associated with the write destination LBA.

[0248] When the old data is associated with the write destination LBA (Yes in S1402 ), the controller 4 obtains the final PBA mapped to the write destination LBA from the L2P table 61 (step S1403 ).

[0249] The controller 4 resets the flag in the valid flag table 62 corresponding to the final PBA (step S1404). In step S1404, the flag in the valid flag table 62 corresponding to the final PBA is set to the second value.

[0250] When the old data is not associated with the write destination LBA (No in S1402 ), the controller 4 skips the processing of S1403 and S1404 .

[0251] The controller 4 allocates a new PBA to the write destination LBA (step S1405). The allocated PBA is a write destination PBA indicating a storage location where data associated with the write command should be written.

[0252] The controller 4 generates a check code in the check code generation circuit 441 using the data associated with the write command received in S1401, the write destination LBA, and the write destination PBA allocated in S1405 (step S1406). The check code is a code for confirming the matching of information including data, write destination LBA, and write destination PBA.

[0253] The controller 4 encodes the data, the write destination LBA and the check code to generate a code word (ECC frame) (step S1407).

[0254] The controller 4 writes the data, the write destination LBA, the check code, and the ECC to the storage location in the NAND flash memory 5 indicated by the write destination PBA (step S1408).

[0255] The controller 4 sets the flag corresponding to the write destination PBA in the valid flag table 62 (step S1409), and ends the write process. In step S1409, the controller 4 sets the flag corresponding to the write destination PBA to the first value.

[0256] in addition, Fig. 20 In the writing process shown, the case where data, a write destination LBA, and a check code are written to the NAND flash memory 5 is described, but the write destination LBA may not be written to the NAND flash memory 5, and only data and a check code may be written to the NAND flash memory 5. This is because the check code is generated using data, a write destination LBA, and a write destination PBA.

[0257] Next, the sequence of the readout process will be described. Fig.21 This is a flowchart showing a third example of the procedure of the read processing of the memory system according to the embodiment.

[0258] The controller 4 receives a write command from the host 2 in response to the SSD 3 (step S1501 ), and starts a read process.

[0259] The controller 4 acquires the PBA corresponding to the LBA designated by the read command received in S1501 from the L2P table 61 (step S1502 ).

[0260] The controller 4 obtains the flag corresponding to the PBA obtained in S1502 from the valid flag table 62 (step S1503).

[0261] The controller 4 reads the read target data (here, data, LBA, and check code) stored in the storage position indicated by the PBA acquired in S1502 from the NAND flash memory 5 (step S1504).

[0262] The controller 4 generates a check code in the check code generation circuit 441 using the user data included in the read target data read out in S1504, the LBA designated by the read command received in S1501, and the PBA acquired in S1502 (step S1505).

[0263] The controller 4 determines whether the check code generated in S1505 matches the check code included in the read target data read in S1504 (step S1506).

[0264] The controller 4 determines whether the flag acquired in S1503 is set to a value indicating validity (step S1507 ).

[0265] The determinations of S1506 and S1507 may be performed in any order.

[0266] When the check code generated in S1505 is consistent with the check code contained in the read object data read out in S1504 (Yes in S1506), and the flag obtained in S1503 is set to indicate a valid value (Yes in S1507), the controller 4 sends the data (user data) contained in the read object data read out in S1504 to the host 2 (step S1508), and ends the read processing.

[0267] In addition, when the check code generated in S1505 is inconsistent with the check code contained in the read object data read in S1504 (No in S1506), or the flag obtained in S1507 is set to a value indicating an invalid value (No in S1507), the controller 4 performs error processing (step S1509) and ends the read processing.

[0268] (Second method (check code determination method) and PBA additional information check)

[0269] Next, a case where read data is checked using (i) a physical address stored together with the data in the NAND flash memory 5 and (ii) a check code generated using the user data and the flag managed by the valid flag table 62 will be described. That is, an example will be described in which the flag is checked using the second method (check code determination method) and the additional information is the PBA itself.

[0270] First, writing data will be described. Fig. 22 It is a diagram showing a fourth example of write data in the memory system according to the embodiment.

[0271] Write-related data includes user data, LBA, PBA, and flag. User data is data associated with a write command received from the host 2. LBA is a request LBA (write destination LBA) specified by the write command. PBA is a write destination PBA allocated to the write destination LBA by the flash PBA allocation unit 433. A flag is a flag having a first value representing valid data, that is, 1-bit data representing "1", for example. In addition, it is sufficient for the write-related data to include user data, PBA, and flag, and it may not necessarily include LBA.

[0272] The check code generation circuit 441 generates a check code using at least the user data and the flag. In addition, the check code generation circuit 441 may also generate a check code using LBA in addition to the user data and the flag.

[0273] The error correction circuit 45 encodes the data group including the user data, LBA, PBA and check code to generate an ECC frame, and writes the ECC frame including the user data, LBA, PBA, check code and ECC into the same page of the NAND flash memory 5.

[0274] Next, the data is read from the NAND flash memory 5. Fig. 22 The case of writing data described in is explained below. Fig.23 It is a diagram showing a fourth example of read data in the memory system according to the embodiment.

[0275] The data read from the NAND flash memory 5 includes user data, LBA, PBA, check code, and ECC. The error correction circuit 45 performs error correction on the read data by performing a decoding process.

[0276] When error correction is completed, the error correction circuit 45 outputs the user data, LBA, PBA and check code.

[0277] The check code generation circuit 441 generates a check code using at least the user data output by the error correction circuit 45 and the flag corresponding to the read target PBA in the valid flag table 62. Furthermore, when LBA is used in addition to the user data and the flag during data writing, the check code generation circuit 441 generates a check code using the read target LBA specified by the read command received from the host 2 in addition to the user data and the flag.

[0278] The check code checking circuit 442 checks whether the check code generated by the check code generating circuit 441 is consistent with the check code output by the error correction circuit 45. If the two check codes are inconsistent, the check code checking circuit 442 determines that erroneous user data has been read. If the two check codes are consistent, the check code checking circuit 442 determines that correct user data has been read.

[0279] The PBA check circuit 444 checks whether the PBA mapped to the LBA specified by the read instruction when the read is executed is consistent with the PBA output by the error correction circuit 45. If the two PBAs are consistent, the PBA check circuit 444 determines that the correct user data has been read. If the two PBAs are inconsistent, the PBA check circuit 444 determines that erroneous user data has been read due to an erroneous operation of the address decoder of the NAND flash memory 5.

[0280] When the check code check circuit 442 and the PBA check circuit 444 determine that correct user data has been read, the controller 4 transmits the read user data to the host 2 .

[0281] When the parity check circuit 442 or the PBA check circuit 444 determines that erroneous user data has been read, the controller 4 performs error processing. For example, the controller 4 notifies the host 2 of the error as error processing. In the above case, the controller 4 may also send a response indicating that the processing of the read command has failed as a completion response indicating that the read command has been completed to the host 2.

[0282] Furthermore, when only the PBA check circuit 444 determines that erroneous user data has been read, the controller 4 may again execute the process of reading data from the storage location in the NAND flash memory 5 indicated by the read target PBA as error processing. This is because, as the cause of the error detection by only the PBA check circuit 444, it is assumed that data is read from a storage location different from the storage location indicated by the read target PBA due to an erroneous operation of the address decoder in the NAND flash memory 5.

[0283] Next, the procedure of the write process will be described. Fig.24 This is a flowchart showing a fourth example of the procedure of the write process of the memory system according to the embodiment.

[0284] The controller 4 receives a write command from the host 2 in response to the SSD 3 (step S1601 ), and starts a write process.

[0285] The controller 4 determines whether the old data is associated with the write destination LBA specified by the write command received in S1601 (step S1602). If the PBA is mapped to the write destination LBA in the L2P table 61, the controller 4 determines that the old data is associated with the write destination LBA.

[0286] When the old data is associated with the write destination LBA (Yes in S1602 ), the controller 4 obtains the final PBA mapped to the write destination LBA from the L2P table 61 (step S1603 ).

[0287] The controller 4 resets the flag in the valid flag table 62 corresponding to the final PBA (step S1604). In step S1604, the flag in the valid flag table 62 corresponding to the final PBA is set to the second value.

[0288] When the old data is not associated with the write destination LBA (No in S1602 ), the controller 4 skips the processing of S1603 and S1604 .

[0289] The controller 4 allocates a new PBA to the write destination LBA (step S1605). The allocated PBA is a write destination PBA indicating a storage location where data associated with the write command should be written.

[0290] The controller 4 generates a check code in the check code generation circuit 441 using the data associated with the write command received in S1601, the write destination LBA, and the flag indicating validity (step S1606). The check code is a code for confirming the matching of information including data, write destination LBA, and flag.

[0291] The controller 4 encodes the data, the write destination LBA, the write destination PBA and the check code to generate a code word (ECC frame) (step S1607).

[0292] The controller 4 writes the data, the write destination LBA, the write destination PBA, the check code, and the ECC to the storage location in the NAND flash memory 5 indicated by the write destination PBA (step S1608).

[0293] The controller 4 sets the flag corresponding to the write destination PBA in the valid flag table 62 (step S1609), and ends the write process. In step S1609, the controller 4 sets the flag corresponding to the write destination PBA to the first value.

[0294] in addition, Fig.24 In the writing process shown, the case where data, writing destination LBA, writing destination PBA, and check code are written to the NAND flash memory 5 is described, but it is also possible to write only data, writing destination PBA, and check code to the NAND flash memory 5 without writing writing destination LBA to the NAND flash memory 5. This is because the check code is generated using data, writing destination LBA, and flags.

[0295] Next, the sequence of the readout process will be described. Fig.25 This is a flowchart showing a fourth example of the procedure of the read processing of the memory system according to the embodiment.

[0296] The controller 4 receives a write command from the host 2 in response to the SSD 3 (step S1701 ), and starts a read process.

[0297] The controller 4 acquires the PBA corresponding to the LBA designated by the read command received in S1701 from the L2P table 61 (step S1702 ).

[0298] The controller 4 obtains the flag corresponding to the PBA obtained in S1702 from the valid flag table 62 (step S1703).

[0299] The controller 4 reads the read target data (here, user data, LBA, PBA, and check code) stored in the storage location indicated by the PBA acquired in S1702 from the NAND flash memory 5 (step S1704).

[0300] The controller 4 generates a check code in the check code generation circuit 441 using the user data included in the read target data read out in S1704, the LBA designated by the read command received in S1701, and the flag acquired in S1703 (step S1705).

[0301] The controller 4 determines whether the check code generated in S1705 matches the check code included in the read target data read in S1704 (step S1706).

[0302] The controller 4 determines whether the PBA acquired from the L2P table 61 in S1702 and the PBA included in the read target data read in S1704 match each other (step S1707).

[0303] The controller 4 determines whether the flag acquired in S1703 is set to a value indicating validity (step S1708 ).

[0304] The determinations of S1706 and S1707 may be performed in any order.

[0305] When the check code generated in S1705 is consistent with the check code contained in the read object data read out in S1704 (Yes in S1706), and the PBA obtained from the L2P table 61 in S1702 is consistent with the PBA contained in the read object data read out in S1704 (Yes in S1707), the controller 4 sends the data (user data) contained in the read object data read out in S1704 to the host 2 (step S1708), and ends the read processing.

[0306] When the check code generated in S1705 is inconsistent with the check code contained in the read object data read out in S1704 (No in S1706), or the PBA obtained from the L2P table 61 in S1702 is inconsistent with the PBA contained in the read object data read out in S1704 (No in S1707), the controller 4 performs error processing (step S1709) and ends the read processing.

[0307] As described above, according to the present embodiment, the controller 4 obtains the physical address (PBA) mapped to the logical address (read target LBA) specified by the read command when the read command is executed from the L2P table 61, and reads data (user data) from the NAND flash memory 5 based on the obtained PBA. In addition, the controller 4 determines whether to send the read data (user data) to the host 2 based on whether the current state of the flag corresponding to the obtained PBA continues to maintain the state set to the first value. In other words, the controller 4 can use the flag to check whether the data read from the NAND flash memory 5 is the latest data corresponding to the read target LBA, that is, correct data, or data other than the latest data corresponding to the read target LBA, that is, erroneous data. Therefore, even if erroneous data is read from the NAND flash memory 5 due to a part of the mapping information of the L2P table 61 being damaged, the erroneous data can be prevented from being sent to the host 2.

[0308] Specifically, when the current state of the flag corresponding to the acquired PBA is set to the second value, the controller 4 notifies the host 2 of an error. Thus, when past data of the same LBA is read due to an error in the L2P table 61, the controller 4 can notify the host 2 of an error.

[0309] Furthermore, the controller 4 can check whether the data read from the NAND flash memory 5 is correct data using the additional information determined directly or indirectly from the physical address.

[0310] When the additional information obtained based on the LBA specified by the read command received from the host 2 is inconsistent with the additional information included in the data read from the NAND flash memory 5, the controller 4 performs error processing. In the above case, due to the poor state of the NAND flash memory 5, it is detected that the PBA specified by the read command is inconsistent with the PBA determined based on the data read from the NAND flash memory 5. Therefore, the controller 4 may also perform a read process by reading data from the NAND flash memory 5 again as an error process. Alternatively, the controller 4 may notify the host 2 of the error as an error process.

[0311] In fact, the mapping information of the L2P table 61 is not often damaged, or the NAND flash memory 5 does not erroneously operate. Therefore, it is possible to check whether the data read from the NAND flash memory 5 is a correct data structure by using only the flag, or it is possible to check whether the data read from the NAND flash memory 5 is a correct data structure by using only the additional information.

[0312] Alternatively, the controller 4 may check whether the data read from the NAND flash memory 5 is correct data by using both the flag and the additional information.

[0313] The controller 4 sends the read data to the host 2 when the following conditions are met, that is, the indication flag is valid, and the additional information obtained based on the LBA specified by the read command received from the host 2 is consistent with the additional information contained in the data read from the NAND flash memory 5. On the other hand, when the above conditions are not met, the controller 4 does not send the read data to the host 2. In this way, the controller 4 determines whether to send the data read from the NAND flash memory 5 to the host 2 based on whether the following conditions are met, that is, the indication flag is valid, and the additional information obtained based on the LBA specified by the read command received from the host 2 is consistent with the additional information contained in the data read from the NAND flash memory 5. Thus, even if the mapping information of the L2P table 61 is damaged or one or both of the NAND flash memory 5 erroneous operations occur, the controller 4 can be prevented from sending erroneous data to the host 2 due to erroneous reading.

[0314] In addition, the controller 4 can use the flag or the physical address to generate a check code in the check code generation circuit 441, and use the generated check code to check whether the read data is correct data.

[0315] In this case, when checking the read data, the SSD 3 only needs to check the code, so the controller 4 does not need to perform flag checks and PBA checks separately.

[0316] Therefore, when using the flag and the physical address to generate the check code, SSD3 does not need a special hardware circuit (for example, Figure 1 In addition, even in the case of an erroneous read due to an erroneous operation of the NAND flash memory 5 without writing the physical address to the NAND flash memory 5, the erroneous read data can be detected, so that the physical storage space of the NAND flash memory 5 can be used more effectively.

[0317] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The embodiments or their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and their equivalents.

Claims

1. A memory system, the memory system being connectable to a host and having Non-volatile memory; and A controller configured to control the non-volatile memory; The controller is composed of: Using a first management table, managing mapping information indicating mapping between a plurality of logical addresses used by the host to access the memory system and a plurality of physical addresses of the nonvolatile memory; Using a second management table, a plurality of flags respectively associated with the plurality of physical addresses are managed, and for each of the plurality of flags, either a first value indicating that data stored in a storage location of the nonvolatile memory corresponding to the associated physical address is valid data or a second value indicating that data is invalid data is set; In response to receiving a write command specifying a first logical address from the host, assigning a first physical address to the first logical address, writing first data associated with the write command to a first storage location of the nonvolatile memory corresponding to the first physical address, and setting a first flag corresponding to the first physical address to the first value; According to the updating or deleting of the first data, the first data is set to invalid data, and the first flag is set to the second value; In response to receiving a read instruction specifying the first logical address from the host, a physical address mapped to the first logical address when the read instruction is executed is obtained from the first management table, data is read from the non-volatile memory based on the obtained physical address, and whether to send the read data to the host is determined based on whether the current state of the flag corresponding to the obtained physical address is set to the first value or the second value.

2. The memory system according to claim 1, wherein the controller is configured as: When writing the first data into the nonvolatile memory, writing the first data together with the first physical address into the first storage location; When reading the first data from the nonvolatile memory, based on the physical address obtained from the first management table, the data and the physical address are read from the nonvolatile memory together; Whether to send the data read from the non-volatile memory to the host is determined based on whether the following conditions are met, namely: the current state of the flag corresponding to the physical address obtained from the first management table is set to the first value, and the physical address read from the non-volatile memory is consistent with the physical address obtained from the first management table.

3. The memory system according to claim 1, wherein the controller is configured as: acquiring, from the second management table, the flag corresponding to the physical address acquired from the first management table; determining whether the value of the acquired flag is set to the first value or the second value; Based on the determination result, it is determined whether to transmit the data read out from the nonvolatile memory to the host.

4. The memory system according to claim 1, wherein the controller is configured as: When writing the first data into the nonvolatile memory, using the first data and the flag having the first value, a first check code is generated for confirming the matching of information including the first data and the flag having the first value; Writing the first data together with the first check code into the first storage location; When reading the first data from the nonvolatile memory, based on the physical address obtained from the first management table, the data and the check code are read from the nonvolatile memory together; acquiring, from the second management table, the flag corresponding to the physical address acquired from the first management table; Using the acquired flag and the read data, generating a second check code for confirming the matching of information including the acquired flag and the read data; Whether to send the read data to the host is determined based on whether the second check code matches the read check code.

5. The memory system according to claim 1, wherein the controller is configured as: When writing the first data into the nonvolatile memory, using the first data, the flag having the first value, and the first physical address, a first check code is generated to confirm the matching of information including the first data, the flag having the first value, and the first physical address; Writing the first data together with the first check code into the first storage location; When reading the first data from the nonvolatile memory, the data and the check code are read from the nonvolatile memory together based on the physical address obtained from the first management table; acquiring, from the second management table, the flag corresponding to the physical address acquired from the first management table; generating a second check code for confirming the matching of information including the acquired flag, the physical address acquired from the first management table, and the read data, using the acquired flag, the physical address acquired from the first management table, and the read data; Whether to send the read data to the host is determined based on whether the second check code matches the read check code.

6. A memory system, the memory system being connectable to a host and comprising: Non-volatile memory; and A controller configured to control the nonvolatile memory; and The controller is composed of: managing mapping information indicating mapping between a plurality of logical addresses used by the host to access the memory system and a plurality of physical addresses of the nonvolatile memory using a first management table; In response to receiving a write command specifying a first logical address from the host, a first physical address is allocated to the first logical address, and first data associated with the write command and first additional information directly or indirectly determined by the first physical address are written into a first storage location of the non-volatile memory corresponding to the first physical address; In response to receiving a read command specifying the first logical address from the host, obtaining from the first management table a physical address mapped to the first logical address when the read command is executed, and reading out data and additional information from the nonvolatile memory based on the obtained physical address; Whether to transmit the read data to the host is determined based on whether the read additional information matches the additional information directly or indirectly determined by the physical address acquired from the first management table.

7. The memory system according to claim 6, wherein the controller is configured as: managing a plurality of flags respectively associated with the plurality of physical addresses using a second management table, and setting, for each of the plurality of flags, either a first value indicating that data stored in a storage location of the nonvolatile memory corresponding to the associated physical address is valid data or a second value indicating that data is invalid data; According to writing the first data together with the first additional information into the first storage location, a first flag corresponding to the first physical address is set to the first value; According to the updating or deleting of the first data, the first data is set to invalid data, and the first flag is set to the second value; Whether to send the read data to the host is determined based on whether the following conditions are met, that is, the read additional information is consistent with the additional information directly or indirectly determined by the physical address obtained from the first management table, and the current state of the flag corresponding to the physical address obtained from the first management table is set to the first value.

8. The memory system of claim 6, wherein Each of the first additional information and the read additional information is a physical address, The controller is composed of: When writing the first data into the nonvolatile memory, writing the first data together with the first physical address into the first storage location; When reading the first data from the nonvolatile memory, based on the physical address obtained from the first management table, the data and the physical address are read from the nonvolatile memory together; Whether or not to transmit the read data to the host is determined based on whether the read physical address matches the physical address acquired from the first management table.

9. The memory system of claim 6, wherein Each of the first additional information and the read additional information is a check code, The controller is composed of: When writing the first data into the nonvolatile memory, using the first data and the first physical address, a first check code is generated for confirming the matching of information including the first data and the first physical address; Writing the first data together with the first check code into the first storage location; When reading the first data from the nonvolatile memory, based on the physical address obtained from the first management table, the data and the check code are read from the nonvolatile memory together; generating a second check code for confirming the consistency of information including the physical address obtained from the first management table and the read data, using the physical address obtained from the first management table and the read data; Whether to send the read data to the host is determined based on whether the second check code matches the read check code.

10. The memory system of claim 6, wherein Each of the first additional information and the read additional information is a physical address, The controller is composed of: managing a plurality of flags respectively associated with the plurality of physical addresses using a second management table, and setting, for each of the plurality of flags, either a first value indicating that data stored in a storage location of the nonvolatile memory corresponding to the associated physical address is valid data or a second value indicating that data is invalid data; According to writing the first data together with the first additional information into the first storage location, a first flag corresponding to the first physical address is set to the first value; According to the updating or deleting of the first data, the first data is set to invalid data, and the first flag is set to the second value; When writing the first data into the nonvolatile memory, using the first data, the flag having the first value, and the first physical address, a first check code is generated for confirming the matching of information including the first data, the flag having the first value, and the first physical address; Writing the first data together with the first check code into the first storage location; When reading the first data from the nonvolatile memory, based on the physical address obtained from the first management table, the data and the check code are read from the nonvolatile memory together; acquiring from the second management table a flag corresponding to the physical address acquired from the first management table; generating a second check code for checking the consistency of information including the physical address obtained from the first management table, the obtained flag, and the read data, using the physical address obtained from the first management table, the obtained flag, and the read data; Whether to send the read data to the host is determined based on whether the second check code matches the read check code.

11. A control method, the control method controlling a memory system including a non-volatile memory, and comprising: managing mapping information indicating mapping between a plurality of logical addresses used by the host to access the memory system and a plurality of physical addresses of the nonvolatile memory using a first management table; Using a second management table to manage a plurality of flags respectively corresponding to the plurality of physical addresses; for each of the plurality of flags, setting either a first value indicating that data stored in a storage location of the nonvolatile memory corresponding to the physical address corresponding thereto is valid data, or a second value indicating that data is invalid data; In response to receiving a write command specifying a first logical address from the host, assigning a first physical address to the first logical address, writing first data associated with the write command to a first storage location of the nonvolatile memory corresponding to the first physical address, and setting a first flag corresponding to the first physical address to the first value; According to the updating or deleting of the first data, the first data is set to invalid data, and the first flag is set to the second value; In response to receiving a read instruction specifying the first logical address from the host, a physical address mapped to the first logical address when the read instruction is executed is obtained from the first management table, data is read from the non-volatile memory based on the obtained physical address, and whether to send the read data to the host is determined based on whether the current state of the flag corresponding to the obtained physical address is set to the first value or the second value.

12. A control method, the control method controlling a memory system including a non-volatile memory, and comprising: managing mapping information indicating mapping between a plurality of logical addresses used by a host to access the memory system and a plurality of physical addresses of the nonvolatile memory using a first management table; In response to receiving a write command specifying a first logical address from the host, a first physical address is allocated to the first logical address, and first data associated with the write command and first additional information directly or indirectly determined by the first physical address are written into a first storage location of the non-volatile memory corresponding to the first physical address; In response to receiving a read command specifying the first logical address from the host, obtaining from the first management table a physical address mapped to the first logical address when the read command is executed, and reading out data and additional information from the nonvolatile memory based on the obtained physical address; Whether to transmit the read data to the host is determined based on whether the read additional information matches the additional information directly or indirectly determined by the physical address acquired from the first management table.

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