Logic lookup table circuit

Abstract

The invention discloses a logic lookup table circuit, which comprises a decoder circuit, a read control circuit, an MRAM (Magnetic Random Access Memory) storage circuit, a discharge read circuit, a reference unit circuit and a first NMOS (N-channel Metal Oxide Semiconductor) tube, the MRAM storage circuit has non-volatility, and the read control circuit only selects a certain storage unit in the MRAM storage circuit under the control of the decoder circuit; the storage unit is communicated with the discharge reading circuit and the first NMOS tube respectively, the discharge reading circuit can be discharged to the ground through the first NMOS tube, the storage state voltage of the storage unit is output to the amplifier circuit, and the reference unit circuit is communicated with the discharge reading circuit and the first NMOS tube respectively under the control of an external read enable signal, so that the storage state voltage of the storage unit is output to the amplifier circuit. Enabling the discharge reading circuit to discharge to the ground through a first NMOS tube, enabling the reference unit circuit to output a reference voltage to the amplifier circuit, and enabling the amplifier circuit to compare the storage state voltage with the reference voltage; the device has the advantages of small static power consumption, small transmission delay, and no disappearance of stored data even if the device is disconnected with a power supply.

Description

Technical Field

[0001] The invention relates to a lookup table circuit, in particular to a logic lookup table circuit. Background Art

[0002] At present, the logic lookup table circuit that can realize the combinational logic function is the key component of the field programmable gate array. The existing logic lookup table circuit is mainly designed by the traditional SRAM circuit. However, since the traditional SRAM circuit needs to continuously provide power when maintaining data to maintain the voltage level of the storage node, it leads to significant static power consumption, especially in large logic lookup table circuits, the problem of static power consumption is more significant. In addition, in the SRAM circuit, the SRAM storage unit is usually implemented by a bistable trigger (bistable multivibrator) composed of 6 MOS tubes. Each SRAM storage unit can store one bit of information, and each MOS tube has parasitic capacitance, including gate capacitance, drain capacitance and source capacitance. These parasitic capacitances need to be charged and discharged during the switching process, so the logic lookup table circuit has a large transmission delay. In addition, the SRAM storage unit needs to be continuously powered to maintain the data. Once the power is disconnected, the state of the SRAM storage unit will be lost, and the stored data will disappear. Therefore, the existing logic lookup table circuit designed by using the traditional SRAM circuit not only has large static power consumption and transmission delay, but also the stored data will disappear when the power is off. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a logic lookup table circuit with low static power consumption, small transmission delay, and storage data that will not disappear even if the power supply is disconnected.

[0004] The technical solution adopted by the present invention to solve the above technical problems is: a logic lookup table circuit, including a decoder circuit, a read control circuit, an MRAM storage circuit, a discharge reading circuit, a reference unit circuit and a first NMOS tube, the MRAM storage circuit includes 64 storage cells distributed in 8 rows and 8 columns, each storage cell is constructed based on a non-volatile device and has non-volatility; the decoder circuit is used to convert two sets of address signals inputted thereto from the outside into two sets of address control signals outputted to the read control circuit, the read control circuit is used to generate a set of read control signals under the control of the two sets of address control signals to select only a certain storage cell in the MRAM storage circuit, when a certain storage cell in the MRAM storage circuit After a storage unit is selected, the storage unit is connected to the discharge reading circuit and the first NMOS tube respectively. At this time, the discharge reading circuit can discharge to the ground through the first NMOS tube, so that the storage state voltage of the storage unit is output to the amplifier circuit; the reference unit circuit is used to be connected to the discharge reading circuit and the first NMOS tube respectively under the control of an external read enable signal. At this time, the discharge reading circuit can discharge to the ground through the first NMOS tube, so that the reference unit circuit outputs a reference voltage to the amplifier circuit. The amplifier circuit is used to compare the storage state voltage input thereto with the reference voltage to obtain a comparison result output.

[0005] The decoder circuit has two groups of input terminals and two groups of output terminals, each of which is used to access three-bit binary data, and each of which is used to output eight-bit binary data. The two groups of input terminals are called the first group of input terminals and the second group of input terminals, and the two groups of output terminals are called the first group of output terminals and the second group of output terminals respectively; the read control circuit has two groups of input terminals and one group of output terminals, each of which is used to access eight-bit binary data, and one group of output terminals is used to output sixty-four-bit binary data. The two groups of input terminals are called the first group of input terminals and the second group of input terminals, and the one group of output terminals is called the first group of output terminals. The MRAM storage circuit has one input terminal, three groups of input terminals and two input-output terminals, each of which is used to access sixty-four bits of binary data, and one input terminal is called the first input terminal, and the three groups of input terminals are respectively called the first group of input terminals, the second group of input terminals and the third group of input terminals, and the two input-output terminals are respectively called the first input-output terminal and the second input-output terminal; in the MRAM storage circuit, each of the storage cells has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first input-output terminal and a second input-output terminal; the first input terminal of the 64 storage cells is configured The first input terminal of the MRAM storage circuit is formed by the second input terminals of the 64 storage units, the third input terminals of the 64 storage units constitute the third input terminal of the MRAM storage circuit, the fourth input terminals of the 64 storage units are connected, and the connection terminal thereof is the first input terminal of the MRAM storage circuit, the first input-output terminals of the 64 storage units are connected, and the connection terminal thereof is the first input-output terminal of the MRAM storage circuit, the second input-output terminals of the 64 storage units are connected, and the connection terminal thereof is the second input-output terminal of the MRAM storage circuit. output terminal; the reference unit circuit has one input terminal and two input-output terminals, the one input terminal is called its first input terminal, and the two input-output terminals are respectively called its first input-output terminal and its second input-output terminal; the discharge reading circuit has one input terminal and two input-output terminals, the one input terminal is called its first input terminal, and the two input-output terminals are respectively called its first input-output terminal and its second input-output terminal; the amplifier circuit has three input terminals and one output terminal, the three input terminals are respectively called its first input terminal, the second input terminal and the third input terminal, and the one output terminal is called its first output terminal;The first group of input terminals of the decoder circuit is used to access the first three-bit address data inputted externally, the second group of input terminals of the decoder circuit is used to access the second three-bit address data inputted externally, the first group of output terminals of the decoder circuit is connected to the first group of input terminals of the read control circuit, the second group of output terminals of the decoder circuit is connected to the second group of input terminals of the read control circuit, and the first group of output terminals of the read control circuit is connected to the first group of input terminals of the MRAM storage circuit; the second group of input terminals of the MRAM storage circuit is used to access the 64-bit bit line signal BL<0:63> inputted externally, the third group of input terminals of the MRAM storage circuit is used to access the 64-bit source line signal SL<0:63> inputted externally, the first input terminal of the MRAM storage circuit is used to access the word line signal WL inputted externally, and the first input and output terminals of the MRAM storage circuit are respectively connected to the discharge read circuit The first input-output terminal is connected to the second input terminal of the amplifier circuit, the second input-output terminal of the MRAM storage circuit is respectively connected to the second input-output terminal of the reference unit circuit and the drain of the first NMOS tube, and the source of the first NMOS tube is grounded; the first input terminal of the reference unit circuit is used to access the read enable signal, the first input-output terminal of the reference unit circuit is respectively connected to the second input-output terminal of the discharge reading circuit and the third input terminal of the amplifier circuit, the first input terminal of the discharge reading circuit is used as the pre-discharge terminal of the logic lookup table circuit, and is used to access the external input pre-discharge signal, the first input terminal of the amplifier circuit is connected to the gate of the first NMOS tube, and its connection terminal is used as the clock terminal of the logic lookup table circuit, and is used to access the external input clock signal, and the first output terminal of the amplifier circuit is used as the output terminal of the logic lookup table circuit. ;

[0006] The decoder circuit includes two 3-8 decoder circuits, each of which has a group of input terminals and a group of output terminals. The group of input terminals is called the first group of input terminals, and the group of output terminals is called the first group of output terminals. The two 3-8 decoder circuits are respectively called the first 3-8 decoder circuit and the second 3-8 decoder circuit. The first group of input terminals of the first 3-8 decoder is the first group of input terminals of the decoder circuit, which is used to access the first three-bit address data. The first group of output terminals of the first 3-8 decoder is the first group of output terminals of the decoder circuit, which is used to output an eight-bit binary column control signal. The first group of input terminals of the second 3-8 decoder is the second group of input terminals of the decoder circuit, which is used to access the second three-bit address data. The first group of output terminals of the second 3-8 decoder is the second group of output terminals of the decoder circuit, which is used to output an eight-bit binary row control signal.

[0007] Each of the 3-8 decoders includes 3 inverters and 8 decoder units, each decoder unit has three input terminals and one output terminal, the three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal, and the one output terminal is referred to as the first output terminal; the three inverters are respectively referred to as the first inverter, the second inverter and the third inverter, and the 8 decoder units are respectively referred to as the first decoder unit, the second decoder unit, the third decoder unit, the fourth decoder unit, the fifth decoder unit, the sixth decoder unit, the seventh decoder unit and the eighth decoder unit; the input terminal of the first inverter The first input end of the first decoder unit, the first input end of the second decoder unit, the first input end of the third decoder unit and the first input end of the fourth decoder unit are connected, and the connection end is the first input end of the 3-8 decoder, the input end of the second inverter, the second input end of the third decoder unit, the second input end of the fourth decoder unit, the second input end of the seventh decoder unit and the second input end of the eighth decoder unit are connected, and the connection end is the second input end of the 3-8 decoder, the input end of the third inverter , the third input end of the second decoder unit, the third input end of the fourth decoder unit, the third input end of the sixth decoder unit and the third input end of the eighth decoder unit, and the connection end is the third input end of the 3-8 decoder, and the first input end to the third input end of the 3-8 decoder constitute the first group of input ends of the 3-8 decoder circuit; the output end of the first inverter is respectively connected to the first input end of the fifth decoder unit, the first input end of the sixth decoder unit, the first input end of the seventh decoder unit and the eighth decoder unit. The first input end of the eight decoder units is connected to the first input end of the eight decoder units, the output end of the second inverter is respectively connected to the second input end of the first decoder unit, the second input end of the second decoder unit, the second input end of the fifth decoder unit and the second input end of the sixth decoder unit, the output end of the third inverter is respectively connected to the third input end of the first decoder unit, the third input end of the third decoder unit, the third input end of the fifth decoder unit and the third input end of the seventh decoder unit, and the first output ends of the eight decoder units constitute the first group of output ends of the 3-8 decoder circuit.

[0008] Each decoder unit includes a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube and a fourth inverter. The drain of the second NMOS tube is the first input terminal of the decoder unit. The gate of the second NMOS tube is connected to the gate of the first PMOS tube, and the connection terminal thereof is the second input terminal of the decoder unit. The source of the second NMOS tube is connected to the source of the third NMOS tube. The gate of the third NMOS tube is connected to the gate of the second PMOS tube, and the connection terminal thereof is the third input terminal of the decoder unit. The drain of the third NMOS tube, the drain of the first PMOS tube, the drain of the second PMOS tube and the input terminal of the fourth inverter are connected. The source of the first PMOS tube and the source of the second PMOS tube are both connected to the power supply voltage VDD. The output terminal of the fourth inverter is the first output terminal of the decoder unit.

[0009] The read control circuit includes 8 read control modules, each of which has nine input terminals and eight output terminals, and the nine input terminals are respectively referred to as the first input terminal, the second input terminal, the third input terminal, the fourth input terminal, the fifth input terminal, the sixth input terminal, the seventh input terminal, the eighth input terminal and the ninth input terminal; the first input terminals of the 8 read control modules constitute the first group of input terminals of the read control circuit, the second input terminals of the 8 read control modules are connected, and their connecting end is the second group of first input terminals of the read control circuit, the third input terminals of the 8 read control modules are connected, and their connecting end is the second group of second input terminals of the read control circuit, the fourth input terminals of the 8 read control modules are connected, and their connecting end is the second group of third input terminals of the read control circuit, and the fifth input terminals of the 8 read control modules are connected , and its connection end is the second group fourth input end of the read control circuit, the sixth input ends of the 8 read control modules are connected, and its connection end is the second group fifth input end of the read control circuit, the seventh input ends of the 8 read control modules are connected, and its connection end is the second group sixth input end of the read control circuit, the eighth input ends of the 8 read control modules are connected, and its connection end is the second group seventh input end of the read control circuit, the ninth input ends of the 8 read control modules are connected, and its connection end is the second group eighth input end of the read control circuit, the second group first input end to the second group eighth input end of the read control circuit constitute the second group of input ends of the read control circuit, the eight output ends of the 8 read control modules, a total of 64 output ends constitute the first group of output ends of the read control circuit.

[0010] Each read control module includes 8 read control units, each read control unit has two input ends and one output end, the two input ends are respectively referred to as the first input end and the second input end, and the one output end is referred to as the first output end, the second input ends of the 8 read control units are connected, and the connecting end is the first input end of the read control module, the first input ends of the 8 read control units constitute the second input end to the ninth input end of the read control module, and the first output ends of the 8 read control units constitute the eight output ends of the read control module; each read control unit includes a first NAND gate and a fifth inverter, the first NAND gate has two input ends and one output end, the two input ends are respectively referred to as the first input end and the second input end, and the one output end is referred to as the first output end, the first input end of the first NAND gate is the first input end of the read control unit, the second input end of the first NAND gate is the second input end of the read control unit, the first output end of the first NAND gate is connected to the input end of the fifth inverter, and the output end of the fifth inverter is the first output end of the read control unit.

[0011] Each storage unit includes a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, a third PMOS tube, a fourth PMOS tube, a sixth inverter and a magnetic tunnel junction device, wherein the magnetic tunnel junction device has a free layer end and a fixed layer end, the input end of the sixth inverter, the gate of the fourth NMOS tube and the gate of the fifth NMOS tube are connected, and the connection end thereof is the fourth input end of the storage unit, the output end of the sixth inverter, the gate of the third PMOS tube and the gate of the fourth PMOS tube are connected, the drain of the fourth NMOS tube is connected to the drain of the third PMOS tube, and the connection end thereof is the second input end of the storage unit, the source, The source of the third PMOS tube and the source of the sixth NMOS tube are connected to the free layer end of the magnetic tunnel junction device; the drain of the fifth NMOS tube is connected to the drain of the fourth PMOS tube, and the connection end thereof is the third input end of the storage unit; the source of the fifth NMOS tube, the source of the fourth PMOS tube, and the source of the seventh NMOS tube are connected to the fixed layer end of the magnetic tunnel junction device; the gate of the sixth NMOS tube is connected to the gate of the seventh NMOS tube, and the connection end thereof is the first input end of the storage unit; the drain of the sixth NMOS tube is the first input-output end of the storage unit, and the drain of the seventh NMOS tube is the second input-output end of the storage unit.

[0012] The reference unit circuit includes an eighth NMOS tube, a ninth NMOS tube and a first resistor; the drain of the eighth NMOS tube is the first input / output terminal of the reference unit circuit; the gate of the eighth NMOS tube is connected to the gate of the ninth NMOS tube, and the connection end thereof is the first input terminal of the reference unit circuit, the source of the eighth NMOS tube is connected to one end of the first resistor, the source of the ninth NMOS tube is connected to the other end of the first resistor, and the drain of the ninth NMOS tube is the second input / output terminal of the reference unit circuit.

[0013] The discharge reading circuit includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first current source and a second current source, wherein the first current source and the second current source each have a positive input terminal and a negative input terminal; the gate and drain of the fifth PMOS tube and the gate of the sixth PMOS tube are connected to the positive input terminal of the first current source, the negative input terminal of the first current source is grounded, the gate and drain of the eighth PMOS tube and the gate of the seventh PMOS tube are connected to the positive input terminal of the second current source, the negative input terminal of the second current source is grounded, The source of the fifth PMOS, the source of the sixth PMOS, the source of the seventh PMOS and the source of the eighth PMOS are all connected to the power supply voltage VDD, the drain of the sixth PMOS tube is connected to the drain of the ninth PMOS tube, the source of the ninth PMOS tube is the first input and output end of the discharge reading circuit, the gate of the ninth PMOS tube is connected to the gate of the tenth PMOS tube, and the connection end thereof is the first input end of the discharge reading circuit, the drain of the tenth PMOS tube is connected to the drain of the seventh PMOS tube, and the source of the tenth PMOS tube is the second input and output end of the discharge reading circuit.

[0014] The amplifier circuit comprises an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube, the source of the eleventh PMOS tube, the source of the twelfth PMOS tube, the source of the thirteenth PMOS tube and the source of the fourteenth PMOS tube are all connected to the power supply voltage VDD, the gate of the eleventh PMOS tube, the gate of the fourteenth PMOS tube and the gate of the fourteenth NMOS tube are connected, and the connection end thereof is the first input end of the amplifier circuit, the drain of the eleventh PMOS tube, the drain of the twelfth PMOS tube, the drain of the tenth NMOS tube, the gate of the eleventh NMOS tube and the thirteenth PMOS tube are connected to the power supply voltage VDD. The gates of the MOS tubes are connected, the drains of the thirteenth PMOS tube, the drains of the fourteenth PMOS tube, the drains of the eleventh NMOS tube, the gates of the tenth NMOS tube and the gates of the twelfth PMOS tube are connected, and the connection ends thereof are the first output end of the amplifier circuit, the source of the tenth NMOS tube is connected to the drain of the twelfth NMOS tube, the gate of the twelfth NMOS tube is the second input end of the amplifier circuit, the source of the eleventh NMOS tube is connected to the drain of the thirteenth NMOS tube, the gate of the thirteenth NMOS tube is the third input end of the amplifier circuit, the source of the twelfth NMOS tube, the source of the thirteenth NMOS tube and the drain of the fourteenth NMOS tube are connected, and the source of the fourteenth NMOS tube is grounded.

[0015] Compared with the prior art, the present invention has the advantages that a logic lookup table circuit is formed by a decoder circuit, a read control circuit, an MRAM storage circuit, a discharge read circuit, a reference unit circuit and a first NMOS tube, the MRAM storage circuit includes 64 storage cells distributed in 8 rows and 8 columns, each storage cell is constructed based on a non-volatile device and has non-volatility; the decoder circuit converts two sets of address signals inputted thereto from the outside into two sets of address control signals outputted to the read control circuit, the read control circuit generates a set of read control signals under the control of the two sets of address control signals to select only a certain storage cell in the MRAM storage circuit, when a certain storage cell in the MRAM storage circuit is selected, the storage cell is connected to the discharge read circuit and the first NMOS tube respectively, at this time, the discharge read circuit discharges to the ground through the first NMOS tube, so that the storage cell The storage state voltage is output to the amplifier circuit; the reference unit circuit is connected to the discharge reading circuit and the first NMOS tube respectively under the control of the external read enable signal. At this time, the discharge reading circuit can discharge to the ground through the first NMOS tube, so that the reference unit circuit outputs the reference voltage to the amplifier circuit. The amplifier circuit compares the storage state voltage and the reference voltage input thereto, and obtains a comparison result output. In the present invention, information is stored by a non-volatile storage unit, which reduces static power consumption and has non-volatility. The storage state voltage generated by the discharge reading circuit and the reference voltage generated by the reference unit circuit are compared by the amplifier circuit, and then the comparison result is output, which improves the reading speed and reduces the transmission delay. Therefore, the present invention has low static power consumption and transmission delay, and even if the power supply is disconnected, the stored data will not disappear. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a structural block diagram of a logic lookup table circuit of the present invention;

[0017] Figure 2 A structural block diagram of an MRAM storage circuit of a logic lookup table circuit of the present invention;

[0018] Figure 3 A structural block diagram of a decoder circuit of a logic lookup table circuit of the present invention;

[0019] FIG4( a) is a block diagram of a 3-8 decoder of a logic lookup table circuit of the present invention;

[0020] FIG4( b) is a circuit diagram of a decoding unit of a logic lookup table circuit of the present invention;

[0021] FIG5( a) is a block diagram of a read control circuit of a logic lookup table circuit of the present invention;

[0022] FIG5( b ) is a block diagram of a read control module of a logic lookup table circuit of the present invention;

[0023] FIG5(c) is a structural diagram of a read control unit of a logic lookup table circuit of the present invention.

[0024] Figure 6 A circuit diagram of a storage unit of a logic lookup table circuit of the present invention;

[0025] Figure 7 A circuit diagram of a reference unit circuit of a logic lookup table circuit of the present invention;

[0026] Figure 8 A circuit diagram of a discharge reading circuit of a logic lookup table circuit of the present invention;

[0027] Fig. 9 A circuit diagram of an amplifier circuit of a logic lookup table circuit of the present invention;

[0028] Fig.10 It is a functional waveform diagram of the logic lookup table circuit of the present invention;

[0029] Fig.11 It is a transmission delay simulation verification diagram of the logic lookup table circuit of the present invention. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below with reference to the accompanying drawings.

[0031] Embodiment 1: Figure 1 As shown, a logic lookup table circuit includes a decoder circuit, a read control circuit, an MRAM storage circuit, a discharge read circuit, a reference unit circuit and a first NMOS tube N1, the MRAM storage circuit includes 64 storage cells distributed in 8 rows and 8 columns, each storage cell is constructed based on a non-volatile device and has non-volatility; the decoder circuit is used to convert two sets of address signals inputted thereto from the outside into two sets of address control signals outputted to the read control circuit, the read control circuit is used to generate a set of read control signals under the control of the two sets of address control signals to select only a certain storage cell in the MRAM storage circuit, when a certain storage cell in the MRAM storage circuit After the storage unit is selected, the storage unit is connected to the discharge reading circuit and the first NMOS tube N1 respectively. At this time, the discharge reading circuit can discharge to the ground through the first NMOS tube N1, so that the storage state voltage of the storage unit is output to the amplifier circuit; the reference unit circuit is used to be connected to the discharge reading circuit and the first NMOS tube N1 respectively under the control of the external read enable signal. At this time, the discharge reading circuit can discharge to the ground through the first NMOS tube N1, so that the reference unit circuit outputs the reference voltage to the amplifier circuit, and the amplifier circuit is used to compare the storage state voltage input thereto with the reference voltage to obtain a comparison result output.

[0032] In this embodiment, information is stored in a non-volatile storage unit, which reduces static power consumption while having non-volatility. Even if the power supply is disconnected, the stored data will not disappear. The storage state voltage generated by the discharge reading circuit and the reference voltage generated by the reference unit circuit are compared through the amplifier circuit, and the comparison result is output, which improves the reading speed and reduces the transmission delay.

[0033] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, the decoder circuit has two groups of input terminals and two groups of output terminals, each of which is used to access three-bit binary data, and each of which is used to output eight-bit binary data. The two groups of input terminals are referred to as the first group of input terminals and the second group of input terminals, and the two groups of output terminals are referred to as the first group of output terminals and the second group of output terminals respectively; the read control circuit has two groups of input terminals and one group of output terminals, each of which is used to access eight-bit binary data, and one group of output terminals is used to output sixty-four-bit binary data, the two groups of input terminals are referred to as the first group of input terminals and the second group of input terminals respectively, and the one group of output terminals is referred to as the first group of output terminals; the MRAM storage circuit has one input terminal, three groups of input terminals and two input and output terminals, each of which is used to access sixty-four-bit binary data, the one input terminal is referred to as the first input terminal, the three groups of input terminals are referred to as the first group of input terminals, the second group of input terminals and the third group of input terminals respectively, and the two input and output terminals are referred to as the first input and output terminals and the second input and output terminals respectively; Figure 2As shown, in the MRAM storage circuit, each storage unit has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first input-output terminal, and a second input-output terminal; the first input terminals of 64 storage units constitute a first group of input terminals of the MRAM storage circuit, the second input terminals of 64 storage units constitute a second group of input terminals of the MRAM storage circuit, the third input terminals of 64 storage units constitute a third group of input terminals of the MRAM storage circuit, the fourth input terminals of 64 storage units are connected, and the connection terminal thereof is the first input terminal of the MRAM storage circuit, the first input-output terminals of 64 storage units are connected, and Its connection end is the first input-output end of the MRAM storage circuit, and the second input-output ends of the 64 storage units are connected, and its connection end is the second input-output end of the MRAM storage circuit; the reference unit circuit has one input end and two input-output ends, and its one input end is called its first input end, and its two input-output ends are respectively called its first input-output end and its second input-output end; the discharge reading circuit has one input end and two input-output ends, and its one input end is called its first input end, and its two input-output ends are respectively called its first input-output end and its second input-output end, and the amplifier circuit has three input ends and a one-bit output terminal, its three input terminals are respectively referred to as its first input terminal, the second input terminal and the third input terminal, and its one-bit output terminal is referred to as its first output terminal; the first group of input terminals of the decoder circuit is used to access the first three-bit address data of the external input, the second group of input terminals of the decoder circuit is used to access the second three-bit address data of the external input, the first group of output terminals of the decoder circuit is connected to the first group of input terminals of the read control circuit, the second group of output terminals of the decoder circuit is connected to the second group of input terminals of the read control circuit, the first group of output terminals of the read control circuit is connected to the first group of input terminals of the MRAM storage circuit; the first group of The second group of input terminals are used to access the external 64-bit bit line signal BL<0:63>, the third group of input terminals of the MRAM storage circuit is used to access the external 64-bit source line signal SL<0:63>, the first input terminal of the MRAM storage circuit is used to access the external word line signal WL, the first input and output terminals of the MRAM storage circuit are respectively connected to the first input and output terminals of the discharge reading circuit and the second input terminal of the amplifier circuit, the second input and output terminals of the MRAM storage circuit are respectively connected to the second input and output terminals of the reference unit circuit and the drain of the first NMOS tube N1, and the source of the first NMOS tube N1 is grounded;The first input terminal of the reference unit circuit is used to access the read enable signal, the first input and output terminals of the reference unit circuit are respectively connected to the second input and output terminals of the discharge reading circuit and the third input terminal of the amplifier circuit, the first input terminal of the discharge reading circuit is used as the pre-discharge terminal of the logic lookup table circuit, and is used to access the external input pre-discharge signal, the first input terminal of the amplifier circuit is connected to the gate of the first NMOS tube N1, and its connection terminal is used as the clock terminal of the logic lookup table circuit, and is used to access the external input clock signal, and the first output terminal of the amplifier circuit is used as the output terminal of the logic lookup table circuit.;

[0034] In this embodiment, the working process of the logic lookup table circuit is as follows: first, the pre-discharge signal is set to a high level, the clock signal is set to a low level, the read enable signal is set to a low level, the word line signal WL is set to a high level, the 64-bit bit line signals BL<0:63> are all set to a low level, the 64-bit source line signals SL<0:63> are set to a high level, the first group of input terminals and the second group of input terminals of the decoder circuit do not input the first three-bit address data and the second three-bit address data, at this time, the pre-discharge signal and the clock signal will control the discharge reading circuit to be unable to discharge to the ground through the first NMOS tube N1, and the clock signal causes the amplifier circuit to enter the pre-charging stage; the word line signal WL controls the second input terminals of the 64 storage cells to read the bit line signal and the first three-bit address data of the 64 storage cells input thereto from the outside. The three input terminals read a one-bit source line signal inputted thereto from the outside, so that the storage unit writes a logic "1" storage state, the read enable signal controls the first input and output terminals of the reference unit circuit to be unable to be connected with the second input and output terminals of the discharge reading circuit, and the second input and output terminals of the reference unit circuit are unable to be connected with the drain of the first NMOS tube N1; the decoder circuit is unable to convert two three-bit address data into two groups of address control signals, the read control circuit is unable to generate a group of read control signals under the control of the two groups of address control signals, and a group of read control signals is unable to select only a certain storage unit in the MRAM storage circuit, so that the first input and output terminals of the storage unit are unable to be connected with the first input and output terminals of the discharge reading circuit, and the second input and output terminals are unable to be connected with the drain of the first NMOS tube N1.Then, the pre-discharge signal is switched from high level to low level, the clock signal is switched from low level to high level, the word line signal WL is switched from high level to low level, the read enable signal is switched from low level to high level, the 64-bit bit line signals BL<0:63> are all set to high level, the 64-bit source line signals SL<0:63> are set to low level, the first input terminal and the second input terminal of the decoder circuit are respectively input with the first three-bit address data and the second three-bit address data from the outside, at this time, the pre-discharge signal and the clock signal will control the discharge reading circuit to discharge to the ground through the first NMOS tube N1, and the clock signal controls the amplifier circuit to end the pre-charging process and start to enter the amplification comparison stage The word line signal WL controls the second input terminals of the 64 storage cells to read a bit line signal inputted from the outside and the third input terminals of the 64 storage cells to read a source line signal inputted from the outside. Neither of them can change the storage state of each storage cell, so that the storage cell still maintains the storage state of the written logic "1". The first input terminal and the second input terminal of the decoder circuit are connected to the two three-bit address data inputted from the outside and converted into two groups of address control signals. The two groups of address control signals are respectively an eight-bit binary column control signal for selecting a certain column and an eight-bit binary row control signal for selecting a certain row. The eight-bit binary column control signal is transmitted through the first input terminal of the decoder circuit. The output terminal is output to the first input terminal of the read control circuit, and the eight-bit binary row control signal is output to the second input terminal of the read control circuit through the second output terminal of the decoder circuit. The read control circuit converts the eight-bit binary column control signal connected to its first input terminal and the eight-bit binary row control signal connected to the second input terminal into a 64-bit read control signal, and outputs it to the first input terminal of the MRAM storage circuit through its first output terminal. At this time, a certain storage unit in the MRAM storage circuit is selected, and the first input and output terminal of the storage unit is connected to the first input and output terminal of the discharge reading circuit, and the second input and output terminal is connected to the drain of the first NMOS tube N1. The reference unit circuit is connected to the discharge reading circuit. The read enable signal connected to the first input terminal of the circuit controls the first input-output terminal of the reference unit circuit to be connected to the second input-output terminal of the discharge reading circuit, and the second input-output terminal of the reference unit circuit is connected to the drain of the first NMOS tube N1; the discharge reading circuit enables the MRAM storage circuit to output the storage state voltage of a currently selected storage unit to the second input terminal of the amplifier circuit, and the discharge reading circuit enables the reference unit circuit to output the reference voltage to the third input terminal of the amplifier circuit; the second input terminal and the third input terminal of the amplifier circuit respectively compare the storage state voltage input thereto with the reference voltage, obtain the comparison result output, and output the written logic "1" storage state.

[0035] Embodiment 3: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Figure 3As shown, the decoder circuit includes two 3-8 decoder circuits, each of which has a group of input terminals and a group of output terminals. The group of input terminals is called the first group of input terminals, and the group of output terminals is called the first group of output terminals. The two 3-8 decoder circuits are respectively called the first 3-8 decoder circuit and the second 3-8 decoder circuit. The first group of input terminals of the first 3-8 decoder is the first group of input terminals of the decoder circuit, which is used to access the first three-bit address data. The first group of output terminals of the first 3-8 decoder is the first group of output terminals of the decoder circuit, which is used to output an eight-bit binary column control signal. The first group of input terminals of the second 3-8 decoder is the second group of input terminals of the decoder circuit, which is used to access the second three-bit address data. The first group of output terminals of the second 3-8 decoder is the second group of output terminals of the decoder circuit, which is used to output an eight-bit binary row control signal.

[0036] In this embodiment, as shown in FIG. 4( a), each 3-8 decoder includes three inverters and eight decoder units. Each decoder unit has three input terminals and one output terminal. The three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal, and the one output terminal is referred to as the first output terminal. The three inverters are respectively referred to as the first inverter F1, the second inverter F2 and the third inverter F3, and the eight decoder units are respectively referred to as the first decoder unit, the second decoder unit, the third decoder unit, the fourth decoder unit, the fifth decoder unit, The sixth decoder unit, the seventh decoder unit and the eighth decoder unit; the input end of the first inverter F1, the first input end of the first decoder unit, the first input end of the second decoder unit, the first input end of the third decoder unit and the first input end of the fourth decoder unit are connected, and their connection end is the first input end of the 3-8 decoder, the input end of the second inverter F2, the second input end of the third decoder unit, the second input end of the fourth decoder unit, the second input end of the seventh decoder unit and the second input end of the eighth decoder unit are connected, and their connection end is the first input end of the 3-8 decoder. The second input end of the decoder is connected to the input end of the third inverter F3, the third input end of the second decoder unit, the third input end of the fourth decoder unit, the third input end of the sixth decoder unit and the third input end of the eighth decoder unit, and the connection end is the third input end of the 3-8 decoder. The first input end to the third input end of the 3-8 decoder constitute the first group of input ends of the 3-8 decoder circuit; the output end of the first inverter F1 is respectively connected to the first input end of the fifth decoder unit, the first input end of the sixth decoder unit, the first input end of the seventh decoder unit The output end of the second inverter F2 is connected to the second input end of the first decoder unit, the second input end of the second decoder unit, the second input end of the fifth decoder unit and the second input end of the sixth decoder unit respectively, the output end of the third inverter F3 is connected to the third input end of the first decoder unit, the third input end of the third decoder unit, the third input end of the fifth decoder unit and the third input end of the seventh decoder unit respectively, and the first output ends of the eight decoder units constitute the first group of output ends of the 3-8 decoder circuit.

[0037] In this embodiment, as shown in FIG. 4( b), each decoder unit includes a second NMOS tube N2, a third NMOS tube N3, a first PMOS tube P1, a second PMOS tube P2 and a fourth inverter F4. The drain of the second NMOS tube N2 is the first input terminal of the decoder unit. The gate of the second NMOS tube N2 is connected to the gate of the first PMOS tube P1, and the connection terminal thereof is the second input terminal of the decoder unit. The source of the second NMOS tube N2 is connected to the source of the third NMOS tube N3. The gate of the third NMOS tube N3 is connected to the gate of the second PMOS tube P2, and the connection terminal thereof is the third input terminal of the decoder unit. The drain of the third NMOS tube N3, the drain of the first PMOS tube P1, the drain of the second PMOS tube P2 and the input terminal of the fourth inverter F4 are connected. The source of the first PMOS tube P1 and the source of the second PMOS tube P2 are both connected to the power supply voltage VDD. The output terminal of the fourth inverter F4 is the first output terminal of the decoder unit.

[0038] Embodiment 4: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, as shown in FIG5(a), the read control circuit includes 8 read control modules, each of which has nine input terminals and eight output terminals, and its nine input terminals are respectively referred to as its first input terminal, second input terminal, third input terminal, fourth input terminal, fifth input terminal, sixth input terminal, seventh input terminal, eighth input terminal and ninth input terminal; the first input terminals of the 8 read control modules constitute a first group of input terminals of the read control circuit, the second input terminals of the 8 read control modules are connected, and their connection end is the second group of first input terminals of the read control circuit, the third input terminals of the 8 read control modules are connected, and their connection end is the second group of second input terminals of the read control circuit, and the fourth input terminals of the 8 read control modules are connected, and their connection end is the first group of second input terminals of the read control circuit. The second group of third input terminals and the fifth input terminals of the eight read control modules are connected, and their connecting end is the second group of fourth input terminals of the read control circuit, the sixth input terminals of the eight read control modules are connected, and their connecting end is the second group of fifth input terminals of the read control circuit, the seventh input terminals of the eight read control modules are connected, and their connecting end is the second group of sixth input terminals of the read control circuit, the eighth input terminals of the eight read control modules are connected, and their connecting end is the second group of seventh input terminals of the read control circuit, the ninth input terminals of the eight read control modules are connected, and their connecting end is the second group of eighth input terminals of the read control circuit, the second group of first input terminals to the second group of eighth input terminals of the read control circuit constitute the second group of input terminals of the read control circuit, the eight output terminals of the eight read control modules, a total of 64 output terminals constitute the first group of output terminals of the read control circuit.

[0039] In this embodiment, as shown in FIG5(b), each read control module includes 8 read control units, each read control unit has two input terminals and one output terminal, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the one output terminal is referred to as the first output terminal, the second input terminals of the 8 read control units are connected, and the connection terminal is the first input terminal of the read control module, the first input terminals of the 8 read control units constitute the second input terminal to the ninth input terminal of the read control module, and the first output terminals of the 8 read control units constitute the eight output terminals of the read control module; as shown in FIG5(c), each read The control units all include a first NAND gate NAND1 and a fifth inverter F5. The first NAND gate NAND1 has two input terminals and one output terminal. The two input terminals are referred to as the first input terminal and the second input terminal, and the one output terminal is referred to as the first output terminal. The first input terminal of the first NAND gate NAND1 is the first input terminal of the read control unit, the second input terminal of the first NAND gate NAND1 is the second input terminal of the read control unit, the first output terminal of the first NAND gate NAND1 is connected to the input terminal of the fifth inverter F5, and the output terminal of the fifth inverter F5 is the first output terminal of the read control unit.

[0040] Embodiment 5: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Figure 6 As shown, each storage unit includes a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, a third PMOS tube P3, a fourth PMOS tube P4, a sixth inverter F6 and a magnetic tunnel junction device T1, the magnetic tunnel junction device T1 has a free layer end and a fixed layer end, the input end of the sixth inverter F6, the gate of the fourth NMOS tube N4 and the gate of the fifth NMOS tube N5 are connected, and the connection end thereof is the fourth input end of the storage unit, the output end of the sixth inverter F6, the gate of the third PMOS tube P3 and the gate of the fourth PMOS tube P4 are connected, the drain of the fourth NMOS tube N4 is connected to the drain of the third PMOS tube P3, and the connection end thereof is the second input end of the storage unit , the source of the fourth NMOS tube N4, the source of the third PMOS tube P3, and the source of the sixth NMOS tube N6 are connected to the free layer end of the magnetic tunnel junction device T1; the drain of the fifth NMOS tube N5 is connected to the drain of the fourth PMOS tube P4, and the connection end thereof is the third input end of the storage unit, the source of the fifth NMOS tube N5, the source of the fourth PMOS tube P4, and the source of the seventh NMOS tube N7 are connected to the fixed layer end of the magnetic tunnel junction device T1; the gate of the sixth NMOS tube N6 is connected to the gate of the seventh NMOS tube N7, and the connection end thereof is the first input end of the storage unit; the drain of the sixth NMOS tube N6 is the first input and output end of the storage unit, and the drain of the seventh NMOS tube N7 is the second input and output end of the storage unit.

[0041] In this embodiment, the working process of the storage unit is as follows: when the word line signal WL is at a high level, the word line signal WL is input to the input end of the sixth inverter F6, and the output end of the sixth inverter F6 outputs the inverted word line signal WLB, the inverted word line signal WLB is at a low level, the word line signal WL and the inverted word line signal WLB turn on the fourth NMOS tube N4, the fifth NMOS tube N5, the third PMOS tube P3 and the fourth PMOS tube P4, at this time, a bit line signal externally output to the storage unit is input to the free layer end of the magnetic tunnel junction device T1, and a source line signal externally output to the storage unit is input to the fixed layer end of the magnetic tunnel junction device T1, when the word line signal WL is at a low level, the inverted word line signal WLB is at a high level, the word line signal WL and the inverted word line signal The signal WLB turns off the fourth NMOS tube N4, the fifth NMOS tube N5, the third PMOS tube P3 and the fourth PMOS tube P4. At this time, a bit line signal externally output to the storage unit cannot be input to the free layer end of the magnetic tunnel junction device T1, and a source line signal externally output to the storage unit cannot be input to the fixed layer end of the magnetic tunnel junction. A read control signal in a group of read control signals output by the read control circuit always controls the sixth NMOS tube N6 and the seventh NMOS tube N7 to be turned on. At this time, the first input and output end of the storage unit can be connected to the free layer end of the magnetic tunnel junction device T1 through the sixth NMOS tube N6, and the second input and output end of the storage unit can be connected to the fixed layer end of the magnetic tunnel junction device T1 through the seventh NMOS tube N7.

[0042] Embodiment 6: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Figure 7 As shown, the reference unit circuit includes an eighth NMOS tube N8, a ninth NMOS tube N9 and a first resistor R1; the drain of the eighth NMOS tube N8 is the first input-output terminal of the reference unit circuit; the gate of the eighth NMOS tube N8 is connected to the gate of the ninth NMOS tube N9, and the connection end thereof is the first input terminal of the reference unit circuit, the source of the eighth NMOS tube N8 is connected to one end of the first resistor R1, the source of the ninth NMOS tube N9 is connected to the other end of the first resistor R1, and the drain of the ninth NMOS tube N9 is the second input-output terminal of the reference unit circuit.

[0043] In this embodiment, the working process of the reference unit circuit is as follows: when the read enable signal is at a low level, the eighth NMOS tube N8 and the ninth NMOS tube N9 are both turned off, the first input and output end of the reference unit circuit cannot be connected to one end of the first resistor R1 through the eighth NMOS tube N8, and the second input and output end of the reference unit circuit cannot be connected to the other end of the first resistor R1 through the ninth NMOS tube N9; when the read enable signal is at a high level, the eighth NMOS tube N8 and the ninth NMOS tube N9 are both turned on, the first input and output end of the reference unit circuit can be connected to one end of the first resistor R1 through the eighth NMOS tube N8, and the second input and output end of the reference unit circuit can be connected to the other end of the first resistor R1 through the ninth NMOS tube N9.

[0044] Embodiment 7: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Figure 8 As shown, the discharge reading circuit includes a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a ninth PMOS tube P9, a tenth PMOS tube P10, a first current source I1 and a second current source I2, the first current source I1 and the second current source I2 each having a positive input terminal and a negative input terminal; the gate and drain of the fifth PMOS tube P5 and the gate of the sixth PMOS tube P6 are connected to the positive input terminal of the first current source I1, the negative input terminal of the first current source I1 is grounded, the gate and drain of the eighth PMOS tube P8 and the gate of the seventh PMOS tube P7 are connected to the positive input terminal of the second current source I2, The inverting input terminal of the second current source I2 is grounded, the source of the fifth PMOS, the source of the sixth PMOS, the source of the seventh PMOS and the source of the eighth PMOS are all connected to the power supply voltage VDD, the drain of the sixth PMOS tube P6 is connected to the drain of the ninth PMOS tube P9, the source of the ninth PMOS tube P9 is the first input and output terminal of the discharge reading circuit, the gate of the ninth PMOS tube P9 is connected to the gate of the tenth PMOS tube P10, and the connection end thereof is the first input terminal of the discharge reading circuit, the drain of the tenth PMOS tube P10 is connected to the drain of the seventh PMOS tube P7, and the source of the tenth PMOS tube P10 is the second input and output terminal of the discharge reading circuit.

[0045] In this embodiment, the working process of the discharge reading circuit is as follows: when the external input pre-discharge signal PRE is at a high level, the ninth PMOS tube P9 and the tenth PMOS tube P10 are turned off, the first current source I1 provides a constant current for the fifth PMOS tube P5 and the sixth PMOS tube P6, and the second current source I2 provides a constant current for the seventh PMOS tube P7 and the eighth PMOS tube P8, so that the fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7 and the eighth PMOS tube P8 are turned on; when the pre-discharge signal PRE is at a low level, the ninth PMOS tube P9 and the tenth PMOS tube P10 are turned on, the first current source I1 provides a constant current for the fifth PMOS tube P5 and the sixth PMOS tube P6, and the second current source I2 provides a constant current for the seventh PMOS tube P7 and the eighth PMOS tube P8. The first PMOS transistor P6 provides a constant current, the second current source I2 provides a constant current for the seventh PMOS transistor P7 and the eighth PMOS transistor P8, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7 and the twenty-sixth PMOS are still turned on, the power supply voltage VDD is discharged to the first input and output terminal of the discharge reading circuit through the sixth PMOS transistor P6 and the ninth PMOS transistor P9, the discharge reading circuit enables the MRAM storage circuit to output the storage state voltage of a currently selected storage unit, the power supply voltage VDD is discharged to the second input and output terminal of the discharge reading circuit through the seventh PMOS transistor P7 and the tenth PMOS transistor P10, and the discharge reading circuit enables the reference unit circuit to output the reference voltage.

[0046] Embodiment 8: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Fig. 9As shown, the amplifier circuit includes an eleventh PMOS tube P11, a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a thirteenth NMOS tube N13 and a fourteenth NMOS tube N14, the source of the eleventh PMOS tube P11, the source of the twelfth PMOS tube P12, the source of the thirteenth PMOS tube P13 and the source of the fourteenth PMOS tube P14 are all connected to the power supply voltage VDD, the gate of the eleventh PMOS tube P11, the gate of the fourteenth PMOS tube P14 and the gate of the fourteenth NMOS tube N14 are connected, and the connection end thereof is the first input end of the amplifier circuit, the drain of the eleventh PMOS tube P11, the drain of the twelfth PMOS tube P12, the drain of the tenth NMOS tube N10, the drain of the eleventh NMOS tube N11 The gate of the OS transistor N11 is connected to the gate of the thirteenth PMOS transistor P13, the drain of the thirteenth PMOS transistor P13, the drain of the fourteenth PMOS transistor P14, the drain of the eleventh NMOS transistor N11, the gate of the tenth NMOS transistor N10 and the gate of the twelfth PMOS transistor P12 are connected, and the connection end thereof is the first output end of the amplifier circuit, the source of the tenth NMOS transistor N10 is connected to the drain of the twelfth NMOS transistor N12, the gate of the twelfth NMOS transistor N12 is the second input end of the amplifier circuit, the source of the eleventh NMOS transistor N11 is connected to the drain of the thirteenth NMOS transistor N13, the gate of the thirteenth NMOS transistor N13 is the third input end of the amplifier circuit, the source of the twelfth NMOS transistor N12, the source of the thirteenth NMOS transistor N13 and the drain of the fourteenth NMOS transistor N14 are connected, and the source of the fourteenth NMOS transistor N14 is grounded.

[0047] In this embodiment, the working process of the amplifier circuit is as follows: when the external clock signal CLK is at a low level, the amplifier circuit starts a pre-charging operation, the eleventh PMOS tube P11 and the fourteenth PMOS tube P14 are turned on, the fourteenth NMOS tube N14 is turned off, the drain of the eleventh PMOS tube P11, the drain of the twelfth PMOS tube P12, the drain of the thirteenth PMOS tube P13 and the drain of the fourteenth PMOS tube P14 are charged to the voltage VDD, the twelfth PMOS tube P12 and the thirteenth PMOS tube P13 are turned off, the tenth NMOS tube N10 and the eleventh NMOS tube N11 are turned on , the pre-charging operation is completed; when the external clock signal CLK is at a high level, the amplifier circuit starts to work, the eleventh PMOS tube P11 and the fourteenth PMOS tube P14 are turned off, and the fourteenth NMOS tube N14 is turned on. When the storage state voltage input to the gate of the twelfth NMOS tube N12 is higher than the reference voltage input to the gate of the thirteenth NMOS tube N13, the conduction degree of the twelfth NMOS tube N12 is higher than the thirteenth NMOS tube N13, resulting in the drains of the eleventh PMOS tube P11 and the twelfth PMOS tube P12 being higher than the drains of the thirteenth PMOS tube P13 and the fourteenth PMOS tube P1 4 has a fast drain discharge speed, the drain voltage of the eleventh PMOS tube P11 and the twelfth PMOS tube P12 will be lower than the drain voltage of the thirteenth PMOS tube P13 and the fourteenth PMOS tube P14, so that the conduction degree of the thirteenth PMOS tube P13 is higher than the conduction degree of the twelfth PMOS tube P12, and the conduction degree of the tenth NMOS tube N10 is higher than the conduction degree of the eleventh NMOS tube N11. At this time, the discharge speed of the drain of the eleventh PMOS tube P11 and the twelfth PMOS tube P12 through the twelfth NMOS tube N12 and the fourteenth NMOS tube N14 is further accelerated. The power supply voltage VDD is fast, and the power supply voltage VDD charges the drains of the thirteenth PMOS tube P13 and the fourteenth PMOS tube P14 through the thirteenth PMOS tube P13, until the drain voltages of the eleventh PMOS tube P11 and the twelfth PMOS tube P12 drop to GND, and the source voltages of the thirteenth PMOS tube P13 and the fourteenth PMOS tube P14 rise to the power supply voltage VDD. Finally, the sources of the thirteenth PMOS tube P13 and the fourteenth PMOS tube P14 output the power supply voltage VDD as the output result obtained by the amplifier circuit comparing the storage state voltage input thereto with the reference voltage.

[0048] To verify the performance of the logic lookup table circuit of the present invention, Spectre was used to perform functional simulation on the logic lookup table circuit of the present invention at the standard voltage of 1.1V of SMIC's 40nm process. The functional simulation waveform of the logic lookup table circuit of the present invention is shown in FIG. Fig.10 Analysis Fig.10It can be seen that the logic lookup table circuit of the present invention has correct functional logic, can realize effective data storage in the magnetic tunnel junction device, and has non-volatility.

[0049] Under the standard voltage of 1.1V of SMIC 40nm process, Monte Carlo simulation is used to perform transmission delay simulation on the logic lookup table circuit of the present invention, wherein the transmission delay simulation waveform of the logic lookup table circuit of the present invention is as follows: Fig.11 Analysis Fig.11 It can be seen that the logic lookup table circuit of the present invention has a smaller transmission delay.

[0050] The logic lookup table circuit of the present invention, the single-ended nonvolatile lookup table circuit based on a three-terminal magnetic tunnel junction structure disclosed in document 1 "M. Natsui, D. Suzuki, Y. Lin and THanyu. A 71%-Area-Reduced six-input nonvolatile lookup-table circuit using a three-terminal magnetic-tunnel-junction-based single-ended structure [J], Japanese Journal of Applied Physics. vol. 52.", the logic lookup table circuit based on a transmission gate write scheme disclosed in document 2 "RF DeMara, A. Roohi, R. Zand and S. D. Pyle. Heterogeneous technology configurable fabrics for field-programmable co-design of CMOS and spin-based devices [J]. IEEE International Conference on Rebooting Computing (ICRC), Washington, pp. 1-4." and the logic lookup table circuit based on a transmission gate write scheme disclosed in document 3 "D. Suzuki, T. Hanyu et al. Design of a highly reliable, high-speed MTJ-Based lookup table circuit using A split magnetic tunnel junction logic lookup table circuit disclosed in the present invention is subjected to power consumption and delay comparison experiments. The logic lookup table circuit of the present invention and a single-terminal non-volatile lookup table circuit based on a three-terminal magnetic tunnel junction structure are subjected to a 90nm CMOS process standard voltage of 1.2V, and a split magnetic tunnel junction logic lookup table circuit is subjected to a 40nm CMOS process standard voltage of 1.1V. The comparative experimental data are shown in Table 1:

[0051] Table 1

[0052] Reference 1 Reference 2 Reference 3 The present invention Power consumption [μW] 6.26 9.05 14.5 7.7 Delay [ps] 195 122 97.4 27

[0053] From the analysis of Table 1, it can be seen that although the power consumption of the logic lookup table circuit of the present invention is slightly increased compared with that of Document 1, the power consumption is significantly reduced compared with that of Document 1. At the same time, the power consumption and transmission delay of the logic lookup table circuit of the present invention are significantly reduced compared with Documents 2 and 3. Obviously, the present invention has the characteristics of significantly low power consumption and low transmission delay, and has a high comprehensive performance.

Claims

1. A logic lookup table circuit, characterized in that The invention comprises a decoder circuit, a read control circuit, an MRAM storage circuit, a discharge read circuit, a reference unit circuit and a first NMOS tube. The MRAM storage circuit comprises 64 storage cells distributed in 8 rows and 8 columns. Each storage cell is constructed based on a non-volatile device and has non-volatility. The decoder circuit is used to convert two sets of address signals inputted thereto from the outside into two sets of address control signals outputted to the read control circuit. The read control circuit is used to generate a set of read control signals under the control of the two sets of address control signals to select only a certain storage cell in the MRAM storage circuit. When a certain storage cell in the MRAM storage circuit is selected, the storage cell The reference unit circuit is respectively connected with the discharge reading circuit and the first NMOS tube. At this time, the discharge reading circuit can discharge to the ground through the first NMOS tube, so that the storage state voltage of the storage unit is output to the amplifier circuit; the reference unit circuit is used to be respectively connected with the discharge reading circuit and the first NMOS tube under the control of an external read enable signal. At this time, the discharge reading circuit can discharge to the ground through the first NMOS tube, so that the reference unit circuit outputs a reference voltage to the amplifier circuit. The amplifier circuit is used to compare the storage state voltage input thereto with the reference voltage to obtain a comparison result output.

2. A logic lookup table circuit according to claim 1, characterized in that The decoder circuit has two groups of input terminals and two groups of output terminals, each of which is used to access three-bit binary data, and each of which is used to output eight-bit binary data. The two groups of input terminals are called the first group of input terminals and the second group of input terminals, and the two groups of output terminals are called the first group of output terminals and the second group of output terminals respectively; the read control circuit has two groups of input terminals and one group of output terminals, each of which is used to access eight-bit binary data, and one group of output terminals is used to output sixty-four-bit binary data. The two groups of input terminals are called the first group of input terminals and the second group of input terminals respectively, and the one group of output terminals is called the first group of output terminals; The MRAM storage circuit has one input terminal, three groups of input terminals and two input-output terminals, each group of input terminals is used to access 64-bit binary data, one input terminal is called the first input terminal, the three groups of input terminals are respectively called the first group of input terminals, the second group of input terminals and the third group of input terminals, and the two input-output terminals are respectively called the first input-output terminal and the second input-output terminal; in the MRAM storage circuit, each of the storage cells has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first input-output terminal and a second input-output terminal; 64 storage The first input terminals of the 64 storage cells constitute the first group of input terminals of the MRAM storage circuit, the second input terminals of the 64 storage cells constitute the second group of input terminals of the MRAM storage circuit, the third input terminals of the 64 storage cells constitute the third group of input terminals of the MRAM storage circuit, the fourth input terminals of the 64 storage cells are connected, and the connection terminal thereof is the first input terminal of the MRAM storage circuit, the first input-output terminals of the 64 storage cells are connected, and the connection terminal thereof is the first input-output terminal of the MRAM storage circuit, the second input-output terminals of the 64 storage cells are connected, and the connection terminal thereof is the first input-output terminal of the MRAM storage circuit, The terminal is the second input-output terminal of the MRAM storage circuit; the reference unit circuit has one input terminal and two input-output terminals, one of which is called its first input terminal, and the two input-output terminals are respectively called its first input-output terminal and its second input-output terminal; the discharge reading circuit has one input terminal and two input-output terminals, one of which is called its first input terminal, and the two input-output terminals are respectively called its first input-output terminal and its second input-output terminal; the amplifier circuit has three input terminals and one output terminal, the three input terminals are respectively called its first input terminal, the second input terminal and the third input terminal, and its one output terminal is called its first output terminal; the first group of input terminals of the decoder circuit is used to access the first three-bit address data inputted externally, the second group of input terminals of the decoder circuit is used to access the second three-bit address data inputted externally, the first group of output terminals of the decoder circuit is connected to the first group of input terminals of the read control circuit, the second group of output terminals of the decoder circuit is connected to the second group of input terminals of the read control circuit, and the first group of output terminals of the read control circuit is connected to the first group of input terminals of the MRAM storage circuit;The second group of input terminals of the MRAM storage circuit is used to access the externally input 64-bit bit line signal BL<0:63>, the third group of input terminals of the MRAM storage circuit is used to access the externally input 64-bit source line signal SL<0:63>, the first input terminal of the MRAM storage circuit is used to access the externally input word line signal WL, the first input and output terminals of the MRAM storage circuit are respectively connected to the first input and output terminals of the discharge reading circuit and the second input terminal of the amplifier circuit, the second input and output terminals of the MRAM storage circuit are respectively connected to the second input and output terminals of the reference unit circuit and the drain of the first NMOS tube, the first The source of the NMOS tube is grounded; the first input end of the reference unit circuit is used to access the read enable signal, the first input and output ends of the reference unit circuit are respectively connected to the second input and output ends of the discharge reading circuit and the third input end of the amplifier circuit, the first input end of the discharge reading circuit serves as the pre-discharge end of the logic lookup table circuit, and is used to access the external input pre-discharge signal, the first input end of the amplifier circuit is connected to the gate of the first NMOS tube, and its connection end serves as the clock end of the logic lookup table circuit, and is used to access the external input clock signal, and the first output end of the amplifier circuit serves as the output end of the logic lookup table circuit. ; 3. A logic lookup table circuit according to claim 2, characterized in that The decoder circuit includes two 3-8 decoder circuits, each of which has a group of input terminals and a group of output terminals. The group of input terminals is referred to as a first group of input terminals, and the group of output terminals is referred to as a first group of output terminals. The two 3-8 decoder circuits are referred to as a first 3-8 decoder circuit and a second 3-8 decoder circuit, respectively. The first group of input terminals of the first 3-8 decoder is the first group of input terminals of the decoder circuit, which is used to access the first three-bit address data. The first group of output terminals of the first 3-8 decoder is the first group of output terminals of the decoder circuit, which is used to output an eight-bit binary column control signal. The first group of input terminals of the second 3-8 decoder is the second group of input terminals of the decoder circuit, which is used to access the second three-bit address data. The first group of output terminals of the second 3-8 decoder is the second group of output terminals of the decoder circuit, which is used to output an eight-bit binary row control signal. Each of the 3-8 decoders includes 3 inverters and 8 decoder units, each decoder unit has three input terminals and one output terminal, the three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal, and the one output terminal is referred to as the first output terminal; the three inverters are respectively referred to as the first inverter, the second inverter and the third inverter, and the 8 decoder units are respectively referred to as the first decoder unit, the second decoder unit, the third decoder unit, the fourth decoder unit, the fifth decoder unit, the sixth decoder unit, the seventh decoder unit and the eighth decoder unit; the input terminal of the first inverter The first input end of the first decoder unit, the first input end of the second decoder unit, the first input end of the third decoder unit and the first input end of the fourth decoder unit are connected, and the connection end is the first input end of the 3-8 decoder, the input end of the second inverter, the second input end of the third decoder unit, the second input end of the fourth decoder unit, the second input end of the seventh decoder unit and the second input end of the eighth decoder unit are connected, and the connection end is the second input end of the 3-8 decoder, the input end of the third inverter , the third input end of the second decoder unit, the third input end of the fourth decoder unit, the third input end of the sixth decoder unit and the third input end of the eighth decoder unit, and the connection end is the third input end of the 3-8 decoder, and the first input end to the third input end of the 3-8 decoder constitute the first group of input ends of the 3-8 decoder circuit; the output end of the first inverter is respectively connected to the first input end of the fifth decoder unit, the first input end of the sixth decoder unit, the first input end of the seventh decoder unit and the eighth decoder unit. The first input end of the eight decoder units is connected to the first input end of the eight decoder units, the output end of the second inverter is respectively connected to the second input end of the first decoder unit, the second input end of the second decoder unit, the second input end of the fifth decoder unit and the second input end of the sixth decoder unit, the output end of the third inverter is respectively connected to the third input end of the first decoder unit, the third input end of the third decoder unit, the third input end of the fifth decoder unit and the third input end of the seventh decoder unit, and the first output ends of the eight decoder units constitute the first group of output ends of the 3-8 decoder circuit.

4. A logic lookup table circuit according to claim 3, characterized in that Each decoder unit includes a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube and a fourth inverter. The drain of the second NMOS tube is the first input terminal of the decoder unit. The gate of the second NMOS tube is connected to the gate of the first PMOS tube, and the connection terminal thereof is the second input terminal of the decoder unit. The source of the second NMOS tube is connected to the source of the third NMOS tube. The gate of the third NMOS tube is connected to the gate of the second PMOS tube, and the connection terminal thereof is the third input terminal of the decoder unit. The drain of the third NMOS tube, the drain of the first PMOS tube, the drain of the second PMOS tube and the input terminal of the fourth inverter are connected. The source of the first PMOS tube and the source of the second PMOS tube are both connected to the power supply voltage VDD. The output terminal of the fourth inverter is the first output terminal of the decoder unit.

5. A logic lookup table circuit according to claim 2, characterized in that The read control circuit includes 8 read control modules, each of which has nine input terminals and eight output terminals, and the nine input terminals are respectively referred to as the first input terminal, the second input terminal, the third input terminal, the fourth input terminal, the fifth input terminal, the sixth input terminal, the seventh input terminal, the eighth input terminal and the ninth input terminal; the first input terminals of the 8 read control modules constitute the first group of input terminals of the read control circuit, the second input terminals of the 8 read control modules are connected, and their connecting end is the second group of first input terminals of the read control circuit, the third input terminals of the 8 read control modules are connected, and their connecting end is the second group of second input terminals of the read control circuit, the fourth input terminals of the 8 read control modules are connected, and their connecting end is the second group of third input terminals of the read control circuit, and the fifth input terminals of the 8 read control modules are connected , and its connection end is the second group fourth input end of the read control circuit, the sixth input ends of the 8 read control modules are connected, and its connection end is the second group fifth input end of the read control circuit, the seventh input ends of the 8 read control modules are connected, and its connection end is the second group sixth input end of the read control circuit, the eighth input ends of the 8 read control modules are connected, and its connection end is the second group seventh input end of the read control circuit, the ninth input ends of the 8 read control modules are connected, and its connection end is the second group eighth input end of the read control circuit, the second group first input end to the second group eighth input end of the read control circuit constitute the second group of input ends of the read control circuit, the eight output ends of the 8 read control modules, a total of 64 output ends constitute the first group of output ends of the read control circuit.

6. A logic lookup table circuit according to claim 5, characterized in that Each read control module includes 8 read control units, each read control unit has two input ends and one output end, the two input ends are respectively referred to as the first input end and the second input end, and the one output end is referred to as the first output end, the second input ends of the 8 read control units are connected, and the connecting end is the first input end of the read control module, the first input ends of the 8 read control units constitute the second input end to the ninth input end of the read control module, and the first output ends of the 8 read control units constitute the eight output ends of the read control module; each read control unit includes a first NAND gate and a fifth inverter, the first NAND gate has two input ends and one output end, the two input ends are respectively referred to as the first input end and the second input end, and the one output end is referred to as the first output end, the first input end of the first NAND gate is the first input end of the read control unit, the second input end of the first NAND gate is the second input end of the read control unit, the first output end of the first NAND gate is connected to the input end of the fifth inverter, and the output end of the fifth inverter is the first output end of the read control unit.

7. A lookup table circuit according to claim 2, characterized in that Each storage unit includes a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, a third PMOS tube, a fourth PMOS tube, a sixth inverter and a magnetic tunnel junction device, wherein the magnetic tunnel junction device has a free layer end and a fixed layer end, the input end of the sixth inverter, the gate of the fourth NMOS tube and the gate of the fifth NMOS tube are connected, and the connection end thereof is the fourth input end of the storage unit, the output end of the sixth inverter, the gate of the third PMOS tube and the gate of the fourth PMOS tube are connected, the drain of the fourth NMOS tube is connected to the drain of the third PMOS tube, and the connection end thereof is the second input end of the storage unit, the source, The source of the third PMOS tube and the source of the sixth NMOS tube are connected to the free layer end of the magnetic tunnel junction device; the drain of the fifth NMOS tube is connected to the drain of the fourth PMOS tube, and the connection end thereof is the third input end of the storage unit; the source of the fifth NMOS tube, the source of the fourth PMOS tube, and the source of the seventh NMOS tube are connected to the fixed layer end of the magnetic tunnel junction device; the gate of the sixth NMOS tube is connected to the gate of the seventh NMOS tube, and the connection end thereof is the first input end of the storage unit; the drain of the sixth NMOS tube is the first input-output end of the storage unit, and the drain of the seventh NMOS tube is the second input-output end of the storage unit.

8. A logic lookup table circuit according to claim 2, characterized in that The reference unit circuit includes an eighth NMOS tube, a ninth NMOS tube and a first resistor; the drain of the eighth NMOS tube is the first input / output terminal of the reference unit circuit; the gate of the eighth NMOS tube is connected to the gate of the ninth NMOS tube, and the connection end thereof is the first input terminal of the reference unit circuit, the source of the eighth NMOS tube is connected to one end of the first resistor, the source of the ninth NMOS tube is connected to the other end of the first resistor, and the drain of the ninth NMOS tube is the second input / output terminal of the reference unit circuit.

9. A logic lookup table circuit according to claim 2, characterized in that The discharge reading circuit includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first current source and a second current source, wherein the first current source and the second current source each have a positive input terminal and a negative input terminal; the gate and drain of the fifth PMOS tube and the gate of the sixth PMOS tube are connected to the positive input terminal of the first current source, the negative input terminal of the first current source is grounded, the gate and drain of the eighth PMOS tube and the gate of the seventh PMOS tube are connected to the positive input terminal of the second current source, the negative input terminal of the second current source is grounded, The source of the fifth PMOS, the source of the sixth PMOS, the source of the seventh PMOS and the source of the eighth PMOS are all connected to the power supply voltage VDD, the drain of the sixth PMOS tube is connected to the drain of the ninth PMOS tube, the source of the ninth PMOS tube is the first input and output end of the discharge reading circuit, the gate of the ninth PMOS tube is connected to the gate of the tenth PMOS tube, and the connection end thereof is the first input end of the discharge reading circuit, the drain of the tenth PMOS tube is connected to the drain of the seventh PMOS tube, and the source of the tenth PMOS tube is the second input and output end of the discharge reading circuit.

10. A logic lookup table circuit according to claim 2, characterized in that The amplifier circuit comprises an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube, the source of the eleventh PMOS tube, the source of the twelfth PMOS tube, the source of the thirteenth PMOS tube and the source of the fourteenth PMOS tube are all connected to the power supply voltage VDD, the gate of the eleventh PMOS tube, the gate of the fourteenth PMOS tube and the gate of the fourteenth NMOS tube are connected, and the connection end thereof is the first input end of the amplifier circuit, the drain of the eleventh PMOS tube, the drain of the twelfth PMOS tube, the drain of the tenth NMOS tube, the gate of the eleventh NMOS tube and the thirteenth PMOS tube are connected to the power supply voltage VDD. The gates of the MOS tubes are connected, the drains of the thirteenth PMOS tube, the drains of the fourteenth PMOS tube, the drains of the eleventh NMOS tube, the gates of the tenth NMOS tube and the gates of the twelfth PMOS tube are connected, and the connection ends thereof are the first output end of the amplifier circuit, the source of the tenth NMOS tube is connected to the drain of the twelfth NMOS tube, the gate of the twelfth NMOS tube is the second input end of the amplifier circuit, the source of the eleventh NMOS tube is connected to the drain of the thirteenth NMOS tube, the gate of the thirteenth NMOS tube is the third input end of the amplifier circuit, the source of the twelfth NMOS tube, the source of the thirteenth NMOS tube and the drain of the fourteenth NMOS tube are connected, and the source of the fourteenth NMOS tube is grounded.

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