Heat generation control for memory system evaluation

Abstract

The invention relates to heat generation control for semiconductor component evaluation. A semiconductor component may be subjected to an evaluation procedure and may include a memory array, a temperature sensor, and circuitry to cause the semiconductor component to perform one or more operations. The semiconductor component may receive an indication to operate in an evaluation mode and may be configured to operate according to a first evaluation mode. The semiconductor component may perform a first evaluation operation according to the first evaluation mode. The semiconductor component may be configured to operate in a second evaluation mode based on a temperature satisfying a temperature threshold in response to performing the first evaluation operation. The semiconductor component may perform a second evaluation operation according to the second evaluation mode.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. Patent Application No. 18 / 742,097, entitled “HEAT GENERATION CONTROL FOR MEMORY SYSTEM EVALUATION,” filed by TARAZONA CORDOBA et al. on June 13, 2024, and U.S. Provisional Patent Application No. 63 / 526,101, entitled “HEAT GENERATION CONTROL FOR MEMORY SYSTEM EVALUATION,” filed by TARAZONA CORDOBA et al. on July 11, 2023, each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to thermal control for memory system evaluation. Background Art

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell is programmable to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell may support more than two states, either of which may be stored by the memory cell. To store information, a memory device may write (e.g., program, set, assign) a state to a memory cell. To access stored information, a memory device may read (e.g., sense, detect, retrieve, determine) a state from a memory cell. Summary of the invention

[0005] An apparatus is described. The apparatus may include: one or more memory arrays of a semiconductor component; one or more temperature sensors of the semiconductor component; and circuitry of the semiconductor component coupled to the one or more memory arrays and the one or more temperature sensors, the circuitry being operable to cause the apparatus to: receive an indication to operate in an evaluation mode; configure the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication; perform one or more first operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the first evaluation mode; configure the semiconductor component to operate in a second evaluation mode in response to performing the one or more first operations based at least in part on a temperature indicated by at least one of the one or more temperature sensors satisfying a temperature threshold, the second evaluation mode being associated with less heat generation than the first evaluation mode; and perform one or more second operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the second evaluation mode.

[0006] A method is described. The method may include: receiving an indication at a semiconductor component to operate in an evaluation mode; configuring the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication; performing one or more first operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the first evaluation mode; configuring the semiconductor component to operate in a second evaluation mode in response to performing the one or more first operations based at least in part on a temperature indicated by at least one temperature sensor of the semiconductor component satisfying a temperature threshold, the second evaluation mode being associated with less heat generation than the first evaluation mode; and performing one or more second operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the second evaluation mode.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium stores code including instructions executable by a processor to: receive an indication at a semiconductor component to operate in an evaluation mode; configure the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication; perform one or more first operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the first evaluation mode; configure the semiconductor component to operate in a second evaluation mode in response to performing the one or more first operations based at least in part on a temperature indicated by at least one temperature sensor of the semiconductor component satisfying a temperature threshold, the second evaluation mode being associated with less heat generation than the first evaluation mode; and perform one or more second operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the second evaluation mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An example of a system supporting thermal control for memory system evaluation according to examples disclosed herein is presented.

[0009] Figure 2 An example of an evaluation system supporting thermal control for memory system evaluation according to examples disclosed herein is presented.

[0010] Figure 3 An example of a system supporting thermal control for memory system evaluation according to examples disclosed herein is presented.

[0011] Figure 4 A block diagram of a semiconductor component supporting thermal control for memory system evaluation according to examples disclosed herein is shown.

[0012] Figure 5 A flow chart illustrating one or several methods supporting thermal control for memory system evaluation according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0013] Some evaluation procedures (such as high temperature tests, combustion tests) can evaluate the operating performance of test items (such as semiconductor components, such as memory systems, memory devices, memory dies, memory wafers) in high temperature environments. Such evaluation procedures can evaluate whether the test items will fail or otherwise operate unfavorably when operating in high temperatures. In some cases, multiple test items can be placed in a temperature chamber (such as a test furnace) for evaluation together, and each test item can be expected to reach or exceed the target temperature when performing the operation in order to meet the high temperature evaluation. However, due to inconsistent room temperature, different heating between test items, or various combinations of these and other factors, some test items may experience higher item temperatures than other test items. Thus, in order to reach the target temperature of each test item, some test items may exceed the upper temperature threshold, thereby causing the test items to stop (e.g., suspend) the evaluation operation. Therefore, the test item fails to pass the evaluation and is subject to additional evaluation attempts, which reduces the efficiency of the evaluation procedure. In some instances, the test item may experience component damage due to such high temperatures, which may cause the test item to fail, thereby reducing the production yield of the evaluated item.

[0014] According to various techniques disclosed herein, a test article (e.g., a semiconductor component) may be configured to operate according to a reduced heat evaluation mode to increase the likelihood of meeting criteria of an evaluation procedure. For example, the test article may detect when a temperature of the test article meets (e.g., reaches or exceeds) an intermediate temperature threshold that is lower than an upper temperature threshold of the evaluation procedure. Based on detecting that the test article temperature meets the intermediate threshold, the test article may adjust its operating characteristics to reduce heat associated with its operation.

[0015] In some examples, the test article may adjust its operating characteristics by adjusting the threshold voltage characteristics of one or more transistors of the test article. For example, the test article may reverse bias one or more transistor wells at a non-zero or otherwise modified (e.g., increased) voltage. This reverse bias may result in a reduction in current flowing through one or more transistors of the test article, thereby reducing associated heating of the test article. Adjusting evaluation operating characteristics according to the described techniques may reduce overheating-related test article damage during an evaluation procedure, which may reduce re-evaluation of the test article and improve evaluation efficiency and production yield.

[0016] Features of the present disclosure are illustrated and described in the context of a system, such as a system including a memory system and a host system. Features of the present disclosure are further illustrated and described in the context of components, evaluation configurations, block diagrams, and flow charts.

[0017] Figure 1 An example of a system 100 supporting thermal control for memory system evaluation according to examples disclosed herein is described. The system 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, a smartphone, a wearable device, an Internet-connected device, a vehicle controller, a single-chip system (SoC), or other fixed or portable electronic system, among other examples. The system 100 includes a host device 105, a memory device 110, and one or more channels 115 coupling the host device 105 with the memory device 110 (e.g., for supporting a communication coupling). The system 100 may include any number of one or more memory systems 110 coupled to the host system 105.

[0018] The host system 105 may include one or more components (e.g., circuitry, processing circuitry, one or more processing components) that use memory to perform processes, any one or more of which may be referred to as or included in a processor 125. The processor 125 may include at least one of one or more processing elements that may be co-located or distributed, including a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a controller, discrete gate or transistor logic, one or more discrete hardware components, or a combination thereof. The processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, or components thereof, as well as other examples.

[0019] The host system 105 may also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement the functionality of an external memory controller (e.g., a host system memory controller), which may be referred to as or included in the host system controller 120. For example, the host system controller 120 may issue commands or other signaling for operating the memory system 110, such as write commands, read commands, configuration signaling, or other operational signaling. In some examples, the host system controller 120 or associated functions described herein may be implemented by or be part of the processor 125. For example, the host system controller 120 may be hardware, instructions (e.g., software, firmware), or some combination thereof implemented by the processor 125 or other components of the host system 105. In various examples, the host system 105 or the host system controller 120 may be referred to as a host.

[0020] The memory system 110 provides physical memory locations (e.g., addresses) that can be used or referenced by the system 100. The memory system 110 can include a memory system controller 140 and one or more memory devices 145 (e.g., memory packages, memory dies, memory chips) operable to store data. The memory system 110 can be configured to operate with different types of host systems 105, and can respond to commands from the host system 105 (e.g., from the host system controller 120). For example, the memory system 110 (e.g., the memory system controller 140) can receive a write command instructing the memory system 110 to store data received from the host system 105, or receive a read command instructing the memory system 110 to provide data stored in the memory device 145 to the host system 105, or receive a refresh command instructing the memory system 110 to refresh data stored in the memory device 145, as well as other types of commands and operations.

[0021] The memory system controller 140 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 140 may include hardware or instructions that support the memory system 110 to perform various operations, and may be operable to receive, transmit, or respond to commands, data, or control information related to the operation of the memory system 110. The memory system controller 140 may be operable to communicate with one or more of the host system controller 120, one or more memory devices 145, or the processor 125. In some examples, the memory system controller 140 may cooperate with the host system controller 120, the local controller 150 of the memory device 145, or any combination thereof to control the operation of the memory system 110. Although examples of the memory system controller 140 are illustrated as separate components of the memory system 110, in some examples, aspects of the functionality of the memory system 110 may be implemented by at least one of the processor 125, the host system controller 120, the one or more local controllers 150, or any combination thereof.

[0022] Each memory device 145 may include a local controller 150 and one or more memory arrays 155. The memory array 155 may be a collection of memory cells (e.g., a two-dimensional array, a three-dimensional array), each of which is operable to store data (e.g., as one or more memory bits). Each memory array 155 may include memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase change memory (PCM) cells, chalcogenide memory cells, or NOR memory cells and NAND memory cells or any combination thereof.

[0023] The local controller 150 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory device 145. In some examples, the local controller 150 may be operable to communicate with the memory system controller 140 (e.g., receive or transmit data or commands or both). In some examples, the memory system 110 may not include the memory system controller 140, and the local controller 150 or the host system controller 120 may perform the functions of the memory system controller 140 described herein. In some examples, the local controller 150 or the memory system controller 140 or both may include a decoding component operable to access addresses of the memory array 155, a sensing component for sensing the state of the memory cells of the memory array 155, a writing component for writing the state to the memory cells of the memory array 155, or various other components operable to support the described operations of the memory system 110.

[0024] The host system 105 (e.g., host system controller 120) and the memory system 110 (e.g., memory system controller 140) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission media, electrical conductors, conductive paths) between terminals (e.g., nodes, pins, contacts) associated with components of the system 100. Terminals may be examples of conductive input or output points of devices of the system 100, and terminals may operate as part of a channel 115. To support communication via channel 115, host system 105 (e.g., host system controller 120) and memory system 110 (e.g., memory system controller 140) may include a receiver (e.g., a latch) for receiving signals, a transmitter (e.g., a driver) for transmitting signals, a decoder for decoding or demodulating received signals or an encoder for encoding or modulating signals to be transmitted, and other components that support signaling via channel 115, which may be included in corresponding interface portions of the corresponding systems.

[0025] The channels 115 are dedicated to conveying one or more types of information, and the channels 115 may include unidirectional channels, bidirectional channels, or both. For example, the channels 115 may include one or more command / address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, the channels 115 may be configured to provide power from one system to another (e.g., from the host system 105 to the memory system 110, according to a regulated voltage). In some examples, at least a subset of the channels 115 may be configured according to a protocol (e.g., a logic protocol, a communication protocol, an operating protocol, an industry standard) that may support configuration operations and interactions between the host system 105 and the memory system 110.

[0026] In some cases, electronic test articles may undergo an evaluation procedure to evaluate operating performance in a high temperature environment. Such an evaluation procedure may test whether a test article will fail when operating in a high temperature. However, multiple test articles may be evaluated at one time, and some test articles may experience higher article temperatures than other test articles (e.g., due to inconsistent room temperatures, due to different heating between test articles, or both). Thus, some test articles may exceed a maximum temperature threshold, causing the test article to stop (e.g., pause) the evaluation operation and fail the evaluation. Therefore, the test article is subjected to additional evaluation attempts and, in some instances, may experience component damage due to such high temperatures.

[0027] According to various techniques disclosed herein, a test article (e.g., a semiconductor component, such as memory system 110, memory device 145, or host system 105, or any component thereof) may be configured to operate according to a reduced heat evaluation mode to reduce the likelihood that the test article will fail criteria of an evaluation procedure or experience component damage. In some instances, the test article may detect when the temperature of the test article meets a temperature threshold that is lower than a maximum temperature threshold of the evaluation procedure but higher than a minimum threshold of the evaluation procedure. In some instances, the test article may adjust (e.g., modify, increase) a threshold voltage characteristic of one or more transistors (e.g., a transistor well) of the test article, which may result in reduced heat generation of the test article (e.g., based on reduced current in the test article). Operating the test article in a reduced heat evaluation mode according to the described techniques may reduce overheating of the test article and increase the likelihood that the test article will meet criteria of the evaluation procedure, thereby improving evaluation efficiency and production yield.

[0028] In addition to being applied in the systems described herein, the techniques for heat control of memory system evaluation can be implemented generally to improve the sustainability of various electronic devices and systems. As the use of electronic devices becomes more widespread, the energy usage and environmental impact associated with the production and operation of electronic devices has increased. In addition, the waste associated with the disposal of electronic devices can also be harmful for various reasons. Implementing the techniques described herein can reduce the impacts associated with electronic devices by reducing the materials used in the production of electronic devices and eliminating repeated evaluation processes, which can lead to reduced electronic waste and lower production emissions, among other benefits.

[0029] Figure 2An example of an evaluation system 200 supporting thermal control for memory system evaluation according to examples disclosed herein is shown. The evaluation system 200 may include a set of test articles 210 in a chamber 205 (e.g., an evaluation chamber, a temperature chamber, a test oven), one or more of which may be operated at least in part by an evaluation controller 225. Each square may represent a respective test article 210 (e.g., a device under test (DUT)), each of which may be an example of or include a semiconductor component such as a semiconductor wafer or a semiconductor die. In various examples, the test article 210 may be an example of or include a memory system 110 (e.g., a packaged memory system), a memory device 145 (e.g., a packaged memory device, a memory die), a host system 105, or a portion thereof, or a combination thereof. The chamber 205 may include one or more arrays 220 of any number of test articles 210. For example, each array 220 may be associated with a set of respective test articles 210 that are placed on (e.g., coupled to) a corresponding evaluation device (e.g., an evaluation board, a burn-in test board) or are part of a larger semiconductor assembly (e.g., the test articles 210 are associated with semiconductor dies that will be separated from the semiconductor wafer associated with the array 220), and the respective arrays 220 may be placed together in the chamber 205 for one or more evaluations. In some examples, each test article 210 may be independently controlled by its own respective components (e.g., internal circuitry, sensors).

[0030] In some cases, an evaluation controller 225 may be coupled to chamber 205. In various examples, evaluation controller 225 may be an example of a host system and may communicate with chamber 205, components within chamber 205 (e.g., evaluation devices, test article 210), or both. For example, evaluation controller 225 may transmit access signaling (e.g., one or more access commands, evaluation routine instructions, or other commands) and may receive corresponding signaling (e.g., data from an access operation, an indication from test article 210, signaling indicating whether an evaluation route was successfully performed) based on the transmitted access signaling.

[0031] Test articles 210 may be placed in chamber 205 for an evaluation procedure (e.g., operational stress testing, burn testing), and each test article 210 may enter an evaluation mode (e.g., based on receiving an indication from evaluation controller 225). The evaluation procedure may include increasing the temperature of chamber 205 while test article 210 performs one or more operations (e.g., internal operations of test article 210, memory access operations). In some cases, the evaluation procedure may ensure that test article 210 operates as expected at high temperatures (e.g., as part of a design verification test, as part of a manufacturing verification, for ensuring that a manufactured part is suitable for final assembly). In order to satisfy (e.g., pass) the evaluation procedure, test article 210 may be expected to satisfy (e.g., reach, exceed) at least one target temperature threshold associated with the evaluation procedure (e.g., minimum temperature, temperature threshold for high temperature evaluation). For example, if test article 210 fails to reach the target temperature threshold, then it fails the evaluation procedure.

[0032] In some cases, the respective temperatures of different zones 215 of chamber 205 or different test articles 210, or both, may not be uniform throughout chamber 205. For example, some zones 215 of chamber 205 or some test articles 210, or both, may have a higher (e.g., hotter) temperature than other zones 215 or other test articles 210. In some examples, test articles 210 in zone 215-a may be associated with a higher article temperature 230 and test articles 210 in zone 215-b may be associated with a lower article temperature 235 (e.g., due to inconsistent room temperature, due to inconsistent heating of test articles 210 in zones 215). Such temperature inconsistencies may result in some test articles 210 in chamber 205 exceeding an upper temperature threshold (e.g., maximum temperature, overtemperature) associated with an evaluation procedure, while some other test articles 210 in chamber 205 fail to reach a lower temperature threshold (e.g., target temperature threshold) associated with the evaluation procedure.

[0033] In some examples, if the temperature of test article 210 exceeds an upper temperature threshold, test article 210 may experience an overheating condition (e.g., thermal runaway) in which test article 210 may generate more heat than test article 210 can dissipate. In some cases, such conditions may result in damage to test article 210 (e.g., and components within test article 210). For example, test article 210-a may be associated with higher article temperature 230 and experience thermal runaway. As a result, one or more portions of test article 210-a may physically deform (e.g., twist, crack), or components of test article 210-a may overheat and fail (e.g., separate, burn, melt), among other high temperature failures.

[0034] In some cases, a test article 210 that exceeds an upper temperature threshold may cease (e.g., pause, interrupt) evaluation operations to stop further heat generation and mitigate component damage. Thus, a test article 210 fails the evaluation procedure and is subject to additional evaluation procedures (e.g., re-evaluation of the test article 210) or may be discarded based on potential or experienced component damage (e.g., due to irreparable component damage). In some other cases, a test article 210 that fails to reach a lower temperature threshold fails the evaluation procedure and is subject to additional evaluation procedures (e.g., re-evaluation of the test article 210 to meet the lower temperature threshold).

[0035] In an illustrative example, test article 210-a may be associated with a higher item temperature 230 and may meet an upper temperature threshold. Therefore, test article 210-a fails the evaluation procedure and may be discarded or subject to an additional evaluation procedure (e.g., retesting). Test article 210-b may be associated with a normal item temperature (e.g., an intermediate temperature between higher item temperature 230 and lower item temperature 235) and may operate as expected. Therefore, test article 210-b may meet the evaluation procedure (e.g., may meet operational expectations as part of a design verification test). Test article 210-c may be associated with a lower item temperature 235 and fail to meet a lower temperature threshold. Therefore, test article 210-c fails to meet the evaluation procedure and is subject to an additional evaluation procedure. Such temperature variations between test articles 210 in the same evaluation procedure may result in reduced efficiency of the evaluation procedure and reduced production yield.

[0036] According to the techniques described herein, a test article 210 (e.g., a semiconductor component) may be configured to operate in a reduced heating mode of operation. In some examples, the test article 210 may operate in the reduced heating mode based on a temperature indicated by one or more temperature sensors of the test article 210 satisfying a temperature threshold (e.g., a reverse bias temperature threshold) while performing one or more evaluation operations. The temperature threshold may be configured (e.g., programmed, set, preconfigured) to be above a target temperature threshold of the evaluation procedure but below an upper temperature threshold (e.g., associated with thermal runaway). The reduced heating mode may be associated with the test article 210 modifying (e.g., increasing) a threshold voltage characteristic of one or more transistors (e.g., reverse biasing one or more transistors or their wells), as well as other configurations that may reduce current and corresponding heating in the test article 210.

[0037] For example, test article 210-a and test article 210-b may be placed in chamber 205 for an evaluation procedure. Test article 210-a and test article 210-b may receive (e.g., from evaluation controller 225) respective indications to operate in an evaluation mode (e.g., a mode for performing evaluation operations such as memory access operations or other internal operations). Thus, test article 210-a and test article 210-b may configure their respective components to operate in a first evaluation mode (e.g., a nominal evaluation mode, a baseline evaluation mode) and may begin performing respective evaluation operations of the evaluation procedure. In response to performing the evaluation operations, one or more temperature sensors at test article 210-a may indicate that the temperature of test article 210-a satisfies a temperature threshold (e.g., a reverse bias temperature threshold), and test article 210-a may be configured to operate in a second evaluation mode (e.g., a reduced heat evaluation mode). However, the temperature sensor of test item 210-b may indicate that the temperature of test item 210-b fails to meet the temperature threshold in response to performing the evaluation operation, and test item 210-b may avoid operating in the second evaluation mode (e.g., may continue to operate in the first evaluation mode).

[0038] Configuring the test articles 210 to operate in an evaluation mode (e.g., reduced heating mode) based on a temperature threshold can enable each test article 210 to individually adjust heating to both reach a target temperature and avoid exceeding an upper temperature threshold. Such techniques can result in improved production yield (e.g., due to an increase in the number of test articles that meet the criteria of the evaluation procedure) and improved efficiency of the evaluation procedure (e.g., due to a reduction in re-evaluations of failed test articles 210).

[0039] Figure 3 An example of a system 300 supporting thermal control for memory system evaluation according to examples disclosed herein is shown. System 300 may include a semiconductor component 305 having one or more subcomponents, such as one or more memory arrays 310, one or more temperature sensors 315, one or more voltage sources 320, and circuitry 325. Semiconductor component 305 may be an example of or include a memory system 110 (e.g., a packaged memory system), a memory device 145 (e.g., a packaged memory device, a memory die), a host system 105 or a portion thereof, or a combination thereof, or a test article 210. Graph 340 may illustrate an example of the temperature of semiconductor component 305 over time (e.g., measurements or calculations based on readings of one or more temperature sensors 315) during an example of an evaluation procedure.

[0040] In some examples, semiconductor components 305 may be subjected to an evaluation procedure (e.g., a burn test, a temperature stress test) for verification during the production process. During the evaluation procedure, semiconductor component 305 may be coupled with one or more other semiconductor components 305 (e.g., placed on a shared evaluation device such as a burn-in test board or included in a common semiconductor wafer). Semiconductor components 305 may be placed in an evaluation chamber (e.g., chamber 205) that may increase the temperature (e.g., ambient temperature) of the evaluation procedure. However, due to non-uniform conditions (e.g., inconsistent temperatures throughout the chamber, inconsistent heating between different semiconductor components 305), some semiconductor components 305 may experience higher or lower temperatures than other semiconductor components 305, which may result in component damage (e.g., due to overheating), repeated evaluation procedures (e.g., due to failure to pass the evaluation procedure), or both and other adverse effects. According to examples disclosed herein, semiconductor component 305 may dynamically adjust its heating based on comparing the temperature of semiconductor component 305 to one or more temperature thresholds.

[0041] The circuit system 325 may be coupled or operable to be coupled (e.g., via one or more internal buses) with one or more memory arrays 310, one or more temperature sensors 315, and one or more voltage sources 320. The circuit system 325 may also be coupled to an external device (e.g., evaluation system 200, host system 105, evaluation controller 225) via input / output (I / O) circuit system 330. In some examples, the circuit system 325 may cause (e.g., configure) the semiconductor component 305 to perform one or more operations described herein. For example, the circuit system 325 may configure the semiconductor component 305 to operate in one or more evaluation operation modes (e.g., test modes) and perform one or more operations (e.g., evaluation operations) according to the evaluation operation modes. In some examples, the circuit system 325 may be an example of or include one or more of the following: the memory system controller 140, the local controller 150, the processor 125, the host system controller 120, or any combination thereof.

[0042] In some examples, the circuit system 325 may receive an indication to operate in the evaluation mode (e.g., from the evaluation system 200, from the evaluation controller 225). Based on the received indication, the circuit system 325 may configure the semiconductor component 305 to operate in a first evaluation mode (e.g., a nominal evaluation mode, an initial operation mode). Therefore, the semiconductor component 305 (e.g., the circuit system 325) may perform one or more first operations (e.g., evaluation operations, test operations) according to the first evaluation mode, which may be in response to a command or instruction from the evaluation controller 225 of the evaluation system 200. In some examples, the one or more first operations may include, for example, an evaluation operation to access (e.g., a read operation, a write operation) one or more memory arrays 310 (e.g., a memory cell in one or more memory arrays 310), an internal operation of the semiconductor component 305, other operations, or any combination thereof.

[0043] Execution of the evaluation operation may cause the temperature of the semiconductor component 305 to increase (e.g., due to the current and power consumption associated with operating the semiconductor component 305). In some examples, the temperature of the semiconductor component 305 may meet (e.g., reach or exceed) one or more temperature thresholds (e.g., temperature threshold 345, temperature threshold 350, temperature threshold 355) based on execution of the evaluation operation. In some examples, the semiconductor component 305 may be expected to reach at least one temperature threshold 345 (e.g., target temperature threshold, minimum temperature) to satisfy the evaluation procedure. In some examples, the semiconductor component 305 may be expected to remain below the temperature threshold 355. For example, exceeding the temperature threshold 355 may cause the semiconductor component 305 to stop the evaluation operation to mitigate potential damage to the semiconductor component 305 caused by an overheating condition (e.g., thermal runaway). For example, in a successful evaluation operation, the temperature of the semiconductor component 305 may remain between the temperature threshold 345 and the temperature threshold 355 during at least a portion of the evaluation operation.

[0044] In some implementations, the circuit system 325 may be configured to compare the one or more temperatures indicated by the one or more temperature sensors 315 with a temperature threshold 350 (e.g., an intermediate temperature threshold) that is above the temperature threshold 345 and below the temperature threshold 355. The one or more temperature sensors 315 may monitor the one or more temperatures of the semiconductor component 305 and may indicate the one or more temperatures to the circuit system 325 during the evaluation procedure. In some examples, the one or more temperature sensors 315 may indicate the one or more temperatures according to a periodicity (e.g., 1 millisecond) or based on a request from the circuit system 325, or both. The circuit system 325 may compare the temperature indicated by the one or more temperature sensors 315 with the temperature thresholds (e.g., the temperature threshold 345, the temperature threshold 350, and the temperature threshold 355) and may determine whether the temperature satisfies any of the temperature thresholds based on the comparison.

[0045] Based on at least one of the one or more temperatures satisfying the temperature threshold 350 (e.g., in response to performing one or more first operations), the circuit system 325 may configure the semiconductor component 305 to operate in the second evaluation mode (e.g., reduced heat generation mode). For example, the circuit system 325 (e.g., or another component of the semiconductor component 305) may set the value of a flag (e.g., a bit) in the one or more registers 335 based on the temperature satisfying the temperature threshold 350. In such an example, configuring the semiconductor component 305 to operate in the second evaluation mode may be based on the value of the flag. The second evaluation mode may be associated with lower heat generation than the first evaluation mode (e.g., initial operation mode). The semiconductor component 305 (e.g., the circuit system 325) may perform one or more second operations (e.g., evaluation operations, test operations) according to the second evaluation mode based on being configured to operate in the second evaluation mode. In some examples, circuitry 325 may transmit (eg, via I / O circuitry 330 to an external device, evaluation controller 225 of evaluation system 200 ) an indication that semiconductor component 305 is configured to operate in the second evaluation operating mode or that the temperature of semiconductor component 305 has satisfied temperature threshold 350 .

[0046] In some examples, the circuit system 325 can configure the semiconductor component 305 to operate in the second evaluation mode by controlling the reverse bias setting of the semiconductor component 305. Therefore, in some examples, the temperature threshold 350 can be referred to as a reverse bias threshold or a reverse bias temperature threshold. Controlling the reverse bias setting can be associated with increasing the threshold voltage (e.g., V t Value, V th In some embodiments, the semiconductor device 305 may be associated with a threshold voltage (e.g., a gate voltage) of one or more transistors. For example, increasing the threshold voltage of one or more transistors may include increasing a bias voltage from one or more voltage sources 320 applied to one or more wells of the semiconductor device 305 associated with the one or more transistors. In some examples, increasing the threshold voltage of a transistor may modify the conductivity of the transistor, for example, by modulating (e.g., increasing) a voltage (e.g., a gate voltage) to activate the transistor. Modulating the threshold voltage of one or more transistors of the semiconductor device 305 may reduce power consumption (e.g., and current flow), thereby reducing heating of the semiconductor device 305. However, in some other examples, other techniques may be implemented to change the threshold voltage characteristics or otherwise reduce heating associated with the operation of the semiconductor device 305 (e.g., reducing current, reducing power consumption).

[0047] Circuitry 325 may increase bias voltages for all transistors of semiconductor component 305 or for a subset of transistors of semiconductor component 305 (e.g., based on different readings from different temperature sensors 315, based on which transistors may be associated with heat generation, based on transistors whose threshold voltage characteristics may be modified). For example, circuitry 325 may increase a first bias voltage for a first subset of wells associated with a first subset of transistors of semiconductor component 305 based on a temperature indicated by one or more first temperature sensors and may maintain a second bias voltage for a second subset of wells associated with a second subset of transistors of semiconductor component 305 based on a temperature indicated by one or more second temperature sensors.

[0048] In some examples, semiconductor component 305 may exceed temperature threshold 355, which may be associated with an upper temperature threshold of the evaluation procedure (e.g., may be greater than temperature threshold 350). In some examples, circuit system 325 may configure semiconductor component 305 to stop evaluation operation (e.g., circuit system 325 may stop performing evaluation operation) based on the temperature indicated by one or more temperature sensors 315 satisfying temperature threshold 355 (e.g., stop generating heat and mitigate damage to semiconductor component 305). In some examples, circuit system 325 may transmit (e.g., to an external device, evaluation controller 225 via I / O circuit system 330) an indication that semiconductor component 305 is configured to stop evaluation operation.

[0049] In the example illustrated by graph 340, the evaluation procedure may begin at time t0. Curve 360 ​​may illustrate the temperature of first semiconductor component 305 (e.g., temperature readings associated with one or more temperature sensors 315) and curve 365 may illustrate the temperature of second semiconductor component 305 over the duration of the evaluation procedure. In some examples, first semiconductor component 305 and second semiconductor component 305 may be placed in the same chamber (e.g., chamber 205) for the evaluation procedure, which may include first semiconductor component 305 and second semiconductor component 305 being members of the same array 220 or different arrays 220.

[0050] At time t0, the first semiconductor component 305 and the second semiconductor component 305 may be configured to perform one or more first evaluation operations according to the first evaluation mode. The temperature of the first semiconductor component 305 and the second semiconductor component 305 may increase accordingly over time. At time t1, the temperature of the first semiconductor component 305 may satisfy the temperature threshold 350 (e.g., the reverse bias temperature threshold). In response, the circuit system 325 of the first semiconductor component 305 may configure the first semiconductor component 305 to operate in a second evaluation mode (e.g., the reduced heating mode), which may include controlling the reverse bias setting of the first semiconductor component 305. Based on operating in the second evaluation mode, the heating of the first semiconductor component 305 may be reduced, so that the temperature of the first semiconductor component 305 may stabilize or decrease before reaching the temperature threshold 355 (e.g., not reaching the temperature threshold 355). As illustrated by curve 365, the temperature of the second semiconductor component 305 may not satisfy the temperature threshold 350, and the second semiconductor component 305 may accordingly continue to operate according to the first evaluation mode during the evaluation procedure (e.g., not operating in the reduced heating mode, not controlling or adjusting the reverse bias setting). At time t2 , the evaluation process may be complete and both the first semiconductor component 305 and the second semiconductor component 305 may satisfy the evaluation process based on meeting operational expectations, satisfying at least the temperature threshold 345 (eg, target temperature), and avoiding reaching the temperature threshold 355 .

[0051] As described herein, controlling the reverse bias setting can enable the semiconductor component 305 to dynamically control its temperature during the evaluation procedure. Thus, the semiconductor component 305 can (e.g., dynamically, autonomously) compensate for non-uniform evaluation conditions (e.g., non-uniform room temperature), thereby reducing the likelihood of component damage (e.g., due to thermal runaway) and increasing the likelihood of satisfying the evaluation procedure (e.g., satisfying criteria of the evaluation procedure). Thus, the efficiency of the evaluation procedure can be increased, resulting in an increased production yield of the manufacturing process.

[0052] Figure 4 A block diagram 400 is shown of a semiconductor component 420 that supports thermal control for memory system evaluation according to examples disclosed herein. The semiconductor component 420 may be a reference Figures 1 to 3 4. The semiconductor component 420 or its various components may be examples of means for performing various aspects of thermal control for memory system evaluation, as described herein. For example, the semiconductor component 420 may include an indication receiving component 425, an evaluation mode component 430, an evaluation operation component 435, a transistor configuration component 440, a register component 445, an indication transmission component 450, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0053] The indication receiving component 425 may be configured as or otherwise support means for receiving an indication to operate in the evaluation mode at the semiconductor component 420. The evaluation mode component 430 may be configured as or otherwise support means for configuring the semiconductor component 420 to operate in the first evaluation mode based at least in part on receiving the indication. The evaluation operation component 435 may be configured as or otherwise support means for performing one or more first operations of the semiconductor component 420 based at least in part on configuring the semiconductor component 420 to operate in the first evaluation mode. In some examples, the evaluation mode component 430 may be configured as or otherwise support means for configuring the semiconductor component 420 to operate in a second evaluation mode in response to performing the one or more first operations based at least in part on a temperature indicated by at least one temperature sensor of the semiconductor component 420 satisfying a temperature threshold, the second evaluation mode being associated with lower heat generation than the first evaluation mode. In some examples, the evaluation operation component 435 may be configured as or otherwise support means for performing one or more second operations of the semiconductor component 420 based at least in part on configuring the semiconductor component 420 to operate in the second evaluation mode.

[0054] In some examples, to support configuring the semiconductor component to operate in the second evaluation mode, transistor configuration component 440 may be configured as or otherwise support means for increasing a threshold voltage characteristic of one or more transistors of semiconductor component 420 during the second evaluation mode. In some examples, to support increasing a threshold voltage characteristic of one or more transistors, transistor configuration component 440 may be configured as or otherwise support means for increasing a bias voltage from one or more voltage sources of semiconductor component 420 applied to one or more wells of semiconductor component 420 associated with the one or more transistors.

[0055] In some examples, transistor configuration component 440 may be configured or otherwise support means for increasing a bias voltage based at least in part on a temperature indicated by at least one temperature sensor. In some examples, transistor configuration component 440 may be configured or otherwise support means for maintaining a second bias voltage applied to one or more second wells of semiconductor component 420 associated with one or more second transistors of semiconductor component 420 based at least in part on a second temperature indicated by at least one second temperature sensor of semiconductor component 420. In some examples, the temperature threshold is below a second temperature threshold associated with stopping the evaluation operation.

[0056] In some examples, the evaluation operation component 435 can be configured to or otherwise support means for configuring the semiconductor component 420 to cease the evaluation operation based at least in part on a second temperature indicated by one or more temperature sensors of the semiconductor component 420 satisfying a second temperature threshold. In some examples, the temperature threshold is above a target temperature associated with the evaluation of the semiconductor component 420.

[0057] In some examples, evaluation mode component 430 can be configured or otherwise support means for comparing the temperature indicated by at least one temperature sensor to a temperature threshold according to a periodicity. In some examples, evaluation mode component 430 can be configured or otherwise support means for determining that the temperature indicated by at least one temperature sensor satisfies the temperature threshold based at least in part on the comparison.

[0058] In some examples, register component 445 can be configured as or otherwise support means for setting a value of a flag of semiconductor component 420 based at least in part on the temperature satisfying a temperature threshold, wherein configuring semiconductor component 420 to operate in the second evaluation mode is based at least in part on the value of the flag. In some examples, one or more first operations, one or more second operations, or both are associated with circuitry of semiconductor component 420 accessing one or more memory arrays of semiconductor component 420.

[0059] In some examples, indication transmitting component 450 can be configured as or otherwise support means for transmitting a first indication that semiconductor component 420 is configured to operate in the second evaluation mode, a second indication that semiconductor component 420 is configured to cease evaluation operations, or both.

[0060] In some examples, the described functionality of semiconductor component 420 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of semiconductor component 420 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0061] Figure 5 A flowchart illustrating a method 500 for supporting thermal control for memory system evaluation according to examples disclosed herein is shown. The operations of the method 500 may be performed by a semiconductor component or an evaluation system described herein, or a combination thereof. For example, at least a portion of the operations of the method 500 may be performed by a reference Figures 1 to 4Additionally or alternatively, at least a portion of the operations of method 500 may be performed by an evaluation system (e.g., evaluation controller 225) or a component thereof as described herein. For example, the operations of method 500 may be performed by reference to Figure 2 The evaluation system 200 described herein performs. In some examples, a semiconductor component or evaluation system may execute a set of instructions to control functional elements of a device to perform the described functions. Additionally or alternatively, a semiconductor component or evaluation system may use dedicated hardware to perform aspects of the described functions.

[0062] At 505, the method may include (eg, at a semiconductor component, at an evaluation system) receiving an indication to operate in an evaluation mode. In some examples, aspects of operation 505 may be referred to as Figure 4 The described instructions are received by component 425 for execution.

[0063] At 510, the method may include configuring the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication. In some examples, aspects of operation 510 may be described with reference to Figure 4 The evaluation mode component 430 is described as executing.

[0064] At 515, the method may include performing one or more first operations (eg, of a semiconductor component or an evaluation system) based at least in part on configuring the semiconductor component to operate in a first evaluation mode. In some examples, aspects of operation 515 may be described with reference to Figure 4 The described evaluation operation component 435 performs.

[0065] At 520, the method may include configuring the semiconductor component to operate in a second evaluation mode in response to performing the one or more first operations based at least in part on a temperature indicated by at least one temperature sensor of the semiconductor component satisfying a temperature threshold, the second evaluation mode being associated with lower heat generation than the first evaluation mode. In some examples, aspects of operation 520 may be described with reference to Figure 4 The evaluation mode component 430 is described as executing.

[0066] At 525, the method may include performing one or more second operations (eg, semiconductor component, evaluation system) based at least in part on configuring the semiconductor component to operate in the second evaluation mode. In some examples, aspects of operation 525 may be described with reference to Figure 4 The described evaluation operation component 435 performs.

[0067] In some examples, the apparatus described herein may perform one or several methods, such as method 500. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0068] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for: receiving an indication to operate in an evaluation mode (e.g., at a semiconductor component, at an evaluation system); configuring the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication; performing one or more first operations (e.g., of the semiconductor component, of the evaluation system) based at least in part on configuring the semiconductor component to operate in the first evaluation mode; configuring the semiconductor component to operate in a second evaluation mode in response to performing the one or more first operations based at least in part on a temperature indicated by at least one temperature sensor of the semiconductor component satisfying a temperature threshold, the second evaluation mode being associated with lower heat generation than the first evaluation mode; and performing one or more second operations (e.g., of the semiconductor component, of the evaluation system) based at least in part on configuring the semiconductor component to operate in the second evaluation mode.

[0069] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, wherein configuring the semiconductor component to operate in the second evaluation mode further comprises operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for increasing a threshold voltage characteristic of one or more transistors of the semiconductor component during the second evaluation mode.

[0070] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to Aspect 2, wherein increasing the threshold voltage characteristics of the one or more transistors includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for increasing a bias voltage from one or more voltage sources of the semiconductor component applied to one or more wells of the semiconductor component associated with the one or more transistors.

[0071] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of Aspect 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: increasing the bias voltage based at least in part on the temperature indicated by the at least one temperature sensor; and maintaining a second bias voltage applied to one or more second wells of the semiconductor component associated with one or more second transistors of the semiconductor component based at least in part on a second temperature indicated by at least one second temperature sensor of the semiconductor component.

[0072] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 4, wherein the temperature threshold is lower than a second temperature threshold associated with stopping evaluation operations.

[0073] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to Aspect 5, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for configuring the semiconductor component to stop evaluating operations based at least in part on a second temperature indicated by one or more temperature sensors of the semiconductor component satisfying the second temperature threshold.

[0074] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 6, wherein the temperature threshold is higher than a target temperature associated with an evaluation of the semiconductor component.

[0075] Aspect 8: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: periodically comparing the temperature indicated by the at least one temperature sensor with the temperature threshold; and determining, at least in part based on the comparison, that the temperature indicated by the at least one temperature sensor satisfies the temperature threshold.

[0076] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 8, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for setting a value of a flag of the semiconductor component based at least in part on the temperature satisfying the temperature threshold, wherein configuring the semiconductor component to operate in the second evaluation mode is based at least in part on the value of the flag.

[0077] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 9, wherein the one or more first operations, the one or more second operations, or both are associated with circuitry of the semiconductor component accessing one or more memory arrays of the semiconductor component.

[0078] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 10, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transmitting a first indication that the semiconductor component is configured to operate in the second evaluation mode, a second indication that the semiconductor component is configured to stop evaluation operation, or both.

[0079] Aspect 12: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 11, further comprising the following operations, features, circuit systems, logic, means, or instructions, or any combination thereof: placing the semiconductor component and a second semiconductor component in a temperature chamber; receiving a second indication of operating in the evaluation mode (for example, at the second semiconductor component); configuring the second semiconductor component to operate in the first evaluation mode based at least in part on receiving the second indication; performing one or more third operations (for example, of the second semiconductor component) based at least in part on configuring the second semiconductor component to operate in the first evaluation mode; and avoiding configuring the second semiconductor component to operate in the second evaluation mode in response to performing the one or more first operations based at least in part on a second temperature indicated by at least one second temperature sensor of the second semiconductor component failing to satisfy the temperature threshold.

[0080] It should be noted that the aspects described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0081] An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

[0082] Aspect 13: A device comprising: one or more memory arrays of a semiconductor component; one or more temperature sensors of the semiconductor component; and a circuit system of the semiconductor component, which is coupled to the one or more memory arrays and the one or more temperature sensors, the circuit system being operable to cause the device (e.g., cause the device, cause the semiconductor component) to: receive an indication to operate in an evaluation mode; configure the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication; perform one or more first operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the first evaluation mode; configure the semiconductor component to operate in a second evaluation mode in response to performing the one or more first operations based at least in part on a temperature indicated by at least one of the one or more temperature sensors satisfying a temperature threshold, the second evaluation mode being associated with lower heat generation than the first evaluation mode; and perform one or more second operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the second evaluation mode.

[0083] Aspect 14: The apparatus of aspect 13, wherein to configure the semiconductor component to operate in the second evaluation mode, the circuit system is operable to: modify (eg, increase) a threshold voltage characteristic of one or more transistors of the circuit system during the second evaluation mode.

[0084] Aspect 15: The apparatus according to Aspect 14 further comprises: one or more voltage sources of the semiconductor component, wherein in order to modify the threshold voltage characteristics of the one or more transistors, the circuit system is operable to: increase the bias voltage from the one or more voltage sources applied to one or more wells of the semiconductor component associated with the one or more transistors.

[0085] Aspect 16: An apparatus according to Aspect 15, wherein the circuit system is further operable to: increase the bias voltage based at least in part on the temperature indicated by at least one of the one or more temperature sensors; and maintain a second bias voltage applied to one or more second wells of the semiconductor component associated with one or more second transistors of the semiconductor component based at least in part on a second temperature indicated by at least one second temperature sensor of the one or more temperature sensors.

[0086] Aspect 17: The apparatus of any one of aspects 13 to 16, wherein the temperature threshold is lower than a second temperature threshold associated with stopping evaluation operations.

[0087] Aspect 18: The apparatus of aspect 17, wherein the circuit system is further operable to: configure the semiconductor component to cease evaluation operations based at least in part on a second temperature indicated by the one or more temperature sensors satisfying the second temperature threshold.

[0088] Aspect 19: The apparatus of any one of aspects 13 to 18, wherein the temperature threshold is higher than a target temperature associated with evaluation of the semiconductor component.

[0089] Aspect 20: An apparatus according to any one of Aspects 13 to 19, wherein the circuit system is operable to: periodically compare the temperature indicated by at least one of the one or more temperature sensors with the temperature threshold; and determine, at least in part based on the comparison, that the temperature indicated by at least one of the one or more temperature sensors satisfies the temperature threshold.

[0090] Aspect 21: An apparatus according to any one of Aspects 13 to 20, wherein the circuit system is further operable to: set a value of a flag of the semiconductor component based at least in part on the temperature satisfying the temperature threshold, wherein configuring the semiconductor component to operate in the second evaluation mode is based at least in part on the value of the flag.

[0091] Aspect 22: The apparatus of any of aspects 13-21, wherein the one or more first operations, the one or more second operations, or both are associated with the circuitry accessing the one or more memory arrays.

[0092] Aspect 23: The apparatus of any one of aspects 13 to 22, wherein the circuit system is further operable to: transmit a first indication that the semiconductor component is configured to operate in the second evaluation mode, a second indication that the semiconductor component is configured to cease evaluation operation, or both.

[0093] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0094] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (e.g., conductive contact, connection, coupling) with each other if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. The conductive path between components that are in electronic communication (e.g., conductive contact, connection, coupling) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or may be an indirect conductive path that includes an intermediate component (e.g., a switch, transistor, or other component). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0095] The term "isolation" may refer to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from one another. When a component isolates two components, the component may induce changes that prevent a signal from flowing between other components using a conductive path that previously permitted the signal to flow.

[0096] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open-circuit relationship between components, where signals cannot currently be communicated between the components (e.g., via conductive paths), to a closed-circuit relationship between the components, where signals can be communicated between the components (e.g., via conductive paths). When a component, such as a controller, couples other components together, the component may induce a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0097] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic.

[0098] The switch components (e.g., transistors) discussed herein may be field effect transistors (FETs) and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and the drain, and a gate (e.g., a gate terminal). The conductivity of the channel may be controlled (e.g., modulated) by applying a voltage to the gate, which may, in some examples, cause the channel to become conductive. The switch component may be an example of an n-type FET or a p-type FET.

[0099] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The "Detailed Description" includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0100] In the accompanying drawings, similar components or features may have the same reference label. Similar components may be distinguished by following the reference label with one or more dashes and an additional label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label, regardless of the additional reference labels.

[0101] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted over a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processing system, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may be physically located at various locations, including distributed such that portions of the functions are implemented at different physical locations.

[0102] The illustrative blocks and modules described herein may be implemented or executed with one or more processors (e.g., DSPs, ASICs, FPGAs), discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0103] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0104] As used herein (including in the claims), the article "a" before a noun is open-ended and should be understood to refer to "at least one" of those nouns or "one or more" of those nouns. Therefore, the terms "one", "at least one", "one or more", and "at least one of one or more" are interchangeable. For example, if a claim recites "a component" that performs one or more functions, each of the individual functions may be performed by a single component or any combination of multiple components. Therefore, the term "a component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. The subsequent use of the term "the / said" to refer to the component introduced with the article "a" may refer to any or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and the subsequent reference to "the component" in the claim may be understood to be equivalent to referring to "at least one of one or more components". Similarly, a component introduced as "one or more components" subsequently referenced using the term "the / said" may refer to any or all of the one or more components. For example, a subsequent reference to "one or more components" in a claim may be understood to be equivalent to referring to "at least one of the one or more components."

[0105] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media or a combination of multiple media that can be accessed by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a computer or processor.

[0106] The description and drawings are provided to enable one of ordinary skill in the art to make or use the present disclosure. One of ordinary skill in the art will appreciate the various modifications of the present disclosure, and the techniques disclosed herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: one or more memory arrays of a semiconductor device; one or more temperature sensors for the semiconductor device; and circuitry of the semiconductor component coupled to the one or more memory arrays and the one or more temperature sensors, the circuitry being operable to cause the apparatus to: receiving an indication to operate in an evaluation mode; configuring the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication; performing one or more first operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the first evaluation mode; configuring the semiconductor component to operate in a second evaluation mode in response to performing the one or more first operations based at least in part on a temperature indicated by at least one of the one or more temperature sensors satisfying a temperature threshold, the second evaluation mode being associated with lower heat generation than the first evaluation mode; and One or more second operations of the semiconductor component are performed based at least in part on configuring the semiconductor component to operate in the second evaluation mode.

2. The apparatus of claim 1 , wherein to configure the semiconductor component to operate in the second evaluation mode, the circuit system is operable to: A threshold voltage characteristic of one or more transistors of the circuitry is increased during the second evaluation mode.

3. The apparatus according to claim 2, further comprising: one or more voltage sources of the semiconductor device, wherein to increase the threshold voltage characteristic of the one or more transistors, the circuit system is operable to: A bias voltage from the one or more voltage sources applied to one or more wells of the semiconductor component associated with the one or more transistors is increased.

4. The apparatus of claim 3, wherein the circuit system is further operable to: increasing the bias voltage based at least in part on the temperature indicated by the at least one of the one or more temperature sensors; and A second bias voltage applied to one or more second wells of the semiconductor component associated with one or more second transistors of the semiconductor component is maintained based at least in part on a second temperature indicated by at least one second temperature sensor of the one or more temperature sensors. 5 . The apparatus of claim 1 , wherein the temperature threshold is lower than a second temperature threshold associated with stopping evaluation operations.

6. The apparatus of claim 1, wherein the circuit system is further operable to: The semiconductor component is configured to cease evaluation operations based at least in part on a second temperature indicated by the one or more temperature sensors satisfying a second temperature threshold that is greater than the temperature threshold. 7 . The apparatus of claim 1 , wherein the temperature threshold is higher than a target temperature associated with an evaluation of the semiconductor component.

8. The apparatus of claim 1, wherein the circuit system is operable to: comparing the temperature indicated by the at least one of the one or more temperature sensors with the temperature threshold according to a periodicity; and A determination is made based at least in part on the comparison that the temperature indicated by the at least one of the one or more temperature sensors satisfies the temperature threshold.

9. The apparatus of claim 1, wherein the circuit system is further operable to: A value of a flag of the semiconductor component is set based at least in part on the temperature satisfying the temperature threshold, wherein configuring the semiconductor component to operate in the second evaluation mode is based at least in part on the value of the flag.

10. The apparatus of claim 1, wherein the one or more first operations, the one or more second operations, or both are associated with the circuitry accessing the one or more memory arrays.

11. The apparatus of claim 1 , wherein the circuit system is further operable to: A first indication that the semiconductor component is configured to operate in the second evaluation mode, a second indication that the semiconductor component is configured to cease evaluation operation, or both are transmitted.

12. A method comprising: receiving, at a semiconductor component, an indication to operate in an evaluation mode; configuring the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication; performing one or more first operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the first evaluation mode; configuring the semiconductor component to operate in a second evaluation mode in response to performing the one or more first operations based at least in part on a temperature indicated by at least one temperature sensor of the semiconductor component satisfying a temperature threshold, the second evaluation mode being associated with lower heat generation than the first evaluation mode; and One or more second operations of the semiconductor component are performed based at least in part on configuring the semiconductor component to operate in the second evaluation mode.

13. The method of claim 12, wherein configuring the semiconductor component to operate in the second evaluation mode further comprises: A threshold voltage characteristic of one or more transistors of the semiconductor device is increased during the second evaluation mode.

14. The method of claim 13, wherein increasing the threshold voltage characteristic of the one or more transistors comprises: A bias voltage from one or more voltage sources of the semiconductor component applied to one or more wells of the semiconductor component associated with the one or more transistors is increased.

15. The method according to claim 14, comprising: increasing the bias voltage based at least in part on the temperature indicated by the at least one temperature sensor; and A second bias voltage applied to one or more second wells of the semiconductor component associated with one or more second transistors of the semiconductor component is maintained based at least in part on a second temperature indicated by at least one second temperature sensor of the semiconductor component. 16 . The method of claim 12 , wherein the temperature threshold is above a target temperature associated with an evaluation of the semiconductor component.

17. The method according to claim 16, further comprising: The semiconductor component is configured to cease evaluation operations based at least in part on a second temperature indicated by one or more temperature sensors of the semiconductor component satisfying a second temperature threshold.

18. The method of claim 12, wherein the temperature threshold is above a target temperature associated with an evaluation of the semiconductor component.

19. The method of claim 12, further comprising: comparing the temperature indicated by the at least one temperature sensor with the temperature threshold according to a periodicity; and A determination is made based at least in part on the comparison that the temperature indicated by the at least one temperature sensor satisfies the temperature threshold.

20. The method of claim 12, further comprising: A value of a flag of the semiconductor component is set based at least in part on the temperature satisfying the temperature threshold, wherein configuring the semiconductor component to operate in the second evaluation mode is based at least in part on the value of the flag.

21. The method of claim 12, wherein the one or more first operations, the one or more second operations, or both are associated with circuitry of the semiconductor component accessing one or more memory arrays of the semiconductor component.

22. The method of claim 12, further comprising: A first indication that the semiconductor component is configured to operate in the second evaluation mode, a second indication that the semiconductor component is configured to cease evaluation operation, or both are transmitted.

23. The method of claim 12, further comprising: placing the semiconductor component and the second semiconductor component in a temperature chamber; receiving, at the second semiconductor component, a second indication of operating in the evaluation mode; configuring the second semiconductor component to operate in the first evaluation mode based at least in part on receiving the second indication; performing one or more third operations of the second semiconductor component based at least in part on configuring the second semiconductor component to operate in the first evaluation mode; and Configuring the second semiconductor component to operate in the second evaluation mode is avoided based at least in part on a second temperature indicated by at least one second temperature sensor of the second semiconductor component failing to satisfy the temperature threshold in response to performing the one or more first operations.

24. A non-transitory computer readable medium storing code, the code comprising instructions executable by a processor to: receiving, at a semiconductor component, an indication to operate in an evaluation mode; configuring the semiconductor component to operate in a first evaluation mode based at least in part on receiving the indication; performing one or more first operations of the semiconductor component based at least in part on configuring the semiconductor component to operate in the first evaluation mode; configuring the semiconductor component to operate in a second evaluation mode in response to performing the one or more first operations based at least in part on a temperature indicated by at least one temperature sensor of the semiconductor component satisfying a temperature threshold, the second evaluation mode being associated with lower heat generation than the first evaluation mode; and One or more second operations of the semiconductor component are performed based at least in part on configuring the semiconductor component to operate in the second evaluation mode.

25. The non-transitory computer-readable medium of claim 24, wherein the instructions for configuring the semiconductor component to operate in the second evaluation mode are executable by the processor to: A threshold voltage characteristic of one or more transistors of the semiconductor device is increased during the second evaluation mode.

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