Power control chain

Abstract

The invention relates to a power control chain. A method includes determining that a power event involving a memory subsystem has occurred. The method further includes, in response to the determining that the power event has occurred, generating signaling indicating an operation is performed to provide power to a plurality of memory components of the memory subsystem, wherein the signaling indicating execution includes applying a power control signal to a first memory component at a first time and to a second memory component at a second time after the first memory component enters a steady state.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to power control chains. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] On the one hand, the present disclosure provides a method for a power control chain, comprising: determining that a power event involving a memory subsystem has occurred; and in response to the determination that the power event has occurred, generating a signal indicating the execution of an operation to provide power to multiple memory components of the memory subsystem, wherein the signal indicating the execution of the operation to provide power to the multiple memory components is sequentially applied to each memory component of the multiple memory components, wherein the signal indicating the execution includes a power control signal, the power control signal: applied to a first memory component of the multiple memory components at a first time; and applied to a second memory component of the multiple memory components at a second time, wherein the power control signal is applied to the second memory component after the first memory component enters a stable state.

[0004] On the other hand, the present disclosure provides a power control chain device, comprising: a plurality of memory components, which are coupled to each other via a power control line; and a power control chain controller, comprising a power controller and a clock controller coupled to the plurality of memory components, wherein the power controller is configured to: determine that a power event involving the plurality of memory components has occurred; and apply a signal indicating the power event involving the plurality of memory components to the power control line to cause the power control line to: sequentially apply a power control signal generated by the power controller to each of the plurality of memory components via the power control line, so that the power control signal: is applied to a first memory component among the plurality of memory components at a first rising edge of a clock signal pulse generated by the clock controller; and is applied to a second memory component among the plurality of memory components at a second rising edge of the clock signal pulse generated by the clock controller.

[0005] On the other hand, the present disclosure provides a power control chain system, which includes: a plurality of memory components arranged in series; a first power control chain, which includes: a plurality of power control chain components, which separate the plurality of memory components arranged in series; and a first power control line, which couples the plurality of memory components and the plurality of power control chain components to each other; a power controller, which is coupled to the first power control chain and is configured to generate a power control signal; a clock controller, which is coupled to the plurality of power control chain components of the first power control chain and is configured to generate a clock signal pulse at a set interval; and a processing device, which is coupled to the power controller and the clock controller, wherein the processing device is configured to: determine that a power event criterion has been met; based on the determination that the power event criterion has been met, cause the power controller to generate the power control signal to the first power control chain; based on the determination that Satisfying the power event criteria causes the clock controller to generate a clock signal pulse to the multiple power control chain components of the first power control chain; causes a first memory component among the multiple memory components to be powered on based on receiving the power control signal; causes the first power control chain component among the multiple power control chain components to be activated after a set interval based on receiving a first clock signal pulse from the clock controller; causes a second memory component among the multiple memory components to be powered on based on receiving the power control signal due to the activation of the first power control chain component; causes any subsequent power control chain components among the multiple power control chain components to be activated sequentially, with each activation separated by the set interval; and causes any additional memory component among the multiple memory components to be powered on based on receiving the power control signal due to the activation of the subsequent power control chain component. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 is a flow chart corresponding to a memory subsystem power control chain according to some embodiments of the present disclosure.

[0009] Figure 3A is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

[0010] Figure 3B is another block diagram of an example computer system in which embodiments of the present disclosure may operate.

[0011] Figure 3Cis yet another block diagram of an example computer system in which embodiments of the present disclosure may operate.

[0012] Figure 3D is yet another block diagram of an example computer system in which embodiments of the present disclosure may operate.

[0013] Figure 3E is yet another block diagram of an example computer system in which embodiments of the present disclosure may operate.

[0014] Figure 4 is a flow chart corresponding to a method for memory subsystem power control chaining according to some embodiments of the present disclosure.

[0015] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0016] Aspects of the present disclosure relate to a power control chain (PCC) system, and in particular, to a memory subsystem comprising a PCC system. The memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system, such as a solid state drive (SSD). Figure 1 and others to describe examples of storage devices and memory modules. In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system may provide data stored at the memory subsystem and may request data retrieved from the memory subsystem.

[0017] Although the non-limiting examples herein are generally described in terms of application to memory systems and subsystems and / or memory devices, the embodiments are not limited thereto and aspects of the present disclosure may also be applied to systems on a chip, computing systems / subsystems, data collection and processing, storage, networking, communications, power, artificial intelligence, control, telemetry, sensing and monitoring, digital entertainment, and other types of systems, subsystems, and / or devices. Thus, aspects of the present disclosure may be applied to these components in conjunction with a power control chain, as described herein.

[0018] During operation, one central controller typically manages the power-up and power-down of all memory components (e.g., random access memory (RAM)) of the memory subsystem via direct parallel wiring to each memory component. Depending on the size and complexity of the memory subsystem, this can result in a large number of wires extending from a single controller area to each memory component (e.g., RAM) in the system, which can result in severe routing congestion. The increased wire capacitance from the long distances required to extend the wires from the central controller area to each RAM can result in delays and charge / discharge currents, which require the addition of repeaters that consume more power and routing area. In addition, the central controller and the memory components it controls typically belong to different clock and / or power domains. Generally speaking, each memory component that does not belong to the same clock and / or power domain as the central controller requires the addition of level shifters and / or synchronizers to convert signals from the controller to the clock domain or power domain to which the memory belongs, further increasing power and space requirements and exacerbating routing congestion.

[0019] Routing congestion can make it challenging to move, add, or remove memory components within a memory subsystem that utilizes a central controller that is wired directly to each memory component. Adding or removing RAM requires controller updates and triggers extensive rerouting in congested areas. Joining or splitting RAM or RAM blocks requires controller changes, complex engineering change orders requiring significant routing changes to modify the design, or causing other placement and routing issues.

[0020] Additionally, depending on the size, complexity, and usage of the memory subsystem, not all memory components may be activated at the same time. Factors such as inrush current may require staggered activation of memory components, which is resource intensive for the central controller.

[0021] Aspects of the present disclosure address the above and other deficiencies by using a power control chain (PCC) system as described herein. The PCC system may include a power control chain (PCC) controller associated with a power control chain (PCC) to initiate an on or off procedure to provide power to a memory component of a memory subsystem and / or other memory subsystem components (which are generally referred to herein as "memory components") by generating a signal indicating the execution of an operation, and sequentially activate each next memory component after a set time interval. For example, in some embodiments, a series of flip-flops may be used to provide a clock signal to the memory component. For example, a flip-flop may gate a power control signal from activating each next memory component (e.g., a RAM), and a clock signal pulse from a controller may be used to activate each next flip-flop at each given interval (e.g., at each rising edge of a clock signal pulse). In this arrangement, when each flip-flop is activated, a power control signal may be applied to the next memory component.

[0022] By using the PCC to initiate sequential power, as disclosed herein, only a few wires need to be connected directly to the controller, so the central controller area can be kept uncongested, and since the PCC controller only initiates the power-up procedure, the power-up process is not resource intensive for the PCC controller, especially compared to the methods discussed above. In addition, since each memory component only has to be connected to the next memory component, the distance each wire must extend can be reduced and such shortened wires require fewer repeaters and take up less space and power than a traditional central control system. Furthermore, the memory components can be arranged by clock domain and / or power domain and therefore require fewer level shifters and / or synchronizers than previous methods, again reducing space and power consumption than such previous methods.

[0023] Although the non-limiting examples herein are generally described in terms of application to RAM or other memory and storage systems and subsystems and / or memory devices, the embodiments are not limited thereto and aspects of the disclosure may be applied to any component, partition, IP or other application. Examples of alternative components may include components such as a physical layer (PHY), a phase-locked loop (PLL), a voltage regulator or other components.

[0024] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (such as memory device 140), one or more non-volatile memory devices (such as memory device 130), or a combination thereof.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, and the like.

[0028] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120, for example, uses the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0029] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., memory device 130) when the memory subsystem 110 is coupled to the host system 120 through a PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices, such as memory device 130, include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on body resistance changes. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130, 140 may include one or more arrays of memory cells. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0033] Although nonvolatile memory components such as a three-dimensional cross-point array of nonvolatile memory cells and NAND-type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory or storage device, such as, for example, read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses, physical media addresses, etc.) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140 and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., a DRAM) and address circuitry (e.g., a row decoder and a column decoder) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130 and / or the memory device 140.

[0039] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] The memory subsystem 110 may include a power control chain (PCC) system 101. Figure 1Although not shown in order to avoid obscuring the drawings, the PCC system 101 may include various circuit systems and / or components to facilitate determining whether a power event involving multiple memory components of a memory subsystem and / or components of a memory subsystem has occurred and generating signaling indicating the execution of an operation to provide power to the multiple memory components in response to determining that the power event has occurred. For example, in addition to the multiple memory components, the PCC system 101 may also include a power control chain (PCC) controller that may generate signaling indicating the execution of an operation to provide power to the multiple memory components, such as by generating a power control signal. The PCC system may also include a power control chain (PCC) that may connect the PCC controller to the multiple memory components and may sequentially apply signaling indicating the execution of an operation to provide power to the multiple memory components (e.g., a power control signal) such that the power control signal is applied to a first memory component at a first time and to a second memory component at a second time after the first memory component enters a stable state. In some embodiments, PCC system 101 may include dedicated circuitry in the form of an ASIC, FPGA, state machine and / or other logic circuitry that may allow PCC system 101 to orchestrate and / or execute operations to sequentially activate memory components of memory device 130 and / or memory device 140.

[0041] In some embodiments, the memory subsystem controller 115 comprises at least a portion of the PCC system 101. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the PCC system 101 is part of a host system 120, an application, or an operating system.

[0042] In a non-limiting example, a device (e.g., computing system 100) may include PCC system 101. PCC system 101 may reside on memory subsystem 110. As used herein, the term "resides on" refers to something being physically located on a particular component. For example, PCC system 101 "resides" on memory subsystem 110 to refer to a condition in which the hardware circuitry including PCC system 101 is physically located on memory subsystem 110. The term "resides on" may be used interchangeably with other terms herein, such as "physically arranged on," "deployed on," or "located on."

[0043] In some embodiments, PCC system 101 includes a power control chain (PCC) controller (e.g., PCC controller 214), which may include a power controller (e.g., power controller 252) and a clock controller (e.g., clock controller 254) that may be coupled to multiple memory components. Multiple memory components may be coupled to each other via power control lines (e.g., power control line 321). The power controller may be configured to determine that a power event has occurred. As described above, the multiple memory components may be memory dies or memory packages that form at least a portion of memory device 130. As described herein, a power event may be an event involving a transition from a first power state to a second power state, such as an input indicating that a transition from a first power state to a second power state should be made. As described herein, a power state may indicate a power consumption level and / or computing activity of a system or device. For example, the power state may be represented by an Advanced Configuration and Power Interface (ACPI) power state, such as a global "G" state (e.g., G states G0 to G3, where: G0 is a "working" state; G1 is a "sleep" state; G2 is a "soft-off" state; and G3 is a "mechanical off" state) or a sleep "S" state (e.g., S states S0 to S5, where: S0 is a "working" state; S0ix is ​​a "modern standby" state or a "low-power S0 idle" state; S1 is a "power-on suspend" state; S2 is a "CPU power off" state; S3 is a "standby" state, a "sleep" state, or a "suspend to Ram" state; S4 is a "hibernate" state or a "suspend to disk" state; and S5 is a "soft-off" state). Examples of power states may also include device "D" states (e.g., D states D0 to D3, where: D0 may be a "fully on" state or operating state; D1 and D2 may be intermediate power states; and where D3 may be divided into a D2 hot state in which the device has auxiliary power and a D3 cold state in which no power is provided to the device), processor (CPU) "C" states (e.g., C states C0 to C3, where: C0 may be an operating state; C1 may be a "suspended" state; C2 may be a "stop clock" state; C3 may be a "sleep" state), or execution "P" states (e.g., P states P0 to Pn, where "n" is not greater than 16 and where: P0 may be the highest execution state with maximum power and frequency, and P1 to Pn may be successively lower execution states with scaled voltage and frequency), or other suitable power states that should be understood. As used herein, the number of power states is inversely correlated to power consumption and / or execution, such that a "zero" state indicates the highest power consumption and / or execution, and successively higher numbers indicate successively lower power consumption and / or execution (e.g., P1 consumes less power than P0, P2 consumes less power than P1, P3 consumes less power than P2, and so on).In some examples, the power event may be a power-on event, wherein the transition from the first power state to the second power state includes a transition from a lower power consumption and / or execution state to a higher power consumption and / or execution state (e.g., the power-on event may be a change from an S3 sleep state to an S0 working state). In some examples, the power event may be a power-off event, wherein the transition from the first power state to the second power state includes a transition from a higher power consumption and / or execution state to a lower power consumption and / or execution state (e.g., the power-off event may be a change from an S0 working state to an S4 sleep state).

[0044] The PCC system 101 may be further configured to apply signaling indicating power events involving the memory subsystem 110 and multiple memory components and thereby cause the PCC system 101 to sequentially apply a power control signal generated by a power controller to each of the memory components via a power control line (e.g., power control line 321). The power control signal applied by the PCC system 101 may include multiple bits, which may correspond to various power states, such as: S0 to S5; P0 to P16; or other power states, which may represent, for example, a "functional" power state, a "light sleep" power state, a "deep sleep" power state, and an "off" power state (e.g., a control vector value represented by a binary number may be 00 for the "off" power state, 01 for the "functional" power state, 11 for the "light sleep" power state, 10 for the "deep sleep" power state, etc.). As described above, the PCC system 101 may also include a power control chain (PCC) (e.g., Figure 2 The PCC 268 in FIG. 260 may include several power control chain (PCC) components (e.g. Figure 2 PCC components 220 in the example, such as flip-flops, level shifters, and clock synchronizers (e.g. Figure 3C 364 in the clock synchronizer), which may also receive the applied signaling, as described in more detail herein. Figure 3C The clock synchronizer 364 in the embodiment may be a synchronous clock shaper that "shortens" the clock signal when crossing from a slow clock domain to a fast clock domain or a synchronous clock expander that "stretches" or "extends" the clock signal when crossing from a fast clock domain to a slow clock domain.

[0045] In some embodiments, the PCC system 101 may apply a power control signal (or cause the power control signal to be applied) such that the power control signal is applied to a first memory component of the memory components at a first rising edge of a clock signal pulse generated by one of the clock controller and / or flip-flops and is applied to a second memory component of the plurality of memory components at a second rising edge of a clock signal pulse generated by one of the clock controller and / or flip-flops. In some embodiments, the first rising edge of the clock signal pulse activates the first flip-flop to apply the power control signal to the first memory component, and the second rising edge of the clock signal activates the second flip-flop to apply the power control signal to the second memory component, but embodiments are not limited to architectures including only edge-triggered flip-flops.

[0046] In some embodiments, signaling indicating execution of an operation to provide power may include applying a power control signal associated with a first power domain and a clock signal associated with a first clock domain. That is, in some embodiments, at least one of the power control circuitry and the memory component may be in the same (e.g., first) power domain and / or the same (e.g., first) clock domain. In such embodiments, signaling to provide power to at least one memory component may be provided without the need for level shifters or other circuitry to allow cross-domain signal application.

[0047] In some embodiments, the PCC system 101 may control the use of a power control chain (PCC) (eg, Figure 2 The PCC 268 shown in FIG. 268 is used to apply power control signals to multiple memory components based on the clock signal. Figure 2 In more detail, herein, a PCC may include various PCC components (e.g. Figure 2 , a PCC component 220 in the memory subsystem 110, which is configured to facilitate applying power control signals to various memory components of the memory subsystem 110.

[0048] In some embodiments, the PCC system 101 may determine that each of the plurality of memory components is in a power-on stable state and interrupt the application of clock signal pulses associated with the execution of an operation to provide power to the plurality of memory components in response to the determination to reduce the amount of power consumed by the memory subsystem. However, the embodiments are not limited thereto, and in some embodiments, the PCC system 101 may control the application of clock signal pulses (e.g., applied by a flip-flop or other timing circuit system) so that once a particular memory component is in a power-on stable state, the clock signal pulses are no longer provided to the particular memory component. Similarly, once the next memory component (e.g., a memory component that is powered on after a particular memory component is powered on) is in a power-on stable state, the application of clock signal pulses to the memory component may be stopped, and so on.

[0049] In some embodiments, the PCC system 101 may determine that a power-off event involving multiple memory components of a memory subsystem has occurred. In response to determining that a power-off event has occurred, the power control circuit system 101 may generate signaling indicating execution of an operation to stop providing power to the multiple memory components. The signaling indicating execution of an operation to stop providing power to the multiple memory components may be sequentially applied to each of the memory components (e.g., in the same or opposite order as the power control signal is applied to the memory components to power on the memory components), such that the power control signal is applied to a first memory component of the multiple memory components at a first time and to a second memory component of the multiple memory components at a second time.

[0050] In a non-limiting example, a device (eg, memory subsystem 110) may include a power control chain (PCC) (eg, Figure 2 268) are coupled to each other. Figure 2 ), the PCC may include power control lines (e.g. Figure 3A ) and a clock network (eg, Figure 3A 324 shown in FIG. 324). The PCC system 101 may include a power controller and a clock controller coupled to multiple memory components, and the power controller may be configured to determine that a power event involving multiple memory components has occurred. The power controller may apply signaling indicating a power event involving multiple memory components. That is, the PCC system 101 may control the power of the multiple memory components via a power control line (e.g., Figure 3A ) sequentially applies a power control signal generated by the power controller to each of the memory components, such that the power control signal is applied to a first memory component (e.g., a power control line 321 shown in FIG. 1 ) of the plurality of memory components at a first rising edge of a clock signal generated by one of the clock controller and / or flip-flops. Figure 3A The power control signal is applied to a second memory component (e.g., a memory component 356-1 in the plurality of memory components) at a second rising edge of a clock signal generated by one of the clock controller and / or flip-flops. Figure 3A Memory component 356-2 in.

[0051] In some embodiments, a first subset of the plurality of memory components (eg, Figure 3DThe memory components of the memory subsystem 110 are physically arranged in a memory component regional cluster 366-1 such that a first subset of the plurality of memory components is associated with a first power domain or a first clock domain, or both, and a second subset of the plurality of memory components (e.g., memory component regional cluster 366-2) is physically arranged in the memory subsystem 110 such that a second subset of the plurality of memory components is associated with a second power domain or a second clock domain, or both. However, embodiments are not limited thereto and memory components may be grouped into subsets having different numbers of memory components associated therewith.

[0052] In some embodiments, the signaling indicating the execution of the operation of providing power may include a power control signal and a clock signal pulse. In such embodiments, the power control signal may be associated with the first power domain and the clock signal may be associated with the first clock domain, but the embodiments are not limited thereto.

[0053] As discussed in more detail herein, some embodiments may include multiple PCC components (e.g. Figure 2 For example, a memory component of the plurality of memory components may be associated with the second power domain and a PCC component of the plurality of PCC components may include a level shifter (e.g., Figure 3C 362 in ). It should be understood that the level shifter may be configured to change the power domain of the power control signal and the power domain of the clock signal from the first power domain to the second power domain. However, the embodiments are not limited thereto, and in some embodiments, the PCC components in the plurality of PCC components may include a clock synchronizer, such as a synchronous clock shaper (e.g. Figure 3C It should be appreciated that the clock synchronizer 364 may be configured to change the clock domain of the clock signal from a first clock domain to a second clock domain.

[0054] In some embodiments, at least one memory component 356 of the plurality of memory components 356 includes random access memory or flash memory. For example, at least one of the memory components 356 can be RAM, SRAM, cache, memory array, or the like.

[0055] In a non-limiting example, a PCC system (e.g. Figure 3E The PCC system 301 in the embodiment may include a first power control chain (PCC) (e.g. Figure 3E The first PCC may include a plurality of PCC components (e.g., Figure 2 PCC component 220 in Figure 3E 356 in the memory component 356), and a first power control line (eg, Figure 3EThe PCC system may further include a power controller (e.g., a power control line 321 in the power control chain) coupled to the first power control chain and configured to generate a power control signal. Figure 3E The PCC system may also include a clock controller (e.g., a power controller 352 in FIG. 1 ) coupled to a plurality of PCC components of the first PCC and configured to generate clock signal pulses at set intervals. Figure 3E The PCC system may further include a clock controller 354 coupled to the PCC controller (e.g. Figure 2 The PCC controller 214 in the embodiment of the present invention is a processing device (e.g., PCC system 101, memory subsystem 115, etc.), the PCC controller may include a power controller and a clock controller. Continuing with this non-limiting example, the PCC controller is configured to determine that a power event criterion has been met and cause the power controller to generate a power control signal to the first PCC based on determining that the power event criterion has been met.

[0056] Based on determining that the power event criteria have been met, the PCC controller may cause the clock controller 354 to send power control lines and clock networks to multiple PCC components (eg, Figure 2 The PCC controller may further cause the first PCC component (e.g., the first flip-flop (e.g., Figure 3C Flip-flop 360-1 in), level shifter (e.g. Figure 3C The level shifter 362 in the embodiment of the present invention), the synchronizer (e.g. Figure 3C The controller may further cause a second memory component (e.g., memory component 356-2) to change power state based on receiving a power control signal due to activation of a first PCC component and / or a second trigger (e.g., trigger 360-2) and cause any subsequent PCC components or memory components to activate sequentially. In this example, each activation is separated by a set time interval, but embodiments are not limited to utilizing static time intervals. The controller may also cause any additional memory components to change power state based on receiving a power control signal due to activation of subsequent PCC components. In some embodiments, the power event criterion is the occurrence of a power event involving multiple memory components of the memory subsystem 110.

[0057] As mentioned above, one or more PCC components (e.g. Figure 2The PCC component 220 in the embodiment may be a level shifter configured to change the power domain of the power control signal and the power domain of the clock signal. In addition or in the alternative, in some embodiments, one or more of the plurality of PCC components may be a synchronous clock expander (e.g., Figure 3C Clock synchronizer 364 in).

[0058] In some embodiments, one or more PCC components (e.g. Figure 2 The PCC component 220 in the embodiment of the present invention can be a trigger that can be configured to cause a memory component to receive a power control signal based on the trigger receiving a clock signal pulse. In some embodiments, activating the PCC component causes multiple memory components to receive the power control signal. In some embodiments, one or more memory components can be a regional cluster of memory components (e.g., Figure 3D Storage component area cluster 366 in.

[0059] Some embodiments may include a second PCC (e.g., Figure 3E The second PCC may include a second plurality of PCC components (e.g., Figure 3E The second plurality of memory components (eg, Figure 3E 368-2). The second plurality of PCC components are coupled to a clock controller and power control lines coupled to the second plurality of memory components via a multiplexer 367. In these embodiments, based on determining that the power event criteria have been met, the PCC controller is configured to cause the power controller to also generate power control signals to the second PCC and cause the clock controller to also generate clock signal pulses to the second plurality of PCC components of the second PCC 368-2.

[0060] The controller is further configured to cause a first memory component (eg, Figure 3E 356-5) in the second plurality of memory components changes power state based on receiving the power control signal, causes a first PCC component in the second plurality of PCC components to activate after a set interval based on receiving a first clock signal pulse from the clock controller, and causes a second memory component (e.g. Figure 3EThe controller may further be configured to cause any subsequent PCC components in the second plurality of PCC components to activate sequentially. As mentioned above, each activation may be separated by a set interval. In addition, the controller may cause any additional memory components in the second plurality of memory components to change power state based on receiving the power control signal due to the subsequent PCC component activation in the second plurality of control logic components.

[0061] Figure 2 An example of a power control chain (PCC) system 201 according to some embodiments of the present disclosure is illustrated. The example PCC system 201 (which may be referred to as a "system" or "device" in the alternative) may be similar to Figure 1 1. The example PCC system 201 may include a power control chain (PCC) controller 214, a power control chain (PCC) 268, and a plurality of memory components 256-1, 256-2, 256-3, 256-4, 256-5, 256-6 (which may be collectively or generally referred to as memory components 256) that may be located on a circuit area 258 (e.g., a die, a circuit portion area, etc.). The PCC controller 214 may include a power controller 252 and a clock controller 254. The PCC 268 may include a number of PCC components 220, such as power control lines (e.g., Figure 3A power control line 321 in), clock network (e.g. Figure 3A ) and / or level shifters (e.g. Figure 3C The clock network may also contain several clock network components, such as clock signal lines (e.g. Figure 3A The clock signal line 323 in the trigger (e.g. Figure 3A Flip-flop 360 in) and / or clock synchronizer (e.g. Figure 3C Since the clock network is a component of the PCC, these clock network components may also be referred to as PCC components 220. PCC components 220 (e.g., flip-flop 360, level shifter 362, etc.) may be located in circuit area 258. Figure 2 In an example of , the PCC 268 may connect the PCC controller 214 to the plurality of memory components 256 located in the circuit area 258 and apply power control signals generated by the PCC controller 214 to the plurality of memory components 256 .

[0062] exist Figure 2, PCC system 201 may include a circuit area 258 that includes a number of memory components 256 (e.g., memory components A to F) that have power supplied to them via voltage supply lines coupled to the PCC, the power supply being controlled by a power controller 252 of the PCC controller 214. The memory components 256 may be logic blocks that may include various hardware that form one or more cores (e.g., "intellectual property (IP) cores"). As used herein, a "core" or "IP core" generally refers to one or more data and / or logic blocks that form a constituent component of an application specific integrated circuit system or a field programmable gate array. The memory components may be designed, constructed, and / or otherwise configured to perform specific tasks and / or functions within the systems described herein. In some embodiments, the memory components 256 include memory devices, such as RAM components and / or NAND memory dies. In some embodiments, the PCC controller 214 and / or PCC 268 may take action (or cause action to be taken) to track, limit, adjust, or manipulate power control signals applied via power control lines of the PCC 268 to voltage supply lines coupled to the PCC 268 to provide voltage manipulation to the memory component 256.

[0063] like Figure 2 , system 201 may be coupled to one or more computing components. The computing components are typically external to PCC system 201 (i.e., the computing components are physically distinct from the chip, such as at least the PCC on which PCC system 201 is deployed), but may be communicatively coupled to PCC system 201 so that signaling may be exchanged between PCC system 201 and the computing components. Non-limiting examples of computing components may include controllers, memory devices, graphics processing units, processors / coprocessors, and / or logic blocks and memory subsystems (e.g., those described herein) deployed in which system 201 operates. Figure 1 Other components on the memory subsystem 110) described in .

[0064] The PCC may include power control lines (e.g. Figure 3A 256 ), which can be, for example, a rail that provides a “power control signal” to one or more electrical components, such as memory component 256 . The power control line can be split into one or more power control lines that control the voltage supply applied to the memory component 256 of system 201 .

[0065] Figure 3A is a block diagram of an example computer system in which embodiments of the present disclosure may operate. For example, Figure 3Ais a diagram of a power control chain (PCC) system 301 configured to stagger power on or off of a plurality of memory components 356-1, 356-2, 356-3, 356-4 (collectively or generally referred to as memory components 356) according to some embodiments of the present disclosure. The PCC system 301 may be similar to Figure 1 and Figure 2 In some embodiments, the PCC system 301 may include a plurality of memory components 356 coupled to each other via a power control line 321, such as a plurality of RAM, NAND or other memory components. The PCC system 301 may also include a power controller 352 and a clock controller 354, which may be coupled to each other via the power control line 321 and / or Figure 3A Other communication paths or traces not explicitly described in the figure are coupled to the plurality of memory components 356. In some configurations, for example, Figure 3A In the PCC system 301 shown in FIG. 1 , a centralized time control scheme (with Figure 3B The source synchronous timing scheme shown in the figure is the opposite of the configuration.

[0066] In some embodiments, the PCC system 301 (which may be similar to Figure 1 and Figure 2 The PCC system 101 / 201 of the embodiment may determine that a power event involving the plurality of memory components 356 has occurred and may receive signaling indicating the power event, such as a power control signal. The signaling received by the PCC system 301 may be received by an external device (e.g., Figure 1 The PCC system 301 may generate power control signals to the power control line 321 and / or may generate power control signals to the clock signal line 323 of the clock network 324. Thus, the signaling indicating the power event may be applied to cause the PCC system 301 to sequentially apply power control signals to each of the memory components 356 via the power controller line 321 at intervals that may be controlled via the clock network 324.

[0067] In some embodiments, after the power control signal is applied to the last memory component 356 (e.g., memory component 356-4), a "done" signal may be sent through the clock network 324 to cause the power controller 352 to determine that each of the plurality of memory components 356 is in a power stable state and cause the clock controller 354 to interrupt the generation of clock signal pulses to reduce the amount of power consumed by the PCC system 301. In some embodiments, neither the clock controller 354 nor the power controller 352 is aware of the total number of memory components 356 in the PCC system 301. That is, in some embodiments, the PCC controllers (e.g., Figure 2 The PCC controller 214 in FIG. 1 (and thus the power controller 352 and the clock controller 354, which are part of the PCC controller) does not necessarily have information about the number of memory components 356. Instead, the power control signals and the clock signals are propagated until a "done" signal 324 is received, thereby indicating that all memory components 356 have changed power states and reached a stable state at the new power state.

[0068] In some embodiments, the power control signal is applied to a first memory component 356-1 of the plurality of memory components 356 at a first rising edge of a clock signal pulse generated by the clock controller 354 (or a clock signal generated by one of the flip-flops 360) and applied via the clock signal line 323, and then the power control signal is applied to a second memory component 356-2 at a second rising edge of the clock signal generated by the clock controller 354. In some implementations, the PCC system 301 includes one or more flip-flops 360-1 through 360-4 (collectively referred to herein as "flip-flops 360") to cause the memory component 356 to receive a power control signal via the power control line 321 based on the flip-flops 360 receiving a clock signal pulse via the clock signal line 323. For example, when the first trigger 360-1 receives the first rising edge of the clock signal pulse, the second memory component 356-2 receives the power control signal via the power signal line 321, and when the second trigger 360-2 receives the second rising edge of the clock signal pulse through the clock signal line 323, the memory component 356-3 receives the power control signal through the power control line 321, and so on.

[0069] In some embodiments, the time between clock signal pulses may be assigned a margin to account for any time differences required for each memory component to reach an electrical steady state (e.g., a steady current state), which may depend on many factors, such as temperature, process, voltage, type of memory component, or other factors. The clock controller 354 may generate single clock pulses spaced far enough apart to allow any memory component 356 to reach a steady state, and at each next clock signal pulse, the next memory component 356 in the PCC system 301 may be activated or deactivated.

[0070] Figure 3B is another block diagram of an example computer system in which embodiments of the present disclosure may operate. For example, Figure 3B is a diagram of a power control chain (PCC) system configured to stagger the power on or off of multiple memory components 356 according to some embodiments of the present disclosure. The PCC system 301 may be similar to Figure 1 and Figure 2 PCC System 101 / 201. Figure 3A compared to, Figure 3B An example of a PCC system 301 configured to use source synchronization chain timing is shown, which can reduce routing and area resources. Figure 3B The trigger 360 in the power control chain (PCC) component (eg Figure 2 The PCC component 220 in FIG. 220 may be a circuit system within the memory component 356. Thus, the PCC component (e.g. Figure 2 The PCC components 220 in the memory component 356 may be located far away from each other on the die (e.g., the memory component 356). For example, a flip-flop 360-1 may be located on the memory component 356-1, which may be far away from a second flip-flop 360-2 located on a second memory component 356-2, and thus keeping all flip-flops 360 synchronized requires excessive clock routing resources. In some embodiments, a source synchronous scheme may allow a clock signal line 323 and a power control line 321 (e.g., as a bundle) that transmit clock signal pulses to travel between PCC components (e.g., flip-flops 360) on the memory component 356, which may save clock routing resources over a centralized clock source scheme. For example, the clock signal line 323 and the power control line 321 may travel as a bundle from a first flip-flop 360-1 on the memory component 356-1 to a second flip-flop 360-2 on the second memory component 356-2, and then travel as a bundle from the second flip-flop 360-2 to a third flip-flop 360-3 on a third memory component 356-3. In some embodiments, for example Figure 3B, may have a buffer 361 (e.g., a buffer gate) to align the propagation of the clock signal via the clock signal line 323 with the appropriate power control accompanying the clock signal pulse. (That is, the power control signal that travels from the output Q of the flip-flop 360-1 to the input D of the flip-flop 360-2 via the power control line 321.) In some embodiments, the PCC system 301 is unidirectional, which can prevent race conditions and reduce the risk of timing anomalies. As used herein, "race conditions" generally refer to conditions of electronic devices, software, or other systems, in which the substantial behavior of the system depends on the sequence or timing of other uncontrollable events. When one or more of the possible behaviors are undesirable, it becomes a vulnerability. When a logic gate combines signals traveling along different paths from the same source, an instance of a race condition may occur. The input of the gate may change at slightly different times in response to a change in the source signal. The output may change to an undesirable state in a short time before returning to the designed state. Some systems can tolerate such failures, but if this output is used as a clock signal for another system containing a memory, for example, the system will quickly deviate from its designed behavior. Timing anomalies generally refer to situations where an expected clock signal is not received at the expected time and / or situations where a race condition causes a clock edge to not occur at the expected time.

[0071] Figure 3C is another block diagram of an example computer system in which embodiments of the present disclosure may operate. For example, Figure 3B is a diagram of a power control chain (PCC) system 301 configured to stagger the power on or off of multiple memory components 356 according to some embodiments of the present disclosure. The PCC system 301 may be similar to Figure 1 and Figure 2 PCC System 101 / 201. Figure 3C The PCC system 301 in FIG. 1 shows a PCC system 301 configured to use a source synchronization chain timing control. The source synchronization chain timing control may be similar to Figure 3B . In some embodiments, signaling indicating execution of an operation to provide power to memory component 356 may include generating a power control signal associated with a first power domain and a clock signal associated with a first clock domain and / or generating a power control signal associated with a second power domain and a clock signal associated with a second clock domain. For example, memory component 356 (e.g., memory components 356-2 and 356-3) may be associated with a second power domain, and power control circuitry 313 may include a level shifter 362 configured to perform power domain crossing, for example, by changing the power domain of the power control signal and the power domain of the clock signal 323 from the first power domain to the second power domain before applying the power control signal to memory component 256 in the second power domain.

[0072] Similarly, in some embodiments, a memory component 356 (e.g., memory component 356-4 (not shown)) or a power control chain (PCC) component (e.g., flip-flop 360-3) may be associated with a second clock domain, and the PCC system 301 may include a synchronous clock shaper 364 configured to perform a clock crossing from a first clock domain to a second clock domain. In some embodiments, the second clock domain may be "faster" (e.g., may operate according to a higher clock frequency) than the first clock domain. For example, this may occur during a clock crossing between RAM logic, where it is necessary to change the clock domain of a clock signal from a first clock domain to a second clock domain. In some embodiments, the PCC system 301 may include a synchronous clock expander (e.g., clock synchronizer 364) to perform a clock crossing from a first clock domain to a second clock domain that is slower than the first clock domain. In some embodiments, the memory component 356 is physically arranged and activated so as to minimize the total number of required level shifters 362 and avoid crossing from a faster clock domain to a slower clock domain to facilitate the use of the synchronous clock shaper 364 over a more complex synchronous clock expander. However, if the clock pulses are spaced far enough apart so that the data is stable at the next flip-flop 360 input, then the clock synchronizer 365 may not be needed. In some embodiments, the PCC system 301 may have a buffer 361 (e.g., a buffer gate) to align the propagation of the clock signal via the clock signal line 323 with the appropriate power control accompanying the clock signal pulses. In some embodiments, the clock signal pulses may travel through the level shifter 362 via the clock signal line 323 without changing the timing scheme.

[0073] Figure 3D is another block diagram of an example computer system in which embodiments of the present disclosure may operate. For example, Figure 3D is a diagram of a power control chain (PCC) system 301 configured to stagger the power on or off of multiple memory components 356 according to some embodiments of the present disclosure. The PCC system may be similar to Figure 1 and Figure 2 PCC System 101 / 201. Figure 3D The PCC system 301 in FIG. 1 shows a PCC system 301 configured to use a source synchronization chain timing control. The source synchronization chain timing control may be similar to Figure 3B and Figure 3C Source synchronization chain timing shown in . Figure 3DA PCC system 301 is shown that may include one or more memory component regional clusters 366-1, 366-2, 366-3 (collectively referred to herein as "memory component regional clusters 366"), such as memory component regional clusters 366, where each memory component regional cluster 366 may include one or more memory components 356 that may be controlled as a group. In some embodiments, grouping memory components 356 into memory component regional clusters 366 may accommodate latency requirements that may be experienced by a subset or group of memory components 356. Figure 3D , a single flip-flop 360 (e.g., 360-2) can control several memory components 356 (e.g., memory component 356-6 and memory component 356-7) contained in a single memory component area cluster 366 (e.g., memory component area cluster 366-3). In some embodiments, the memory components 356 can be physically arranged into memory component area clusters 366 on a die based on the memory components 356 in each memory component area cluster 366 being associated with the same power domain, clock domain, or both. In some embodiments, the PCC system 301 can have a buffer 361 (e.g., a buffer gate) to align the propagation of the clock signal via the clock signal line 323 with the appropriate power control that accompanies the clock signal pulses.

[0074] Figure 3E is another block diagram of an example computer system in which embodiments of the present disclosure may operate. For example, Figure 3E is a diagram of a power control chain (PCC) system 301 configured to stagger the power on or off of multiple memory components 356 according to some embodiments of the present disclosure. The PCC system 301 may be similar to Figure 1 and Figure 2 PCC System 101 / 201. Figure 3E The PCC system 301 in FIG. 1 is shown configured to use a method similar to Figure 3A The centralized timing scheme shown in PCC system 301 is more desirable for small areas. Figure 3E A PCC system is shown that may include a first power control chain (PCC) 368-1 and a second PCC 368-2 in parallel, which has less latency than multiple PCCs 368 provided in series or a single PCC 368 having a length for controlling the number of memory components 356 contained in multiple parallel PCCs 368-1, 368-2. In some embodiments, the PCC 368 may include multiple memory components 356 arranged in series and separated by multiple power control chain (PCC) components and multiple memory components 356 and multiple PCC components (e.g., Figure 2368-2). In some embodiments, the power controller 352 generates power control signals to the first PCC 368-1 (directly) and the second PCC 368-2 (via the multiplexer 367) via the power control line 321. In some embodiments, the clock controller 354 generates clock signal pulses to both the first PCC 368-1 and the second PCC 368-2 at set intervals. Embodiments of the present disclosure are not limited to the first PCC 368-1 and the second PCC 368-2. Some embodiments of the PCC system 301 may include three or more PCCs 368.

[0075] In some embodiments, the power control signal may be applied to two or more PCCs 368 in parallel or sequentially via the power control line 321. Whether applied in parallel or sequentially depends on the input and control of the multiplexer 367. In some embodiments, each PCC 368 may be individually configured for power on or off. For example, PCC 368-1 and PCC 368-2 may be powered off or asleep in parallel and powered on sequentially or vice versa, as well as other possibilities. In some embodiments, one or more gates (e.g., AND gate 369) may be used to independently complete the operation of PCCs 368 of various lengths. In some embodiments, a clock signal may be gated from a PCC 368 that completes a power state change earlier than other PCCs 368.

[0076] Figure 4 4 is a flowchart corresponding to a method 470 for memory subsystem power control according to some embodiments of the present disclosure. The method 470 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 470 is performed by Figure 1 The PCC system 101, memory subsystem controller 115 and / or processor 117 are executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0077] At operation 472, the occurrence of a power event involving the memory subsystem may be determined. The power event may correspond to a startup (or resume from a sleep state) of a computing system, whereby various memory devices (e.g., memory components) of a memory subsystem of the computer must be powered on. As discussed above, the occurrence of a power event may be determined by a processing device (e.g., PCC system 101) in response to signaling received from the host system 120 in response to the host system 120 powering on or initializing from a sleep state (e.g., S1 to S5 system sleep states). In some embodiments, the memory subsystem may be similar to Figure 1 As described above, the memory components may be memory dies or memory packages coupled to each other to create a memory cell array, such as RAM, a three-dimensional stackable cross-grid memory cell array used by the memory subsystem to store data, or other suitable memory components.

[0078] At operation 474, in response to determining that a power event has occurred, signaling may be generated to indicate the execution of an operation. For example, signaling may be generated to a plurality of memory components (e.g., Figure 2 and Figures 3A to 3E The memory component 256 / 356) provides a power control signal (e.g., via Figures 3A to 3E In some embodiments, the signaling indicating the execution of the operation of providing power to the plurality of memory components may be sequentially applied to each of the memory components such that the first memory component is powered on, then the second memory component is powered on, and so on. In some embodiments, the signaling indicating the execution of the operation of providing power may include applying a power control signal associated with the first power domain and a clock signal associated with the first clock domain.

[0079] At operation 476, a power control signal may be applied to a first memory component of the plurality of memory components at a first time. For example, during a first period of time, the first memory component may receive a power control signal and / or a clock signal while other memory components do not receive the power control signal and / or the clock signal. Once the first memory component has entered the steady state powered-up mode of operation, at operation 478, the power control signal may be applied to a second memory component of the plurality of memory components at a second time such that the power control signal is applied to the second memory component after the first memory component enters the steady state. This process may be repeated until each of the memory components has been powered up to the steady state mode of operation.

[0080] In some embodiments, method 470 may include using a power control chain (PCC) system (eg, Figure 1 , Figure 2 and Figures 3A to 3EThe PCC system 101 / 201 / 301) controls the application of power control signals to multiple memory components based on the clock signal, as described above in conjunction with Figures 3A to 3E In some embodiments, method 470 may include determining that each of the plurality of memory components is in a powered-on stable state and, in response to the determination, interrupting application of a clock signal associated with execution of an operation to provide power to the plurality of memory components. By interrupting application of the clock signal to the powered-on memory components, the amount of power consumed by the memory subsystem is reduced compared to methods that do not interrupt application of such signals under these conditions.

[0081] In some embodiments, method 470 may include determining that a power-off event involving multiple memory components of a memory subsystem has occurred. In response to determining that a power-off event has occurred, signaling indicative of execution of an operation to stop providing power to the multiple memory components may be generated. The signaling indicative of execution of an operation to stop providing power to the multiple memory components may be sequentially applied to each of the memory components such that a power control signal is applied to a first memory component of the multiple memory components at a first time and to a second memory component of the multiple memory components at a second time. This may continue for each of the memory components until each of the memory components has been powered off.

[0082] Figure 5 is a block diagram of an example computer system 500 in which embodiments of the present disclosure may operate. For example, Figure 5 An example machine illustrating a computer system 500 in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0083] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0084] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0085] The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or several processors that implement a combination of instruction sets. The processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 may further include a network interface device 508 for communicating over a network 520.

[0086] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or the processing device 502 during execution by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0087] In one embodiment, instructions 526 include implementing instructions corresponding to PCC system 101 (e.g. Figure 1The PCC system 101 of the present invention may be a computer program product that stores instructions for the functionality of the computer program product. Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0088] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is generally conceived here to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0089] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0090] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0091] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various such systems will appear as described in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure described herein may be implemented using various programming languages.

[0092] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0093] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list such as at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0094] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded as intended to be illustrative rather than restrictive.

Claims

1. A method for a power control chain, comprising: determining that a power event involving a memory subsystem (110) has occurred; and In response to the determining that the power event has occurred, generating signaling indicating execution of an operation to provide power to a plurality of memory components (256-1, 256-2, 256-3, 256-4, 256-5, 256-6, 356-1, 356-2, 356-3, 356-4, 356-5, 356-6, 356-7, 356-8) of the memory subsystem, wherein the signaling indicating execution of the operation to provide power to the plurality of memory components is sequentially applied to each of the plurality of memory components, wherein the signaling indicating execution includes a power control signal, the power control signal: applied to a first memory component of the plurality of memory components at a first time; and The power control signal is applied to a second memory component of the plurality of memory components at a second time, wherein the power control signal is applied to the second memory component after the first memory component enters a stable state.

2. The method according to claim 1, wherein: The power control signal is associated with a first power domain; the signaling indicating performance of the operation of providing power includes a clock signal associated with a first clock domain; and Controlling the application of the power control signal to the plurality of memory components is based on the clock signal using a power control chain component (220) coupled to the plurality of memory components.

3. The method according to claim 1, further comprising: determining that each of the plurality of memory components is in a powered-on stable state; and In response to the determination, application of a clock signal associated with performance of the operation of providing power to the plurality of memory components is interrupted to reduce an amount of power consumed by the memory subsystem.

4. The method according to any one of claims 1 to 2, further comprising: determining that a power-off event involving the plurality of memory components of the memory subsystem has occurred; and In response to the determining that the power-off event has occurred, generating signaling instructing execution of an operation of stopping supplying power to the plurality of memory components, wherein the signaling instructing execution of the operation of stopping supplying power to the plurality of memory components is sequentially applied to each of the plurality of memory components such that the power control signal: applied to said first one of said plurality of memory components at said first time; and applied to the second memory component of the plurality of memory components at the second time.

5. A power control chain device (101, 201, 301, 500), comprising: A plurality of memory components (256-1, 256-2, 256-3, 256-4, 256-5, 256-6, 356-1, 356-2, 356-3, 356-4, 356-5, 356-6, 356-7, 356-8), which are coupled to each other via a power control line (321); and A power control chain controller (214) comprising a power controller (252, 352) and a clock controller (254, 354) coupled to the plurality of memory components, wherein the power controller is configured to: determining that a power event involving the plurality of memory components has occurred; and applying signaling indicative of the power event involving the plurality of memory components to the power control line to cause the power control line to: sequentially applying a power control signal generated by the power controller to each of the plurality of memory components via the power control line such that the power control signal: applied to a first memory component of the plurality of memory components at a first rising edge of a clock signal pulse generated by the clock controller; and The clock signal is applied to a second memory component of the plurality of memory components at a second rising edge of the clock signal pulse generated by the clock controller.

6. The apparatus according to claim 5, wherein: A first subset (366-1) of the plurality of memory components is physically arranged on a die (258) based on the first subset of the plurality of memory components being associated with a first power domain or a first clock domain or both; and A second subset (366-2) of the plurality of memory components is physically arranged on the die based on the second subset of the plurality of memory components being associated with a second power domain or a second clock domain or both.

7. The apparatus of claim 5, further comprising a plurality of power control chain components (220), wherein: the signaling indicating the occurrence of the power event includes the power control signal and the clock signal pulse, and wherein the power control signal is associated with a first power domain and the clock signal is associated with a first clock domain; A memory component of the plurality of memory components is associated with a second power domain; and A power control chain component of the plurality of power control chain components includes a level shifter (362) configured to: changing the first power domain of the power control signal from the first power domain to the second power domain; and The power domain of the clock signal is changed from the first power domain to the second power domain.

8. The apparatus of claim 5, further comprising a plurality of power control chain components, wherein: the signaling indicating the occurrence of the power event includes the power control signal and the clock signal pulse, and wherein the power control signal is associated with a first power domain and the clock signal is associated with a first clock domain; A memory component of the plurality of memory components is associated with a second clock domain; and A power control chain component of the plurality of power control chain components includes a synchronous clock shaper (364) configured to change the first clock domain of the clock signal from the first clock domain to the second clock domain.

9. The apparatus of claim 5, wherein at least one memory component of the plurality of memory components comprises random access memory or flash memory.

10. A power control chain system, comprising: a plurality of memory components (256-1, 256-2, 256-3, 256-4, 256-5, 256-6, 356-1, 356-2, 356-3, 356-4, 356-5, 356-6, 356-7, 356-8) arranged in series; A first power control chain (368-1), comprising: a plurality of power control chain components (220) that separate the plurality of memory components arranged in series; and a first power control line (321) coupling the plurality of memory components and the plurality of power control chain components to each other; a power controller (252, 352) coupled to the first power control chain and configured to generate a power control signal; a clock controller (254, 354) coupled to the plurality of power control chain components of the first power control chain and configured to generate clock signal pulses at set intervals; and a processing device coupled to the power controller and the clock controller, wherein the processing device is configured to: Determining that power event criteria have been met; causing the power controller to generate the power control signal to the first power control chain based on the determining that the power event criteria has been met; causing the clock controller to generate clock signal pulses to the plurality of power control chain components of the first power control chain based on the determination that the power event criteria have been met; causing a first memory component of the plurality of memory components to be powered on based on receiving the power control signal; causing a first power control chain component of the plurality of power control chain components to activate after a set interval based on receiving a first clock signal pulse from the clock controller; causing a second memory component of the plurality of memory components to be powered on based on receiving the power control signal as a result of the activation of the first power control chain component; causing any subsequent power control chain components of the plurality of power control chain components to activate sequentially, with each activation separated by the set interval; and Any additional memory components of the plurality of memory components are powered on based on receipt of the power control signal as a result of the activation of the subsequent power control chain component.

11. The system of claim 10, wherein: The power event criterion is the occurrence of a power event involving the plurality of memory components of the memory subsystem (110); activating a power control chain component causing the plurality of memory components to receive the power control signal; and One or more memory components of the memory subsystem are a memory component zone cluster (366).

12. The system of any of claims 10-11, wherein one or more of the plurality of power control chain components is a level shifter (362) configured to change a power domain of the power control signal.

13. The system of any one of claims 10-11, wherein one or more of the plurality of power control chain components is a synchronous clock expander (364) configured to change the clock signal pulses from a first clock domain to a second clock domain.

14. The system of any one of claims 10 to 11, wherein one or more of the plurality of power control chain components is a flip-flop (360-1, 360-2, 360-3, 360-4, 360-5, 360-6, 360-7, 360-8) configured to cause a memory component to receive the power control signal based on the flip-flop receiving the clock signal pulse.

15. The system of claim 10, further comprising: A second power control chain (368-2), coupled to the power controller, the second power control chain comprising: a second plurality of power control chain components separating a second plurality of memory components arranged in series, the second plurality of power control chain components being coupled to the clock controller; and a second power control line coupling the second plurality of memory components and the second plurality of power control chain components to each other; Wherein based on the determining that the power event criteria have been met, the power controller is configured to: causing the power controller to also generate the power control signal to the second power control chain; causing the clock controller to also generate clock signal pulses to the second plurality of power control chain components of the second power control chain; causing a first memory component of the second plurality of memory components to be powered on based on receiving the power control signal; causing a first power control chain component of the second plurality of power control chain components to activate after the set interval based on receiving the first clock signal pulse from the clock controller; causing a second memory component of the second plurality of memory components to be powered on based on receiving the power control signal as a result of the activation of the first power control chain component of the second plurality of power control chain components; causing any subsequent power control chain components of the second plurality of power control chain components to activate sequentially, each activation being separated by the set interval; and Any additional memory components in the second plurality of memory components are powered on based on receiving the power control signal as a result of the activation of the subsequent power control chain component in the second plurality of power control chain components.

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