Method for measuring metal silicide resistance in semiconductor devices, polysilicon size monitoring method, and product electrical property monitoring method

Abstract

The present invention discloses a method for measuring the resistance of metal silicide in semiconductor devices, a method for monitoring the size of polysilicon, and a method for monitoring the electrical properties of products. The present invention measures the total resistance of the metal silicide block resistance by applying a high potential or a low potential to both ends of the block resistance corresponding to the metal silicide; because the total resistance of the metal silicide block resistance is interfered by the resistance of the ion implantation layer, the total resistance of the metal silicide block resistance is removed from the interference of the ion implantation layer resistance to obtain the metal silicide resistance. The present invention innovatively raises the issue of ion implantation layer interference and removes it through an accurate calculation method, thereby being able to obtain the actual resistance of the metal silicide that is not interfered by the ion implantation layer. Compared with traditional measurement methods, the measurement results of the present invention are more accurate and reliable, providing a solid data foundation for subsequent polysilicon size monitoring and semiconductor device performance evaluation.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing, and in particular relates to a method for measuring the resistance of metal silicide in a semiconductor device, a method for monitoring the size of polysilicon, and a method for monitoring the electrical properties of a product. Background Art

[0002] In semiconductor manufacturing, metal silicide sheet resistors are a key monitoring tool used to track critical process parameters such as the size of the polysilicon or monocrystalline silicon active area and the thickness of the metal silicide. These parameters are crucial to transistor performance and reliability. To ensure real-time process monitoring and quality control, the manufacturing process of metal silicide sheet resistors must include an ion implantation step into the polysilicon. This step simulates the ion implantation of the source and drain regions during actual transistor manufacturing, ensuring process consistency and accuracy.

[0003] In the actual transistor manufacturing process, ion implantation of the source and drain regions is unavoidable, and this process affects both polysilicon and single-crystal silicon. To simulate this actual process, ion implantation of polysilicon is also required during the manufacture of the metal silicide sheet resistor. This step helps ensure that the metal silicide sheet resistor accurately reflects process variations under different manufacturing conditions.

[0004] Due to the presence of source and drain ion implantation, the actual metal silicide resistance consists of two parallel resistors: one is the resistance of the metal silicide itself, and the other is the resistance of the polysilicon after ion implantation. This structure makes the measurement of metal silicide sheet resistance more complicated because ion implantation changes the electrical properties of polysilicon.

[0005] Currently, when measuring the sheet resistance of metal silicide on the active area and polysilicon gate of MOS devices (Metal-Oxide-Semiconductor Field-Effect Transistor), it is found that the wafer-map of the sheet resistance of metal silicide on different wafers is inconsistent. In particular, the wafer-map inconsistency of the sheet resistance of metal silicide corresponding to different silicon doping types (i.e., N-type and P-type) is more obvious, and even shows opposite trends. The main reasons for this phenomenon are as follows:

[0006] ① The non-uniformity of N-type ion implantation and P-type ion implantation itself;

[0007] ② The non-uniformity of annealing temperature: During the annealing activation process, N-type ions and P-type ions react differently to the thermal factors in the annealing process;

[0008] ③ The locations of different test structures are different: the density of the patterns around different locations is inconsistent, resulting in inconsistent heat absorption during the annealing process.

[0009] like Figure 1 The figure in the middle is the wafer-map of the sheet resistance of metal silicide on N-type polysilicon. Figure 2 The figure in the figure is the wafer-map of the sheet resistance of metal silicide on P-type polysilicon. The redder the color, the larger the sheet resistance. The sheet resistance gradually decreases as it transitions to green. The greener the color, the smaller the sheet resistance. Figure 1 The square resistance in the wafer shows a distribution phenomenon where the square resistance is high in the center of the wafer and low in the surrounding areas. Figure 2 The sheet resistance in the wafer exhibits a distribution phenomenon where the sheet resistance is low in the center and high in the periphery. This makes it impossible to accurately determine the sheet resistance of the metal silicide across the entire wafer, and thus, it is impossible to accurately monitor key process parameters such as the thickness of the metal silicide and the dimensions of the polysilicon gate and / or silicon active area, as well as the uniformity of these parameters across the wafer.

[0010] Therefore, a major challenge facing existing technologies is how to accurately measure and evaluate the sheet resistance of metal silicides, especially considering the impact of ion implantation on resistance measurement. To improve the reliability and performance of semiconductor devices, a new method or technology is needed to accurately evaluate the sheet resistance of metal silicides to ensure accurate monitoring of polysilicon size.

[0011] The present invention aims to solve the problems in the existing metal silicide block resistance measurement method and provide a new method that can accurately evaluate the metal silicide resistance and monitor the size of polysilicon, so as to improve the monitoring accuracy of the semiconductor manufacturing process and the reliability of the device. Summary of the Invention

[0012] The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art and to provide a method for measuring the resistance of metal silicide in semiconductor devices, a method for monitoring the size of polysilicon, and a method for monitoring the electrical properties of products.

[0013] The present invention is implemented as follows. In a first aspect, the present invention provides a method for measuring the resistance of a metal silicide in a semiconductor device, wherein the metal silicide in the semiconductor device is a metal silicide layer formed by depositing the metal silicide on an ion-implanted layer of polysilicon; the method comprises:

[0014] By applying a high potential or a low potential to both ends of the block resistor corresponding to the metal silicide, the total resistance value Rsilicide of the metal silicide block resistor is measured; since the total resistance value Rsilicide of the metal silicide block resistor is interfered by the ion implantation layer resistance R2, the total resistance value Rsilicide of the metal silicide block resistor is removed from the interference of the ion implantation layer resistance R2 to obtain the metal silicide resistance R1.

[0015] Preferably, the method specifically comprises the following steps:

[0016] applying a high potential or a low potential to both ends of the sheet resistor corresponding to the metal silicide, respectively, to measure the total resistance value of the sheet resistor of the metal silicide;

[0017] Construct a mathematical expression for the total resistance of the metal silicide layer thickness, the ion implantation layer thickness, and the metal silicide sheet resistance;

[0018] Calculating the total thickness of the metal silicide layer and the ion implantation layer, and then obtaining the thickness of the metal silicide layer based on a mathematical expression of the total resistance value of the metal silicide layer thickness, the ion implantation layer thickness, and the metal silicide sheet resistance;

[0019] According to the resistance mathematical expression of the metal silicide layer, the resistance of the metal silicide layer is finally obtained.

[0020] Preferably, the process of constructing the mathematical expression of the total resistance of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance is as follows:

[0021] Since the total resistance of the metal silicide block, Rsilicide, is the parallel connection of the metal silicide layer resistance R1 and the ion implantation layer resistance R2, we get:

[0022] Formula (1)

[0023] Substitute the resistance mathematical expressions (2)-(3) of the metal silicide layer and the ion implantation layer into formula (1) to construct the total resistance mathematical expression (4) of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide block resistance:

[0024] Formula (2)

[0025] Formula (3)

[0026] Formula (4)

[0027] Where L is the length of polysilicon, W is the width of polysilicon, ρ1 and ρ2 are the resistivities of the metal silicide layer and the ion implantation layer, respectively, which are negatively correlated with the carrier concentration; is the thickness of the metal silicide layer, and h1 is the total thickness of the metal silicide layer and the ion implantation layer.

[0028] Preferably, the total thickness of the metal silicide layer and the ion implantation layer is calculated as follows:

[0029] By performing the same ion implantation method on the polysilicon of the same semiconductor device, a test ion implantation layer having a thickness equal to the total thickness of the metal silicide layer and the ion implantation layer is formed; and the metal silicide layer and the ion implantation layer are calculated based on a mathematical expression of the resistance of the test ion implantation layer.

[0030] Preferably, the resistance mathematical expression of the test ion implantation layer is:

[0031] Formula (5)

[0032] Where L is the length of polysilicon, W is the width of polysilicon, ρ3 is the resistivity of the test ion implantation layer, and h1 is the total thickness of the metal silicide layer and the ion implantation layer.

[0033] Preferably, ρ3=ρ2, where ρ2 is the resistivity of the ion implantation layer in the semiconductor device where the metal silicide resistor to be measured is located.

[0034] Preferably, the thickness of the metal silicide layer is obtained according to the mathematical expression of the total resistance of the metal silicide layer thickness, the ion implantation layer thickness, and the metal silicide sheet resistance; and the specific process of finally obtaining the metal silicide layer resistance according to the mathematical expression of the resistance of the metal silicide layer is as follows:

[0035] Substituting the total thickness of the metal silicide layer and the ion implantation layer into the mathematical expression of the total resistance value of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance to obtain the thickness of the metal silicide layer;

[0036] Then, the thickness of the metal silicide layer is substituted into the resistance mathematical expression of the metal silicide layer to obtain the resistance of the metal silicide layer;

[0037] The resistance mathematical expression of the metal silicide layer is specifically:

[0038] Formula (6)

[0039] Where L is the length of polysilicon, W is the width of polysilicon, and ρ1 is the resistivity of the metal silicide layer; is the thickness of the metal silicide layer.

[0040] Preferably, the ion implantation layer is an N-type doped ion implantation layer or a P-type doped ion implantation layer.

[0041] In a second aspect, the present invention provides a polysilicon size monitoring method, wherein the polysilicon size is monitored using the actual resistance of the metal silicide calculated by the method.

[0042] In a third aspect, the present invention provides a method for monitoring the electrical properties of a semiconductor device, and the method is used to monitor the electrical properties of the product.

[0043] The beneficial effects of the present invention include at least the following:

[0044] The present invention innovatively proposes the existence of ion implantation layer interference. By avoiding the interference of the ion implantation layer and combining it with the traditional metal silicide block resistance measurement method, the actual resistance value of the metal silicide that is not interfered by the ion implantation layer is obtained, ensuring accurate monitoring of the polysilicon size and improving the accuracy of the electrical performance evaluation of semiconductor device products. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 Wafer image of metal silicide sheet resistor on N-type polysilicon.

[0047] Figure 2 This is a wafer image of a metal silicide block resistor on P-type polysilicon.

[0048] Figure 3 The embodiment of the present invention provides a metal silicide deposition process for a semiconductor device where a metal silicide resistor to be tested is located.

[0049] Figure 4 yes Figure 3 The corresponding circuit schematic diagram.

[0050] Figure 5 The present invention provides an embodiment of a deposition process for constructing a test ion implantation layer using a semiconductor device having the same metal silicide resistor as that to be tested.

[0051] Figure 6 yes Figure 5 The corresponding circuit schematic diagram.

[0052] Figure 7 This is a layout of a metal silicide resistor structure provided by an embodiment of the present invention.

[0053] Figure 8 4 is a cross-section of a metal silicide resistor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] As we know from the background, traditional metal silicide sheet resistance measurement methods cannot accurately determine the actual resistance of the metal silicide. Interference from the ion implantation layer causes the measured metal silicide resistance to exhibit abnormal trends, making it impossible to accurately monitor the polysilicon size. This inaccuracy affects the evaluation of semiconductor device performance, and thus affects device design and optimization.

[0055] To solve the above technical problems, the present invention provides a method for measuring the true resistance of metal silicide in a semiconductor device, comprising:

[0056] By applying a high potential or a low potential to both ends of the sheet resistance corresponding to the metal silicide, the total resistance value Rsilicide of the metal silicide sheet resistance is measured;

[0057] Since the total resistance value Rsilicide of the metal silicide block resistor is affected by the ion implantation layer resistance R2, the total resistance value Rsilicide of the metal silicide block resistor is removed from the interference of the ion implantation layer resistance R2 to obtain the metal silicide resistance R1.

[0058] This invention innovatively addresses the presence of interference from the ion implantation layer. By avoiding this interference and combining it with traditional metal silicide sheet resistance measurement methods, the actual resistance of the metal silicide, unaffected by the ion implantation layer, is obtained. This ensures accurate monitoring of polysilicon size and improves the accuracy of electrical performance evaluation of semiconductor device products. These methods are crucial for ensuring high performance, high reliability, and precise process control of semiconductor devices, and are directly related to the precision of the semiconductor manufacturing process and the quality of the final product.

[0059] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0060] refer to Figure 3 , shows a flow chart of an embodiment of a method for measuring metal silicide resistance in a semiconductor device of the present invention.

[0061] The metal silicide in the semiconductor device used in this embodiment is a metal silicide layer formed by depositing the metal silicide on the ion implantation layer of polysilicon;

[0062] Specifically, the process of preparing the metal silicide by depositing it on the ion implantation layer of polysilicon may be:

[0063] Obtaining polysilicon and pre-processing it;

[0064] Performing ion implantation on the pre-treated polysilicon to form an ion implantation layer;

[0065] Subsequently, metal silicide is deposited on the ion implantation layer to generate a metal silicide layer; wherein the total thickness of the ion implantation layer and the metal silicide layer is set to h1, that is, the thickness of the ion implantation layer is h1-h2, and the thickness of the metal silicide layer is h2.

[0066] Specifically, the ion implantation layer is an N-type doped (NP IMP) ion implantation layer or a P-type doped (PP IMP) ion implantation layer.

[0067] like Figure 8 As shown, the polysilicon provided in this embodiment is formed by growing a bottom oxide dielectric layer SiO2 on the shallow trench isolation (STI) region of the device, and then forming polysilicon on the oxide dielectric layer. Sidewalls are provided on both sides of the polysilicon, and ion implantation is performed on the polysilicon to form an ion implantation layer. Subsequently, a metal silicide layer is formed on the ion implantation layer.

[0068] The metal silicide resistor structure provided by the embodiment of the present invention may be in the form of a serpentine (see Figure 7 ), and is not limited to the above structure.

[0069] The method for measuring the resistance of the metal silicide in the semiconductor device of the present invention is to apply a high potential or a low potential to both ends of the sheet resistance corresponding to the metal silicide, respectively, to measure the total resistance value Rsilicide of the metal silicide sheet resistance; because the total resistance value Rsilicide of the metal silicide sheet resistance is interfered by the ion implantation layer resistance R2, the total resistance value Rsilicide of the metal silicide sheet resistance is obtained by removing the interference of the ion implantation layer resistance R2 and obtaining the metal silicide resistance R1;

[0070] More specifically, the method is:

[0071] Step S1, see Figure 4 Device structure, applying high potential or low potential to both ends of the sheet resistance corresponding to the metal silicide, and measuring the total resistance value Rsilicide of the metal silicide sheet resistance;

[0072] For example, prepare specialized test equipment, ensuring it has the ability to accurately apply potential and measure resistance, such as a high-precision source-measure unit (SMU). Precisely connect the test probes to the two ends of the sheet resistor corresponding to the metal silicide, and set the output parameters of the source meter so that it can stably apply a high potential (such as +V) and a low potential (such as -V) across the sheet resistor. While applying the potential, the source meter measures the current I passing through the sheet resistor. According to Ohm's law, R = V / I, the total resistance value, Rsilicide, of the metal silicide sheet resistor is calculated using the known applied potential V and the measured current I.

[0073] To improve measurement accuracy, take multiple measurements and average them. Ensure the measurement environment is stable to avoid interference from external factors (such as temperature and electromagnetic fields). Repeated measurements can overcome errors such as equipment accuracy limitations, contact resistance, and environmental interference.

[0074] Device Accuracy Limitations: Source meters have inherent measurement accuracy errors, and the displayed potential and measured current values ​​may deviate slightly from the actual values. For example, a source meter's potential measurement accuracy may be ±0.1%, and its current measurement accuracy may be ±0.05%. These accuracy errors are amplified when calculating resistance values, affecting the accuracy of the final measurement results.

[0075] Contact resistance: The contact between the test probe and the sheet resistor is not an ideal zero-resistance connection; a certain amount of contact resistance exists. This resistance varies depending on factors such as probe material, contact pressure, and surface cleanliness. If the contact resistance is high and unstable, the measured total resistance value will be biased upward, resulting in measurement error.

[0076] Environmental interference: Factors such as temperature, humidity, and electromagnetic fields in the measurement environment may affect the measurement results. For example, temperature changes can cause the resistivity of metal silicide and polysilicon to change, thereby changing the actual resistance value of the sheet resistor. Generally, for every 1°C increase in temperature, the resistivity may change by approximately 0.1% to 0.5%. This change is directly reflected in the measured resistance value, causing measurement errors.

[0077] Step S2: Due to the source-drain ion implantation, the actual metal silicide resistor is composed of two resistors connected in parallel. Figure 4 :One is the metal silicide itself, and the other is the polysilicon resistance after ion implantation. That is, the total resistance of the metal silicide block, Rsilicide, is the parallel resistance of the metal silicide layer resistance R1 and the ion implantation layer resistance R2. According to the calculation formula of parallel resistance, we can get:

[0078] Formula (1)

[0079] Substituting the expressions (2)-(3) of the metal silicide layer resistance R1 and the ion implantation layer resistance R2 into formula (1), we can obtain formula (4):

[0080] Formula (2)

[0081] Formula (3)

[0082] Formula (4)

[0083] Where L is the length of polysilicon and W is the width of polysilicon. Under the premise of stable process conditions, both W and L can be considered as fixed constants. is the thickness of the metal silicide layer, h1 is the total thickness of the metal silicide layer and the ion implantation layer; ρ1 and ρ2 are the resistivities of the metal silicide and ion implantation layers, respectively; the carrier concentration of the metal silicide is closely related to the material type. By ensuring that the process parameters such as the metal silicide deposition temperature are stable, ρ1 can remain unchanged; similarly, by keeping the ion implantation energy and dose process parameters stable, ρ2 can also remain unchanged.

[0084] The present invention can also adjust the h2 thickness by adjusting the metal silicide reaction time to obtain a series of Rsilicide values ​​that vary with h2, and use mathematical regression methods to obtain an accurate relationship between Rsilicide and h2, namely, formula (4).

[0085] Step S3, see Figure 5 By performing the same ion implantation method on the polysilicon of the same semiconductor device, a test ion implantation layer with a thickness of h1 is formed. A high potential or a low potential is applied to both ends of the block resistor corresponding to the test ion implantation layer, and the current test ion implantation layer resistance R3 is obtained by measurement; this operation refers to the SAB resistor (silicide barrier layer resistance), that is, after the ion implantation process, no metal silicide is grown. It should be noted that the ion implantation process of this resistor is the same as that of the metal silicide resistor and is carried out at the same time.

[0086] See also Figure 6 , according to the calculation formula (5) of the test ion implantation layer resistance R3, the thickness h1 of the test ion implantation layer is calculated;

[0087] Formula (5)

[0088] Where L is the length of polysilicon, W is the width of polysilicon, ρ3 is the resistivity of the test ion implantation layer, and ρ3=ρ2;

[0089] The current step needs to ensure that the ion implantation process does not change, so as to keep R3 stable, which is sufficient to ensure that the parameter h1 remains unchanged.

[0090] For the polysilicon of the same semiconductor device, the exact same ion implantation method is used to form a test ion implantation layer with a thickness of h1. For the corresponding sheet resistance of this test ion implantation layer, high or low potentials are applied across it using high-precision testing equipment (such as a source meter), and the current test ion implantation layer resistance R3 is measured. The reference here is the SAB resistor (silicide barrier layer resistance), which means that no metal silicide is grown after the ion implantation process. It is important to note that the ion implantation process for this resistor must be exactly the same as that for the metal silicide resistor and must be performed simultaneously to ensure that both are formed under the same process conditions, thereby ensuring accurate measurement and calculation.

[0091] Step S4: Substitute h1 into formula (4) and solve the equation by mathematical calculation to obtain the thickness of the metal silicide layer. ; During the calculation process, ensure that the values ​​​​entered are accurate, and use appropriate mathematical tools (such as numerical calculation software) to improve the accuracy and efficiency of the calculation.

[0092] Step S5: Substitute h2 obtained in step S4 into equation (2) to calculate the metal silicide layer resistance R1. This step is the ultimate goal of the entire measurement method. The obtained R1 value is the accurate metal silicide resistance value after removing the interference of the ion implantation layer, which can be used for subsequent polysilicon size monitoring and semiconductor device performance evaluation.

[0093] The present invention also provides a polysilicon size monitoring method based on the aforementioned metal silicide resistance measurement method. By accurately calculating the actual metal silicide resistance R1, effective monitoring of polysilicon size is achieved. Because the metal silicide layer resistance R1 is closely related to the polysilicon's dimensions (e.g., length, width, thickness, etc.) and electrical properties (e.g., carrier concentration), changes in polysilicon size directly affect the value of the metal silicide layer resistance R1. Therefore, by real-time monitoring of changes in R1, fluctuations in polysilicon size can be promptly detected, allowing appropriate measures (e.g., adjusting process parameters) to ensure polysilicon size stability and guarantee the manufacturing quality and performance consistency of semiconductor devices.

[0094] The present invention also provides a method for monitoring the electrical properties of semiconductor devices, which is implemented using the aforementioned polysilicon size monitoring method. Because the stability of polysilicon size significantly impacts the electrical performance of semiconductor devices, monitoring polysilicon size (indirectly through the actual resistance R1 of the metal silicide) can further assess the electrical characteristics of semiconductor devices. For example, during the semiconductor device manufacturing process, the product's electrical parameters (such as resistance, capacitance, and on-state voltage) are promptly monitored and compared with expected standard values. If abnormal changes in electrical parameters are detected, the problem can be quickly located by combining the polysilicon size monitoring data. This may be caused by polysilicon size changes or problems in other process steps. This allows for timely adjustments to the manufacturing process, improving the product's electrical reliability and ensuring that the resulting semiconductor device meets design requirements and performance standards.

[0095] Therefore, the present invention innovatively addresses the issue of ion-implanted layer interference and eliminates it through precise calculation methods, thereby obtaining the actual resistance value R1 of the metal silicide without interference from the ion-implanted layer. Compared with traditional measurement methods, the present invention's measurement results are more accurate and reliable, providing a solid data foundation for subsequent polysilicon size monitoring and semiconductor device performance evaluation.

[0096] Based on accurate metal silicide resistance measurement, this invention enables precise monitoring of polysilicon size. By monitoring changes in the metal silicide resistance R1 in real time, it can promptly detect even small changes in polysilicon size and take appropriate measures to adjust them. This effectively avoids the performance degradation of semiconductor devices caused by uncontrolled polysilicon size, improving the stability of the semiconductor manufacturing process and the consistency of product quality.

[0097] In terms of electrical performance monitoring for semiconductor devices, this invention enables more accurate assessment of product electrical performance by correlating polysilicon size monitoring with product electrical parameters. Any electrical anomalies can be quickly traced back to polysilicon size variations or other potential process issues, providing strong support for product design optimization and quality improvement, and helping to enhance the overall reliability and market competitiveness of semiconductor devices.

[0098] In summary, the present invention has important technical value and practical application significance in the field of semiconductor device manufacturing. It provides an effective solution to key problems such as metal silicide resistance measurement and polysilicon size monitoring, and helps promote the continuous development and progress of semiconductor manufacturing technology.

[0099] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for measuring the resistance of a metal silicide in a semiconductor device, wherein the metal silicide in the semiconductor device is a metal silicide layer formed by depositing the metal silicide on an ion implanted layer of polysilicon; characterized in that: The method measures the total resistance of the metal silicide block resistor by applying a high potential or a low potential to both ends of the block resistor corresponding to the metal silicide. Since the total resistance of the metal silicide block resistor is interfered by the resistance of the ion implantation layer, the total resistance of the metal silicide block resistor is obtained by removing the interference of the ion implantation layer resistance from the total resistance of the metal silicide block resistor to obtain the metal silicide resistance.

2. The method for measuring the resistance of metal silicide in a semiconductor device according to claim 1, wherein: The method specifically comprises the following steps: applying a high potential or a low potential to both ends of the sheet resistor corresponding to the metal silicide, respectively, to measure the total resistance value of the sheet resistor of the metal silicide; Construct a mathematical expression for the total resistance of the metal silicide layer thickness, the ion implantation layer thickness, and the metal silicide sheet resistance; Calculating the total thickness of the metal silicide layer and the ion implantation layer, and then obtaining the thickness of the metal silicide layer based on a mathematical expression of the total resistance value of the metal silicide layer thickness, the ion implantation layer thickness, and the metal silicide sheet resistance; According to the resistance mathematical expression of the metal silicide layer, the resistance of the metal silicide layer is finally obtained.

3. The method for measuring the resistance of metal silicide in a semiconductor device according to claim 2, wherein: The process of constructing the mathematical expression of the total resistance value of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance is as follows: Since the total resistance of the metal silicide block, Rsilicide, is the parallel connection of the metal silicide layer resistance R1 and the ion implantation layer resistance R2, we get: Formula (1) Substitute the resistance mathematical expressions (2)-(3) of the metal silicide layer and the ion implantation layer into formula (1) to construct the total resistance mathematical expression (4) of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide block resistance: Formula (2) Formula (3) Formula (4) Where L is the length of polysilicon, W is the width of polysilicon, ρ1 and ρ2 are the resistivities of the metal silicide layer and the ion implantation layer, respectively; is the thickness of the metal silicide layer, and h1 is the total thickness of the metal silicide layer and the ion implantation layer.

4. The method for measuring the resistance of metal silicide in a semiconductor device according to claim 2, wherein: The calculation process of the total thickness of the metal silicide layer and the ion implantation layer is: By performing the same ion implantation method on the polysilicon of the same semiconductor device, a test ion implantation layer having a thickness equal to the total thickness of the metal silicide layer and the ion implantation layer is formed; and the metal silicide layer and the ion implantation layer are calculated based on a mathematical expression of the resistance of the test ion implantation layer.

5. The method for measuring the resistance of metal silicide in a semiconductor device according to claim 4, wherein: The specific mathematical expression of the resistance of the test ion implantation layer is: Formula (5) Where L is the length of polysilicon, W is the width of polysilicon, ρ3 is the resistivity of the test ion implantation layer, and h1 is the total thickness of the metal silicide layer and the ion implantation layer.

6. The method for measuring the resistance of metal silicide in a semiconductor device according to claim 5, wherein: ρ3=ρ2, where ρ2 is the resistivity of the ion implantation layer in the semiconductor device where the metal silicide resistor to be measured is located.

7. The method for measuring the resistance of metal silicide in a semiconductor device according to claim 1, wherein: The thickness of the metal silicide layer is obtained according to the mathematical expression of the total resistance value of the metal silicide layer thickness, the ion implantation layer thickness, and the metal silicide sheet resistance; and the specific process of finally obtaining the metal silicide layer resistance according to the mathematical expression of the metal silicide layer resistance is as follows: Substituting the total thickness of the metal silicide layer and the ion implantation layer into the mathematical expression of the total resistance value of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance to obtain the thickness of the metal silicide layer; Then, the thickness of the metal silicide layer is substituted into the resistance mathematical expression of the metal silicide layer to obtain the resistance of the metal silicide layer; The resistance mathematical expression of the metal silicide layer is specifically: Formula (6) Where L is the length of polysilicon, W is the width of polysilicon, and ρ1 is the resistivity of the metal silicide layer; is the thickness of the metal silicide layer.

8. The method for measuring the resistance of metal silicide in a semiconductor device according to claim 1, wherein: The ion implantation layer is an N-type doped ion implantation layer or a P-type doped ion implantation layer.

9. A method for monitoring the size of polysilicon, comprising monitoring the size of polysilicon using the actual resistance of the metal silicide calculated by the method according to any one of claims 1 to 8.

10. A method for monitoring the electrical properties of a semiconductor device, wherein the method according to claim 9 is used to monitor the electrical properties of the semiconductor device.

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