ADC front-end circuit

Abstract

The invention relates to an ADC front-end circuit. The ADC front-end circuit comprises a variable gain amplifier and a negative feedback circuit, the variable gain amplifier carries out amplification processing on the front-end signal to generate an ADC input signal, and the negative feedback circuit is configured to generate the ADC input signal when the voltage of the ADC input signal is larger than a first reference voltage. According to the ADC front-end circuit, the potential of the gain adjusting end of the variable gain amplifier is changed, so that the voltage of the ADC input signal is reduced by reducing the amplification factor of the variable gain amplifier, the ADC front-end circuit can prevent the maximum value of the ADC input signal from exceeding the first reference voltage, namely, the error of the amplitude of the ADC input signal can be reduced; the accuracy of an ADC input signal and the analog-to-digital conversion precision of the ADC are improved, and the analog-to-digital conversion effect of the ADC is improved.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to an ADC front-end circuit. Background Art

[0002] With the continuous advancement and improvement of science and technology, ADC (Analog-to-Digital Converter) has been widely used, such as in a variety of computer equipment, measuring instruments and process control equipment. As the application requirements increase, the resolution and accuracy of ADC are getting higher and higher. For example, some microprocessors (MCUs) have integrated 16-bit or 14-bit ADCs.

[0003] As the resolution and accuracy of ADC become higher and higher, the requirements for the input signal of ADC also increase accordingly, otherwise it will affect the analog-to-digital conversion effect of ADC. Generally speaking, the input signal of ADC needs to have higher accuracy within the working voltage range of ADC, otherwise it is easy to produce large LSB (least significant bit) error. However, because the input signal of ADC is usually not completely consistent with the power supply voltage (VDDA) of ADC and the resistor amplified by the operational amplifier is inaccurate, the input signal of ADC still has large error. Summary of the invention

[0004] In order to improve the accuracy of a signal input to an ADC and reduce errors, the present invention provides an ADC front-end circuit.

[0005] The ADC front-end circuit provided by the present invention comprises:

[0006] A variable gain amplifier is configured to receive a front-end signal, amplify the front-end signal, generate an ADC input signal and output it, wherein the variable gain amplifier has a gain adjustment terminal, and the gain factor of the variable gain amplifier changes with the potential of the gain adjustment terminal; and

[0007] A negative feedback circuit is coupled between the output terminal of the variable gain amplifier and the gain adjustment terminal. The negative feedback circuit is configured to change the potential of the gain adjustment terminal when the voltage of the ADC input signal is greater than a first reference voltage, so as to reduce the voltage of the ADC input signal by reducing the amplification factor of the variable gain amplifier.

[0008] Optionally, when the voltage of the ADC input signal is greater than the first reference voltage, the negative feedback circuit causes the potential of the gain adjustment terminal to rise, causing the amplification factor of the variable gain amplifier to decrease so as to reduce the voltage of the ADC input signal; when the voltage of the ADC input signal is subsequently less than the first reference voltage, the negative feedback circuit causes the potential of the gain adjustment terminal to drop, causing the amplification factor of the variable gain amplifier to rise again.

[0009] Optionally, the initial potential of the gain adjustment terminal is less than the first reference voltage.

[0010] Optionally, when the charging quantity and the discharging quantity of the negative feedback circuit in one cycle of the front-end signal are equal, the potential of the gain adjustment end is stable.

[0011] Optionally, the negative feedback circuit includes:

[0012] a first comparator configured to compare the voltage of the ADC input signal with the first reference voltage and generate a corresponding comparison result;

[0013] A capacitor, wherein the upper plate is coupled to the gain adjustment terminal and the voltage dividing node of the voltage dividing circuit, and the lower plate is grounded; and

[0014] a diode, a positive terminal of which is coupled to the output terminal of the first comparator, and a negative terminal of which is coupled to the upper plate of the capacitor via a resistor;

[0015] When the voltage of the ADC input signal is greater than the first reference voltage, the diode is turned on and the capacitor is charged, causing the potential of the gain adjustment end to rise; when the voltage of the ADC input signal is less than the first reference voltage, the diode is turned off, the capacitor stops charging and discharges, and the potential of the gain adjustment end drops back to the potential of the voltage divider node.

[0016] Optionally, the voltage-dividing circuit includes two voltage-dividing resistors connected in series between a preset voltage and ground, a connection point of the two voltage-dividing resistors is the voltage-dividing node, and an initial voltage of the voltage-dividing node is less than the first reference voltage.

[0017] Optionally, the ADC front-end circuit further includes:

[0018] The front-end operational amplifier circuit is configured to receive an analog signal, amplify the analog signal and raise it above a DC level to generate the front-end signal.

[0019] Optionally, the front-stage operational amplifier circuit amplifies the analog signal and raises it to above zero level.

[0020] Optionally, the pre-stage operational amplifier circuit includes a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a third resistor and a fourth resistor, wherein: the non-inverting input terminal of the second operational amplifier is coupled to the output terminal of the first operational amplifier, the output terminal of the second operational amplifier is coupled to the inverting input terminal, and the output terminal of the second operational amplifier outputs the front-end signal; the first resistor is coupled between the analog signal and the non-inverting input terminal of the first operational amplifier, the second resistor is coupled between the non-inverting input terminal of the first operational amplifier and the power input terminal of the first operational amplifier, the third resistor is coupled between the inverting input terminal of the first operational amplifier and ground, and the fourth resistor is coupled between the inverting input terminal and the output terminal of the first operational amplifier.

[0021] Optionally, the ADC front-end circuit further includes:

[0022] a second comparator configured to compare the voltage of the ADC input signal with a second reference voltage and generate a corresponding comparison result, wherein the second reference voltage is less than the first reference voltage; and

[0023] The MCU device obtains a comparison result generated by the second comparator, wherein when the comparison result indicates that the ADC input signal is constantly greater than the second reference voltage within the period of the front-end signal, the MCU device adjusts the resistance values ​​of the first resistor, the second resistor, the third resistor, and the fourth resistor until the ADC input signal is less than the second reference voltage during a portion of the period of the period of the front-end signal.

[0024] Optionally, the second reference voltage is 0V.

[0025] The ADC front-end circuit provided by the present invention includes a variable gain amplifier and a negative feedback circuit, wherein the variable gain amplifier amplifies the front-end signal to generate an ADC input signal, and the negative feedback circuit is configured to change the potential of the gain adjustment end of the variable gain amplifier when the voltage of the ADC input signal is greater than a first reference voltage, so as to reduce the voltage of the ADC input signal by reducing the amplification factor of the variable gain amplifier. The ADC front-end circuit can avoid the maximum value of the ADC input signal exceeding the first reference voltage, that is, it can reduce the error of the amplitude of the ADC input signal, which helps to improve the accuracy of the ADC input signal and the analog-to-digital conversion precision of the ADC, and enhance the analog-to-digital conversion effect of the ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the connection between the ADC front-end circuit and the ADC according to an embodiment of the present invention.

[0027] Figure 2 4 is a circuit diagram of an ADC front-end circuit according to an embodiment of the present invention.

[0028] Figure 3 It is a simulation diagram of an ADC front-end circuit according to an embodiment of the present invention.

[0029] Figure 4 In one embodiment of the present invention, Figure 3 Waveform diagrams of multiple node signals obtained from the simulation circuit shown.

[0030] Figure 5 In another embodiment of the present invention, Figure 3 Waveform diagrams of multiple node signals obtained from the simulation circuit shown.

[0031] Figure 6 is a circuit diagram of an ADC front-end circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0032] The ADC front-end circuit of the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0033] As described in the background technology, as the requirements for the resolution and accuracy of the ADC increase, it is necessary to reduce the error of the analog signal input to the ADC for analog-to-digital conversion. Therefore, before the analog signal is input to the ADC, the analog signal is processed to reduce the error. This can improve the accuracy of the signal input to the ADC and help improve the analog-to-digital conversion effect of the ADC.

[0034] Figure 1 Schematic diagram of the connection between the ADC front-end circuit and the ADC according to an embodiment of the present invention. Figure 1 An embodiment of the present invention relates to an ADC front-end circuit, which receives an analog signal SIG_IN and generates an ADC input signal VOUT. The ADC receives the ADC input signal VOUT and performs analog-to-digital processing on the ADC input signal VOUT.

[0035] Specifically, the ADC front-end circuit mainly includes a variable gain amplifier 10 and a negative feedback circuit 20; the variable gain amplifier 10 is configured to receive a front-end signal VIN, amplify the front-end signal VIN, generate an ADC input signal VOUT and output it, wherein the variable gain amplifier 10 has a gain adjustment terminal VG, and the amplification factor of the front-end signal VIN by the variable gain amplifier 10 changes with the potential of the gain adjustment terminal VG; the negative feedback circuit 20 is coupled between the output terminal of the variable gain amplifier 10 and the gain adjustment terminal VG, and the negative feedback circuit 20 is configured to change the potential of the gain adjustment terminal VG when the output signal of the variable gain amplifier 10, i.e., the ADC input signal VOUT, has a voltage greater than a first reference voltage VREF1, so as to reduce the voltage of the ADC input signal VOUT by reducing the amplification factor of the variable gain amplifier 10. The negative feedback circuit 20 can prevent the maximum value of the ADC input signal VOUT from exceeding the first reference voltage VREF1, and can reduce the amplitude error of the ADC input signal VOUT, which helps to improve the accuracy of the ADC input signal VOUT and the analog-to-digital conversion precision of the ADC, and enhance the analog-to-digital conversion effect of the ADC.

[0036] Considering that the signal received by the actual ADC front-end circuit may have a negative voltage and the need to adjust its level, such as Figure 1 As shown, optionally, the ADC front-end circuit may further include a pre-stage operational amplifier circuit 30, and the pre-stage operational amplifier circuit 30 is configured to access the analog signal SIG_IN, amplify the analog signal SIG_IN and raise it above the DC level, and the output signal of the pre-stage operational amplifier circuit 30 is connected to the above-mentioned variable gain amplifier 10 as the front-end signal VIN.

[0037] Figure 2 FIG. 1 is a circuit diagram of an ADC front-end circuit according to an embodiment of the present invention. Figure 1 and Figure 2 Specifically, in one embodiment, the ADC front-end circuit includes the variable gain amplifier 10 , the negative feedback circuit 20 , and the front-stage operational amplifier circuit 30 .

[0038] The pre-stage operational amplifier circuit 30 is, for example, a dual-channel operational amplifier circuit, specifically including a first operational amplifier U1A, a second operational amplifier U1B, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, wherein the analog signal SIG_IN to be converted into analog-to-digital is coupled to the in-phase input terminal of the first operational amplifier U1A through the first resistor R1 (that is, the first resistor R1 is coupled between the analog signal SIG_IN and the in-phase input terminal of the first operational amplifier U1A), the first operational amplifier U1A also has a power supply input terminal for connecting to a power supply voltage, and the second resistor R2 is coupled to the in-phase input terminal of the first operational amplifier U1A. Between the non-inverting input terminal of the first operational amplifier U1A and the power input terminal, the third resistor R3 is coupled between the inverting input terminal of the first operational amplifier U1A and the ground (GND), the fourth resistor R4 is coupled between the inverting input terminal and the output terminal of the first operational amplifier U1A (i.e., forming a voltage follower), the non-inverting input terminal of the second operational amplifier U1B is coupled to the output terminal of the first operational amplifier U1A, the output terminal of the second operational amplifier U1B is coupled to the inverting input terminal (i.e., forming a voltage follower), and the output terminal of the second operational amplifier U1B outputs the front-end signal VIN.

[0039] The function of the front-stage operational amplifier circuit 30 is to raise the analog signal SIG_IN to be converted to a DC level (such as zero level) and amplify it. The amplitude of the raise, the DC level to be raised to, and the amplification factor can be set according to specific needs. The values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are related to the raised voltage Uoz and the gain value G to be achieved by the front-stage operational amplifier circuit 30. The first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 satisfy the following relationships (1), (2), and (3):

[0040] R2=R1*G*VDD / Voz (1)

[0041] R3=R1*[(Uoz / VDD+G)*G*VDD / Uoz] / [(1+G*VDD / Uoz)*(Uoz / VDD+G-1)] (2)

[0042] R4=(Uoz / VDD+G-1)*R3 (3)

[0043] Wherein, VDD represents the supply voltage of the first operational amplifier U1A, Uoz represents the lift voltage, and G represents the gain value (ie, the amplification factor).

[0044] According to expressions (1), (2) and (3), when the lift-off voltage Uoz and the gain value G are set, the resistance values ​​of the second resistor R2, the third resistor R3 and the fourth resistor R4 can be calculated after the first resistor R1 is determined. When the lift-off voltage Uoz and / or the gain value G changes, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 can be adjusted accordingly. In one embodiment, the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 can be digital resistors, and their resistance values ​​can be adjusted by the MCU device, which is more convenient to operate than non-digital resistors.

[0045] As an example, the analog signal SIG_IN to be converted to analog-to-digital is a sine wave with a frequency of 1kHz and a peak and a trough of 500mV and -500mV respectively. The power supply voltage VDD of the first operational amplifier U1A is, for example, 5V. In order to amplify the analog signal SIG_IN and raise it above the zero level, in the pre-stage operational amplifier circuit 30, the raising voltage Uoz can be set to 1V, and the gain value G can be set to 2, so that the analog signal SIG_IN can be converted into a sine wave with a peak of 2V and a trough of 0. According to the above expressions (1), (2) and (3), it can be calculated that R2=10*R1, R3=1.667*R1, and R4=2*R1. By selecting the appropriate first resistor R1, second resistor R2, third resistor R3, and fourth resistor R4, the above pre-stage operational amplifier circuit 30 can be formed. It can be understood that the analog signal SIG_IN to be converted into digital form is not limited to an AC signal, but may also be a DC signal or a signal with other waveforms. The specific waveform and parameters of the analog signal SIG_IN may be determined according to the working requirements of the ADC.

[0046] The preamplifier signal VIN output by the preamplifier circuit 30 is illustratively a sine wave signal with a peak value of 2V and a trough value of 0. The preamplifier signal VIN is input to the variable gain amplifier 10 .

[0047] An AGC (automatic gain control) chip may be selected as the variable gain amplifier 10, and the AGC chip is, for example, a commercial AGC chip, such as the TI-VCA821 chip of Texas Instruments. Depending on the specific AGC chip used, the specific circuit for implementing the variable gain of the variable gain amplifier 10 may be different, and the overall achievable gain value may also be different.

[0048] like Figure 2As shown, in one embodiment, the variable gain amplifier 10 uses an AGC chip U2, the positive input terminal VIN+ of the AGC chip U2 is coupled to the output terminal of the second operational amplifier U1B in the above-mentioned pre-stage operational amplifier circuit 30 to access the front-end signal VIN, and the negative input terminal VIN- of the AGC chip U2 is grounded. The AGC chip U2 may also include an external fifth resistor R5 and a sixth resistor R6, and the fifth resistor R5 and the sixth resistor R6 are related to the hardware circuit gain of the AGC chip U2. In addition, the AGC chip U2 has a gain adjustment terminal VG, and the gain adjustment terminal VG can be coupled to an external signal so that the potential can change according to the external signal. In this embodiment, the amplification factor (or gain value) of the AGC chip U2 will change with the different potentials of the gain adjustment terminal VG. According to the different types of AGC chips specifically used in the variable gain amplifier 10, the specific change relationship between the amplification factor and the potential of the gain adjustment terminal may be different.

[0049] In this embodiment, as an example, within the operating voltage range of the AGC chip U2, when the potential of the gain adjustment terminal VG increases, the amplification factor of the AGC chip U2 decreases, and when the potential of the gain adjustment terminal VG decreases, the amplification factor of the AGC chip U2 increases.

[0050] Reference Figure 2 In this embodiment, the negative feedback circuit 20 coupled between the output terminal of the variable gain amplifier 10 and the gain adjustment terminal VG includes a first comparator U3A, a capacitor C1, a diode D1 and a voltage divider circuit; wherein the first comparator U3A is configured to compare the output signal of the variable gain amplifier 10, i.e., the ADC input signal VOUT, with the first reference voltage VREF1, and generate a corresponding comparison result; the upper plate of the capacitor C1 is coupled to the gain adjustment terminal VG and the voltage divider node of the voltage divider circuit, and the lower plate is grounded; the positive terminal of the diode D1 is coupled to the output terminal of the first comparator U3A, and the negative terminal is coupled to the upper plate of the capacitor C1 through the seventh resistor R7.

[0051] The non-inverting input terminal of the first comparator U3A is coupled to the output terminal of the variable gain amplifier U2, thereby receiving the ADC input signal VOUT generated by the variable gain amplifier U2. The non-inverting input terminal of the first comparator U3A is coupled to the first reference voltage VREF1.

[0052] The voltage divider circuit, for example, includes an eighth resistor R8 and a ninth resistor R9 connected in series between a preset voltage and ground. The eighth resistor R8 and the ninth resistor R9 are voltage divider resistors, and their connection point is the voltage divider node. The initial voltage of the voltage divider node is less than the first reference voltage VREF1. Figure 2As shown, as an example, the preset voltage is, for example, 2V, and the initial voltage of the voltage division node is less than 2V. The first reference voltage is, for example, 2.5V, and the working process of the negative feedback circuit 20 is as follows:

[0053] The initial voltage of the capacitor C1 is the voltage of the voltage dividing node. Since the upper plate of the capacitor C1 is coupled to the gain adjustment terminal VG, the initial potential of the gain adjustment terminal VG is the potential of the voltage dividing node (e.g., a value less than 2V), which is less than the first reference voltage (e.g., 2.5V).

[0054] When the voltage of the ADC input signal VOUT is greater than the first reference voltage VREF1, the signal output by the first comparator U3A is at a high level, so that the diode D1 is turned on, and the RC circuit composed of the seventh resistor R7 and the capacitor C1 charges the capacitor C1. The charging of the capacitor C1 causes the potential of the gain adjustment terminal VG to increase. The charging operation causes the gain value of the variable gain amplifier 10 to change, for example, the amplification factor of the variable gain amplifier 10 decreases.

[0055] When the voltage of the ADC input signal VOUT is less than the first reference voltage VREF1, the signal output by the first comparator U3A is at a low level, so that the diode D1 is turned off, and the capacitor C1 stops charging and discharges, so that the upper plate potential of the capacitor C1, that is, the potential of the gain adjustment end VG, drops back to the potential of the voltage divider node. This discharge operation causes the gain value of the variable gain amplifier 10 to change, for example, the amplification factor of the variable gain amplifier 10 increases.

[0056] It can be seen that in the ADC front-end circuit, the variable gain amplifier 10 and the negative feedback circuit 20 can automatically adjust the ADC input signal VOUT, suppressing the voltage of the ADC input signal VOUT to avoid exceeding the first reference voltage VREF1. The automatic adjustment is a dynamic process, not a high-low level flipping process. In order to ensure that the negative feedback circuit 20 can respond to the periodic change of the ADC input signal VOUT in a timely manner, the period of the RC circuit composed of the seventh resistor R7 and the capacitor C1 is less than the change period of the front-end signal VIN (in this embodiment, that is, the period of the RC circuit is less than the change period of the analog signal SIG_IN). In this embodiment, the front-end signal VIN is, for example, a sine wave with a frequency of 1kHz, and the frequency of the RC circuit is, for example, greater than 1kHz.

[0057] According to the working process of the variable gain amplifier 10 and the negative feedback circuit 20, when the steady state is reached, that is, the potential of the gain adjustment terminal VG remains stable, within a change cycle of the front-end signal VIN (or the analog signal SIG_IN), the increase in charge generated by charging the upper plate of the capacitor C1 is equal to the decrease in charge generated by discharging, that is, the charge amount of the gain adjustment terminal VG does not change at the beginning and end of this cycle. That is, when the charging amount and the discharging amount of the negative feedback circuit 20 within a cycle of the front-end signal VIN are equal, the potential of the gain adjustment terminal VG is stable. It should be noted that the stable potential of the gain adjustment terminal VG does not mean that the potential of the gain adjustment terminal VG is constant. In a stable state, the potential of the gain adjustment terminal VG can also change within a certain range.

[0058] Figure 3 and Figure 4 A simulation circuit of the ADC front-end circuit and waveform diagrams of multiple node signals in the simulation circuit are shown respectively. Figure 3 and Figure 4 According to one embodiment, the simulation circuit includes the variable gain amplifier 10, the negative feedback circuit 20 and the front-stage operational amplifier circuit 30. The simulation circuit exemplarily shows Figure 2 Although some circuit components in the simulation circuit are similar to Figure 2 The corresponding circuit components in the embodiment are not labeled with the same reference numerals, but those skilled in the art will recognize the same reference numerals according to the invention. Figure 2 and Figure 3 , understandable Figure 2 and Figure 3 The correspondence between various circuit components.

[0059] like Figure 3 As shown, in the simulation circuit, a signal generator is used to form an analog signal SIG_IN to be converted into analog-to-digital. In the simulation circuit, Figure 2 The first resistor R1 is set to 1 kΩ, the second resistor R2 is set to 10 kΩ, the third resistor R3 is set to 1.67 kΩ, the fourth resistor R4 is set to 2 kΩ, and the first reference voltage VREF1 is, for example, 2.5 V.

[0060] Use Figure 3 The simulation circuit shown is Figure 2 The ADC front-end circuit shown in the figure is simulated to obtain the following Figure 4 The oscilloscope waveforms of multiple node signals are shown. Figures 2 to 4, the analog signal SIG_IN connected to the first operational amplifier U1A is shown as the node signal VF5, which is a sine wave with a frequency of 1kHz and a peak value of ±500mV. After amplification and level raising by the pre-stage operational amplifier circuit 10, the front-end signal VIN connected to the variable gain amplifier 10, that is, the node signal VF2, is a sine wave with both crests and troughs above the zero level (not shown). The output terminal signal of the first comparator U3A is shown as the node signal VF3, which has a periodic high level. The signal of the upper plate of the capacitor C1, that is, the gain adjustment terminal VG, is shown as the node signal VF4, which changes periodically within the range of 0 to 1V, and the change period of the node signal VF4 is consistent with the period of the node signal VF5. The waveform of the ADC input signal VOUT actually generated by the variable gain amplifier 10 obtained by simulation is shown as the node signal VF1, and its maximum value (i.e., positive peak value) is about 2.5V. It can be seen that by using the ADC front-end circuit of the embodiment of the present invention, the maximum value of the ADC input signal VOUT can be limited so that it does not exceed the first reference voltage VREF1.

[0061] The analog signal SIG_IN connected to the first operational amplifier U1A can be adjusted as needed. For example, in another embodiment, Figure 3 The node signal VF5 (ie, the analog signal SIG_IN) in the simulation circuit shown is a sine wave with a frequency of 1kHz and a peak value of ±300mV. The first reference voltage VREF1 is still set to 2.5V. The corresponding waveform diagram is as shown in FIG. Figure 5 As shown. Figure 5 It can be seen that relative to Figure 4 , the amplitude of the analog signal SIG_IN, i.e., the node signal VF5, changes. The output signal of the first comparator U3A, i.e., the node signal VF3, has a periodic high level. The signal of the gain adjustment terminal VG, i.e., the node signal VF4, changes periodically within the range of 0 to 1V. The change period of the node signal VF4 is the same as that of the node signal VF5. The node signals VF5 and VF4 are automatically adjusted. The maximum value (i.e., the positive peak value) of the ADC input signal VOUT, i.e., the node signal VF1, generated by the variable gain amplifier 10 is still approximately 2.5V.

[0062] like Figure 5 As shown, in this embodiment, the minimum value of the ADC input signal VOUT generated by the variable gain amplifier 10, that is, the node signal VF1, is not 0V. This is because this embodiment is different from Figure 4 Although the amplitudes of the analog signal SIG_IN in the embodiments shown are different, they all adopt the following Figure 3The same front-stage operational amplifier circuit 30 (with the same circuit elements and parameters) is shown to amplify and level-raise, resulting in different DC levels raised to different minimum values ​​of the ADC input signal VOUT formed by the variable gain amplifier 10 and the negative feedback circuit 20. If the minimum value of the ADC input signal VOUT is to be close to or equal to 0, the circuit elements and parameters in the front-stage operational amplifier circuit 10 can be adjusted accordingly.

[0063] In order to facilitate adjustment of circuit elements and parameters of the front-stage operational amplifier circuit 30 , in another embodiment, the first resistor R1 , the second resistor R2 , the third resistor R3 and the fourth resistor R4 are digital resistors so that their resistance values ​​can be adjusted by the MCU device. Figure 6 FIG. 1 is a circuit diagram of an ADC front-end circuit according to another embodiment of the present invention. Figure 6 In another embodiment, the ADC front-end circuit also includes Figure 2 The variable gain amplifier 10, the negative feedback circuit 20 and the front-stage operational amplifier circuit 30 in the ADC front-end circuit shown, their structures and functions can refer to the description in the above embodiments.

[0064] Specifically, Figure 6 As shown, in this other embodiment, the ADC front-end circuit also includes a second comparator U4A, and the second comparator U4A is configured to compare the voltage of the ADC input signal VOUT generated by the variable gain amplifier 10 with the second reference voltage VREF2 to generate a corresponding comparison result. The second reference voltage VREF2 is less than the first reference voltage VREF1. The second reference voltage VREF2 is, for example, 0V or a value close to 0V, to verify whether the minimum value of the ADC input signal VOUT is zero potential. In this other embodiment, the ADC front-end circuit may also include an MCU device (not shown), and the comparison result output by the second comparator U4A is sent to the MCU device (such as Figure 6 When the comparison result indicates that the ADC input signal VOUT is always greater than the second reference voltage VREF2 during the period of the front-end signal VIN, indicating that the minimum value of the ADC input signal VOUT is not a zero potential, the MCU device adjusts the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 in the front-stage operational amplifier circuit 30 until the output signal of the second comparator U4A is less than the second reference voltage VREF2 during a portion of the period of the period of the front-end signal VIN.

[0065] In this other embodiment, the voltage of the ADC input signal VOUT is compared with the second reference voltage VREF2 through the second comparator U4A, and the corresponding comparison result is fed back to the MCU device, and then the parameters of the front-stage operational amplifier circuit 30 are adjusted (for example, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are adjusted), thereby changing the minimum value of the ADC input signal VOUT, forming a feedback loop, which can lower the minimum value of the ADC input signal VOUT while maintaining the maximum value of the ADC input signal VOUT unchanged, so as to facilitate the ADC input signal VOUT to reach the optimal value of the input signal required for the ADC to work.

[0066] In the ADC front-end circuit described in the above embodiment, the variable gain amplifier 10 amplifies the front-end signal VIN to generate the ADC input signal VOUT, and the negative feedback circuit 20 is configured to change the potential of the gain adjustment terminal VG of the variable gain amplifier 10 when the voltage of the ADC input signal VOUT is greater than the first reference voltage VREF1, so as to reduce the voltage of the ADC input signal VOUT by reducing the amplification factor of the variable gain amplifier 10. By using the variable gain amplifier 10 and the negative feedback circuit 20, the ADC front-end circuit can avoid the maximum value of the ADC input signal VOUT exceeding the first reference voltage VREF1, that is, the error of the amplitude of the ADC input signal VREF1 can be reduced, which helps to improve the accuracy of the ADC input signal VREF1 and the analog-to-digital conversion accuracy of the ADC, and enhance the analog-to-digital conversion effect of the ADC.

[0067] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. An ADC front-end circuit, characterized in that: include: A variable gain amplifier is configured to receive a front-end signal, amplify the front-end signal, generate an ADC input signal and output it, wherein the variable gain amplifier has a gain adjustment terminal, and the gain factor of the variable gain amplifier changes with the potential of the gain adjustment terminal; as well as A negative feedback circuit is coupled between the output terminal of the variable gain amplifier and the gain adjustment terminal. The negative feedback circuit is configured to change the potential of the gain adjustment terminal when the voltage of the ADC input signal is greater than a first reference voltage, so as to reduce the voltage of the ADC input signal by reducing the amplification factor of the variable gain amplifier.

2. The ADC front-end circuit according to claim 1, characterized in that: When the voltage of the ADC input signal is greater than the first reference voltage, the negative feedback circuit causes the potential of the gain adjustment terminal to rise, causing the amplification factor of the variable gain amplifier to decrease so as to reduce the voltage of the ADC input signal. When the voltage of the ADC input signal is subsequently less than the first reference voltage, the negative feedback circuit causes the potential of the gain adjustment terminal to drop, causing the amplification factor of the variable gain amplifier to rise again.

3. The ADC front-end circuit according to claim 2, characterized in that: The initial potential of the gain adjustment terminal is less than the first reference voltage.

4. The ADC front-end circuit according to claim 1, characterized in that: When the charging quantity and the discharging quantity of the negative feedback circuit in one cycle of the front-end signal are equal, the potential of the gain adjustment end is stable.

5. The ADC front-end circuit according to claim 1, characterized in that: The negative feedback circuit comprises: a first comparator configured to compare the voltage of the ADC input signal with the first reference voltage and generate a corresponding comparison result; A capacitor, wherein the upper plate is coupled to the gain adjustment terminal and the voltage dividing node of the voltage dividing circuit, and the lower plate is grounded; and A diode, a positive terminal of which is coupled to the output terminal of the first comparator, and a negative terminal of which is coupled to the upper plate of the capacitor via a resistor; When the voltage of the ADC input signal is greater than the first reference voltage, the diode is turned on and the capacitor is charged, causing the potential of the gain adjustment end to rise; when the voltage of the ADC input signal is less than the first reference voltage, the diode is turned off, the capacitor stops charging and discharges, and the potential of the gain adjustment end drops back to the potential of the voltage divider node.

6. The ADC front-end circuit according to claim 5, characterized in that: The voltage-dividing circuit includes two voltage-dividing resistors connected in series between a preset voltage and ground, a connection point of the two voltage-dividing resistors is the voltage-dividing node, and an initial voltage of the voltage-dividing node is less than the first reference voltage.

7. The ADC front-end circuit according to claim 1, characterized in that: Also includes: The front-end operational amplifier circuit is configured to receive an analog signal, amplify the analog signal and raise it above a DC level to generate the front-end signal.

8. The ADC front-end circuit according to claim 7, characterized in that: The front-stage operational amplifier circuit amplifies the analog signal and raises it to above zero level.

9. The ADC front-end circuit according to claim 7, characterized in that: The front-stage operational amplifier circuit includes a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a third resistor and a fourth resistor, wherein: The non-inverting input terminal of the second operational amplifier is coupled to the output terminal of the first operational amplifier, the output terminal of the second operational amplifier is coupled to the inverting input terminal, and the output terminal of the second operational amplifier outputs the front-end signal; The first resistor is coupled between the analog signal and the non-inverting input terminal of the first operational amplifier, the second resistor is coupled between the non-inverting input terminal of the first operational amplifier and the power input terminal of the first operational amplifier, the third resistor is coupled between the inverting input terminal of the first operational amplifier and ground, and the fourth resistor is coupled between the inverting input terminal and the output terminal of the first operational amplifier.

10. The ADC front-end circuit according to claim 9, characterized in that: Also includes: a second comparator configured to compare the voltage of the ADC input signal with a second reference voltage and generate a corresponding comparison result, wherein the second reference voltage is less than the first reference voltage; as well as The MCU device obtains a comparison result generated by the second comparator, wherein when the comparison result indicates that the ADC input signal is constantly greater than the second reference voltage within the period of the front-end signal, the MCU device adjusts the resistance values ​​of the first resistor, the second resistor, the third resistor, and the fourth resistor until the ADC input signal is less than the second reference voltage during a portion of the period of the period of the front-end signal.

11. The ADC front-end circuit according to claim 10, characterized in that: The second reference voltage is 0V.

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