A high-speed serial bus synchronization system and method for digital phased array

Abstract

The present invention relates to the field of data synchronization, and specifically to a high-speed serial bus synchronization system and method applied to a digital phased array; comprising a main control FPGA and several sub-array FPGAs, each of the sub-array FPGAs is connected to several antenna units on a digital phased array radar; the main control FPGA and at least one of the sub-array FPGAs are directly connected and communicate through a high-speed serial bus, the sub-array FPGAs are serially extended and / or parallel extended, and the sub-array FPGAs communicate with each other through a high-speed serial bus; wherein the sub-array FPGAs include: a GTX communication module, a GTX uplink synchronization module, a GTX downlink synchronization module, a frame parsing module, a digital-to-analog conversion module, and a data synthesis module. The present invention significantly reduces the burden of data transmission and processing, effectively improves the bottleneck upper limit of data transmission, and successfully overcomes the problem of processing delay, thereby greatly enhancing the scalability of the phased array system.

Description

Technical Field

[0001] The present invention relates to the field of data synchronization in digital phased array technology, and in particular to a high-speed serial bus synchronization system and method applied to a digital phased array. Background Art

[0002] As the electromagnetic environment deteriorates, it has become an inevitable requirement to improve radar performance using sampling phased array radar technology. In order to meet the needs of adaptive multifunctional performance of phased array radar, digital phased array radar came into being, which uses digital signal processing instead of analog methods to achieve high-speed, flexible and accurate phased array performance. In order to further improve the range and scanning speed of the antenna beam, it is necessary to increase the antenna area and establish a high-speed communication link, which poses a challenge to the ability to process large and high-speed data.

[0003] A Chinese patent application with application number CN201910810850.0 discloses a fully digital phased array system command synchronization distribution control device, including a reference clock and synchronization clock generation module, which uses an external reference clock and synchronization clock to generate a working reference clock and synchronization clock for a master command distribution control unit and a distributed command receiving synchronization control unit. The master command distribution control unit distributes control instructions to the distributed command receiving synchronization control unit according to the working reference clock and synchronization clock. The distributed command receiving synchronization control unit counts the precise time of receiving instructions according to the working reference clock and synchronization clock, and sets the control instructions and synchronization execution time according to the maximum instruction receiving time of all distributed command receiving synchronization control units. After the instructions are correctly received, the control instructions are executed synchronously immediately and synchronized to the same digital reference clock.

[0004] This patented product is currently limited to scenarios where one master device controls multiple slave devices in parallel, and cannot support serial expansion to adapt to a wider range of system configuration requirements. In addition, the patented product is designed to send a large amount of data generated by all slave devices to the master device for unified processing. This centralized data flow method is very likely to cause data transmission bottlenecks and processing delays, thereby limiting the overall processing capacity and expansion potential of the system.

[0005] A Chinese patent application with application number CN202310439400.1 discloses a data synchronization method based on a phased array system, which includes the following steps: system determination, system clock synchronization, system acquisition synchronization, DDC module synchronization, and system data transmission synchronization of a digital phased array system.

[0006] The design idea of ​​this patented product is to control the sync all the way through the flag, and realize clock synchronization, sampling, digital down conversion (DDC) and data transmission in sequence. However, this design has two main problems: first, it fails to consider the synchronization problem between serial distributed devices and cannot cope with a wider range of needs; second, because all flag and synchronization operations are completely dependent on the sync signal, the robustness of the entire system is poor. Once the sync signal has problems, the entire synchronization process may be affected or even interrupted. Summary of the invention

[0007] The present invention provides a high-speed serial bus synchronization system and method for digital phased array, which aims to independently store uplink and downlink data and local data transmitted by the high-speed serial bus, and then control the reading and writing of the stored data through the main control instruction and the synchronization signal, so as to finally realize the data synchronization and synthesis of the digital phased array radar; and solve the problem that the prior art is prone to data transmission bottleneck and processing delay during serial expansion;

[0008] The present invention provides a high-speed serial bus synchronization system and method for digital phased array, and its purpose is to use AC variable frequency synchronization signal to replace the traditional DC pulse synchronization signal to solve the problem of poor robustness in the prior art.

[0009] To achieve the above object, the technical solution of the present invention is:

[0010] The present invention provides a high-speed serial bus synchronization system applied to a digital phased array, comprising a main control FPGA and a plurality of sub-array FPGAs, each of the sub-array FPGAs being connected to a plurality of antenna units on a digital phased array radar;

[0011] The main control FPGA and at least one of the sub-array FPGAs are directly connected and communicate via a high-speed serial bus. The sub-array FPGAs are serially expanded and / or parallel expanded. The sub-array FPGAs communicate with each other via a high-speed serial bus.

[0012] Wherein, the sub-array FPGA includes:

[0013] GTX communication module, used to communicate with the master control FPGA and other sub-array FPGAs;

[0014] A GTX uplink synchronization module, connected to the GTX communication module and the following digital-to-analog conversion module, respectively, for storing the lower-level data uploaded by the lower-level sub-array FPGA through the GTX communication module and the local data processed by the following digital-to-analog conversion module;

[0015] A GTX downlink synchronization module, connected to the GTX communication module, and used to store downlink data received through the GTX communication module;

[0016] A frame parsing module, connected to the GTX downlink synchronization module and the following digital-to-analog conversion module, for reading the downlink data stored in the GTX downlink synchronization module and sending the parsed instructions, transmission data of the antenna unit and beam pointing to the following digital-to-analog conversion module;

[0017] A digital-to-analog conversion module is connected to several local antenna units and is used to control the antenna units to complete transmission and collection according to instructions, transmission data of the antenna units and beam pointing, and then process the collected local data and send the processed local data to the GTX uplink synchronization module;

[0018] The data synthesis module is connected to the GTX communication module and the GTX uplink synchronization module, and is used to read the subordinate data and local data from the GTX uplink synchronization module, and process and synthesize the subordinate data and local data and upload them to the upper sub-array FPGA or the master control FPGA through the GTX communication module.

[0019] Furthermore, the GTX uplink synchronization module includes a local data storage block for storing local data and a subordinate upload data storage block for storing subordinate data.

[0020] Furthermore, the GTX downlink synchronization module includes a downlink data storage block.

[0021] Furthermore, the local data storage block, the lower-level upload data storage block and the downlink data storage block are all FIFO storage blocks.

[0022] A high-speed serial bus synchronization method applied to a digital phased array comprises the following steps:

[0023] S1. After the device is powered on, the master FPGA automatically starts high-speed serial bus synchronization and sends downlink data to all sub-array FPGAs. Then the master FPGA sends GTX synchronization instructions to all sub-array FPGAs.

[0024] S2. After receiving the GTX synchronization instruction, the subarray FPGA immediately enters the GTX synchronization mode;

[0025] S3. The subarray FPGA continues to write the newly received downlink data into the downlink data storage block;

[0026] S4. After waiting for a certain period of time to ensure that the farthest sub-array FPGA also receives the GTX synchronization command, the master FPGA sends a variable frequency sync synchronization signal;

[0027] S5. After the sub-array FPGA detects the variable frequency sync synchronization signal, it starts reading data from the downlink data storage block of the downlink synchronization module to complete the downlink data synchronization;

[0028] S6. After the sub-array FPGA detects the variable frequency sync synchronization signal, it starts writing local data and variable frequency sync synchronization signal to the local data storage block;

[0029] S7. After the sub-array FPGA detects the variable frequency sync synchronization signal in the data uploaded by the lower sub-array FPGA, it starts writing the lower data uploaded by the lower sub-array FPGA into the lower uploaded data storage block;

[0030] S8. When the local variable frequency sync synchronization signal and the variable frequency sync synchronization signal uploaded by the lower level are received by the sub-array FPGA, the sub-array FPGA starts to read data from the local data storage block and the lower level upload data storage block at the same time to complete the uplink data synchronization; and the synchronized local data and lower level data are synthesized and then uploaded to the upper level;

[0031] S8. After the uplink data synchronization and the downlink data synchronization are completed, the master FPGA sends a GTX synchronization test command;

[0032] S10. The subarray FPGA receives the GTX synchronization test instruction and enters the GTX synchronization test mode to test whether both the uplink and the downlink are synchronized.

[0033] Furthermore, the subarray FPGA enters the GTX synchronization mode specifically including the following steps:

[0034] S21. The downstream data storage block of the GTX downstream synchronization module in the subarray FPGA is reset, the residual data in the FIFO storage block is cleared, and the read enable is kept in an invalid state;

[0035] S22. The local data storage block and the lower-level upload data storage block of the GTX upstream synchronization module in the subarray FPGA are reset, and the residual data are cleared and the read enable and write enable are kept in an invalid state.

[0036] The beneficial effects achieved by the present invention are:

[0037] The present invention uses a high-speed serial bus as a communication medium and innovatively implements a distributed data processing and synthesis strategy between each sub-array. This measure significantly reduces the burden of data transmission and processing, effectively improves the bottleneck upper limit of data transmission, and successfully overcomes the problem of processing delay, thereby greatly enhancing the scalability of the phased array system. In addition, the present invention not only supports serial expansion, but also supports parallel expansion, supports synchronization between each level of equipment and other cascaded devices, has stronger compatibility, and realizes true distributed processing.

[0038] At the technical solution level, the present invention ensures efficient and accurate synchronization of high-speed data streams by finely optimizing the transmission mechanism of synchronization signals and the storage management of high-speed serial bus communication data. The key to this progress is the use of an innovative detection method - monitoring the frequency change moment of the sync signal, rather than the traditional pulse moment detection. This design not only enhances the driving performance of the sync signal in long-distance transmission, but also greatly reduces the risk of false detection caused by signal burr interference, laying an indestructible technical foundation for the further expansion of digital phased arrays.

[0039] In summary, the present invention has not only achieved remarkable results in improving data transmission efficiency and processing speed, but also achieved a qualitative leap in the reliability of synchronous signal transmission and the compatibility of system architecture, opening up a new path for the future development of digital phased array technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0041] Figure 1 Flowchart for scalable distributed high-speed serial bus synchronization for digital phased arrays.

[0042] Figure 2 This is the communication link diagram of the digital processing module of the digital phased array.

[0043] Figure 3 This is a block diagram for implementing downstream synchronization of a high-speed serial bus.

[0044] Figure 4 Block diagram for high-speed serial bus upstream synchronization.

[0045] Figure 5 Schematic diagram of DC and AC modes of synchronous sync signal. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings of the specification of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0048] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if the meaning of "and / or" appearing in the full text is to include three parallel schemes, taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0049] The present invention provides a high-speed serial bus synchronization system and method for digital phased array, which is an innovation of the existing digital phased array radar synchronization system; the present invention is to solve the challenge of processing huge and high-speed data capabilities faced by digital phased array radar after increasing the antenna area and establishing a high-speed communication link; the present invention communicates through a high-speed serial bus and performs data synthesis in a distributed manner in each sub-array, thereby reducing the pressure of data transmission and processing and improving the scalability of the phased array. In addition, the present invention realizes effective synchronization of high-speed data by optimizing the synchronization signal transmission method and the storage control of the high-speed serial bus communication data.

[0050] Specifically, Figure 1~2 As shown, the high-speed serial bus synchronization system is arranged on a digital phased array radar, and specifically comprises a main control FPGA and a plurality of sub-array FPGAs, and each of the sub-array FPGAs is connected to a plurality of antenna units on the digital phased array radar;

[0051] The main control FPGA and at least one of the sub-array FPGAs are directly connected and communicate through a high-speed serial bus. The sub-array FPGAs are serially expanded and / or parallel expanded, and the sub-array FPGAs communicate with each other through a high-speed serial bus. Specifically, the present invention supports the sub-array FPGAs to implement a serial expansion architecture, a parallel expansion architecture, and a serial-parallel combination architecture.

[0052] The master control FPGA is the control center of the digital phased array radar, which is used to send GTX synchronization instructions, send variable frequency sync synchronization signals, send downlink data, data processing, etc.

[0053] Wherein, the sub-array FPGA includes:

[0054] GTX communication module, used to communicate with the master control FPGA and other sub-array FPGAs;

[0055] A GTX uplink synchronization module, connected to the GTX communication module and the following digital-to-analog conversion module, respectively, for storing the lower-level data uploaded by the lower-level sub-array FPGA through the GTX communication module and the local data processed by the following digital-to-analog conversion module;

[0056] A GTX downlink synchronization module, connected to the GTX communication module, and used to store downlink data received through the GTX communication module;

[0057] A frame parsing module, connected to the GTX downlink synchronization module and the following digital-to-analog conversion module, for reading the downlink data stored in the GTX downlink synchronization module and sending the parsed instructions, transmission data of the antenna unit, and beam pointing, etc. to the following digital-to-analog conversion module;

[0058] A digital-to-analog conversion module is connected to a plurality of local antenna units, and is used to control the antenna units to complete transmission and collection according to instructions, transmission data of the antenna units, and beam pointing, and then process the collected local data and send the processed local data to the GTX uplink synchronization module;

[0059] The data synthesis module is connected to the GTX communication module and the GTX uplink synchronization module, and is used to read the subordinate data and local data from the GTX uplink synchronization module, and process and synthesize the subordinate data and local data and upload them to the upper sub-array FPGA or the master control FPGA through the GTX communication module.

[0060] Among them, since the sub-array FPGAs are arranged in series and / or parallel, except for the sub-array FPGA directly connected to the main control FPGA and the sub-array FPGA at the very end, the remaining sub-array FPGAs are directly connected to multiple sub-array FPGAs; among these directly connected sub-array FPGAs, the one close to the main control FPGA can be called the upper sub-array FPGA, and the others are called lower sub-array FPGAs; in addition, it is worth noting that the upper level of the sub-array FPGA directly connected to the main control FPGA is the main control FPGA; and the sub-array FPGA at the very end has no lower sub-array FPGA; the same is true below and will not be repeated.

[0061] The instructions issued by the master FPGA will be passed down through the sub-array FPGAs connected in series one by one, and the data of the sub-array FPGAs will be uploaded back to the master FPGA through the sub-array FPGAs connected in series one by one. The synchronization sync signal is sent out by the master FPGA. The paths from the master FPGA to each sub-array FPGA are of equal length. It can be considered that the master FPGA sends out a sync signal once, and the time when each sub-array FPGA receives the sync signal is the same.

[0062] As the area of ​​digital phased array radars becomes larger and larger, the path of the sync signal routing is also correspondingly lengthened, and the original DC pulse is difficult to drive long-distance transmission. Therefore, the present invention designs the sync signal transmission as an AC mode (i.e., periodic high and low level conversion at a certain frequency). Figure 5 As shown, in order to make the sync signal in the AC mode also have an instantaneous effect like a pulse, the sync is controlled to be a clock signal with a changing frequency, and the pulse moment is detected instead of the sync frequency changing moment.

[0063] Specifically, the original pulse detection is to detect a level or a rising edge; however, AC sync cannot generate stable pulses, so the frequency of sync is changed at the time of the original pulse, such as 60M to 30M. This frequency change is agreed in advance, and the frequency difference is obvious. By detecting the frequency of the rising or falling edge of the AC sync, the time when the sync frequency changes can be detected, and uplink synchronization can be performed at the same time.

[0064] The AC design of the Sync signal improves the driving capability of long-distance transmission, reduces the probability of false detection caused by glitches, and provides a solid foundation for the expansion of digital phased array radars. The high-speed serial bus synchronization technology in the present invention can realize distributed data processing of each sub-array, and supports a series-parallel combination architecture, which improves the scalability of the digital phased array and has been implemented and verified in a flat-panel digital phased array.

[0065] Furthermore, the GTX uplink synchronization module includes a local data storage block for storing local data and a subordinate upload data storage block for storing subordinate data.

[0066] Furthermore, the GTX downlink synchronization module includes a downlink data storage block.

[0067] Furthermore, the local data storage block, the lower-level upload data storage block and the downlink data storage block are all FIFO storage blocks. The FIFO storage block, namely the First In First Out storage block, is a storage structure that stores and reads data in the order in which the data enters the memory.

[0068] The GTX synchronization instruction, on the one hand, enables the sub-array FPGA to enter the GTX synchronization mode, and on the other hand, controls the antenna unit connected to the sub-array FPGA to achieve the purpose of transmitting signals to detect a specific airspace.

[0069] like Figures 3-5 As shown, a high-speed serial bus synchronization method applied to a digital phased array comprises the following steps:

[0070] S1. Each time the device is powered on, the master FPGA automatically turns on the high-speed serial bus synchronization, the mode of the GTX communication module is set to stream mode, and the master FPGA sends downlink data to all sub-array FPGAs; then the master FPGA sends GTX synchronization instructions to all sub-array FPGAs. Among them, the high-speed serial bus synchronization is divided into two parts: GTX downlink synchronization and GTX uplink synchronization. The uplink data is mainly the antenna's received data. The downlink data includes invalid data used to fill the blank period, antenna unit transmission data, beam pointing, transmission and reception power, calibration angle, etc. It is worth noting that if the GTX communication module is set to stream mode, then whether there is valid working data or not, the uplink and downlink synchronization are continuous, and data is sent, but when there is no valid working data, invalid data such as 0 or 1 is sent; that is, the master FPGA sends invalid data at the beginning, and only sends working data after a period of time.

[0071] S2. After receiving the GTX synchronization command, the sub-array FPGA immediately enters the GTX synchronization mode; in this mode, functions such as data synthesis in the normal working mode are not performed. The GTX uplink synchronization module and the GTX downlink synchronization module in the sub-array FPGA simultaneously perform GTX synchronization preparation.

[0072] S21. The downlink data storage block of the GTX downlink synchronization module in the subarray FPGA is reset, the residual data in the FIFO storage block is cleared, and the read enable is kept in an invalid state;.

[0073] Specifically, the GTX downlink synchronization module on the sub-array FPGA is mainly composed of a FIFO storage block. The downlink data received by the sub-array FPGA will be automatically written into the FIFO. By controlling the reset and read enable of the FIFO storage block, the synchronization of the downlink data of all sub-array FPGAs is achieved. The specific method of GTX downlink synchronization is as follows: Figure 3As shown in the figure, after parsing the GTX synchronization instruction sent by the master FPGA, the downlink data storage block is reset, and the residual data in the FIFO will be cleared. After the reset is completed, the downlink data will continue to be written into the FIFO. After waiting for the sync signal sent by the master FPGA, the FIFO read enable signal is set to high. At this time, the data read from the FIFO is the synchronized GTX downlink data. For different sub-array FPGAs, the time of receiving the synchronization instruction is different. The sub-array directly connected to the master FPGA receives the synchronization instruction first. The farther the sub-array FPGA is from the master FPGA, the later it receives the instruction. However, all sub-array FPGAs are cleared after receiving the synchronization instruction, and no data is read out after clearing. Until the master FPGA sends the sync signal, all sub-array FPGAs receive the sync signal at the same time and start to read data from the FIFO. At this time, the amount of data stored in the FIFO of different sub-arrays is different. The one close to the master FPGA receives the instruction first and starts to reset and write first. Therefore, the amount of data written into the FIFO is large, and the amount of data far away is small. However, the data read out are all data immediately following the synchronization instruction, so the GTX downlink synchronization of all sub-array FPGAs is achieved.

[0074] S22. The local data storage block and the lower-level upload data storage block of the GTX upstream synchronization module in the subarray FPGA are reset, and the residual data are cleared and the read enable and write enable are kept in an invalid state.

[0075] Specifically, the GTX uplink synchronization module of the subarray FPGA is mainly composed of two FIFO storage blocks, which are used to store local data and data uploaded by the lower level. By controlling the reset, write enable and read enable of the two FIFO storage blocks, the synchronization of all subarray GTX uplink data is achieved. The specific method of GTX uplink synchronization is as follows: Figure 4As shown in the figure, after parsing the GTX synchronization instruction sent by the master FPGA, the two FIFO storage blocks of the upstream synchronization are reset, and the residual data in the FIFO will be cleared. After the reset is completed, the read and write enable of the FIFO are turned off, and the FIFO remains empty; until the sync signal sent by the master FPGA is received, the local collected and processed data and the sync received locally are written into the local data storage block; when the sync signal in the data uploaded by the lower level is received, the data uploaded by the lower level is written into the lower level uploaded data storage block. When the local and lower level sync signals are received, data is read from the two FIFOs at the same time, and the data read from the FIFO at this time is the synchronized GTX upstream data. For the local data storage block and the lower-level upload data storage block, the synchronization instructions are all local parsing of the GTX downlink signal, so the two FIFOs are reset at the same time; the sync time received by different sub-array FPGAs is the same, but the lower-level sub-array FPGA uploads the received sync to the local sub-array, which consumes transmission time. Therefore, the local sub-array first detects the local sync signal and then detects the sync signal of the lower-level accompanying path. In this way, the time to start writing data to the two FIFOs is different, but the first data written is the data at the sync time, and then the data in the two FIFOs is read simultaneously in the subsequent time to achieve GTX uplink synchronization of local data and lower-level data. The synchronized local data and lower-level data are synthesized and then uploaded to the upper level.

[0076] S3. The subarray FPGA continues to write the newly received downlink data into the downlink data storage block;

[0077] S4. Wait for a certain period of time (the specific waiting time can be estimated and determined by experiments, for example, if the first level is 100ns, then the sixth level is 600ns, which is related to the number of series connected levels) to ensure that the farthest sub-array FPGA also receives the GTX synchronization command, and then the main control FPGA sends a variable frequency sync synchronization signal.

[0078] S5. After the sub-array FPGA detects the variable frequency sync synchronization signal, it starts reading data from the downlink data storage block of the downlink synchronization module to complete the downlink data synchronization;

[0079] S6. After the sub-array FPGA detects the variable frequency sync synchronization signal, it starts to write the local data and the variable frequency sync synchronization signal collected by the antenna unit connected to this sub-array FPGA into the local data storage block.

[0080] S7. After the sub-array FPGA detects the variable frequency sync synchronization signal in the data uploaded by the lower sub-array FPGA, it starts to write the lower-level data uploaded by the lower sub-array FPGA into the lower-level uploaded data storage block.

[0081] S8. When the local variable frequency sync signal and the variable frequency sync signal uploaded by the lower level are received by the sub-array FPGA, the sub-array FPGA starts to read data from the local data storage block and the lower level uploaded data storage block at the same time to complete the uplink data synchronization; and synthesize the synchronized local data and the lower level data, and then upload it to the upper level. Specifically, the data uplink is level by level and uninterrupted, through relay-style data upload and synthesis, and finally gathered to the main control FPGA, realizing distributed data processing.

[0082] S9. After the uplink data synchronization and the downlink data synchronization are completed, the master FPGA sends a GTX synchronization test instruction.

[0083] S10. The subarray FPGA receives the GTX synchronization test instruction and enters the GTX synchronization test mode to test whether both the uplink and the downlink are synchronized.

[0084] Specifically, after completing the GTX uplink and downlink synchronization, the master FPGA sends a GTX synchronization test instruction, and the sub-array FPGA enters the GTX synchronization test mode. In this mode, each sub-array FPGA occupies a GTX bit position. When the sub-array FPGA detects a sync signal or receives a GTX instruction sent by the master FPGA, it uploads a pulse on the bit position. The master FPGA determines whether the GTX synchronization is completed based on the timing relationship of the pulses received at each bit position. When the master FPGA sends a sync signal and the received pulses are aligned, it indicates that the uplink is synchronized; when the master FPGA sends an instruction and the received pulses are aligned, it indicates that the downlink is synchronized.

[0085] The above descriptions are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A high-speed serial bus synchronization system for a digital phased array, characterized in that: It includes a main control FPGA and several sub-array FPGAs, each of which is connected to several antenna units on the digital phased array radar; The main control FPGA and at least one of the sub-array FPGAs are directly connected and communicate via a high-speed serial bus. The sub-array FPGAs are serially expanded and / or parallel expanded. The sub-array FPGAs communicate with each other via a high-speed serial bus. Wherein, the sub-array FPGA includes: GTX communication module, used to communicate with the master control FPGA and other sub-array FPGAs; A GTX uplink synchronization module, connected to the GTX communication module and the following digital-to-analog conversion module, respectively, for storing the lower-level data uploaded by the lower-level sub-array FPGA through the GTX communication module and the local data processed by the following digital-to-analog conversion module; A GTX downlink synchronization module, connected to the GTX communication module, and used to store downlink data received through the GTX communication module; A frame parsing module, connected to the GTX downlink synchronization module and the following digital-to-analog conversion module, for reading the downlink data stored in the GTX downlink synchronization module and sending the parsed instructions, transmission data of the antenna unit and beam pointing to the following digital-to-analog conversion module; A digital-to-analog conversion module is connected to several local antenna units and is used to control the antenna units to complete transmission and collection according to instructions, transmission data of the antenna units and beam pointing, and then process the collected local data and send the processed local data to the GTX uplink synchronization module; The data synthesis module is connected to the GTX communication module and the GTX uplink synchronization module, and is used to read the subordinate data and local data from the GTX uplink synchronization module, and process and synthesize the subordinate data and local data and upload them to the upper sub-array FPGA or the master control FPGA through the GTX communication module.

2. The high-speed serial bus synchronization system for digital phased array according to claim 1, characterized in that: The GTX uplink synchronization module includes a local data storage block for storing local data and a subordinate upload data storage block for storing subordinate data.

3. The high-speed serial bus synchronization system for digital phased array according to claim 2, characterized in that: The GTX downlink synchronization module includes a downlink data storage block.

4. The high-speed serial bus synchronization system for digital phased array according to claim 3, characterized in that: The local data storage block, the lower-level upload data storage block and the downlink data storage block are all FIFO storage blocks.

5. A high-speed serial bus synchronization method applied to a digital phased array, applied to the high-speed serial bus synchronization system according to any one of claims 1 to 4, characterized in that: The following steps are involved: S1. After the device is powered on, the master FPGA automatically starts high-speed serial bus synchronization and sends downlink data to all sub-array FPGAs. Then the master FPGA sends GTX synchronization instructions to all sub-array FPGAs. S2. After receiving the GTX synchronization instruction, the subarray FPGA immediately enters the GTX synchronization mode; S3. The subarray FPGA continues to write the newly received downlink data into the downlink data storage block; S4. After waiting for a certain period of time to ensure that the farthest sub-array FPGA also receives the GTX synchronization command, the master FPGA sends a variable frequency sync synchronization signal; S5. After the sub-array FPGA detects the variable frequency sync synchronization signal, it starts reading data from the downlink data storage block of the downlink synchronization module to complete the downlink data synchronization; S6. After the sub-array FPGA detects the variable frequency sync synchronization signal, it starts writing local data and variable frequency sync synchronization signal to the local data storage block; S7. After the subarray FPGA detects the variable frequency sync synchronization signal in the data uploaded by the lower subarray FPGA, it starts writing the lower data uploaded by the lower subarray FPGA to the lower upload data storage block; S8. When the local variable frequency sync synchronization signal and the lower-level uploaded variable frequency sync synchronization signal are received by the sub-array FPGA, the sub-array FPGA starts to read data from the local data storage block and the lower-level uploaded data storage block at the same time to complete the uplink data synchronization; The synchronized local data and the lower-level data are synthesized and then uploaded to the upper level; S8. After the uplink data synchronization and the downlink data synchronization are completed, the master FPGA sends a GTX synchronization test command; S10. The subarray FPGA receives the GTX synchronization test instruction and enters the GTX synchronization test mode to test whether both the uplink and the downlink are synchronized.

6. The high-speed serial bus synchronization method for a digital phased array according to claim 5, characterized in that: The subarray FPGA enters the GTX synchronization mode specifically including the following steps: S21. The downstream data storage block of the GTX downstream synchronization module in the subarray FPGA is reset, the residual data in the FIFO storage block is cleared, and the read enable is kept in an invalid state; S22. The local data storage block and the lower-level upload data storage block of the GTX upstream synchronization module in the subarray FPGA are reset, and the residual data are cleared and the read enable and write enable are kept in an invalid state.

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