Two-step differential full-parallel ADC (Analog to Digital Converter) circuit and module for CIS (Contact Image Sensor)

Abstract

The invention relates to the technical field of CMOS image sensor design, in particular to a two-step differential full-parallel ADC circuit and module for a CIS. The invention provides a two-step differential full-parallel ADC circuit for a CIS. The two-step differential full-parallel ADC circuit comprises a coarse quantization generation part, a fine quantization generation part, a comparator part, a storage capacitor part, a quantization switch part, a logic control part, a signal processing part, a counter part and an adder part. According to the method, two-step column-level differential full parallel processing is adopted, the 11-bit quantization process is decomposed into parallel 5-bit coarse quantization and 6-bit fine quantization, the overall quantization time can be effectively shortened, and the data quantization rate of the ADC is improved. According to the invention, the problem that the frame frequency of the CMOS image sensor is limited due to long quantization time and low conversion speed of the traditional SS ADC is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of CMOS image sensor design, and more specifically to: 1. a two-step differential full-parallel ADC circuit for CIS; 2. a two-step differential full-parallel ADC module for CIS. Background Art

[0002] CMOS image sensors (CIS for short) are increasingly used in modern electronic devices. Their performance has a direct impact on the imaging effect of the image, and a high-performance analog-to-digital converter (ADC for short) is the core part of the CMOS image sensor.

[0003] In general, column-level ADC is faster than chip-level ADC, and its power consumption and area are better than pixel-level ADC. It can achieve a good compromise between speed, area, accuracy, and power consumption, and is currently the mainstream architecture of ADC in CMOS image sensor readout circuits.

[0004] There are many types of column-level ADCs in common use, including SS ADC, SAR ADC, Cyclic ADC, etc., and their structural characteristics are different. Among them, SS ADC has a simple structure, low power consumption, small area, and can generate high-precision and high-linearity ramp signals, which is very suitable for column-level ADC.

[0005] Today’s CMOS image sensors require high frame rates in a variety of practical application scenarios. However, the traditional SSADC is slow. The single quantization time of an N-bit SS ADC is 2 N clock cycles, which results in a long quantization time and a low conversion speed, thus limiting the frame rate of the CMOS image sensor. Summary of the invention

[0006] Based on this, it is necessary to provide a two-step differential full-parallel ADC circuit and module for CIS to address the problem that the traditional SS ADC has a long quantization time and a low conversion speed, which limits the frame rate of the CMOS image sensor.

[0007] The present invention is implemented by the following technical solutions:

[0008] In a first aspect, the present invention provides a two-step differential full-parallel ADC circuit for CIS, for processing a single-column pixel signal V IN Perform 11-bit quantization.

[0009] The two-step differential full-parallel ADC circuit for CIS includes: a coarse quantization generating part DAC1, a fine quantization generating part DAC2, a comparator part, a storage capacitor part, a quantization switch part, a logic control part Logic1, a signal processing part Logic2, a counter part, and an adder part Adder.

[0010] DAC1 is used to provide a step ramp voltage signal RAMP_Coarse and serve as a coarse quantization ramp voltage.

[0011] DAC2 is used to provide a set of differential ramp voltage signals RAMP_Fine1 - RAMP_Fine2 and serve as a fine quantized ramp voltage.

[0012] The comparator section is used to convert V IN Compare with RAMP_Coarse, RAMP_Fine1, RAMP_Fine2. The comparator section includes: 2 comparators COMP1 ~ COMP2; COMP1, COMP2 inverting input terminals are connected to V IN The in-phase input terminals of COMP1 and COMP2 are connected to RAMP_Coarse, RAMP_Fine1, RAMP_Fine2, and the reference voltage V through the storage capacitor and the quantization switch. REF ; The output end of COMP1 is used to output the control signal CN1; the output end of COMP2 is used to output the control signal CN2.

[0013] Logic1 is used to control the quantization switch part according to CN1.

[0014] Logic2 is used to generate control signals RB1, COUNT1, COUNT2 according to CN1 and CN2.

[0015] The counter section includes: two counters Counter1 and Counter2; Counter1 is used for counting 5-bit coarse quantization according to COUNT1; Counter2 is used for counting 6-bit fine quantization according to COUNT2.

[0016] Adder is used to process the count values ​​of Counter1 and Counter2 according to RB1 according to preset rules to obtain the final 11-bit quantization result.

[0017] The implementation of the two-step differential fully parallel ADC circuit for CIS is based on the method or process of an embodiment of the present disclosure.

[0018] In a second aspect, the present invention discloses a two-step differential fully parallel ADC module for CIS, which adopts the layout of the two-step differential fully parallel ADC circuit for CIS disclosed in the first aspect.

[0019] The implementation of the two-step differential fully parallel ADC module for CIS is based on the method or process of an embodiment of the present disclosure.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. The present invention adopts two-step column-level differential full parallel processing to decompose the 11-bit quantization process into parallel 5-bit coarse quantization and 6-bit fine quantization, which can effectively shorten the overall quantization time and improve the data quantization rate of ADC.

[0022] 2. The present invention takes into account the possible situation that the fine quantization reversal point is before the coarse quantization reversal point, and adopts a differential ramp voltage signal for fine quantization, thereby compensating for the missing quantization interval to ensure the accuracy of the quantization result.

[0023] 3. The present invention also takes into account the errors caused by non-ideal factors such as the parasitic capacitance of the MOS tube switch in the circuit and the offset voltage of the comparator, and designs the counter for fine quantization to be 7 bits, using a calibration rule based on redundant bits to eliminate errors and ensure the accuracy of the quantization results. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0025] Figure 1 The overall structure diagram of the two-step differential full-parallel ADC circuit for CIS provided by the present invention;

[0026] Figure 2 for Figure 1 The circuit diagram of DAC1 in Figure 2;

[0027] Figure 3 for Figure 1 The circuit diagram of DAC2 in the figure;

[0028] Figure 4 for Figure 1 The circuit diagram of Logic1 in Figure 1;

[0029] Figure 5 for Figure 1 The circuit diagram of Logic2 in the figure;

[0030] Figure 6 V IN, coarse quantization ramp voltage, fine quantization ramp voltage, signal waveforms of CN1 and CN2;

[0031] Figure 7 This is a schematic diagram of the 11-bit quantization time without redundant calibration;

[0032] Figure 8 This is a schematic diagram of the time taken for 11-bit quantization during redundancy calibration;

[0033] Fig. 9 It is a schematic diagram of the corresponding operation process when the upward slope refinement result is valid without redundant calibration;

[0034] Fig.10 It is a schematic diagram of the corresponding operation process when the downward slope refinement result is valid without redundant calibration;

[0035] Fig.11 A schematic diagram of the corresponding operation process when the upward slope refinement result is valid in the case of redundant calibration;

[0036] Fig.12 Schematic diagram of the corresponding operation process when the downward slope refinement result is valid in the case of redundant calibration. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more related listed items.

[0040] Example 1

[0041] See also Figure 1 , Figure 1 The overall structure of a two-step differential full-parallel ADC circuit for CIS provided by the present invention is shown, which belongs to a column-level ADC and is used for a single-column pixel signal V IN Perform 11-bit quantization.

[0042] like Figure 1 As shown, the two-step differential full-parallel ADC circuit for CIS includes: a coarse quantization generating part DAC1, a fine quantization generating part DAC2, a comparator part, a storage capacitor part, a quantization switch part, a logic control part Logic1, a signal processing part Logic2, a counter part, and an adder part Adder.

[0043] The following explains them one by one:

[0044] (i) DAC1 is used to provide a step ramp voltage signal RAMP_Coarse and serve as a coarse quantization ramp voltage.

[0045] DAC1 can be used as Figure 2 Design:

[0046] DAC1 includes: a counter Counter3, a decoder Decoder, an operational amplifier A0, a resistor string array, and a control switch array.

[0047] In general, Counter3 is a Gray code counter, which is used to generate 5-bit Gray code; Decoder converts the 5-bit Gray code into binary code and controls the control switch array; the control switch array is placed between the high level VH and the low level VL, and changes the switch state under the control of the Decoder, and cooperates with the resistor string array, through A0 connected in the form of unit negative feedback, and the output end of A0 outputs RAMP_Coarse.

[0048] The specific connection relationship is as follows:

[0049] The resistor string array includes 32 resistors R_C1~R_C in series. 32 ; Among them, the first end of R_C1 is connected to the high level VH; R_C 32 The second end of R_C is connected to the low level VL; x The first end of the R_C x-1 The second end is connected to R_C x+1 The first end of ; x∈[2,31];

[0050] The control switch array includes 33 switches S_C1~S_C 33 ; Among them, R_C y The first end passes through S_Cy Connect the positive input of A0 and the second end through S_C y+1 Connect the positive input terminal of A0; y∈[1,32];

[0051] The output of Counter3 is connected to the input of Decoder;

[0052] Decoder is used to generate control signals a1~a 33 ; Among them, a j For controlling S_C j The opening or closing of; j∈[1,33];

[0053] The output terminal of A0 is connected to its negative input terminal and outputs RAMP_Coarse.

[0054] Of course, DAC1 can also be designed in other ways as long as it can generate RAMP_Coarse.

[0055] (ii) DAC2 is used to provide a set of differential ramp voltage signals RAMP_Fine1 - RAMP_Fine2 and serve as a fine-scale ramp voltage.

[0056] DAC2 can be used as Figure 3 Design:

[0057] DAC2 includes: 1 current source array, 1 differential switch array, 1 load resistor sub-section, 1 segment decoder Segment_Decoder, and 1 operational amplifier sub-section.

[0058] In general, the segmented decoder generates a control signal to control the differential switch array to realize the corresponding current source in the current source array output to the load resistor sub-section; the load resistor sub-section is divided into two branches, one of which passes through the resistor R1 to complete the current-to-voltage conversion, and cooperates with the operational amplifier sub-section to generate a gradually rising ramp voltage signal RAMP_Fine1; the other branch passes through the load resistor R2, and cooperates with the operational amplifier sub-section to generate a gradually falling ramp voltage signal RAMP_Fine2.

[0059] The specific connection relationship is as follows:

[0060] The current source array includes: 18 current sources I0~I 17 ; Among them, I0 is the unit current source I, I1 is the 2 times current source 2I, I2 is the 4 times current source 4I, I3~I 17 Both are 8 times current source 8I.

[0061] The differential switch array includes: 18 switches S_I0~S_I 17 ; S_I0~S_I 17All are single-pole double-throw switches;

[0062] Among them, I k The output terminal is connected to S_I k The fixed end of S_I k The moving end 1 is connected to RAMP_Fine1, and the moving end 2 is connected to RAMP_Fine2; k∈[0,7];

[0063] Segment_Decoder is used to generate control signals b0~b 17 ; Among them, b k For S_I k It is important to note that b0~b2 are binary codes; b3~b 17 Thermometer code.

[0064] The load resistor sub-section includes: two resistors R1-R2; the first end of R1 is connected to RAMP_Fine1, the first end of R2 is connected to RAMP_Fine2; the second end of R1 is connected to the second end of R2;

[0065] The operational amplifier sub-unit includes: 1 operational amplifier A1, 1 capacitor C0, and 1 NMOS tube N1; the positive input terminal of A1 is connected to the second end of R1, the first end of C0, and the drain of N1; the negative input terminal of A1 is connected to the control voltage V0; the gate of N1 is connected to the output terminal of A1, the drain is connected to the second end of C0, and the source is grounded.

[0066] Of course, DAC1 can also be designed in other ways as long as it can generate RAMP_Fine1 and RAMP_Fine2.

[0067] (III) The comparator section is used to convert V IN Compare with the coarse quantization ramp voltage and the fine quantization ramp voltage.

[0068] See also Figure 1 The comparator unit includes: 2 comparators COMP1~COMP2.

[0069] The inverting input terminals of COMP1 and COMP2 are connected to V IN ;

[0070] The in-phase input of COMP1 and COMP2 is connected to RAMP_Coarse, RAMP_Fine1, RAMP_Fine2, and the reference voltage V through the storage capacitor and the quantization switch. REF .

[0071] The quantization switch unit includes six switches S11, S22, S21, S22, S31, and S32; and the storage capacitor unit includes two storage capacitors C1-C2.

[0072] The first ends of S11 and S12 are connected to RAMP_Coarse; the second end of S11 is connected to the non-inverting input end of COMP1 and the first end of C1; the second end of S12 is connected to the non-inverting input end of COMP2 and the first end of C2; the first end of S21 is connected to RAMP_Fine1, and the second end is connected to the second end of C1 and the first end of S31; the first end of S22 is connected to RAMP_Fine2, and the second end is connected to the second end of C2 and the first end of S32; the second ends of S31 and S32 are connected to V REF .

[0073] It should be noted that the capacitance values ​​of C1 and C2 are the same, both C.

[0074] The output end of COMP1 is used to output a control signal CN1; the output end of COMP2 is used to output a control signal CN2.

[0075] (iv) Logic1 is used to control the quantization switch section according to CN1.

[0076] See also Figure 4 , Logic1 includes: 2 D flip-flops DFF5~DFF6, 2 inverters INV3~INV4, and 1 AND gate AND5.

[0077] Specifically, the clock input CLK terminal of DFF5 is connected to the clock signal CK, the D terminal is connected to CN1, and the RB terminal is connected to the reset signal RST; the clock input non-CLK terminal of DFF6 is connected to the Q terminal of DFF5, the D terminal is connected to the digital power supply voltage VCC12, and the RB terminal is connected to the reset signal RST; the input terminal of INV3 is connected to the Q terminal of DFF6; the input terminal 1 of AND5 is connected to the output terminal of INV3, the input terminal 2 is connected to the total switch signal T0, and the output terminal outputs the switch signal SC1; the input terminal of INV4 is connected to SC1, and the output terminal outputs the switch signal SC2.

[0078] Among them, SC1 controls S11, S12, S31, S32 to be opened or closed; SC2 controls S31, S32 to be opened or closed.

[0079] (V) Logic2 is used to generate control signals RB1, COUNT1, COUNT2 according to CN1 and CN2.

[0080] See also Figure 5 , Logic2 includes: 4 D flip-flops DFF1~DFF4, 3 AND gates AND1~AND3, and 1 OR gate OR.

[0081] Specifically, the RB terminals of DFF1 and DFF2 are connected to the reset signal RST; the clock input CLK terminal of DFF1 is connected to CN2, and the D terminal and the Q non-terminal are connected; the input terminal 1 of AND1 is connected to the Q terminal of DFF1 and recorded as the control signal CM2, and the input terminal 2 is connected to CN1; the clock input CLK terminal of DFF2 is connected to the output terminal of AND1, the D terminal is connected to the digital power supply voltage VCC12, and the Q terminal outputs COUNT1; the clock input CLK non-terminal of DFF3 is connected to CN1, the D terminal is connected to VCC12, and the RB terminal is connected Connected to RB1, the Q end outputs the control signal A1; the input terminal 1 of AND2 is connected to the Q non-end of DFF3, the input terminal 2 is connected to RST, and the output end outputs the control signal RB2; the clock input CLK non-end of DFF4 is connected to CM2, the D end is connected to VCC12, the RB end is connected to RB2, and the Q end outputs the control signal B1; the input terminal 1 of AND3 is connected to the Q non-end of DFF4, the input terminal 2 is connected to RST, and the output end outputs RB1; the input terminal 1 of OR is connected to A1, the input terminal 2 is connected to B1, and the output end outputs COUNT2.

[0082] (VI) The counter section includes two counters Counter1 and Counter2. Counter1 is used for performing 5-bit coarse quantization counting according to COUNT1; Counter2 is used for performing 6-bit fine quantization counting according to COUNT2.

[0083] like Figure 1 As shown, COUNT1 is connected to the control end of Counter1, and COUNT2 is connected to the control end of Counter2.

[0084] It should be noted that since the 11-bit quantization process is decomposed into parallel 5-bit coarse quantization and 6-bit fine quantization; if redundant calibration is not required, Counter1 can use a 5-bit counter and Counter2 can use a 6-bit counter; if redundant calibration is required, Counter1 can use a 5-bit counter and Counter2 can use a 7-bit counter.

[0085] (VII) Adder is used to process the count values ​​of Counter1 and Counter2 according to RB1 according to preset rules to obtain the final 11-bit quantization result (ie, OUT<10:0>).

[0086] like Figure 1 As shown, input terminal 1 of Adder is connected to the output terminal of Counter1, input terminal 2 is connected to the output terminal of Counter2, and the control terminal is connected to RB1.

[0087] The two-step differential full parallel ADC circuit for CIS based on the above structure works as follows:

[0088] First, T0 maintains a high level, SC1 is a high level, SC2 is a low level, S11, S12, S31, S32 are closed, S21, S22 are open, RAMP_Coarse, RAMP_Fine1, RAMP_Fine2 start at the same time, and Counter1, Counter2 also start counting at the same time.

[0089] The voltage at the first end of C1 and C2 rises with RAMP_Coarse and is sent to the non-inverting input of COMP1 and COMP2. The inverting input of COMP1 and COMP2 is connected to V IN ;

[0090] At the beginning, CN1 and CN2 are at low level;

[0091] When RAMP_Coarse is greater than V IN When , CN1 and CN2 flip and output high level, Counter1 stops counting, and 5-bit coarse quantization is completed; at this time, the voltage value of the first terminal of C1 and C2 is V REF +m*MSB; m represents the count value of Counter1 at this time, and MSB represents the most significant bit.

[0092] CN1 is processed by Logic1, so that SC1 is cut to a low level and SC2 is cut to a high level, S11, S12, S31, and S32 are disconnected, S21 and S22 are closed, RAMP_Fine1 connects to the second end of C1, and RAMP_Fine2 connects to the second end of C2. The voltage values ​​of the first ends of C1 and C2 will follow the change of the fine quantization ramp voltage based on the voltage value when the coarse quantization is completed, and Counter2 continues to count and continue to perform fine quantization.

[0093] Since RAMP_Fine1 and RAMP_Fine2 are a pair of differential ramps, the voltage at the in-phase input of COMP1 slopes down based on the voltage value when coarse quantization is completed; the voltage at the in-phase input of COMP2 slopes up based on the voltage value when coarse quantization is completed.

[0094] It should be noted that according to V IN The following four situations will occur during the quantization process, and the quantization schematic diagram and the corresponding output waveforms of CN1 and CN2 are as follows: Figure 6 As shown:

[0095] Case 1: V IN It is located above the MSB / 2 of a coarse quantization voltage interval and only intersects with the upward slope of fine quantization, such as Figure 6 (a) shown.

[0096] Case 2: V IN It is located above MSB / 2 of a coarse quantization voltage interval and has intersections with both the upward and downward slopes of the fine quantization, but the downward slope intersection is earlier than the upward slope intersection, such as Figure 6 (b) as shown.

[0097] Case 3: V IN It is located below the MSB / 2 of a coarse quantization voltage interval and has intersections with both the upward and downward slopes of the fine quantization, but the intersection of the upward slope is earlier than the intersection of the downward slope, such as Figure 6 (c) as shown.

[0098] Case 4: V IN It is located below the MSB / 2 of a coarse quantization voltage interval and only intersects with the downward slope of fine quantization, such as Figure 6 (d) as shown.

[0099] When CN1 flips from high level to low level, the quantization downward slope ends; when CN2 flips from low level to high level, the quantization upward slope ends; at this time, the amount of charge stored in C1 and C2 is m*MSB*C; where the voltage value of the first terminal of C1 is V REF +m*MSB-n*LSB; the voltage value of the first terminal of C2 is V REF +(m-1)*MSB+n*LSB; n represents the count value of Counter2 at this time, and LSB represents the least significant bit.

[0100] In the fine quantization process, RB1 is detected to determine whether the upward or downward slope fine quantization result is valid, and then the count values ​​of Counter1 and Counter2 are processed accordingly according to different situations, thereby obtaining the final result of 11-bit quantization.

[0101] Specifically, RB1 reflects the falling edge flip time of CN1 and CM2, which can be used to make judgments:

[0102] 1. If RB1 changes from high level to low level, that is, CN1 flips on the falling edge first, it is judged that the upward slope refinement result is valid.

[0103] 2. If RB1 keeps high level, that is, CM2 signal falls first, it is judged that the downward slope refinement result is valid.

[0104] If the errors caused by non-ideal factors such as parasitic capacitance of MOS switches and offset voltage of comparators in the circuit are not considered, redundant calibration is not necessary. Figure 7 In this case, the overall quantization time of 11bit is shortened to 2 6T; T represents the clock cycle. In this case, Counter1 uses a 5-bit counter and Counter2 uses a 6-bit counter. The corresponding preset rules are designed as follows:

[0105] ① When the result of the upward slope refinement is valid, first fill the low bit of the count value of Counter1 with zero to obtain the code value P1, and fill the high bit of the count value of Counter2 with zero to obtain the code value P2; then add P1 and P2 to obtain the code value P3.

[0106] Where P1 = d H10 d H9 d H8 d H7 d H6 000000; P2 = 00000d L5 d L4 d L3 d L2 d L1 d L0 ;

[0107] P3=D 10 D9D8D7D6D5D4D3D2D1D0.

[0108] Among them, d H10 ~d H6 5 bits representing the count value of Counter1; d L5 d L4 d L3 d L2 d L1 d L0 6 bits representing the count value of Counter2; D 10 ~D0 represents the 11 bits of the final 11-bit quantization result.

[0109] For ease of understanding, the calculation process of ① can be found in Fig. 9 .

[0110] ② When the downward slope refinement result is valid, the count value of Counter1 is first filled with zeros at the low bit and then added with 0000100000 to obtain the code value P4. The count value of Counter2 is first filled with zeros at the high bit and then added with 00000000001 to obtain the code value P5. Then P5 is first inverted and then added to P4 to obtain the code value P6.

[0111] Where P4 = d H10 d H9 d H8 d H7 d H6 000000+00001000000;

[0112] P5=00000d L5 d L4 d L3 d L2 d L1 d L0 +00000000001;

[0113] P6=D 10 D9D8D7D6D5D4D3D2D1D0.

[0114] Among them, d H10 ~d H6 5 bits representing the count value of Counter1; d L5 d L4 d L3 d L2 d L1 d L0 6 bits representing the count value of Counter2; D 10 ~D0 represents the 11 bits of the final 11-bit quantization result.

[0115] For ease of understanding, the calculation process of ② can be found in Fig.10 .

[0116] Of course, if you want to further ensure the accuracy of the 11-bit quantization results, you need to consider the errors caused by non-ideal factors such as the parasitic capacitance of the MOS tube switch in the circuit and the offset voltage of the comparator, and perform redundant calibration; see Figure 8 In this case, the overall quantization time of 11bit is shortened to 2 6 T+ΔT; where T represents the clock cycle; ΔT represents the time taken for redundant calibration. In this case, Counter1 uses a 5-bit counter and Counter2 uses a 7-bit counter. The corresponding preset rules are designed as follows:

[0117] ③ When the result of the upward slope refinement is valid, first fill the low bit of the count value of Counter1 with zero to obtain the code value Q1, and fill the high bit of the count value of Counter2 with zero to obtain the code value Q2; then add Q1 and Q2 to obtain Q3.

[0118] Where Q1 = d H10 d H9 d H8 d H7 d H6 000000; Q2 = 0000d L6 d L5 d L4 d L3 d L2 d L1 d L0 ;

[0119] Q3=D 10 D9D8D7D6D5D4D3D2D1D0.

[0120] Among them, d H10 ~d H6 5 bits representing the count value of Counter1; d L6 d L5 d L4 d L3 d L2 d L1 d L0 7 bits representing the count value of Counter2; D 10 ~D0 represents the 11 bits of the final 11-bit quantization result.

[0121] For easier understanding, the calculation process of ③ can be found in Fig.11 .

[0122] ④ When the downward slope refinement result is valid, the count value of Counter1 is first filled with zeros at the low bit and then added with 0000100000 to obtain the code value Q4. The count value of Counter2 is first filled with zeros at the high bit and then added with 00000000001 to obtain the code value Q5. Then, Q5 is first inverted and then added to Q4 to obtain the code value Q6.

[0123] Where Q4 = d H10 d H9 d H8 d H7 d H6 000000+00001000000;

[0124] Q5=0000d L6 d L5 d L4 d L3 d L2 d L1 d L0 +00000000001;

[0125] Q6=D 10 D9D8D7D6D5D4D3D2D1D0.

[0126] Among them, d H10 ~d H6 5 bits representing the count value of Counter1; d L6 d L5 d L4 d L3 d L2 d L1 d L0 7 bits representing the count value of Counter2; D10 ~D0 represents the 11 bits of the final 11-bit quantization result.

[0127] For easier understanding, the calculation process of ④ can be found in Fig.12 .

[0128] Example 2

[0129] This embodiment 2 discloses a two-step differential full parallel ADC module for CIS, which adopts the layout of the two-step differential full parallel ADC circuit for CIS disclosed in embodiment 1. The mode of packaging into a module makes it easier to promote and apply the above circuit.

[0130] The two-step differential full parallel ADC module for CIS includes: a coarse quantization generation module (corresponding to DAC1), a fine quantization generation module (corresponding to DAC2), a comparator module (corresponding to the comparator part), a storage capacitor module (corresponding to the storage capacitor part), a quantization switch module (corresponding to the quantization switch part), a logic control module (corresponding to Logic1), a signal processing module (corresponding to Logic2), a counter module (corresponding to the counter part), and an adder module (corresponding to Adder). The specific circuit distribution is shown in Example 1, which will not be repeated here.

[0131] This embodiment 2 also simultaneously discloses a CMOS image sensor, which adopts the above-mentioned two-step differential full-parallel ADC module for CIS.

[0132] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A two-step differential full parallel ADC circuit for CIS, used for single column pixel signal V IN 11-bit quantization is performed; it is characterized in that: The two-step differential full parallel ADC circuit for CIS comprises: A coarse quantization generating unit DAC1, which is used to provide a step ramp voltage signal RAMP_Coarse as a coarse quantization ramp voltage; A fine quantization generating section DAC2, which is used to provide a set of differential ramp voltage signals RAMP_Fine1-RAMP_Fine2 and serve as a fine quantization ramp voltage; Storage capacitor unit; Quantitative switch department; The comparator section is used to convert V IN Compare with the coarse quantization ramp voltage and the fine quantization ramp voltage; the comparator section includes: 2 comparators COMP1 ~ COMP2; the inverting input terminals of COMP1 and COMP2 are both connected to V IN The in-phase input terminals of COMP1 and COMP2 are connected to RAMP_Coarse, RAMP_Fine1, RAMP_Fine2, and the reference voltage V through the storage capacitor and the quantization switch. REF ; The output end of COMP1 is used to output the control signal CN1; the output end of COMP2 is used to output the control signal CN2; A logic control unit Logic1, which is used to control the quantization switch unit according to CN1; A signal processing unit Logic2, which is used to generate control signals RB1, COUNT1, COUNT2 according to CN1, CN2; The counter section includes: two counters Counter1 and Counter2; Counter1 is used for counting 5-bit coarse quantization according to COUNT1; Counter2 is used for counting 6-bit fine quantization according to COUNT2; as well as The adder part Adder is used to process the count values ​​of Counter1 and Counter2 according to RB1 according to preset rules to obtain the final 11-bit quantization result.

2. The two-step differential full-parallel ADC circuit for CIS according to claim 1, characterized in that: The quantization switch section includes: 6 switches S11, S22, S21, S22, S31, S32; The storage capacitor unit includes: 2 storage capacitors C1-C2; The first ends of S11 and S12 are connected to RAMP_Coarse; The second end of S11 is connected to the non-inverting input end of COMP1 and the first end of C1; The second end of S12 is connected to the non-inverting input end of COMP2 and the first end of C2; The first end of S21 is connected to RAMP_Fine1, and the second end is connected to the second end of C1 and the first end of S31; The first end of S22 is connected to RAMP_Fine2, and the second end is connected to the second end of C2 and the first end of S32; The second end of S31 and S32 is connected to V REF .

3. The two-step differential full-parallel ADC circuit for CIS according to claim 2, characterized in that: Logic1 includes: 2 D flip-flops DFF5-DFF6, 2 inverters INV3-INV4, and 1 AND gate AND5; The clock input CLK terminal of DFF5 is connected to the clock signal CK, the D terminal is connected to CN1, and the RB terminal is connected to the reset signal RST; The clock input non-CLK terminal of DFF6 is connected to the Q terminal of DFF5, the D terminal is connected to the digital power supply voltage VCC12, and the RB terminal is connected to the reset signal RST; The input end of INV3 is connected to the Q end of DFF6; The input terminal 1 of AND5 is connected to the output terminal of INV3, the input terminal 2 is connected to the switch total signal T0, and the output terminal outputs the switch signal SC1; The input end of INV4 is connected to SC1, and the output end outputs a switching signal SC2; Among them, SC1 controls S11, S12, S31, and S32 to open or close; SC2 controls S31 and S32 to open or close.

4. The two-step differential full-parallel ADC circuit for CIS according to claim 1, characterized in that: Logic2 includes: 4 D flip-flops DFF1~DFF4, 3 AND gates AND1~AND3, and 1 OR gate OR; The RB terminals of DFF1 and DFF2 are both connected to the reset signal RST; The clock input CLK terminal of DFF1 is connected to CN2, and the D terminal and the Q non-terminal are connected; The first input terminal of AND1 is connected to the Q terminal of DFF1 and recorded as the control signal CM2, and the second input terminal is connected to CN1; The clock input CLK terminal of DFF2 is connected to the output terminal of AND1, the D terminal is connected to the digital power supply voltage VCC12, and the Q terminal outputs COUNT1; The clock input CLK non-end of DFF3 is connected to CN1, the D end is connected to VCC12, the RB end is connected to RB1, and the Q end outputs the control signal A1; The input terminal 1 of AND2 is connected to the Q non-terminal of DFF3, the input terminal 2 is connected to RST, and the output terminal outputs the control signal RB2; The clock input CLK non-end of DFF4 is connected to CM2, the D end is connected to VCC12, the RB end is connected to RB2, and the Q end outputs the control signal B1; Input terminal 1 of AND3 is connected to the Q NOT terminal of DFF4, input terminal 2 is connected to RST, and the output terminal outputs RB1; Input 1 of OR is connected to A1, input 2 is connected to B1, and the output is COUNT2.

5. The two-step differential full-parallel ADC circuit for CIS according to claim 1, characterized in that: If RB1 changes from high level to low level, it is judged that the upward slope refinement result is valid; If RB1 remains at a high level, it is determined that the downward slope refinement result is valid.

6. The two-step differential full-parallel ADC circuit for CIS according to claim 5, characterized in that: If Counter1 is a 5-bit counter and Counter2 is a 6-bit counter, the default rules are: When the result of the upward slope refinement is valid, the low bits of the count value of Counter1 are first filled with zeros to obtain the code value P1, and the high bits of the count value of Counter2 are filled with zeros to obtain the code value P2; then P1 and P2 are added to obtain the code value P3; Among them, P1 = d H10 d H9 d H8 d H7 d H6 000000; P2 = 00000d L5 d L4 d L3 d L2 d L1 d L0 ; <h2 style=";text-align:left;direction:ltr">P3=D<h2 style=";text-align:left;direction:ltr"> 10 <h2 style=";text-align:left;direction:ltr"> D9D8D7D6D5D4D3D2D1D0; When the result of the downward slope refinement is valid, the count value of Counter1 is first filled with zeros at the lower bits, and then 0000100000 is added to obtain the code value P4. The count value of Counter2 is first filled with zeros at the upper bits, and then 00000000001 is added to obtain the code value P5. Then, P5 is first inverted and then added to P4 to obtain the code value P6. Where P4 = d H10 d H9 d H8 d H7 d H6 000000+00001000000; P5=00000d L5 d L4 d L3 d L2 d L1 d L0 +00000000001; <h2 style=";text-align:left;direction:ltr">P6=D<h2 style=";text-align:left;direction:ltr"> 10 <h2 style=";text-align:left;direction:ltr"> D9D8D7D6D5D4D3D2D1D0; Among them, d H10 ~d H6 5 bits representing the count value of Counter1; d L5 d L4 d L3 d L2 d L1 d L0 6 bits representing the count value of Counter2; D 10 ~D0 represents the 11 bits of the final 11-bit quantization result.

7. The two-step differential full-parallel ADC circuit for CIS according to claim 5, characterized in that: If Counter1 is a 5-bit counter and Counter2 is a 7-bit counter, the default rules are: When the result of the upward slope refinement is valid, the low bits of the count value of Counter1 are first filled with zeros to obtain the code value Q1, and the high bits of the count value of Counter2 are filled with zeros to obtain the code value Q2; then Q1 and Q2 are added to obtain Q3; where Q1 = d H10 d H9 d H8 d H7 d H6 000000; Q2 = 0000d L6 d L5 d L4 d L3 d L2 d L1 d L0 ; <h2 style=";text-align:left;direction:ltr">Q3=D<h2 style=";text-align:left;direction:ltr"> 10 <h2 style=";text-align:left;direction:ltr"> D9D8D7D6D5D4D3D2D1D0; When the result of the downward slope refinement is valid, the count value of Counter1 is first filled with zeros at the lower bits, and then 0000100000 is added to obtain the code value Q4. The count value of Counter2 is first filled with zeros at the upper bits, and then 00000000001 is added to obtain the code value Q5. Then, Q5 is first inverted and then added to Q4 to obtain the code value Q6. Where Q4 = d H10 d H9 d H8 d H7 d H6 000000+00001000000; Q5=0000d L6 d L5 d L4 d L3 d L2 d L1 d L0 +00000000001; Q6=D 10 D9D8D7D6D5D4D3D2D1D0; Among them, d H10 ~d H6 5 bits representing the count value of Counter1; d L6 d L5 d L4 d L3 d L2 d L1 d L0 7 bits representing the count value of Counter2; D 10 ~D0 represents the 11 bits of the final 11-bit quantization result.

8. The two-step differential full-parallel ADC circuit for CIS according to claim 1, characterized in that: DAC1 includes: 1 counter Counter3, 1 decoder Decoder, 1 operational amplifier A0, 1 resistor string array, and 1 control switch array; The resistor string array includes 32 resistors R_C1~R_C in series. 32 ; Among them, the first end of R_C1 is connected to the high level VH; R_C 32 The second end of R_C is connected to the low level VL; x The first end of the R_C x-1 The second end is connected to R_C x+1 The first end of ; x∈[2,31]; The control switch array includes 33 switches S_C1~S_C 33 ; Among them, R_C y The first end passes through S_C y Connect the positive input of A0 and the second end through S_C y+1 Connect the positive input terminal of A0; y∈[1,32]; The output of Counter3 is connected to the input of Decoder; Decoder is used to generate control signals a1~a 33 ; Among them, a j For controlling S_C j The opening or closing of; j∈[1,33]; The output terminal of A0 is connected to its negative input terminal and outputs RAMP_Coarse.

9. The two-step differential full-parallel ADC circuit for CIS according to claim 1, characterized in that: DAC2 includes: 1 current source array, 1 differential switch array, 1 load resistor sub-section, 1 segment decoder Segment_Decoder, and 1 op amp sub-section; The current source array includes: 18 current sources I0~I 17 ; Among them, I0 is the unit current source I, I1 is the 2 times current source 2I, I2 is the 4 times current source 4I, I3~I 17 All are 8 times current source 8I; The differential switch array includes: 18 switches S_I0~S_I 17 ; S_I0~S_I 17 All are single-pole double-throw switches; Among them, I k The output terminal is connected to S_I k The fixed end of S_I k The moving end 1 is connected to RAMP_Fine1, and the moving end 2 is connected to RAMP_Fine2; k∈[0,7]; Segment_Decoder is used to generate control signals b0~b 17 ; Among them, b k For S_I k Control the switching of The load resistor sub-section includes: two resistors R1-R2; the first end of R1 is connected to RAMP_Fine1, the first end of R2 is connected to RAMP_Fine2; the second end of R1 is connected to the second end of R2; The operational amplifier sub-unit includes: 1 operational amplifier A1, 1 capacitor C0, and 1 NMOS tube N1; the positive input terminal of A1 is connected to the second end of R1, the first end of C0, and the drain of N1; the negative input terminal of A1 is connected to the control voltage V0; the gate of N1 is connected to the output terminal of A1, the drain is connected to the second end of C0, and the source is grounded.

10. A two-step differential full parallel ADC module for CIS, characterized in that: It adopts the layout of the two-step differential full-parallel ADC circuit for CIS as described in any one of claims 1-9.

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