Wireless communication system and method based on reconfigurable FPGA component development

Abstract

The present invention relates to a wireless communication system and method based on reconfigurable FPGA component development. Through the ingenious design of key technologies such as the connection control matrix between the FPGA proxy component on the CPU side and the static / dynamic component on the FPGA side, the waveform of the FPGA component can be quickly and dynamically reconstructed. The waveform reconstruction speed can reach the millisecond level, which is much higher than the second level achieved by directly updating the BIT file code of the entire FPGA at present. The system code update rate can be increased by about 1000 times, which can well adapt to the rapidly changing spectrum conditions in modern emergency rescue scenarios, automatically perform high-speed real-time reconstruction and switching of the waveform, and effectively ensure the reliability of wireless communication.

Description

Technical Field

[0001] The present invention belongs to the technical field of wireless communication, and relates to a wireless communication system and method based on reconfigurable FPGA component development. Background Art

[0002] In the design of emergency rescue wireless communication network system based on software radio technology, componentized waveform design can achieve high code reuse and reduce development workload, and can realize real-time switching of waveforms by replacing all or part of the components, which improves the speed of waveform switching and meets the ever-changing spectrum changes in emergency rescue scenarios. The hardware design of emergency rescue wireless communication network system often adopts a heterogeneous processor platform composed of FPGA and CPU. In the current componentized waveform design, only the code on the CPU side is generally componentized. For the code on the FPGA side, it is limited by the FPGA implementation architecture and often generates a large BIT file for the function of the entire FPGA. When switching waveforms, the entire FPGA must be reloaded. For large-scale FPGAs (such as K series and V series), the loading time is relatively long, which can reach seconds, and it is difficult to meet the needs of fast waveform switching of modern emergency rescue wireless communication networks. Although some manufacturers' FPGAs currently provide some reconfigurable functions, due to the lack of interface specifications between FPGA components, they are not common in the design of emergency rescue wireless communication networks based on software radio, and it is difficult to meet actual application needs. Summary of the invention

[0003] In response to the problems existing in the hardware design and application of the above-mentioned traditional emergency rescue wireless communication network system, the present invention proposes a wireless communication system based on reconfigurable FPGA component development and a wireless communication method based on reconfigurable FPGA component development, which can effectively meet the application requirements of rapid waveform switching of modern emergency rescue wireless communication networks.

[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, a wireless communication system based on reconfigurable FPGA component development is provided, including a heterogeneous hardware platform, a software radio operating system, a componentized waveform, and a waveform operation interface, wherein the componentized waveform includes a CPU side, an FPGA side, and a radio frequency side;

[0006] The CPU side is used to implement a complete waveform component flow graph, which includes a component parameter control module, multiple CPU components, multiple FPGA proxy components, and an FPGA interface driver component. Each CPU component includes a signal source and sink component, an audio codec component, a network protocol component, an IO interface driver component, and a low-rate signal processing component. Each FPGA proxy component is used to control the parameters of each component on the FPGA side.

[0007] The implementation logic on the FPGA side includes framework code and user code. The framework code is used to implement dynamic configuration of interface drivers and component connection relationships. The user code is used to implement modulation and demodulation, extraction filtering, and up and down frequency conversion. The framework code includes a CPU interface driver component, multiple flow control port modules, a static component connection control matrix module, a dynamic component connection control matrix module, and multiple RF driver modules. The CPU interface driver component is interconnected with the FPGA interface driver component through a high-speed serial bus. The user code includes multiple FPGA custom components that are preset to a BIT file for compilation;

[0008] The flow control port module is used to establish, start and stop the data flow, and to establish the flow buffer. The static component connection control matrix module is used to control the connection relationship between the FPGA custom components that are shared unchanging components in each FPGA custom component through software instructions. The dynamic component connection control matrix module is used to control the connection relationship between the FPGA custom components that are independent variable components in each FPGA custom component through software instructions. Each RF driver module is used to implement the interface drive of the RF module on the RF side.

[0009] On the other hand, a wireless communication method based on reconfigurable FPGA component development is also provided, based on a wireless communication system based on reconfigurable FPGA component development, the wireless communication system includes a heterogeneous hardware platform, a software radio operating system, a componentized waveform and a waveform operation interface, the componentized waveform includes a CPU side, an FPGA side and a radio frequency side;

[0010] The CPU side is used to implement a complete waveform component flow graph, which includes a component parameter control module, multiple CPU components, multiple FPGA proxy components, and an FPGA interface driver component. Each CPU component includes a signal source and sink component, an audio codec component, a network protocol component, an IO interface driver component, and a low-rate signal processing component. Each FPGA proxy component is used to control the parameters of each component on the FPGA side.

[0011] The implementation logic on the FPGA side includes framework code and user code. The framework code is used to implement dynamic configuration of interface drivers and component connection relationships. The user code is used to implement modulation and demodulation, extraction filtering, and up and down frequency conversion. The framework code includes a CPU interface driver component, multiple flow control port modules, a static component connection control matrix module, a dynamic component connection control matrix module, and multiple RF driver modules. The CPU interface driver component is interconnected with the FPGA interface driver component through a high-speed serial bus. The user code includes multiple FPGA custom components that are preset to a BIT file for compilation;

[0012] The flow control port module is used to establish, start and stop the data flow, and to establish the flow buffer. The static component connection control matrix module is used to control the connection relationship between the FPGA custom components that are common unchanged components in each FPGA custom component through software instructions. The dynamic component connection control matrix module is used to control the connection relationship between the FPGA custom components that are independent variable components in each FPGA custom component through software instructions. Each RF driver module is used to realize the interface drive of the RF module on the RF side.

[0013] The wireless communication method based on reconfigurable FPGA component development includes the following steps:

[0014] With the help of software radio integrated development environment, the FPGA side development is carried out, and the framework code on the FPGA side and all FPGA components used by each waveform in the application are jointly compiled to generate a complete BIT file;

[0015] Use software radio integrated development environment to develop on CPU side and obtain the waveform files and corresponding waveform applications needed;

[0016] Starting a waveform application, loading a first waveform and setting FPGA parameters of the first waveform, starting the first waveform and creating a data stream connection for the first waveform;

[0017] Transferring the FPGA parameters of the first waveform to the framework code on the FPGA side, and establishing connections between the FPGA components corresponding to the first waveform through the static component connection control matrix and the dynamic component connection control matrix;

[0018] According to the actual spectrum conditions in the emergency rescue scenario, the waveform application is used to switch to the second waveform in real time and set the FPGA parameters of the second waveform, start the second waveform and create a data stream connection for the second waveform;

[0019] The FPGA parameters of the second waveform are transferred to the framework code on the FPGA side, and connections between the FPGA components corresponding to the second waveform are established through the static component connection control matrix and the dynamic component connection control matrix.

[0020] One of the above technical solutions has the following advantages and beneficial effects:

[0021] The above-mentioned wireless communication system and method based on reconfigurable FPGA component development can realize fast dynamic reconstruction of the waveform of FPGA components through the ingenious design of key technologies such as the connection control matrix between the FPGA proxy component on the CPU side and the static / dynamic component on the FPGA side. The waveform reconstruction speed can reach milliseconds, which is much higher than the current second level achieved by directly updating the BIT file code of the entire FPGA. The system's code update rate can be increased by about 1,000 times, which can well adapt to the rapidly changing spectrum conditions in modern emergency rescue scenarios, automatically perform high-speed real-time reconstruction and switching of waveforms, and effectively ensure the reliability of wireless communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A schematic diagram of the overall architecture of a wireless communication system developed based on a reconfigurable FPGA component in one embodiment;

[0024] Figure 2 A schematic diagram of a structure of an FPGA component implementation in one embodiment;

[0025] Figure 3 A logical schematic diagram of an FPGA component in one embodiment;

[0026] Figure 4 A schematic diagram of an example of FM / FSK dual waveform componentization in an embodiment;

[0027] Figure 5 The figure is a flowchart of a wireless communication method based on reconfigurable FPGA component development in one embodiment. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0029] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0030] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0031] Before formally introducing the design of the present invention, some necessary professional technical terms in this field are explained as follows:

[0032] Waveform: describes the entire radio function from user input to RF output, which can be roughly understood as a communication system, such as GSM waveform, WCDMA waveform, which includes waveform parameters such as frequency, bandwidth, modulation and coding type, message standard and network protocol.

[0033] Component: refers to a specific software module that processes data flow, with input and output ports, and configurable parameter interfaces. By defining a complete set of inter-component interface specifications, standard connections can be achieved between components to achieve data flow and control signal transmission. Components can be written in languages ​​such as C++, Python, or Matlab, and XML / YML is used to describe component interface information. In order to achieve code reuse and improve development efficiency, the software radio system adopts a component-based approach to waveform development.

[0034] Software Radio Integrated Development Environment: A software developed for the field of software radio waveform design. It provides waveform developers with multi-functional software interfaces such as visual component development, waveform development and resource management, and provides functions such as waveform remote control and remote observation.

[0035] Flowchart: refers to the implementation process of waveform componentization in the software radio integrated development environment. In order to complete a specific waveform function, multiple components are connected to the input and output ports according to a certain logical relationship to generate a flowchart. After the flowchart is compiled, a waveform code based on the Python syntax structure is formed. A waveform flow Figure 1Generally, it includes at least a source component and a sink component. For a typical componentized implementation of a communication transmission waveform, it can be divided into a voice source component, a source coding component, a framing component, a channel coding component, a modulation component, and a radio frequency sink component.

[0036] Data streams include transmit data streams and receive data streams. Receive data streams refer to a continuous or burst data stream from the original sampled IO data of the RF port after being processed by a series of FPGA and CPU sides and finally received by the user. Transmit data streams refer to the continuous or burst data streams sent by the user, which are processed by the CPU and FPGA sides and finally sent to the IO data of the RF port. For bidirectional data streams, the receive data stream and the transmit data stream can be merged into one data stream for processing.

[0037] In one embodiment, Figure 1 As shown, a wireless communication system based on reconfigurable FPGA component development is provided, which may include a heterogeneous hardware platform, a software radio operating system, a componentized waveform, and a waveform operation interface, wherein the componentized waveform includes a CPU side, an FPGA side, and a radio frequency side. The CPU side is used to implement a complete waveform componentized flow graph, and the waveform componentized flow graph includes a component parameter control module, multiple CPU components, multiple FPGA agent components, and an FPGA interface driver component. Each CPU component includes a source and sink component, an audio codec component, a network protocol component, an IO interface driver component, and a low-rate signal processing component. Each FPGA agent component is used to perform parameter control on each component on the FPGA side.

[0038] The implementation logic on the FPGA side includes framework code and user code. The framework code is used to implement dynamic configuration of interface drivers and component connection relationships. User code is used to implement modulation and demodulation, extraction filtering, and up and down conversion. The framework code includes a CPU interface driver component, multiple flow control port modules, a static component connection control matrix module, a dynamic component connection control matrix module, and multiple RF driver modules. The CPU interface driver component is interconnected with the FPGA interface driver component through a high-speed serial bus. The user code includes multiple FPGA custom components preset to a BIT file for compilation.

[0039] The flow control port module is used to establish, start and stop the data flow, and to establish the flow buffer. The static component connection control matrix module is used to control the connection relationship between the FPGA custom components that are common constant components in each FPGA custom component through software instructions. The dynamic component connection control matrix module is used to control the connection relationship between the FPGA custom components that are independent variable components in each FPGA custom component through software instructions. Each RF driver module is used to realize the interface drive of the RF module on the RF side.

[0040] It can be understood that this embodiment proposes a componentized waveform development technology on the FPGA side in a software radio integrated development environment, which integrates traditional CPU componentization and FPGA componentization design based on the CPU and FPGA heterogeneous hardware platform, and can realize the rapid reconstruction of all or part of the components of the FPGA code.

[0041] Specifically, the reconfigurable FPGA component development also uses software radio technology design. The overall system architecture of the wireless communication system based on the reconfigurable FPGA component development can be as follows: Figure 1 As shown, it includes components such as heterogeneous hardware platform, software radio operating system, componentized waveform and waveform operation interface. Among them, the heterogeneous hardware platform is composed of the existing CPU subsystem, FPGA subsystem and RF subsystem (wideband RF transceiver) in this field, the software radio operating system is the existing basic general system software of software radio, and the waveform operation interface is an existing application interface provided to users to operate and display waveforms.

[0042] The improvement in this specification focuses on the design of the componentized waveform part, which is the core of the software radio complex waveform generation system in the wireless communication system based on the reconfigurable FPGA component development, and is composed of CPU components, FPGA components and RF components. Figure 2 As shown, the specific implementation scheme of reconfigurable FPGA componentization (waveform) development includes CPU side design, FPGA side design and RF side design.

[0043] The CPU side is designed to implement a complete waveform componentized flow graph. A typical flow graph includes several CPU components (such as CPU component 1 to CPU component N, N is a positive integer not less than 1), several FPGA proxy components (such as FPGA proxy component 1 to FPGA proxy component M, M is a positive integer not less than 1) and FPGA interface driver components, as well as component parameter control modules for the aforementioned components on the CPU side (such as CPU component parameter control 1 to CPU component parameter control L, L is a positive integer not less than 1). CPU components may include components with functions such as signal source and sink, audio codec, network protocol, IO interface driver, and other low-rate signal processing functions.

[0044] In some embodiments, the high-speed serial bus includes a PCIE bus, an Ethernet bus, or a USB bus. It is understood that the hardware modules on the CPU side and the FPGA side can be interconnected through various types of high-speed serial buses. For example, the hardware modules on the CPU side and the FPGA side can be interconnected using, but not limited to, high-speed serial buses such as PCIE / Ethernet / USB, thereby achieving high-speed transmission of data and control signals between the CPU side and the FPGA side to more effectively ensure communication efficiency.

[0045] Correspondingly, the CPU side also includes an FPGA interface driver component for providing the necessary FPGA interface driver functions. In addition, since the waveform operation interface is located on the CPU side, in order to enable the user to control the parameters of the components on the FPGA side, a corresponding FPGA agent component is set for each FPGA side component on the CPU side.

[0046] The implementation logic on the FPGA side includes framework code and user code, where the framework code includes: CPU interface driver component, several flow control port modules (such as flow control port 1 to RF driver P, P is a positive integer not less than 1), static component connection control matrix module (where static components refer to common waveform components such as up and down frequency conversion, extraction and filtering), dynamic component connection control matrix module (where dynamic components refer to specific waveform components such as FM, FSK modulation and demodulation) and several RF driver modules (such as RF driver 0 to RF driver R, R is a positive integer not less than 1). The framework code is used to realize the dynamic configuration of interface driver and component connection relationship. The user code includes several FPGA custom components (such as Figure 2 As shown in the dotted box part on the FPGA side, it includes FPGA component 1 to FPGA component K, and their corresponding component interface controls, where K is a positive integer not less than 1), which is used to realize existing high-speed signal processing functions such as modulation and demodulation, extraction filtering, and up and down conversion.

[0047] The CPU interface driver component is used to implement interface control and data interaction with the CPU side. The flow control port module is used to establish, start and stop data flows, and to establish flow buffers. The flow control port module can be used for each RF module on the RF side (such as Figure 2 The RF module 0 to RF module R in the FPGA creates a flow, so the maximum number of flow control ports P is the number of RF modules in the RF side system hardware form. The RF driver module on the FPGA side is used to implement the interface driver for the RF module on the RF side. Each RF module in the hardware form corresponds to an RF driver instance on the FPGA side.

[0048] In the user code, the FPGA component is a component that specifically implements signal processing inside the FPGA. Since the FPGA chips currently on the market do not have the ability to be reconstructed online, this embodiment presets the set of all FPGA components used by the supported waveforms into a BIT file corresponding to the FPGA chip for compilation. Specifically, assume that waveform 1 requires FPGA components A, B, and C; waveform 2 requires FPGA components A, D, and C; and waveform 3 requires FPGA components A, E, and C. Then a user application that supports waveforms 1, 2, and 3 needs to preset a total of 5 FPGA components, namely, FPGA components A, B, C, D, and E, into a BIT file corresponding to the FPGA chip for compilation. When the user starts waveform 1, the CPU side sends instructions to the FPGA side, and the FPGA side can automatically establish a data flow connection of FPGA components A→B→C; when the user switches waveform 1 to waveform 2, the CPU side sends instructions to the FPGA side, and the FPGA side can automatically disconnect the data flow of FPGA components A→B→C and reestablish the data flow of FPGA components A→D→C.

[0049] It can be seen that in the three waveforms 1, 2, and 3, FPGA components A and C are the common fixed components of the three waveforms, while FPGA components B, D, and E are the independent variable components of the three waveforms. In order to reduce the implementation overhead of FPGA componentization, all FPGA components used are divided into common fixed components and independent variable components. The connection relationship between the common fixed components is controlled by the static component connection control matrix, while the connection relationship between the independent variable components is controlled by the dynamic component connection control matrix. Since the dynamic connection relationship of the components is controlled by software instructions, the switching speed of the waveform can reach milliseconds, which is much higher than the seconds achieved by the existing direct update of the BIT file of the entire FPGA. The system code update rate can be increased by about 1,000 times.

[0050] The above-mentioned wireless communication system developed based on reconfigurable FPGA components can realize fast dynamic reconstruction of the waveform of FPGA components through the ingenious design of key technologies such as the connection control matrix between the FPGA proxy component on the CPU side and the static / dynamic component on the FPGA side. The waveform reconstruction speed can reach milliseconds, which is much higher than the current second level achieved by directly updating the BIT file code of the entire FPGA. The system's code update rate can be increased by about 1,000 times, which can well adapt to the rapidly changing spectrum conditions in modern emergency rescue scenarios, automatically perform high-speed real-time reconstruction and switching of waveforms, and effectively ensure the reliability of wireless communication.

[0051] In one embodiment, the FPGA custom component includes user logic, IO ports and component interface control. The component interface control includes a clock subsystem, a control channel and a data channel. The component interface control serves as the external interface of the FPGA custom component. The user logic is used to implement modulation and demodulation, extraction filtering and up and down conversion. The IO port is used to connect to the RF module on the RF side.

[0052] It can be understood that the logic diagram implemented by any FPGA component can be as follows Figure 3 As shown, it consists of user logic, IO ports and (component) interface control. As the external interface of each FPGA component, the interface control includes the clock subsystem, control channel and data channel, as well as the buffer control not shown. The code of the FPGA component is written in advance and can be reused. For each FPGA component, the user only needs to care about the code design of the user logic part, thereby minimizing the workload of code development.

[0053] The typical application process of a two-waveform application system can be as follows: With the help of the software radio integrated development environment, (1) FPGA-side development: jointly compile the framework code and all FPGA components used by each waveform in the application to generate a complete BIT file; (2) CPU-side development: based on the existing componentized waveform design concept, independently develop and store each waveform file that needs to be used, and develop the corresponding waveform application at the same time; (3) Start the waveform application, load waveform 1 (called the first waveform) and set the FPGA parameters of waveform 1, start waveform 1 and create a data stream connection for waveform 1; (4) FPGA parameters (such as modulation rate, filter coefficients, etc.) are passed to the framework code on the FPGA side, and the static / dynamic component connection control matrix establishes the connection of FPGA components A→B→C; (5) The waveform application can switch to waveform 2 (called the second waveform) in real time and set the FPGA parameters of waveform 2 according to the actual spectrum conditions in the emergency rescue scenario, start waveform 2 and create a data stream connection for waveform 2; (6) The FPGA parameters of waveform 2 are passed to the framework code on the FPGA side, and the static / dynamic component connection control matrix disconnects the connection of FPGA components A→B→C and re-establishes the connection of FPGA components A→D→C. It can be understood that the above-mentioned FPGA-side development and CPU-side development can be developed with the help of the software radio integrated development environment according to the actual application needs and the rules of the environment, as long as the components with the required functions can be obtained.

[0054] In some implementations, in order to better demonstrate the application implementation of the wireless communication system based on the reconfigurable FPGA component development, as shown in FIG. Figure 4As shown, it is assumed that a wireless communication network application system supports FM analog waveform and FSK digital waveform, wherein the FM analog waveform can be composed of a voice driving component, a voice coding component, a channel coding component, an FM modulation and demodulation component, a digital up-down frequency conversion component and an extraction interpolation filter component. Correspondingly, the FSK digital waveform is composed of a voice driving component, a voice coding component, a channel coding component, an FSK modulation and demodulation component, a digital up-down frequency conversion component and an extraction interpolation filter component. Among them, the voice driving component, the voice coding component and the channel coding component in the two waveforms are implemented on the CPU side; the FM / FSK modulation and demodulation component, the digital up-down frequency conversion component and the extraction interpolation filter component are implemented on the FPGA side. It can be seen that all the components on the CPU side can be reused, and the digital up-down frequency conversion component and the extraction interpolation filter component on the FPGA side can be reused as common unchanged components, and their connection relationship is controlled by the static component connection control matrix; while the FM / FSK modulation and demodulation component is a variable component of the waveform, and its connection relationship is controlled by the dynamic component connection control matrix.

[0055] The typical application process of the system can be as follows: With the help of the software radio integrated development environment, (1) FPGA side development: jointly compile the framework code on the FPGA side and the FM modulation and demodulation components, FSK modulation and demodulation components, digital up and down conversion components and extraction and interpolation filter components used in the waveform application to generate a complete BIT file; (2) CPU side development: independently develop FM analog waveform files and FSK digital waveform files based on the componentized waveform design concept, and develop the corresponding waveform application at the same time; (3) Start the waveform application, load the FM analog waveform and set the FPGA parameters of the FM analog waveform, start the FM analog waveform and create a data flow for the FM analog waveform. (4) The FPGA parameters of the FM analog waveform are passed to the framework code on the FPGA side, and the static / dynamic component connection control matrix establishes the connection of the FM modulation and demodulation component → digital up and down conversion component → extraction and interpolation filter component; (5) The waveform application switches to the FSK digital waveform in real time according to the actual spectrum conditions of the emergency rescue scenario, sets the FPGA parameters of the FSK digital waveform, starts the FSK digital waveform and creates a data stream connection for the FSK digital waveform; (6) The FPGA parameters of the FSK digital waveform are passed to the framework code on the FPGA side, and the static / dynamic component connection control matrix establishes the connection of the FSK modulation and demodulation component → digital up and down conversion component → extraction and interpolation filter component.

[0056] In one embodiment, Figure 5As shown, a wireless communication method based on reconfigurable FPGA component development is also provided, based on a wireless communication system based on reconfigurable FPGA component development, the wireless communication system includes a heterogeneous hardware platform, a software radio operating system, a componentized waveform and a waveform operation interface, and the componentized waveform includes a CPU side, an FPGA side and a radio frequency side. The CPU side is used to implement a complete waveform componentized flow graph, and the waveform componentized flow graph includes a component parameter control module, multiple CPU components, multiple FPGA agent components and an FPGA interface driver component. Each CPU component includes a source and sink component, an audio codec component, a network protocol component, an IO interface driver component and a low-rate signal processing component. Each FPGA agent component is used to control the parameters of each component on the FPGA side.

[0057] The implementation logic on the FPGA side includes framework code and user code. The framework code is used to realize dynamic configuration of interface driver and component connection relationship. The user code is used to realize modulation and demodulation, extraction filtering and up and down conversion. The framework code includes CPU interface driver component, multiple flow control port modules, static component connection control matrix module, dynamic component connection control matrix module and multiple RF driver modules. The CPU interface driver component is interconnected with the FPGA interface driver component through a high-speed serial bus. The user code includes multiple FPGA custom components preset into a BIT file for compilation.

[0058] The flow control port module is used to establish, start and stop the data flow, and to establish the flow buffer. The static component connection control matrix module is used to control the connection relationship between the FPGA custom components that are shared unchanging components in each FPGA custom component through software instructions. The dynamic component connection control matrix module is used to control the connection relationship between the FPGA custom components that are independent variable components in each FPGA custom component through software instructions. Each RF driver module is used to implement the interface drive of the RF module on the RF side.

[0059] The wireless communication method based on reconfigurable FPGA component development may include the following processing steps S10 to S20:

[0060] S10, using the software radio integrated development environment to develop on the FPGA side, jointly compile the framework code on the FPGA side and all FPGA components used by each waveform in the application to generate a complete BIT file;

[0061] S12, performing CPU-side development with the aid of a software radio integrated development environment to obtain various waveform files required to be used and corresponding waveform applications;

[0062] S14, start the waveform application, load the first waveform and set the FPGA parameters of the first waveform, start the first waveform and create a data stream connection for the first waveform;

[0063] S16, transferring the FPGA parameters of the first waveform to the framework code on the FPGA side, and establishing connections between the FPGA components corresponding to the first waveform through the static component connection control matrix and the dynamic component connection control matrix;

[0064] S18, switching to the second waveform in real time through the waveform application according to the actual spectrum condition in the emergency rescue scenario and setting the FPGA parameters of the second waveform, starting the second waveform and creating a data stream connection for the second waveform;

[0065] S20, transferring the FPGA parameters of the second waveform to the framework code on the FPGA side, and establishing connections between the FPGA components corresponding to the second waveform through the static component connection control matrix and the dynamic component connection control matrix.

[0066] The above-mentioned wireless communication method based on reconfigurable FPGA component development can realize fast dynamic reconstruction of the waveform of FPGA components through the ingenious design of key technologies such as the connection control matrix between the FPGA proxy component on the CPU side and the static / dynamic component on the FPGA side. The waveform reconstruction speed can reach milliseconds, which is much higher than the current second level achieved by directly updating the BIT file code of the entire FPGA. The system's code update rate can be increased by about 1,000 times, which can well adapt to the rapidly changing spectrum conditions in modern emergency rescue scenarios, automatically perform high-speed real-time reconstruction and switching of waveforms, and effectively ensure the reliability of wireless communication.

[0067] In one embodiment, the high-speed serial bus includes a PCIE bus, an Ethernet bus, or a USB bus.

[0068] In one embodiment, the FPGA custom component includes user logic, IO ports and component interface control. The component interface control includes a clock subsystem, a control channel and a data channel. The component interface control serves as the external interface of the FPGA custom component. The user logic is used to implement modulation and demodulation, extraction filtering and up and down conversion. The IO port is used to connect to the RF module on the RF side.

[0069] For the specific limitations on the wireless communication method based on reconfigurable FPGA component development, please refer to the above limitations on the wireless communication system based on reconfigurable FPGA component development, which will not be repeated here.

[0070] It should be understood that although Figure 5The steps in the flowchart are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Moreover, Figure 5 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0071] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0072] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A wireless communication system based on reconfigurable FPGA component development, characterized in that: It includes a heterogeneous hardware platform, a software radio operating system, a componentized waveform, and a waveform operation interface, wherein the componentized waveform includes a CPU side, an FPGA side, and a radio frequency side; The CPU side is used to implement a complete waveform componentized flow graph, which includes a component parameter control module, multiple CPU components, multiple FPGA proxy components and an FPGA interface driver component. Each of the CPU components includes a source and sink component, an audio codec component, a network protocol component, an IO interface driver component and a low-rate signal processing component. Each of the FPGA proxy components is used to perform parameter control on each component on the FPGA side. The implementation logic on the FPGA side includes a framework code and a user code. The framework code is used to implement dynamic configuration of interface drivers and component connection relationships. The user code is used to implement modulation and demodulation, extraction filtering, and up and down frequency conversion. The framework code includes a CPU interface driver component, multiple flow control port modules, a static component connection control matrix module, a dynamic component connection control matrix module, and multiple radio frequency driver modules. The CPU interface driver component is interconnected with the FPGA interface driver component through a high-speed serial bus. The user code includes multiple FPGA custom components that are preset to a BIT file for compilation; The flow control port module is used to establish, start and stop the data flow, and to establish a flow buffer. The static component connection control matrix module is used to control the connection relationship between the FPGA custom components that are common unchanged components in each of the FPGA custom components through software instructions. The dynamic component connection control matrix module is used to control the connection relationship between the FPGA custom components that are independent variable components in each of the FPGA custom components through software instructions. Each of the RF driver modules is used to implement interface drive for the RF module on the RF side.

2. The wireless communication system based on reconfigurable FPGA component development according to claim 1, characterized in that: The high-speed serial bus includes a PCIE bus, an Ethernet bus or a USB bus.

3. The wireless communication system based on reconfigurable FPGA component development according to claim 1 or 2, characterized in that: The FPGA custom component includes user logic, IO ports and component interface control. The component interface control includes a clock subsystem, a control channel and a data channel. The component interface control serves as the external interface of the FPGA custom component. The user logic is used to realize modulation and demodulation, extraction filtering and up and down conversion. The IO port is used to connect the RF module on the RF side.

4. A wireless communication method based on reconfigurable FPGA component development, characterized in that: A wireless communication system based on reconfigurable FPGA component development, the wireless communication system includes a heterogeneous hardware platform, a software radio operating system, a componentized waveform and a waveform operation interface, the componentized waveform includes a CPU side, an FPGA side and a radio frequency side; The CPU side is used to implement a complete waveform componentized flow graph, which includes a component parameter control module, multiple CPU components, multiple FPGA proxy components and an FPGA interface driver component. Each of the CPU components includes a source and sink component, an audio codec component, a network protocol component, an IO interface driver component and a low-rate signal processing component. Each of the FPGA proxy components is used to perform parameter control on each component on the FPGA side. The implementation logic on the FPGA side includes a framework code and a user code. The framework code is used to implement dynamic configuration of interface drivers and component connection relationships. The user code is used to implement modulation and demodulation, extraction filtering, and up and down frequency conversion. The framework code includes a CPU interface driver component, multiple flow control port modules, a static component connection control matrix module, a dynamic component connection control matrix module, and multiple radio frequency driver modules. The CPU interface driver component is interconnected with the FPGA interface driver component through a high-speed serial bus. The user code includes multiple FPGA custom components that are preset to a BIT file for compilation; The flow control port module is used to establish, start and stop the data flow, and to establish the flow buffer. The static component connection control matrix module is used to control the connection relationship between the FPGA custom components that are common unchanged components in each of the FPGA custom components through software instructions. The dynamic component connection control matrix module is used to control the connection relationship between the FPGA custom components that are independent variable components in each of the FPGA custom components through software instructions. Each of the RF driver modules is used to realize the interface drive of the RF module on the RF side. The wireless communication method based on reconfigurable FPGA component development comprises the following steps: With the help of software radio integrated development environment, the FPGA side development is carried out, and the framework code on the FPGA side and all FPGA components used by each waveform in the application are jointly compiled to generate a complete BIT file; Use software radio integrated development environment to develop on CPU side and obtain the waveform files and corresponding waveform applications needed; Starting the waveform application, loading the first waveform and setting FPGA parameters of the first waveform, starting the first waveform and creating a data stream connection for the first waveform; Transferring the FPGA parameters of the first waveform to the framework code on the FPGA side, and establishing connections between the FPGA components corresponding to the first waveform through the static component connection control matrix and the dynamic component connection control matrix; According to the actual spectrum conditions in the emergency rescue scenario, the waveform application is used to switch to the second waveform in real time and set the FPGA parameters of the second waveform, start the second waveform and create a data stream connection for the second waveform; The FPGA parameters of the second waveform are transferred to the framework code on the FPGA side, and connections between the FPGA components corresponding to the second waveform are established through the static component connection control matrix and the dynamic component connection control matrix.

5. The wireless communication method based on reconfigurable FPGA component development according to claim 4 is characterized in that: The high-speed serial bus includes a PCIE bus, an Ethernet bus or a USB bus.

6. The wireless communication method based on reconfigurable FPGA component development according to claim 4 or 5, characterized in that: The FPGA custom component includes user logic, IO ports and component interface control. The component interface control includes a clock subsystem, a control channel and a data channel. The component interface control serves as the external interface of the FPGA custom component. The user logic is used to realize modulation and demodulation, extraction filtering and up and down conversion. The IO port is used to connect the RF module on the RF side.

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