Electronic device and electronic equipment

Abstract

The embodiment of the invention discloses an electronic device and electronic equipment, relates to the field of welding spot temperature cycle reliability, and solves the problem of the existing welding spot temperature cycle reliability. The electronic device comprises a substrate, a plurality of bonding pads and a buffer structure. Wherein the substrate is provided with a first surface; the plurality of pads are disposed on the first surface of the substrate. The substrate is internally provided with a plurality of conductive holes, and the plurality of conductive holes and the plurality of bonding pads are arranged correspondingly and are electrically connected with each other. The buffer structure is arranged around the peripheries of the plurality of conductive holes. And the buffer structure is located in partial areas, close to the bonding pads, of the conductive holes. The buffer structure can absorb the pulling force of the electronic device circuit board to the welding structure on the bonding pad, the shearing force borne by the welding structure between two electronic devices due to the mismatching of the thermal expansion coefficients of the two electronic devices is reduced, the shearing deformation of the welding structure is avoided, and the temperature cycle reliability of the welding spot is improved.

Description

Technical Field

[0001] The present application relates to the technical field of solder joint temperature cycle reliability, and in particular to an electronic device and an electronic device. Background Art

[0002] With the rapid evolution of application specific integrated circuit (ASIC) chip size, materials and power, the fatigue reliability of solder joints between ASIC chips and motherboards (such as printed circuit boards) has become the main reason for the deterioration of all influencing factors.

[0003] The solder balls between the motherboard and the packaging substrate of the ASIC chip / chip module are subject to temperature changes during operation. Due to the large packaging size of large-size chips, the coefficient of thermal expansion (CTE) of the motherboard and the packaging substrate does not match, resulting in shear deformation of the solder balls due to the pulling of the motherboard and the packaging substrate. In addition, as the working time of the motherboard and the packaging substrate increases, the damage to the solder balls continues to accumulate until fatigue damage occurs, resulting in poor fatigue reliability of the solder joints. Summary of the invention

[0004] The embodiments of the present application provide an electronic device and an electronic device, which improve the problem of temperature cycle reliability of existing solder joints.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides an electronic device, which can be various electronic products, such as a circuit board, a packaging substrate, a transfer board or an intermediate board. The electronic device includes a substrate, a plurality of pads and a buffer structure. Among them, the substrate has a first surface. A plurality of pads are arranged on the first surface of the substrate. A plurality of conductive holes are provided in the substrate, and the plurality of conductive holes are respectively arranged opposite to the plurality of pads. Moreover, the relatively arranged conductive holes and the pads are electrically connected to each other. If a connecting circuit is provided in the substrate, the plurality of conductive holes can be electrically connected to the connecting circuit. The above-mentioned buffer structure is arranged around the periphery of the plurality of conductive holes. Moreover, the buffer structure is located on the periphery of a partial area of ​​the conductive hole close to the pad.

[0007] Take the electronic device of the embodiment of the present application as a circuit board, and the circuit board and the packaging substrate are electrically connected by welding as an example. Compared with the prior art, a buffer structure is provided on the periphery of a plurality of conductive holes connected to a plurality of pads in the circuit board of the embodiment of the present application, and the buffer structure is located in a partial area of ​​the conductive holes close to the pads. When the circuit board and the packaging substrate are working, the heat generated by the chip on the packaging substrate, other high-power electronic devices on the circuit board, etc., causes the packaging substrate and the circuit board to deform. The buffer structure can absorb the pulling force of the circuit board on the plurality of conductive holes, thereby reducing the pulling force of the deformation of the circuit board on the pads connected to the plurality of conductive holes and the welding structure on the pads. Therefore, the buffer structure can reduce the shear force on the welding structure (such as solder balls) between the packaging substrate and the circuit board, making it difficult for the welding structure to produce shear deformation. Thereby, the accumulation of shear deformation of the welding structure is avoided to produce fatigue damage, so that the fatigue reliability of the solder joint is higher, and the temperature cycle reliability of the solder joint is improved.

[0008] Based on the above, in some embodiments of the present application, the buffer structure is a buffer material layer. That is, the buffer material layer is arranged in the substrate, and the plurality of pads are arranged on the outer surface of the buffer material. The outer surface of the buffer material layer is the first surface. The buffer material layer can directly replace the hierarchical structure in the substrate (such as the outermost insulating layer of the circuit board), and the manufacturing process is relatively simple.

[0009] In addition, in some other embodiments of the present application, the buffer structure includes a buffer material area, and the outer surface of the buffer material area forms a partial area of ​​the first surface. The buffer material has a small coverage area and a low material cost.

[0010] In some embodiments, the buffer structure includes only one buffer material area, and the buffer material area surrounds the outer periphery of the plurality of conductive holes.

[0011] In other embodiments, the buffer structure includes a plurality of buffer material areas, and the plurality of buffer material areas can be respectively wrapped around the peripheries of the plurality of conductive holes. For example, the plurality of buffer material areas are arranged around the peripheries of the plurality of conductive holes in a one-to-one correspondence. Alternatively, the number of buffer material areas is less than the number of conductive holes. That is, the plurality of buffer materials include some first buffer material areas, and any first buffer material area is arranged around the peripheries of two or more conductive holes.

[0012] In order to enable the buffer structure to absorb the shear force on the solder ball, the elastic modulus of the buffer structure can be designed to be low. Therefore, in some embodiments of the present application, the elastic modulus of the buffer structure is below 2 GPa to ensure that the buffer structure can absorb the pulling force of the circuit board deformation on the conductive hole.

[0013] Therefore, in some embodiments of the present application, the buffer structure may be made of polytetrafluoroethylene, which has the advantages of heat resistance, cold resistance, corrosion resistance, and high temperature resistance.

[0014] The buffer structure in the embodiment of the present application can be applied between two electronic devices that are welded to each other. Therefore, in some embodiments of the present application, the above-mentioned two electronic devices that are welded to each other are a packaging substrate and a chip, respectively. The chip is welded on the packaging substrate. The packaging substrate can adopt the structure of the electronic device described in the above embodiment. That is, the surface of the packaging substrate close to the chip is the above-mentioned first surface, and the first surface is provided with a plurality of pads. The plurality of pads are connected to the pins of the chip by welding. In addition, a plurality of conductive holes are provided in the packaging substrate, and the plurality of conductive holes are electrically connected to the plurality of pads, respectively. The buffer structure is arranged on the periphery of the plurality of conductive holes. In addition, the buffer structure is located on the periphery of the conductive holes close to the pads. Thus, the welding structure between the packaging substrate and the chip is not prone to shear deformation.

[0015] In some other embodiments of the present application, the two electronic devices welded to each other are respectively a package substrate and a circuit board, and the circuit board can adopt the structure of the electronic device described in the above embodiment. That is, the circuit board includes multiple insulating layers and multiple conductive layers, and the multiple insulating layers are staggered and stacked with the multiple conductive layers. That is, a conductive layer is provided between any two insulating layers. Among the multiple insulating layers, the insulating layer closest to the package substrate is the first insulating layer. The surface of the first insulating layer close to the package substrate is the above-mentioned first surface. A plurality of first pads for welding with the package substrate are provided on the first surface. A plurality of second pads are respectively provided at positions corresponding to the plurality of first pads on the package substrate. The plurality of second pads can be welded with the plurality of first pads respectively. In addition, a plurality of first conductive holes are provided in the first insulating layer, and the plurality of first conductive holes are electrically connected to the plurality of first pads respectively. The first insulating layer can be a buffer material layer. Alternatively, one or more buffer material areas are provided in the first insulating layer, and all buffer materials can be arranged around the periphery of the plurality of first conductive holes. The buffer material layer or buffer material area can make the welding structure between the circuit board and the package substrate less prone to shear deformation, thereby improving the temperature cycle reliability of the welding structure.

[0016] Moreover, a chip can also be welded on the above-mentioned packaging substrate. Therefore, the packaging substrate can also adopt the structure of the electronic device described in the above-mentioned embodiment. That is, a plurality of third pads are provided on the surface of the packaging substrate close to the chip, and the plurality of third pads are connected to the pins of the chip by welding. Moreover, a plurality of second conductive holes connected to the plurality of third pads are provided in the packaging substrate. The buffer structure is arranged on the periphery of the plurality of second conductive holes and is located in a partial area close to the plurality of third pads. Thus, the welding structure between the packaging substrate and the chip is also not prone to shear deformation. The fatigue reliability of all solder joints of the circuit board assembly composed of the circuit board, the packaging substrate and the chip is high, which improves the temperature cycle reliability of all solder joints.

[0017] In addition, the above-mentioned buffer structure can also be set on the surface of the packaging substrate close to the circuit board. That is, a plurality of third conductive holes are also provided in the packaging substrate, and the plurality of third conductive holes are electrically connected to the plurality of second pads respectively. The buffer structure is arranged on the periphery of the plurality of third conductive holes and is located in a partial area close to the plurality of second pads. Thus, the welding structure between the circuit board and the packaging substrate is further made less prone to shear deformation, and the temperature cycle reliability of the welding structure is further improved.

[0018] In a second aspect, an embodiment of the present application provides an electronic device, which includes a controller and the electronic device described in the above embodiment. The controller is electrically connected to the electronic device. The electronic device can be a device with a large-size chip such as a hub, a bridge, a switch, a router, a gateway, a repeater, a multiplexer, a modulator, and a server. Since the electronic device in the electronic device of the embodiment of the present application has the same structure as the electronic device described in the above embodiment, both can solve the same technical problems and obtain the same technical effects, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to illustrate the technical solution of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be described below.

[0020] Figure 1 This is a three-dimensional diagram of an electronic device in an embodiment of the present application, which is a switch;

[0021] Figure 2 This is a schematic diagram of the structure of a circuit board assembly in a switch according to an embodiment of the present application;

[0022] Figure 3 This is a schematic diagram of the chip packaging structure in the switch according to the embodiment of the present application;

[0023] Figure 4 This is a three-dimensional structural diagram of an electronic device having a buffer material layer according to an embodiment of the present application;

[0024] Figure 5It is a cross-sectional schematic diagram of an electronic device having a buffer material layer according to an embodiment of the present application;

[0025] Figure 6 A three-dimensional structural diagram of an electronic device having a buffer material area according to an embodiment of the present application;

[0026] Figure 7 A cross-sectional schematic diagram of welding an electronic device having multiple buffer material areas and a packaging substrate according to an embodiment of the present application;

[0027] Figure 8 A three-dimensional structural diagram of an electronic device having two buffer material areas according to an embodiment of the present application;

[0028] Fig. 9 This is a three-dimensional structural diagram of an electronic device having three buffer material areas according to an embodiment of the present application;

[0029] Fig.10 is a schematic cross-sectional view of a circuit board with a buffer material layer according to Example 1;

[0030] Fig.11 is a schematic cross-sectional view of a circuit board having multiple buffer material areas according to Example 1;

[0031] Fig.12 is a cross-sectional schematic diagram of a circuit board in the related art;

[0032] Fig.13 for Fig.12 The temperature cycle damage simulation result diagram of the solder balls between the circuit board and the package substrate;

[0033] Fig.14 for Fig.10 The temperature cycle damage simulation result diagram of the solder balls between the circuit board and the package substrate;

[0034] Fig.15 for Fig.11 The temperature cycle damage simulation result diagram of the solder balls between the circuit board and the package substrate;

[0035] Fig.16 is a cross-sectional schematic diagram of a packaging substrate with a buffer material layer according to Example 2;

[0036] Fig.17 is a cross-sectional schematic diagram of a package substrate having multiple buffer material areas according to Example 2;

[0037] Fig.18 is a schematic cross-sectional view of a package substrate with a buffer material layer according to Example 3;

[0038] Fig.19 Schematic cross-sectional view of a packaging substrate having multiple buffer material areas according to Example 3.

[0039] Figure Number:

[0040] 1000-switch; 100-housing; 200-circuit board assembly; 10-mainboard; 101-metal layer; 101a-first metal layer; 102-insulating layer; 102a-first insulating layer; 103-solder resist layer; 20-chip packaging structure; 21-packaging substrate; 211-core board; 2111-first conductive hole; 211a, 1101S, 1101-first surface; 1102S, 211b-second surface; 212-first build-up board; 212a-third surface; 2121-second connecting circuit; 2122-first solder pad; 2123-second conductive hole; 213-second build-up board ;213a-fourth surface;2131-third connecting circuit;2132-second solder pad;2133-third conductive hole;214-first buffer structure;131,131S,214a-buffer material layer;132,132S,214b-buffer material area;215-second buffer structure;215a-buffer material layer;215b-buffer material area;216-first solder resist layer;217-second solder resist layer;22-chip;23-plastic encapsulation material;1-circuit board;1S-electronic device;11S-substrate;111S,111-conductive hole;12S,12-solder pad;13S-buffer structure. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0042] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0043] In addition, in the present application, directional terms such as "up", "down", "left", "right", "horizontal" and "vertical" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to the changes in the orientation of the components in the drawings.

[0044] In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can refer to the connection of mechanical structure or physical structure. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be directly connected or indirectly connected through an intermediate medium. It can also be understood as the physical contact and electrical conduction of components, and it can also be understood as the form in which different components in the circuit structure are connected through physical lines such as PCB copper foil or wires that can transmit electrical signals.

[0045] The embodiment of the present application includes an electronic device, which may be a hub, a bridge, a switch, a router, a gateway, a repeater, a multiplexer, a modem, a server, or other device with a large-size chip. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device. For the convenience of explanation, the following is an example of the electronic device. Figure 1 The switch shown is used as an example for illustration.

[0046] Figure 1 The electronic device of the embodiment of the present application is a three-dimensional diagram of a switch. Figure 1 and Figure 2 , the switch 1000 includes a housing 100, a controller (not shown in the figure) and a circuit board assembly 200. The controller and the circuit board assembly 200 are both arranged in the housing. The circuit board assembly 200 includes a mainboard 10 and a chip packaging structure 20, and the chip packaging structure 20 is arranged on the mainboard 10. For example, the chip packaging structure 20 can be electrically connected to the mainboard 10 through packaging methods such as quad flat no-leads package (QFN), land grid array package (LGA), ball grid array package (BGA), etc. That is, the chip packaging structure 20 is connected to the mainboard 10 by welding. Thereby, the chip packaging structure 20 can realize signal transmission with other electronic devices (such as chips, chip stacking structures, resistors, capacitors, etc.) on the mainboard 10.

[0047] It should be noted that the mainboard 10 may be a printed circuit board (PCB). The present application does not limit the number of chip packaging structures 20 on the mainboard 10. The chip packaging structures 20 may be one, two, or more than two. The electronic devices on the mainboard 10 may also be one, two, or more than two.

[0048] The structure of the chip packaging structure 20 is described below by way of example. Figure 3The chip packaging structure 20 may include a packaging substrate (SUB) 21, a chip 22 disposed on the packaging substrate 21, and a molding material 23 for molding the chip 22. The packaging substrate 21 is electrically connected to the mainboard 10. The present application does not limit the number of chips 22 packaged in the chip packaging structure 20, which may be one, two, or more than two.

[0049] The size of the chip 22 in the switch 1000 is relatively large, so the size of the chip packaging structure 20 is also relatively large. Therefore, during the operation of the switch 1000, the mainboard 10 and the chip packaging structure 20 will be deformed by the load changes caused by heating and cooling. In addition, since the thermal expansion coefficient of the mainboard 10 is different from that of the packaging substrate 21, the deformation amount of the mainboard 10 and the packaging substrate 21 is different, so that the welding structure (such as the solder ball) between the mainboard 10 and the packaging substrate 21 will be pulled by the mainboard 10 and the packaging substrate 21 and produce shear deformation. In addition, as the working time increases, the damage on the welding structure continues to accumulate until fatigue damage occurs, resulting in poor fatigue reliability of the solder joint and poor temperature cycle reliability of the solder joint.

[0050] Therefore, in order to solve this problem, the embodiment of the present application provides an electronic device with an improved structure. The electronic device can be the above-mentioned circuit board or the above-mentioned packaging substrate 21, and can also be an intermediate board or a transfer board, etc., which is not limited by the present application. The electronic device can be any one of the two electronic devices connected by welding. Figure 4 The electronic device 1S includes a substrate 11S and a plurality of pads 12S. The substrate 11S has a first surface 1101S and a second surface 1102S that are arranged opposite to each other. The plurality of pads 12S are arranged on the first surface 1101S. The substrate 11S is provided with a plurality of pads 12S. Figure 5 The conductive holes 111S shown in the figure are respectively disposed below the plurality of pads 12S (eg Figure 5 The substrate 11S is also provided with a buffer structure 13S, which is arranged around the outer periphery of the plurality of conductive holes 111S and located in a portion of the plurality of conductive holes 111S close to the plurality of pads 12S.

[0051] Take the above-mentioned electronic device 1S as a circuit board, and the circuit board is connected to the package substrate 21 as an example. Compared with the prior art, the outer periphery of the plurality of conductive holes 111S connected to the plurality of pads 12S in the circuit board of the present application embodiment is provided with a buffer structure 13S, and the buffer structure 13S is located in a partial area of ​​the plurality of conductive holes 111S close to the plurality of pads 12S. Figure 6 and Figure 7When the electronic device 1S and the packaging substrate 21 are working, the heat generated by the chip 22 on the packaging substrate 21 and other high-power electronic devices on the circuit board will cause the packaging substrate 21 and the circuit board to deform. Since the thermal expansion coefficient of the circuit board does not match the thermal expansion coefficient of the packaging substrate 21, the deformation of the circuit board is different from the deformation of the packaging substrate 21. The buffer structure 13S can absorb the pulling force of the circuit board on the multiple conductive holes 111S, thereby reducing the pulling force of the circuit board deformation on the pads 12S connected to the multiple conductive holes 111S and the welding structure on the pads 12S. Therefore, the buffer structure 13S can reduce the welding structure (such as Figure 7 The shear force on the solder ball (shown in FIG. 1 ) makes it difficult for the solder structure to produce shear deformation. Thus, the shear deformation accumulation of the solder structure is avoided to produce fatigue damage, so that the fatigue reliability of the solder joint is higher and the temperature cycle reliability of the solder joint is improved.

[0052] Based on the above, in some embodiments of the present application, the buffer structure 13S can be as follows: Figure 4 and Figure 5 The buffer material layer 131S shown. The surface of the buffer material layer 131S in contact with the plurality of pads 12S is the first surface 1101S. The buffer material layer 131S can directly replace the hierarchical structure in the substrate (such as the outermost insulating layer of the circuit board), and the manufacturing process is relatively simple.

[0053] Alternatively, the buffer structure 13S may also only constitute a partial area on the first surface 1101S. Figure 6 and Figure 7 The buffer structure 13S includes a buffer material area 132S, which can surround the outer periphery of the plurality of conductive holes 111S and constitute a partial area on the first surface 1101S. The buffer structure 13S has a small coverage area and a low material cost.

[0054] It should be noted that, depending on the distribution positions of the plurality of pads 12S on the first surface 1101S, the buffer structure 13S may include only one buffer material area 132S or may include multiple buffer material areas 132S. If the plurality of pads 12S are concentrated in one area of ​​the first surface 1101S and the distance between two adjacent pads 132S is small, the buffer structure 13S may include only one buffer material area 132S. Figure 6 As shown in FIG. 1 , the buffer material area 132S surrounds the outer periphery of the plurality of conductive holes 111S. If the plurality of pads 12S are dispersedly disposed in a plurality of regions of the first surface 1101S, such as Figure 7 , Figure 8 and Fig. 9As shown, the buffer structure 13S may include a plurality of buffer material regions 132S, and the plurality of buffer material regions 132S respectively surround the peripheries of the plurality of conductive holes 111S. Figure 7 As shown in FIG. 1 , a buffer material region 132S only surrounds the periphery of a conductive hole 111S. Figure 8 and Fig. 9 As shown, a buffer material area 132S may surround the periphery of a plurality of conductive holes 111S located in the same area, but the present application does not limit this.

[0055] Furthermore, in order to enable the buffer structure 13S to absorb the shear force on the welding structure, the elastic modulus of the buffer structure 13S needs to be designed to be low, so that when other areas of the substrate 11S are greatly deformed, the buffer structure 13S will not be greatly deformed and pull the welding structure. Therefore, in some embodiments of the present application, the elastic modulus of the buffer structure 13S is less than 2 GPa.

[0056] Based on this, in some embodiments of the present application, the buffer structure 13S may be made of polytetrafluoroethylene (PTFE), which has the advantages of heat resistance, cold resistance, corrosion resistance, and high temperature resistance.

[0057] The electronic device 1S described above has many application objects, which will be described below with reference to specific examples.

[0058] Example 1

[0059] The electronic device 1S in this example is a circuit board. Fig.10 The circuit board 1 includes multiple metal layers 101 and multiple insulating layers 102, and the multiple metal layers 101 and the multiple insulating layers 102 are staggered and stacked. That is, a metal layer 101 is provided between every two insulating layers 102. For example, the metal layer 101 can be made of copper, and the insulating layer 102 can be made of resin. Taking the connection between the circuit board 1 and the package substrate 21 as an example, the insulating layer 102 closest to the package substrate 21 among the multiple insulating layers 102 is the first insulating layer 102a. The top surface of the first insulating layer 102a (such as Fig.10The bottom surface is the first surface 1101, and a plurality of pads 12 are arranged on the first surface 1101. A plurality of conductive holes 111 are arranged in the first insulating layer 102a, and the plurality of conductive holes 111 correspond to the plurality of pads 12 respectively. Moreover, the corresponding conductive holes 111 are electrically connected to the pads 12. A metal layer 101 adjacent to the first insulating layer 102a is the first metal layer 101a. The first metal layer 101a may have a first connection circuit (not shown in the figure). The plurality of conductive holes 111 are connected to the first connection circuit on the first metal layer 101a. In addition, the area on the first surface 1101 of the first insulating layer 102a where the pads 12 are not arranged is also covered with a solder resist layer 103.

[0060] And, in some embodiments, as Fig.10 As shown, the first insulating layer 102a can be made directly of buffer material, that is, the first insulating layer 102a is a buffer material layer 131. Therefore, the other structures in the circuit board 1 except the solder resist layer 103 are the substrate 11S in the above-mentioned electronic device 1S.

[0061] When the circuit board 1 and the packaging substrate 21 are working, the packaging substrate 21 and the circuit board 1 are subjected to temperature loads and generate deformation forces. The buffer material layer 131 can absorb the pulling force of the circuit board deformation on the multiple conductive holes 111, thereby reducing the pulling force of the circuit board deformation on the multiple pads 12 connected to the multiple conductive holes 111 and the welding structures on the multiple pads 12. The buffer material layer 131 reduces the shear force on the welding structure between the packaging substrate 21 and the circuit board 1, making it difficult for the welding structure to produce shear deformation. Thus, the accumulation of shear deformation of the welding structure to produce fatigue damage is avoided, so that the fatigue reliability of the solder joint is higher, and the temperature cycle reliability of the solder joint is improved. In addition, the buffer material layer 131 is easier to manufacture.

[0062] In other embodiments, Fig.11 As shown, a buffer material area 132 is provided in the first insulating layer 102a, and the buffer material area 132 only covers the peripheral area of ​​the plurality of conductive holes 111, forming a partial surface of the first surface 1101. Therefore, the other structures in the circuit board 1 except the solder resist layer 103 are the substrate 11S in the electronic device 1S. The buffer material area 132 can also improve the temperature cycle reliability of the solder joint, and the material cost is low.

[0063] Fig.12 The structure of the circuit board 1 without the buffer material layer 131 or the buffer material area 132 is shown. Fig.13 Shows Fig.12 The simulation result of the thermal cycle damage of the solder ball between the circuit board 1 and the package substrate 21 is shown. The thermal cycle damage amount of the solder ball is 5.26×10-3 J / mm3. Fig.14 Shows Fig.10The simulation result of temperature cycle damage of the solder ball between the circuit board 1 and the package substrate 21 is shown in FIG. The temperature cycle damage of the solder ball is 1.03×10-3 J / mm3. Therefore, the temperature cycle damage of the solder ball between the circuit board 1 and the package substrate 21 with the buffer material layer 131 is significantly reduced.

[0064] Fig.15 Shows Fig.11 The simulation results of temperature cycle damage of solder balls between circuit board 1 and package substrate 21 are shown in Figure 1. The temperature cycle damage of the solder balls is 0.84×10-3J / mm3. Therefore, the temperature cycle damage of solder balls between the circuit board with buffer material area 132 and package substrate 21 is also significantly reduced. Moreover, the temperature cycle reliability of solder balls between the circuit board with buffer material area 132 and package substrate 21 is better than the temperature cycle reliability of solder balls between the circuit board with buffer material layer 131 and package substrate 21.

[0065] Example 2

[0066] The electronic device 1S of this example is a package substrate 21. Fig.16 The package substrate 21 is a core substrate, which includes a core board 211, a first laminate board 212 and a second laminate board 213. The core board 211 has a first surface 211a and a second surface 211b arranged opposite to each other. The first laminate board 212 is covered on the first surface 211a, and the second laminate board 213 is covered on the second surface 211b. A second connection circuit 2121 is formed in the first laminate board 212. A third connection circuit 2131 is formed in the second laminate board 213. A plurality of first conductive holes 2111 arranged at intervals are formed in the core board 211. The plurality of first conductive holes 2111 penetrate the core board 211 and electrically connect the second connection circuit 2121 on the first laminate board 212 with the third connection circuit 2131 on the second laminate board 213. The surface of the first laminate board 212 away from the core board 211 is the third surface 212a. The third surface 212a is provided with a plurality of first pads 2122 distributed at intervals, and the plurality of first pads 2122 are respectively used to be connected to the plurality of pins of the chip 22 by welding. The first build-up board 212 is also provided with a plurality of second conductive holes 2123, and the plurality of second conductive holes 2123 are respectively electrically connected to the plurality of first pads 2122. The first build-up board 212 is also provided with a first buffer structure 214, and the first buffer structure 214 is arranged around the periphery of the plurality of second conductive holes 2123. Moreover, the first buffer structure 214 is located in a partial area of ​​the second conductive holes 2123 close to the first pads 2122. In addition, the core board 211, the first build-up board 212 and the second build-up board 213 constitute the substrate 11S in the above-mentioned electronic device 1S.

[0067] The first buffer structure 214 can absorb the pulling force of the multiple second conductive holes 2123 caused by the deformation of the package substrate 21 due to the temperature load, thereby reducing the pulling force of the multiple first pads 2122 connected to the multiple second conductive holes 2123 and the welding structure on the multiple first pads 2122 caused by the deformation of the package substrate 21. The first buffer structure 214 reduces the shear force on the welding structure between the package substrate 21 and the chip 22, making it difficult for the welding structure to produce shear deformation. Thus, the accumulation of shear deformation of the welding structure to produce fatigue damage is avoided, so that the fatigue reliability of the solder joint is higher, and the temperature cycle reliability of the solder joint is improved.

[0068] It should be noted that the area on the third surface 212 a of the first build-up board 212 where the plurality of first pads 2122 are not provided may also be covered with the first solder resist layer 216 .

[0069] In some embodiments, Fig.16 As shown, the first buffer structure 214 may be a buffer material layer 214a. The buffer material layer 214a is easy to manufacture.

[0070] In some other embodiments, the first buffer structure 214 includes a buffer material area 214b, or a plurality of buffer material areas 214b. Fig.17 The buffer material area 214b is shown. The buffer material area 214b is only disposed at the periphery of the plurality of second conductive holes 2123. Moreover, the buffer material area 214b is located in a portion of the plurality of second conductive holes 2123 close to the plurality of first pads 2122 (such as the upper end portion). The material cost of the buffer material area 214b is relatively low.

[0071] Example 3

[0072] The electronic device 1S of this example is also a packaging substrate 21. The structure of the packaging substrate 21 is similar to that of Example 2. The difference is that Fig.18 , the surface of the second laminate board 213 of the package substrate 21 away from the core board 211 is the fourth surface 213a. A plurality of second solder pads 2132 are arranged on the fourth surface 213a, and the plurality of second solder pads 2132 are respectively used to be connected with the plurality of solder pads 12 on the circuit board 1 by welding. A plurality of third conductive holes 2133 are also arranged in the second laminate board 213, and the plurality of third conductive holes 2133 are respectively electrically connected with the plurality of second solder pads 2132. Moreover, the plurality of third conductive holes 2133 are electrically connected with the third connection circuit 2131. A second buffer structure 215 is also arranged in the second laminate board 213, and the second buffer structure 215 is arranged around the periphery of the plurality of third conductive holes 2133. Moreover, the second buffer structure 215 is located in a partial area of ​​the third conductive holes 2133 close to the second solder pads 2132.

[0073] It should be noted that the area on the fourth surface 213 a of the second build-up board 213 where the plurality of second pads 2132 are not provided is also covered with the second solder resist layer 217 .

[0074] In some embodiments, Fig.18 As shown, the second buffer structure 215 can be a buffer material layer 215a. The buffer material layer 215a is easy to manufacture.

[0075] In other embodiments, the second buffer structure 215 includes a buffer material area 215b, or a plurality of buffer material areas 215b. Fig.19 The buffer material area 215b is shown. The buffer material area 215b is only arranged at the periphery of the plurality of third conductive holes 2133. Moreover, the buffer material area 215b is located in a part of the third conductive hole 2133 close to the second pad 2132 (such as the lower end of the third conductive hole 2133). The material cost of the buffer material area 215b is relatively low.

[0076] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An electronic device, characterized in that: include: A substrate having a first surface and a plurality of conductive holes disposed therein; A plurality of pads, the plurality of pads being disposed on the first surface of the substrate and being electrically connected to the plurality of conductive holes respectively; A buffer structure is disposed around the periphery of the plurality of conductive holes and is located in a partial area of ​​the conductive holes close to the pad.

2. The electronic device according to claim 1, characterized in that The buffer structure is a buffer material layer, and a surface of the buffer material layer in contact with the plurality of pads is the first surface.

3. The electronic device according to claim 1, characterized in that The buffer structure includes a buffer material area, and the buffer material area forms a partial area of ​​the first surface.

4. The electronic device according to claim 3, characterized in that: The buffer structure includes a plurality of buffer material areas, which are respectively arranged around the peripheries of the plurality of conductive holes and located in a partial area of ​​the conductive holes close to the pads.

5. The electronic device according to any one of claims 1 to 3, characterized in that: The elastic modulus of the buffer structure is less than 2 GPa.

6. The electronic device according to any one of claims 1 to 4, characterized in that: The buffer structure is made of polytetrafluoroethylene.

7. The electronic device according to any one of claims 1 to 5, characterized in that: The electronic device is a circuit board.

8. The electronic device according to any one of claims 1 to 5, characterized in that: The electronic device is a packaging substrate.

9. The electronic device according to any one of claims 1 to 5, characterized in that: The electronic device is a transfer board.

10. The electronic device according to any one of claims 1 to 5, characterized in that: The electronic device is an intermediate board.

11. An electronic device, characterized in that: The invention comprises a controller and the electronic device according to any one of claims 1 to 10, wherein the electronic device is electrically connected to the controller.

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