Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises: a substrate; a semiconductor column located on the surface of the substrate, the semiconductor column has a channel region, and the semiconductor column has a first side surface, and at least part of the first side surface corresponding to the channel region is recessed towards the center of the semiconductor column; and a word line, the word line covers at least the first side surface corresponding to the channel region. The semiconductor structure provided by the embodiment of the present disclosure can at least improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Memory is a common semiconductor structure. As the size of semiconductor structures continues to shrink, more memory can be incorporated on the chip, which helps increase the capacity of the product. There are many tiny conductive structural units inside the semiconductor structure, such as channels and source and drain electrodes. Among them, the channel is used to form a conductive channel between the source and the drain. The semiconductor structure also has a word line, which is in electrical contact with the channel region and is used to provide a control voltage to the channel region sufficient to turn on the channel, thereby controlling the conduction between the source and the drain. The control ability of the word line over the channel has an important impact on the performance of the semiconductor structure. The stronger the control ability of the word line over the channel, the faster the response rate of the transistor in the semiconductor structure and the better the performance of the semiconductor structure.

[0003] However, the performance of current semiconductor structures needs to be further improved. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the performance of the semiconductor structure.

[0005] An embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate; a semiconductor column located on a surface of the substrate, the semiconductor column having a channel region, the semiconductor column having a first side surface, at least a portion of the first side surface corresponding to the channel region being recessed toward the center of the semiconductor column; and a word line, the word line at least covering the first side surface corresponding to the channel region.

[0006] In some embodiments, the semiconductor column further includes: doped regions located on both sides of the channel region, the arrangement direction of the channel region and the doped regions is perpendicular to the substrate surface, and the portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor column to form a first groove, the first groove extends in a direction away from the substrate surface, and the first groove spans the doped region and the channel region.

[0007] In some embodiments, a portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor column to form a first groove. There are multiple first grooves, and the multiple first grooves are arranged at intervals.

[0008] In some embodiments, the semiconductor pillar has a second side surface opposite to the first side surface, a portion of the second side surface corresponding to the channel region is recessed toward the center of the semiconductor pillar, and the word line further covers the second side surface corresponding to the channel region.

[0009] In some embodiments, the number of semiconductor pillars is multiple, including: multiple rows of semiconductor pillars arranged at intervals along the first direction, wherein each row of semiconductor pillars includes multiple semiconductor pillars arranged at intervals along the second direction, the number of word lines is multiple, each word line extends along the second direction, and one word line covers the first side surface corresponding to the channel region of each semiconductor pillar in a row of the semiconductor pillars.

[0010] In some embodiments, the word line surrounds an entire side surface of the semiconductor pillar of the channel region.

[0011] In some embodiments, there are multiple semiconductor pillars, and the multiple semiconductor pillars include: first sub-semiconductor pillars and second sub-semiconductor pillars arranged alternately along a first direction, wherein the first side surface of the first sub-semiconductor pillar and the first side surface of the second sub-semiconductor pillar are arranged opposite to each other along the first direction.

[0012] In some embodiments, the word line covers a first side surface of a channel region of a first semiconductor sub-column and a first side surface of a channel region of a second semiconductor sub-column that are oppositely disposed.

[0013] In some embodiments, the first sub-semiconductor pillar and the second sub-semiconductor pillar each include a second side surface opposite to the first side surface, and the second side surface is exposed outside the word line.

[0014] In some embodiments, the first sub-semiconductor column and the second sub-semiconductor column both include: a third side surface connected to the first side surface, and a fourth side surface arranged opposite to the third side surface, and the word line also covers at least a portion of the third side surface and at least a portion of the fourth side surface of the first sub-semiconductor column, and covers at least a portion of the third side surface and at least a portion of the fourth side surface of the second sub-semiconductor column.

[0015] In some embodiments, the semiconductor structure includes: multiple rows of first sub-semiconductor columns arranged at intervals along the first direction, each row of the first sub-semiconductor columns includes multiple first sub-semiconductor columns arranged at intervals along the second direction; multiple rows of second sub-semiconductor columns arranged at intervals along the second direction, each row of the second sub-semiconductor columns includes multiple second sub-semiconductor columns arranged at intervals along the second direction, each row of the first sub-semiconductor columns and each row of the second sub-semiconductors are alternately arranged along the first direction; there are multiple word lines, and each word line covers the first side surface corresponding to the channel region in a row of the first sub-semiconductor columns and a row of the second sub-semiconductors that are alternately arranged.

[0016] In some embodiments, the method further includes: a gate dielectric layer, wherein the gate dielectric layer is located between the word line and the semiconductor pillar.

[0017] In some embodiments, there are multiple semiconductor pillars, and the multiple semiconductor pillars include: first sub-semiconductor pillars and second sub-semiconductor pillars arranged alternately along a first direction, a word line covers the first side surface of the channel region of a first sub-semiconductor pillar and the first side surface of the channel region of a second sub-semiconductor pillar that are relatively arranged, and the gate dielectric layer covers the entire side surface of the channel region of the first sub-semiconductor pillar corresponding to a word line and the entire side surface of the channel region of the second sub-semiconductor pillar corresponding to another adjacent word line.

[0018] Correspondingly, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, including: providing a substrate; forming a semiconductor column on the surface of the substrate, the semiconductor column having a channel region, the semiconductor column having a first side surface, and at least a portion of the first side surface corresponding to the channel region being recessed toward the center of the semiconductor column; forming a word line, the word line at least covering the first side surface corresponding to the channel region.

[0019] In some embodiments, the method for forming the semiconductor column includes: providing an initial substrate; etching a portion of the initial substrate to form a semiconductor layer arranged at intervals along a second direction, and the remaining portion of the initial substrate serves as the substrate; forming a first graphic layer on a portion of the surface of the semiconductor layer, the first graphic layer being used to define the cross-sectional shape of the semiconductor column parallel to the surface of the substrate; etching the semiconductor layer not covered by the first graphic layer, and the remaining portion of the semiconductor layer forming the semiconductor column.

[0020] In some embodiments, the plurality of semiconductor pillars include: first sub-semiconductor pillars and second sub-semiconductor pillars alternately arranged along a first direction, wherein the first side surface of the first sub-semiconductor pillar and the first side surface of the second sub-semiconductor pillar are arranged opposite to each other along the first direction, and a word line covers the first side surface of the channel region of the oppositely arranged first sub-semiconductor pillar and the first side surface of the channel region of the second sub-semiconductor pillar. The method for forming the semiconductor pillars includes: forming a first pattern layer on a portion of the surface of the semiconductor layer, the first pattern layer including a first sub-pattern layer and a second sub-pattern layer alternately arranged along the first direction, the first sub-pattern layer including a first recessed side having a first recessed side, the second sub-pattern layer including a second recessed side having a second recessed side, and the first recessed side and the second recessed side are arranged opposite to each other along the first direction; etching the semiconductor layer not covered by the first sub-pattern layer and the semiconductor layer not covered by the second sub-pattern layer, and the remaining portion of the semiconductor layer forms the semiconductor pillars.

[0021] In some embodiments, the orthographic projection shape of the first sub-pattern layer on the surface of the substrate is a "concave" shape, and the orthographic projection shape of the second sub-pattern layer on the surface of the substrate is a "concave" shape.

[0022] In some embodiments, the first sub-patterned layer includes a first non-recessed side opposite to the first recessed side, and the second sub-patterned layer includes a second non-recessed side opposite to the second recessed side. The method for forming the word line includes: forming an isolation layer between adjacent semiconductor layers, wherein the isolation layer contacts the sidewalls of the semiconductor layer and a top surface of the isolation layer is flush with the top surface of the semiconductor layer; forming a plurality of second patterned layers spaced apart along a first direction on the top surface of the isolation layer, wherein a second patterned layer is aligned with a gap between the first non-recessed side and the second non-recessed side; etching the semiconductor layer to a second predetermined thickness along a surface of the semiconductor layer not covered by the first patterned layer to form a first trench, and etching the isolation layer to a first predetermined thickness along a surface of the isolation layer not covered by the second patterned layer to form a second trench, wherein the first trench communicates with the second trench; forming a gate dielectric layer on the sidewalls of the semiconductor pillar, wherein the gate dielectric layer also fills the gap between the first non-recessed side and the second non-recessed side; forming the word line filling the first trench and the second trench, and the word line covering the gate dielectric layer.

[0023] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0024] In the semiconductor structure provided by the embodiments of the present disclosure, the first side surface corresponding to the channel region of the semiconductor pillar has a recess, thereby increasing the surface area of ​​the first side surface compared to a case without the recess. The word line covers the first side surface corresponding to the channel region. Due to the increased surface area of ​​the first side surface, the contact area between the word line and the channel region is increased, thereby increasing the channel length of the transistor, enhancing the word line's ability to control the transistor, and improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 Schematic diagram of a top view of a semiconductor structure;

[0027] Figure 2 A schematic top view of a semiconductor structure provided in one embodiment of the present disclosure;

[0028] Figure 3 for Figure 2 Schematic diagram of the partial cross-section structure in the aa' direction;

[0029] Figure 4 A schematic top view of another semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 5 A schematic top view of another semiconductor structure provided by an embodiment of the present disclosure;

[0031] Figures 6 to 22 A schematic top view of the structure corresponding to each step of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0032] As can be seen from the background technology, the performance of the current semiconductor structure needs to be further improved. Figure 1 An analysis of one of the reasons for the poor performance of semiconductor structures reveals that current semiconductor structures include: a semiconductor pillar 1 and a word line 2 disposed around the channel region of the semiconductor pillar 1. As semiconductor structures become smaller, the contact area between the word line and the channel region in the semiconductor pillar decreases, resulting in a shorter transistor channel and weaker control of the word line over the channel, leading to poor electrical performance of the semiconductor structure.

[0033] Embodiments of the present disclosure provide a semiconductor structure in which a first side surface corresponding to a channel region of a semiconductor pillar has a recess, thereby increasing the surface area of ​​the first side surface compared to a case without the recess. A word line covers the first side surface corresponding to the channel region. Due to the increased surface area of ​​the first side surface, the contact area between the word line and the channel region is increased, thereby increasing the channel length of the transistor, enhancing the word line's ability to control the transistor, and improving the electrical performance of the semiconductor structure.

[0034] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0035] Figure 2 A schematic top view of a semiconductor structure provided in one embodiment of the present disclosure; Figure 3 for Figure 2 A partial structural diagram of the cross-sectional structure along the aa' direction; Figure 4 Another schematic diagram of a top view of a semiconductor structure provided by an embodiment of the present disclosure; Figure 5 A schematic top view of another semiconductor structure provided in an embodiment of the present disclosure.

[0036] refer to Figures 2 to 5 The semiconductor structure includes a substrate. The semiconductor structure also includes a semiconductor pillar 101 located on a surface of the substrate. The semiconductor pillar 101 has a channel region 111. The semiconductor pillar 101 has a first side surface 11. At least a portion of the first side surface 11 corresponding to the channel region 111 is recessed toward the center of the semiconductor pillar 101. The semiconductor structure also includes a word line 102. The word line 102 at least covers the first side surface 11 corresponding to the channel region 111.

[0037] In some embodiments, the substrate may be made of a semiconductor material, silicon, germanium, silicon germanium, or silicon on insulator.

[0038] In some embodiments, the material of the semiconductor pillar 101 can be the same as that of the substrate. In some implementations, the material of the semiconductor pillar 101 can be silicon. In some embodiments, the material of the semiconductor pillar 101 can also be germanium, silicon germanium, or silicon on insulator.

[0039] refer to Figure 3 In some embodiments, the semiconductor pillar 101 further includes doped regions located on both sides of the channel region 111. The doped regions may include a first doped region 112 and a second doped region 113. The first doped region 112 is located on the side of the channel region 111 facing the substrate, and the second doped region 113 is located on the side of the channel region 111 facing away from the substrate. The first doped region 112, the second doped region 113, and the channel region 111 are used to form a transistor. In some embodiments, the first doped region 112 is used to form the source of the transistor, the second doped region 113 is used to form the drain of the transistor, and the channel region 111 is used to form the channel of the transistor.

[0040] In some embodiments, the doping ion type of the first doping region 112 is the same as the doping ion type of the second doping region 113 , and the doping ion type of the first doping region 112 is different from the doping ion type of the channel region 111 .

[0041] In some embodiments, the doping ion type of the first doping region 112 is P-type, the doping ion type of the second doping region 113 is N-type, and the doping ion type of the channel region 111 is P-type.

[0042] In some embodiments, the doping ion type of the first doping region 112 is N-type, the doping ion type of the second doping region 113 is P-type, and the doping ion type of the channel region 111 is N-type.

[0043] In some embodiments, the doping ion type of the first doping region 112 is the same as the doping ion type of the second doping region 113 and the doping ion type of the channel region 111 , and the doping ion concentration of the channel region 111 is lower than the doping ion concentration of the first doping region 112 and the second doping region 113 .

[0044] In some embodiments, the P-type dopant ions may include any one of boron ions, aluminum ions, gallium ions, or indium ions. In some embodiments, the N-type dopant ions may include any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0045] In some embodiments, the semiconductor structure further includes a bit line 104 . The bit line 104 is located on a side of the first doped region 112 facing the substrate and is in electrical contact with a surface of the first doped region 112 facing the substrate.

[0046] In some embodiments, the bit line 104 can be obtained by doping a substrate corresponding to the semiconductor pillar 101 so that a portion of the substrate corresponding to the bottom surface of the semiconductor pillar 101 has conductivity.

[0047] In some embodiments, the substrate corresponding to the semiconductor pillar 101 may be etched to form a groove in the substrate corresponding to the bottom of the semiconductor pillar 101, exposing the bottom surface of the semiconductor pillar 101. The bit line 104 may then be deposited in the groove. In one embodiment, the material of the bit line 104 may include a metal material, such as at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or ruthenium.

[0048] In some embodiments, there are a plurality of semiconductor pillars 101, and the plurality of semiconductor pillars 101 are arranged at intervals along the first direction X and the second direction Y. There are a plurality of bit lines 104, and each bit line 104 extends along the first direction X. The plurality of bit lines 104 are arranged at intervals along the second direction Y, and the bit lines 104 are electrically in contact with the first doped region 112 of each of the plurality of semiconductor pillars 101 arranged at intervals along the first direction X.

[0049] The first side surface 11 of the semiconductor pillar 101 has a recess, which increases the surface area of ​​the first side surface 11 compared to the case where the first side surface 11 does not have a recess, thereby increasing the contact area between the word line 102 on the first side surface 11 covering the channel region 111 and the channel region 111, thereby increasing the channel length of the transistor, thereby enhancing the control ability of the word line 102 over the channel, improving the response rate of the transistor, and improving the electrical performance of the semiconductor structure.

[0050] It is worth noting that the semiconductor pillar 101 has a top surface and a bottom surface parallel to the substrate surface, and also has a side surface connected to the top surface and the bottom surface. The first side surface 11 referred to herein is the side surface of the semiconductor pillar 101.

[0051] In some embodiments, the orthographic projection of the semiconductor pillar 101 on the substrate surface is circular or elliptical, that is, the semiconductor pillar 101 has no ridges, and the first side surface 11 can be any portion of the side surface of the semiconductor. In some embodiments, the semiconductor pillar 101 has ridges, that is, the semiconductor pillar 101 has multiple side surfaces divided by the ridges in different directions, and the first side surface 11 can be one of the side surfaces of the semiconductor pillar 101.

[0052] refer to Figure 2 , only a portion of the first side surface 11 is recessed toward the center of the semiconductor pillar 101. In some embodiments, the semiconductor pillar further includes: doped regions located on both sides of the channel region 111. The arrangement direction of the channel region 111 and the doped regions is perpendicular to the substrate surface. A portion of the first side surface 11 corresponding to the channel region 111 is recessed toward the center of the semiconductor pillar 101 to form a first groove. The first groove extends in a direction away from the surface of the substrate, and the first groove spans the doped region and the channel region 111.

[0053] In some embodiments, the orthographic projection shape of the first groove on the surface of the substrate may be a “concave” shape.

[0054] In some embodiments, the doped region includes a first doped region 112 and a second doped region 113. The first doped region 112 is located on the side of the channel region 111 facing the substrate, and the second doped region 113 is located on the side of the channel region 111 away from the substrate. In this way, the first groove may only span the channel region 111 and the second doped region 113. In other words, the first side surface 11 corresponding to the first doped region 112 does not have a depression toward the center of the semiconductor pillar 101. In this way, the semiconductor pillar 101 corresponding to the first doped region 112 can be ensured to have a larger area, thereby increasing the contact area between the bit line 104 and the bottom surface of the semiconductor pillar 101 corresponding to the first doped region 112, thereby improving the electrical connection performance between the bit line 104 and the first doped region 112. The second doped region 113 and the first side surface 11 of the channel region 111 have a recess toward the center of the semiconductor column 101, so that in the actual step of forming the recess, the second doped region 113 can be etched from the top of the second doped region 113. The second doped region 113 is located at the top of the semiconductor column 101, that is, the semiconductor column 101 can be etched from the top of the semiconductor column 101 to form a first groove, which is conducive to simplifying the process of forming the first groove.

[0055] In some embodiments, the first groove may also span the first doping region 112 , the second doping region 113 and the channel region 111 , that is, the first side surfaces 11 corresponding to the first doping region 112 , the second doping region 113 and the channel region 111 all have a depression toward the center of the semiconductor pillar 101 .

[0056] In some embodiments, a portion of the first side surface 11 corresponding to the channel region 111 is recessed toward the center of the semiconductor pillar 101 to form a first groove. The number of first grooves is multiple, and the multiple first grooves are arranged at intervals. In other words, the multiple first grooves can be dispersed and arranged on the first side surface 11. In some embodiments, the multiple first grooves can be arranged at intervals along a direction perpendicular to the substrate surface.

[0057] In some embodiments, the orthographic projection shape of the first groove on the first side surface 11 may be at least one of a circle, a rectangle, or a polygon.

[0058] In some embodiments, the semiconductor pillar 101 has a second side surface 12 opposite to the first side surface 11, and the distance between the first side surface 11 and the second side surface 12 is a first distance. The first groove is recessed from the first side surface 11 toward the second side surface 12, and the ratio of the recess depth of the first groove to the first distance is less than or equal to 0.7. Within this range, on the one hand, the recess depth of the first groove is larger, thereby making the first side surface 11 have a larger surface area, which is beneficial to increase the contact area between the word line 102 and the first side surface 11. On the other hand, within the above range, the recess depth of the first groove is not too large, preventing the first distance from being too small due to the recess depth of the first groove being too large, that is, the distance between the first side surface 11 and the second side surface 12 being too small, making the volume of the semiconductor pillar 101 too small, and thus causing the electrical performance of the semiconductor pillar 101 to deteriorate.

[0059] refer to Figure 4 In some embodiments, a portion of the second side surface 12 corresponding to the channel region is recessed toward the center of the semiconductor pillar 101, and the word line 102 also covers the second side surface 12 corresponding to the channel region 111. That is, both the first side surface 11 and the second side surface 12 are recessed toward the center of the semiconductor pillar 101. Part of the first side surface 11 is recessed toward the second side surface 12, and part of the second side surface 12 is recessed toward the first side surface 11. In this way, the surface area of ​​the side surface of the semiconductor pillar 101 in the channel region 111 can be further increased. The word line 102 covers the first side surface 11 of the channel region 111 and the second side surface 12 of the channel region 111, so that the contact area between the word line 102 and the channel region 111 is further increased, thereby further increasing the length of the channel, enhancing the control ability of the word line 102 over the channel, and thus improving the electrical performance of the semiconductor structure.

[0060] In some embodiments, a portion of the second side surface 12 is recessed toward the center of the semiconductor pillar 101 to form a second groove.

[0061] In some embodiments, the second groove spans the large second doped region 113 and the channel region 111 .

[0062] In some embodiments, the second groove is adjacent to the first doped region 112 , the channel region 111 , and the second doped region 113 .

[0063] In some embodiments, there are multiple second grooves, and the multiple second grooves are arranged at intervals. In a specific example, the multiple second grooves are arranged at intervals along a direction perpendicular to the surface of the substrate.

[0064] In some embodiments, a portion of the first side surface 11 is recessed toward the center of the semiconductor pillar 101 to form a first recess, and a portion of the second side surface 12 is recessed toward the center of the semiconductor pillar 101 to form a second recess. The ratio of the sum of the recess depths of the first recess and the second recess to the first distance is less than or equal to 0.7. Within this range, the first distance is ensured to be small, so that the thickness of the semiconductor pillar 101 in the direction from the first side surface 11 to the first side surface 11 is not too small, thereby ensuring that the electrical performance of the semiconductor pillar 101 is good.

[0065] refer to Figure 4 In some embodiments, a portion of the second side surface 12 is recessed toward the center of the semiconductor pillar 101, and the word line 102 surrounds the entire side surface of the semiconductor pillar 101 in the channel region 111. In other words, the word line 102 completely surrounds the entire side surface of the semiconductor pillar 101 in the channel region 111. This ensures that the word line 102 is located within the first groove and the second groove, thereby increasing the contact area between the word line 102 and the channel region 111.

[0066] Specifically, in some embodiments, the side surfaces of the semiconductor pillar 101 further include a third side surface and a fourth side surface, the third side surface and the fourth side surface are arranged opposite to each other, and the first side surface 11, the second side surface 12, the third side surface, and the fourth side surface are sequentially connected to form the semiconductor pillar 101. The entire side surface of the semiconductor pillar 101 referred to herein includes the first side surface 11, the second side surface 12, the third side surface, and the fourth side surface.

[0067] It is worth noting that in some embodiments, a portion of the first side surface 11 is recessed toward the center of the semiconductor pillar 101, a portion of the second side surface 12 is recessed toward the center of the semiconductor pillar 101, and the number of semiconductor pillars is multiple, including: multiple rows of semiconductor pillars 101 spaced apart along the first direction X, wherein each row of semiconductor pillars 101 includes multiple semiconductor pillars 101 spaced apart along the second direction Y, the number of word lines 102 is multiple, each word line 102 extends along the second direction Y, and one word line 102 covers the first side surface 11 corresponding to the channel region 111 of each semiconductor pillar 101 in a row of semiconductor pillars 101.

[0068] That is, one word line 102 corresponds to a row of semiconductor pillars 101 , one word line 102 only covers the side surfaces of the channel regions 111 of one row of semiconductor pillars 101 , and one word line 102 covers the side surfaces of the semiconductor pillars 101 in the entire channel regions 111 of one row of semiconductor pillars 101 .

[0069] In some embodiments, an isolation layer 105 is provided between adjacent word lines 102, with the side surfaces of the isolation layer 105 contacting the side surfaces of the word lines 102. The isolation layer 105 is used to isolate adjacent word lines 102 and prevent signal crosstalk between adjacent word lines 102. In some embodiments, the isolation layer 105 may be made of an insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. In some embodiments, the word lines 102 may be made of a metal material, such as at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or ruthenium.

[0070] refer to Figure 5 In some embodiments, there are multiple semiconductor pillars, and the multiple semiconductor pillars 101 include: first sub-semiconductor pillars 101 and second sub-semiconductor pillars 101 alternately arranged along the first direction X, wherein the first side surface 11 of the first sub-semiconductor pillars 101 and the first side surface 11 of the second sub-semiconductor pillars 101 are arranged opposite to each other along the first direction X.

[0071] Specifically, part of the first side surface 11 of the first sub-semiconductor column 101 is recessed toward the center of the first sub-semiconductor column 101 to form a first sub-groove, and part of the first side surface 11 of the second sub-semiconductor column 101 is recessed toward the center of the second sub-semiconductor column 101 to form a second sub-groove, and the first sub-groove and the second sub-groove are arranged face to face.

[0072] In some embodiments, the orthographic projection shape of the first sub-groove on the surface of the substrate is a "concave" shape, and the orthographic projection shape of the second sub-groove on the surface of the substrate is a "concave" shape.

[0073] In some embodiments, a word line 102 covers the first side surface 11 of the channel region 111 of a first sub-semiconductor pillar 101 and the first side surface 11 of the channel region 111 of a second sub-semiconductor pillar 101 that are disposed opposite each other. In other words, the word line 102 is located between the first side surface 11 and the second side surface 12 of the first sub-semiconductor pillar 101, and the word line 102 is also located in the first sub-recess and the second sub-recess. The word line 102 is in electrical contact with both the first sub-semiconductor pillar 101 and the second sub-semiconductor pillar 101, that is, one word line 102 controls both the first sub-semiconductor pillar 101 and the second sub-semiconductor pillar 101.

[0074] The channel region 111 of the first sub-semiconductor column 101 and the channel region 111 of the second sub-semiconductor column 101 are jointly used to form the channel region 111 of a transistor. Compared with the word line 102 only covering the first side surface 11 of a semiconductor column 101, the word line 102 contacts the first side surface 11 of the first sub-semiconductor column 101 and the first side surface 11 of the second sub-semiconductor column 101, so that the contact area between the word line 102 and the channel region 111 is further increased, so that the channel length of the transistor formed by the first sub-semiconductor column 101 and the second sub-semiconductor column 101 is increased, which is beneficial to enhance the control ability of the word line 102 over the transistor.

[0075] In some embodiments, the first sub-semiconductor pillar 101 and the second sub-semiconductor pillar 101 each include a second side surface 12 opposite to the first side surface 11, and the second side surface 12 is exposed outside the word line 102. In other words, the word line 102 does not cover the second side surface 12. It is understood that if the same word line 102 covers the first side surface 11 of the first sub-semiconductor pillar 101 and the first side surface 11 of the second sub-semiconductor pillar 101, and the word line 102 also covers the second side surface 12 of the first sub-semiconductor pillar 101 and the second side surface 12 of the second sub-semiconductor pillar 101, then compared to a case where the word line 102 only surrounds the side surface of one semiconductor pillar 101, the thickness of the word line 102 in the direction from the first side surface 11 to the second side surface 12 will increase, resulting in a decrease in the number of word lines 102 within the same area, which is not conducive to improving the integration density of the semiconductor structure.

[0076] Therefore, setting the word line 102 not to cover the second side surface 12 can ensure that the contact area between the word line 102 and the channel region 111 is increased without increasing the thickness of the word line 102 in the direction from the first side surface 11 to the second side surface 12, thereby enhancing the control ability of the word line 102 over the channel.

[0077] In a specific example, the first sub-semiconductor column 101 and the second sub-semiconductor column 101 both include: a third side surface connected to the first side surface 11, and a fourth side surface arranged opposite to the third side surface. The word line 102 also covers at least a portion of the third side surface and at least a portion of the fourth side surface of the first sub-semiconductor column 101, and covers at least a portion of the third side surface and at least a portion of the fourth side surface of the second sub-semiconductor column 101.

[0078] That is to say, the first sub-semiconductor column 101 and the second sub-semiconductor column 101 that are arranged opposite to each other are surrounded on three sides by the same word line 102, so that the contact area between the word line 102 and the side surfaces of the channel region 111 of the first sub-semiconductor column 101 and the side surfaces of the channel region 111 of the second sub-semiconductor column 101 is further increased.

[0079] In some embodiments, the word line 102 surrounds a portion of the third side surface of the channel region 111 of the first sub-semiconductor pillar 101 and a portion of the fourth side surface of the channel region 111. In some embodiments, the word line 102 surrounds a portion of the third side surface of the channel region 111 of the second sub-semiconductor pillar 101 and a portion of the fourth side surface of the channel region 111. In some embodiments, the word line 102 surrounds the entire third side surface of the channel region 111 of the first sub-semiconductor pillar 101 and the entire fourth side surface of the channel region 111.

[0080] In some embodiments, the first and second semiconductor sub-pillars 101 each include a third side surface connected to the first side surface 11, and a fourth side surface opposite the third side surface. In one specific example, the word line 102 may cover at least a portion of the third side surface, at least a portion of the fourth side surface, and the first side surface 11 of the first semiconductor sub-pillar 101, and only cover the first side surface 11 of the second semiconductor sub-pillar 101. In another specific example, the word line 102 may only cover the first side surface 11 of the first semiconductor sub-pillar 101, and at least a portion of the third side surface, at least a portion of the fourth side surface, and the first side surface 11 of the second semiconductor sub-pillar 101.

[0081] refer to Figure 5 In some embodiments, the semiconductor structure includes: multiple rows of first sub-semiconductor pillars 101 arranged at intervals along a first direction X, each row of the first sub-semiconductor pillars 101 including multiple first sub-semiconductor pillars 101 arranged at intervals along a second direction Y; multiple rows of second sub-semiconductor pillars 101 arranged at intervals along the second direction Y, each row of the second sub-semiconductor pillars 101 including multiple second sub-semiconductor pillars 101 arranged at intervals along the second direction Y, each row of the first sub-semiconductor pillars 101 and each row of the second sub-semiconductors being alternately arranged along the first direction X; and a plurality of word lines 102, each word line 102 covering a first side surface 11 corresponding to a channel region 111 in a row of the alternatingly arranged first sub-semiconductor pillars 101 and a row of the second sub-semiconductors.

[0082] Specifically, a row of first sub-semiconductor pillars 101 and a row of second sub-semiconductor pillars 101 arranged opposite each other are referred to as a semiconductor pillar 101 group. In each semiconductor pillar 101 group, the first sub-grooves on the first side surfaces 11 of the first sub-semiconductor pillars 101 are arranged opposite each other to the second sub-grooves on the first side surfaces 11 of the second sub-semiconductor pillars 101. A word line 102 corresponds to one semiconductor pillar 101 group and is located between a row of first sub-semiconductor pillars 101 and a row of second sub-semiconductor pillars 101 belonging to the same semiconductor pillar 101 group.

[0083] In some embodiments, reference Figures 2 to 5 , further comprising: a gate dielectric layer 103, located between the word line 102 and the semiconductor pillar 101. The gate dielectric layer 103 is located on the side of the semiconductor pillar 101 in the channel region 111, and the word line 102 covers the surface of the gate dielectric layer 103. In some embodiments, the material of the gate dielectric layer 103 may be silicon oxide.

[0084] refer to Figures 2 to 4 In some embodiments, a word line 102 covers the channel regions 111 of a row of semiconductor pillars 101 spaced apart along the second direction Y, and the gate dielectric layer 103 is located on a side of the channel region 111 of each semiconductor pillar 101 .

[0085] refer to Figure 5 In some embodiments, there are multiple semiconductor pillars, and the multiple semiconductor pillars 101 include: first sub-semiconductor pillars 114 and second sub-semiconductor pillars 115 are alternately arranged along the first direction X, a word line 102 covers the first side surface 11 of the channel region 111 of a first sub-semiconductor pillar 114 and the first side surface 11 of the channel region 111 of a second sub-semiconductor pillar 115 that are oppositely arranged, and the gate dielectric layer 103 covers the entire side surface of the channel region 111 of the first sub-semiconductor pillar 114 corresponding to the word line 102 and the entire side surface of the channel region 111 of the second sub-semiconductor pillar 115 corresponding to another adjacent word line 102.

[0086] Specifically, the semiconductor pillars arranged at intervals along the first direction X are divided into first sub-semiconductor pillar groups 14 and second sub-semiconductor pillar groups 15 that are alternately arranged. The second sub-semiconductor pillars 115 in the first sub-semiconductor pillar group 14 are adjacent to the first sub-semiconductor pillars 114 in the second sub-semiconductor pillar group 15 .

[0087] The word lines 102 include: first sub-word lines 102 located between adjacent first sub-semiconductor pillars 114 and adjacent second sub-semiconductor pillars 115 in the first sub-semiconductor pillar group 14, and second sub-word lines 102 located between adjacent first sub-semiconductor pillars 114 and adjacent second sub-semiconductor pillars 115 in the second sub-semiconductor pillar group 15. That is, the first sub-word lines 102 correspond to the first sub-semiconductor pillar group 14, and the second sub-word lines 102 correspond to the second sub-semiconductor pillar group 15. An isolation layer 105 is provided between the first sub-word lines 102 and the second sub-word lines 102 to isolate the first sub-word lines 102 from the second sub-word lines 102.

[0088] The gate dielectric layer 103 covers the side surfaces of the channel region 111 of the second sub-semiconductor pillar 115 belonging to the first sub-semiconductor pillar group 14 and covers the side surfaces of the channel region 111 of the first sub-semiconductor pillar 114 belonging to the second sub-semiconductor pillar group 15. The gate dielectric layer 103 is also located in the gap between the second sub-semiconductor pillar 115 belonging to the first sub-semiconductor pillar group 14 and the first sub-semiconductor pillar 114 belonging to the second sub-semiconductor pillar group 15, and is used to isolate the first sub-semiconductor pillar 114 and the second sub-semiconductor pillar 115 that do not belong to the same semiconductor pillar 101 group.

[0089] In the semiconductor structure provided in the above embodiment, the first side surface 11 corresponding to the channel region 111 of the semiconductor pillar 101 has a recess, thereby increasing the surface area of ​​the first side surface 11 compared to a case without the recess. The word line 102 covers the first side surface 11 corresponding to the channel region 111. Due to the increased surface area of ​​the first side surface 11, the contact area between the word line 102 and the channel region 111 is increased, thereby increasing the channel length of the transistor, enhancing the control ability of the word line 102 over the transistor, and improving the electrical performance of the semiconductor structure.

[0090] Correspondingly, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided by the above embodiment. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0091] Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along the AA' direction, Figure 9 for Figure 8 Schematic diagram of the cross-sectional structure along the AA' direction, Figure 11 for Figure 10 Schematic diagram of the cross-sectional structure along the AA' direction, Figure 13 for Figure 12 Schematic diagram of the cross-sectional structure along the AA' direction, Figure 15 for Figure 14 Schematic diagram of the cross-sectional structure along the AA' direction.

[0092] refer to Figures 6 to 15 , a method for preparing a semiconductor structure includes:

[0093] A substrate 100 is provided, and a semiconductor column 101 is formed on the surface of the substrate 100 . The semiconductor column 101 has a channel region 111 . The semiconductor column 101 has a first side surface 11 . At least a portion of the first side surface 11 corresponding to the channel region 111 is recessed toward the center of the semiconductor column 101 .

[0094] In some embodiments, a method of forming the semiconductor pillar 101 includes:

[0095] refer to Figure 6 as well as Figure 7 , providing an initial substrate (not shown). In some embodiments, the material of the initial substrate can be a semiconductor material. In some embodiments, the material of the initial substrate can be silicon. In some embodiments, the initial substrate can also be germanium, silicon germanium, or silicon on insulator.

[0096] Afterwards, a portion of the initial substrate is etched to form semiconductor layers 20 arranged at intervals along the second direction Y, and the remaining portion of the initial substrate serves as the substrate 100. Each semiconductor layer 20 extends along the first direction X.

[0097] In some embodiments, the method of etching a portion of the initial substrate to form the semiconductor layer 20 includes: performing a patterning process on the surface of the initial substrate to define the position of the initial semiconductor portion. In some embodiments, the initial substrate surface can be patterned using either a SADP (Self-aligned Double Patterning) process or a SAQP (Self-Aligned Quadruple Patterning) process. Thereafter, the patterned initial substrate surface is etched to a portion of the thickness of the initial substrate to form the mutually separated semiconductor layers 20. In some embodiments, the etching process can be either a dry etching process or a wet etching process.

[0098] refer to Figure 8 as well as Figure 9In some embodiments, after forming separate semiconductor layers 20, bit lines 104 are formed. Adjacent semiconductor layers 20 expose portions of the substrate 100 surface, and a doping process is performed on the substrate 100 through the gaps between the adjacent semiconductor layers 20 to convert the portion of the substrate 100 directly opposite the semiconductor layers 20 into a conductive bit line 104. In some embodiments, the substrate 100 can be doped using an ion implantation process. The implantation angle of the ion implantation process can be controlled to transform the portion of the substrate 100 directly opposite the semiconductor layers 20 into the bit line 104, such that the formed bit line 104 extends in the same direction as the semiconductor layers 20, i.e., along the first direction X. In this manner, after the semiconductor layer 20 is subsequently etched to form semiconductor pillars 101 spaced apart along the first direction X, the semiconductor pillars 101 extending along the first direction X can electrically contact each of the plurality of semiconductor pillars 101 spaced apart along the first direction X.

[0099] refer to Figure 12 as well as Figure 13 A first patterned layer 30 is formed on a portion of the surface of the semiconductor layer 20. The first patterned layer 30 is used to define the cross-sectional shape of the semiconductor pillar 101 parallel to the surface of the substrate 100. In some embodiments, the first patterned layer 30 can be formed on the surface of the semiconductor layer 20 using either a SADP process or a SAQP process. In some embodiments, the first patterned layer 30 can be a photoresist, a spin-on hard mask, or silicon oxide.

[0100] refer to Figure 14 as well as Figure 15 After forming the first patterned layer 30, the semiconductor layer 20 not covered by the first patterned layer 30 is etched, and the remaining portion of the semiconductor layer 20 forms the semiconductor pillar 101. The semiconductor layer 20 outside the first patterned layer 30 is etched, and the semiconductor layer 20 covered by the first patterned layer 30 remains. The cross-sectional shape of the unetched semiconductor layer 20 along a direction parallel to the surface of the substrate 100 is the same as that of the first patterned layer 30. The first patterned layer 30 is configured to have a concave shape, so that the formed semiconductor pillar 101 also has a concave shape.

[0101] In some embodiments, the semiconductor pillar 101 has a channel region 111 and first and second doped regions 113 located on both sides of the channel region 111. The first doped region 112 is located on the side of the channel region 111 facing the substrate 100, and the second doped region 113 is located on the side of the channel region 111 away from the substrate 100.

[0102] In some embodiments, doping processes may be performed on different portions of the same semiconductor pillar 101 to form the first doping region 112 , the second doping region 113 , and the channel region 111 , respectively.

[0103] In some embodiments, after etching to form the semiconductor pillar 101, different portions of the semiconductor pillar 101 may be doped to respectively form a first doping region 112, a second doping region 113, and a channel region 111. Specifically, the semiconductor pillar 101 includes a first region, a second region, and a third region sequentially arranged in a direction perpendicular to the surface of the substrate 100. The method for forming the semiconductor pillar 101 includes:

[0104] Doping processes are performed on the first region, the second region, and the third region, respectively, to transform the first region into a first doping region 112, the second region into a channel region 111, and the third region into a second doping region 113. The doping ion type of the first doping region 112 is the same as the doping ion type of the second doping region 113, and the doping ion type of the second doping region 113 is different from the doping ion type of the channel region 111. In some embodiments, the doping process may be an ion implantation process.

[0105] Since the doping ion type of the first doping region 112 is the same as the doping ion type of the second doping region 113, the first region and the third region can be doped in the same process step to form the second doping region 113 and the first doping region 112, respectively. During the doping steps of the first region and the third region, a mask layer is formed on the side surface of the semiconductor portion of the second region to protect the second region and prevent the doping ions from diffusing into the second region.

[0106] It is understood that during the step of doping the second region, a mask layer may be formed on the side surfaces of the semiconductor portions of the first and third regions to protect the first and third regions and prevent dopant ions from diffusing into the first and third regions. In some embodiments, the mask layer may be silicon oxide, which may be formed using a thermal oxidation process.

[0107] In some embodiments, P-type dopant ions may be implanted into the first and third regions, and N-type dopant ions may be implanted into the second region. In some embodiments, N-type dopant ions may be implanted into the first and third regions, and P-type dopant ions may be implanted into the second region.

[0108] In some embodiments, the P-type dopant ions may include any one of boron ions, aluminum ions, gallium ions, or indium ions. In some embodiments, the N-type dopant ions may include any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0109] In some embodiments, before forming the semiconductor pillar 101, different portions of the semiconductor layer 20 may be doped to form the first doping region 112, the second doping region 113, and the channel region 111. In this way, only a small number of semiconductor layers 20 need to be doped, simplifying the process.

[0110] In some embodiments, the plurality of semiconductor pillars 101 include: first sub-semiconductor pillars 114 alternately arranged along the first direction X (refer to Figure 5 ) and the second semiconductor sub-column 115 (reference Figure 5 ), wherein the first side surface 11 of the first sub-semiconductor pillar 114 and the first side surface 11 of the second sub-semiconductor pillar 115 are arranged opposite to each other along the first direction X, and a word line 102 covers the first side surface 11 of the channel region 111 of the first sub-semiconductor pillar 114 and the first side surface 11 of the channel region 111 of the second sub-semiconductor pillar 115. The method for forming the semiconductor pillar 101 includes:

[0111] refer to Figure 12 as well as Figure 13 A first patterned layer 30 is formed on a portion of the surface of the semiconductor layer 20. The first patterned layer 30 includes first sub-patterned layers and second sub-patterned layers alternately arranged along the first direction X. The first sub-patterned layer includes a first recessed side having a first recess, and the second sub-patterned layer includes a second recessed side having a second recess. The first recessed side and the second recessed side are arranged opposite to each other along the first direction X.

[0112] The first sub-pattern layer is used to define the cross-sectional shape of the first sub-semiconductor pillar 114 parallel to the surface of the substrate 100 , and the second sub-pattern layer is used to define the cross-sectional shape of the second sub-semiconductor pillar 115 parallel to the surface of the substrate 100 .

[0113] The first recess is used to define the orthographic projection shape of the first groove of the first side surface 11 of the first sub-semiconductor column 114 on the surface of the substrate 100 . The second recess is used to define the orthographic projection shape of the first groove of the first side surface 11 of the second sub-semiconductor column 115 on the surface of the substrate 100 .

[0114] The first recessed side and the second recessed side are oppositely arranged along the first direction X. In the first sub-semiconductor column 114 and the second sub-semiconductor column 115 formed subsequently, the first side surface 11 of the first sub-semiconductor column 114 and the first side surface 11 of the second sub-semiconductor column 115 are face to face.

[0115] In some embodiments, either SADP process or SAQP process can be used to form the first graphic layer 30 and the second graphic layer. The material of the first graphic layer 30 can be any one of photoresist, spin-on hard mask or silicon oxide, and the material of the second graphic layer can be any one of photoresist, spin-on hard mask or silicon oxide.

[0116] In some embodiments, the orthographic projection of the first sub-patterned layer 30 on the surface of the substrate 100 is a "concave" shape, and the orthographic projection of the second sub-patterned layer on the surface of the substrate 100 is a "concave" shape. The concave side of the "concave" shape of the first sub-patterned layer is a first concave side, and the concave side of the "concave" shape of the second sub-patterned layer is a second concave side.

[0117] refer to Figure 14 as well as Figure 15 The semiconductor layer 20 not covered by the first sub-pattern layer and the semiconductor layer 20 not covered by the second sub-pattern layer are etched, and the remaining portion of the semiconductor layer 20 forms the semiconductor pillar 101. In some embodiments, only a portion of the semiconductor layer 20 is etched. For example, only the semiconductor layer 20 corresponding to the second doped region 113 and the channel region 111 may be etched, so that the formed first groove only spans the second doped region 113 and the channel region 111, that is, the first side surface 11 corresponding to the first doped region 112 does not have a recess.

[0118] In some embodiments, the semiconductor layer 20 corresponding to the first doping region 112 , the second doping region 113 and the channel region 111 may also be etched so that the formed first groove spans the first doping region 112 , the second doping region 113 and the channel region 111 .

[0119] Figure 17 for Figure 16 Schematic diagram of the cross-sectional structure along the AA' direction, Figure 19 for Figure 18 Schematic diagram of the cross-sectional structure along the AA' direction.

[0120] refer to Figures 16 to 19 , forming word line 102, which covers at least first side surface 11 corresponding to channel region 111. The recessed first side surface 11 significantly increases the surface area of ​​first side surface 11 compared to a first side surface 11 without the recess. That is, the area of ​​channel region 111 is significantly increased, thereby increasing the contact area between word line 102 and channel region 111, increasing the channel length of the transistor, and thus enhancing the control capability of word line 102 over the channel region 111 of the transistor.

[0121] In some embodiments, the first sub-pattern layer includes a first non-recessed side opposite the first recessed side, and the second sub-pattern layer includes a second non-recessed side opposite the second recessed side. The first non-recessed side is the side of the first sub-pattern layer without a recess, and the second non-recessed side is the side of the second sub-pattern layer without a recess. In some embodiments, the orthographic projection of the first sub-pattern layer on the surface of the substrate 100 is a "concave" shape, and the orthographic projection of the second sub-pattern layer on the surface of the substrate 100 is a "concave" shape. The recessed side of the "concave" shape of the first sub-pattern layer is the first recessed side, and the non-recessed side opposite the recessed side is the first non-recessed side; the recessed side of the "concave" shape of the second sub-pattern layer is the second recessed side, and the non-recessed side opposite the recessed side is the second non-recessed side. The method for forming word line 102 includes:

[0122] An isolation layer 105 is formed between adjacent semiconductor layers 20 . The isolation layer 105 contacts the sidewalls of the semiconductor layer 20 , and a top surface of the isolation layer 105 is flush with a top surface of the semiconductor layer 20 .

[0123] In some embodiments, reference Figure 10 as well as Figure 11 After forming the bit lines 104, an isolation layer 105 may be formed between adjacent semiconductor layers 20. In some embodiments, a deposition process, such as an atomic layer deposition process or a chemical vapor deposition process, may be used to form the isolation layer 105 between adjacent semiconductor layers 20. In some embodiments, the material of the isolation layer 105 may be silicon nitride or silicon oxynitride.

[0124] refer to Figure 12 as well as Figure 13 A plurality of second patterned layers 31 are formed on the top surface of the isolation layer 105, spaced apart along the first direction X. A second patterned layer 31 is aligned with the gap between the first non-recessed side and the second non-recessed side. The second patterned layer 31 is used to define the shape of the isolation layer 105 to be retained. After the subsequent formation of multiple word lines 102, the isolation layer 105 defined by the second patterned layer 31 can be used to isolate adjacent word lines 102.

[0125] Since each subsequently formed word line 102 covers the first side surface 11 of the first sub-semiconductor pillar 114 and the first side surface 11 of the second sub-semiconductor pillar 115, the first recessed side is used to define the first side surface 11 of the first sub-semiconductor pillar 114, and the second recessed side is used to define the first side surface 11 of the second semiconductor pillar 101. That is, the subsequently formed word line 102 is located in the area between the first recessed side and the second recessed side. Therefore, the second patterned layer 31 is arranged to face the gap between the first non-recessed side and the second non-recessed side, so that the subsequently formed isolation layer 105 and the formed word lines 102 can be staggered, thereby isolating adjacent word lines 102.

[0126] In some embodiments, the second pattern layer 31 may be formed by using either a SADP process or a SAQP process. In some embodiments, the material of the second pattern layer 31 may be any one of a photoresist, a spin-on hard mask, or silicon oxide.

[0127] refer to Figure 14 as well as Figure 15 The semiconductor layer 20 is etched to a second predetermined thickness along the surface of the semiconductor layer 20 not covered by the first patterned layer 30 to form a first trench 40. The isolation layer 105 is etched to a first predetermined thickness along the surface of the isolation layer 105 not covered by the second patterned layer 31 to form a second trench (not shown). The first trench 40 communicates with the second trench. The first trench 40 communicates with the second trench, allowing a subsequently formed word line 102 to be located in both the first trench 40 and the second trench. The word lines 102 located in the first trench 40 and the second trench communicate with each other, forming a word line 102 extending along the second direction Y. In this way, the same word line 102 can cover the first side surface 11 of the channel region 111 of a plurality of first sub-semiconductor pillars 114 arranged at intervals along the second direction Y, and the first side surface 11 of the channel region 111 of a plurality of second sub-semiconductor pillars 115 arranged at intervals along the second direction Y.

[0128] In some embodiments, the semiconductor layer 20 and the isolation layer 105 may be etched using either a dry etching process or a wet etching process.

[0129] refer to Figure 16 as well as Figure 17 In some embodiments, before forming the word line 102 , the process further includes forming a gate dielectric layer 103 on the sidewall of the semiconductor pillar 101 , wherein the gate dielectric layer 103 also fills the gap between the first non-recessed side and the second non-recessed side.

[0130] In some embodiments, a deposition process can be used to form a gate dielectric layer 103 on the surface of the semiconductor pillar 101 in the channel region 111. In some embodiments, the material of the gate dielectric layer 103 can be silicon oxide, and a thermal oxidation process can be used to form the gate dielectric layer 103 on the surface of the semiconductor pillar 101. In some embodiments, the gate dielectric layer 103 located on the non-recessed side of the first sub-semiconductor layer 20 is also connected to the gate dielectric layer 103 located on the non-recessed side of the second sub-semiconductor pillar 115, and the gate dielectric layer 103 located between the first sub-semiconductor pillar 114 and the second sub-semiconductor pillar 115 is directly opposite the isolation layer 105, so that the gate dielectric layer 103 located between the first sub-semiconductor pillar 114 and the second sub-semiconductor pillar 115 serves to isolate the adjacent first sub-semiconductor pillar 114 from the adjacent second sub-semiconductor pillar 115.

[0131] refer to Figures 16 to 19 , a word line 102 is formed filling the first trench 40 and the second trench, and the word line 102 covers the gate dielectric layer 103 .

[0132] refer to Figures 16 and 17 An initial word line 22 is formed on the top surface of the semiconductor pillar 101, the top surface of the isolation layer 105, and the top surface of the gate dielectric layer 103. The initial word line 22 entirely covers the top surface of the semiconductor pillar 101, the top surface of the isolation layer 105, and the surface of the gate dielectric layer 103. The initial word line 22 is located on the surface of the gate dielectric layer 103 in the channel region 111 and on the surface of the gate dielectric layer 103 in the second doped region 113.

[0133] In some embodiments, a deposition process, such as an atomic layer deposition process or a chemical vapor deposition process, may be used to form the initial word line 22. In some embodiments, the material of the initial word line 22 may be a metal material, such as at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or ruthenium.

[0134] refer to Figures 18 and 19 ,in, Figure 19 for Figure 18 In the cross-sectional structural diagram along the AA' direction, the initial word line 22 is patterned to form a plurality of word lines 102 arranged at intervals along the first direction X, each word line 102 extends along the second direction Y, and each word line 102 covers the first side surface 11 of the channel region 111 of each first sub-semiconductor of the plurality of first sub-semiconductor pillars 114 arranged at intervals along the second direction Y, and covers the first side surface 11 of the channel region 111 of each second sub-semiconductor pillar 115 arranged at intervals along the second direction Y.

[0135] In some embodiments, the word line 102 also covers at least a portion of the third side of the channel region 111 of the first sub-semiconductor column 114 and at least a portion of the fourth side of the channel region 111, and the word line 102 also covers at least a portion of the third side of the channel region 111 of the second sub-semiconductor column 115 and at least a portion of the fourth side of the channel region 111.

[0136] In some embodiments, the word line 102 covers a portion of the third side surface and a portion of the fourth side surface of the channel region 111 of the first sub-semiconductor pillar 114, and the word line 102 covers a portion of the third side surface and a portion of the fourth side surface of the channel region 111 of the second sub-semiconductor. Figure 12 , the width of the second pattern layer 31 along the first direction X can be controlled to be greater than the distance between the first non-recessed side and the second non-recessed side. Figure 14, part of the third side and part of the fourth side of the first sub-semiconductor column 114 formed subsequently are opposite to the isolation layer 105, so that the word lines 102 located on both sides of the isolation layer 105 cannot cover the third side and the fourth side opposite to the isolation layer 105, so that the formed word lines 102 only cover part of the third side and part of the fourth side.

[0137] In some embodiments, the word line 102 covers the entire third side surface of the channel region 111 of the first sub-semiconductor column 114 and the entire fourth side surface of the channel region 111, and the word line 102 covers the entire third side surface of the channel region 111 of the second sub-semiconductor column and the entire fourth side surface of the channel region 111. Figure 12 , the second graphic layer 31 can be controlled to be equal to the spacing between the first non-recessed side and the second non-recessed side along the first direction X, so that Figure 14 , part of the third side and part of the fourth side of the first sub-semiconductor column 114 formed subsequently are staggered with the isolation layer 105, so that the word lines 102 located on both sides of the isolation layer 105 cover the entire third side of the channel region 111 and the entire fourth side of the channel region 111.

[0138] In some embodiments, the method of patterning the initial word line 22 may include: performing a patterning process on the top surface of the initial word line 22 to define the position of the word line 102. In some embodiments, the initial word line 22 may be etched using either a SADP process or a SAQP process. Subsequently, the patterned initial word line 22 is etched to remove the gate dielectric layer 103 and the initial word line 22 located on the side of the first sub-semiconductor pillar 114 in the second doped region 113, and to remove the gate dielectric layer 103 and the initial word line 22 located on the side of the second sub-semiconductor pillar 115 in the second doped region 113. The remaining initial word line 22 forms a plurality of word lines 102 arranged in a first direction X, each word line 102 extending in a second direction Y. In some embodiments, the etching process may be either a dry etching process or a wet etching process.

[0139] refer to Figures 20 to 22 , forming an isolation structure 106 . The isolation structure 106 is used to isolate the adjacent semiconductor pillars 101 corresponding to the second doping regions 113 .

[0140] In some embodiments, a method of forming the isolation structure 106 may include:

[0141] refer to Figures 20 to 21, forming an initial isolation structure 23. The initial isolation structure 23 is located on the top surface of the word line 102, the top surface of the gate dielectric layer 103, and the top surface of the second doped region 113, and is also located between adjacent semiconductor pillars 101 corresponding to the second doped region 113. In some embodiments, a deposition process, such as an atomic layer deposition process, can be used to form the initial isolation structure 23. The material of the initial isolation structure 23 can be silicon nitride.

[0142] refer to Figure 22 The initial isolation structure 23 is etched to expose the top surface of the semiconductor pillar 101 in the second doped region 113. The remaining initial isolation structure 23 forms the isolation structure 106. In this way, other conductive structures, such as a capacitor structure, can be formed on the top surface of the semiconductor pillar 101 corresponding to the second doped region 113.

[0143] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a semiconductor column located on the surface of the substrate, the semiconductor column having a channel region and a first side surface, wherein at least a portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor column; a word line, the word line at least covering the first side surface corresponding to the channel region; In which, the semiconductor column also includes: doped regions located on both sides of the channel region, the arrangement direction of the channel region and the doped regions is perpendicular to the substrate surface, and the portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor column to form a first groove, the first groove extends in a direction away from the substrate surface, and the first groove spans the doped region and the channel region.

2. The semiconductor structure according to claim 1, wherein: A portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor column to form a first groove. There are a plurality of first grooves, and the plurality of first grooves are arranged at intervals.

3. The semiconductor structure according to claim 1, wherein: The semiconductor pillar has a second side surface opposite to the first side surface. A portion of the second side surface corresponding to the channel region is recessed toward the center of the semiconductor pillar, and the word line also covers the second side surface corresponding to the channel region.

4. The semiconductor structure according to claim 1, wherein: There are multiple semiconductor pillars, and the multiple semiconductor pillars include: first sub-semiconductor pillars and second sub-semiconductor pillars alternately arranged along a first direction, wherein the first side surface of the first sub-semiconductor pillar and the first side surface of the second sub-semiconductor pillar are arranged opposite to each other along the first direction.

5. The semiconductor structure according to claim 4, wherein: The word line covers a first side surface of the channel region of the first sub-semiconductor column and a first side surface of the channel region of the second sub-semiconductor column which are oppositely arranged.

6. The semiconductor structure according to claim 5, wherein: The first sub-semiconductor pillar and the second sub-semiconductor pillar each include a second side surface opposite to the first side surface, and the second side surface is exposed outside the word line.

7. The semiconductor structure according to claim 6, wherein: The first sub-semiconductor column and the second sub-semiconductor column both include: a third side surface connected to the first side surface, and a fourth side surface arranged opposite to the third side surface. The word line also covers at least a portion of the third side surface and at least a portion of the fourth side surface of the first sub-semiconductor column, and covers at least a portion of the third side surface and at least a portion of the fourth side surface of the second sub-semiconductor column.

8. The semiconductor structure according to any one of claims 5 to 7, wherein: The semiconductor structure comprises: A plurality of rows of first sub-semiconductor pillars arranged at intervals along the first direction, wherein each row of the first sub-semiconductor pillars includes a plurality of first sub-semiconductor pillars arranged at intervals along the second direction; A plurality of rows of second sub-semiconductor columns are arranged at intervals along the second direction, each row of the second sub-semiconductor columns includes a plurality of second sub-semiconductor columns arranged at intervals along the second direction, and each row of the first sub-semiconductor columns and each row of the second sub-semiconductors are alternately arranged along the first direction; there are a plurality of word lines, and each word line covers the first side surface corresponding to the channel region in a row of the first sub-semiconductor columns and a row of the second sub-semiconductors that are alternately arranged.

9. The semiconductor structure according to claim 1 or 5, characterized in that: Also includes: a gate dielectric layer, the gate dielectric layer being located between the word line and the semiconductor pillar; There are multiple semiconductor pillars, and the multiple semiconductor pillars include: first sub-semiconductor pillars and second sub-semiconductor pillars arranged alternately along a first direction, a word line covers the first side surface of the channel region of a first sub-semiconductor pillar and the first side surface of the channel region of a second sub-semiconductor pillar that are relatively arranged, and the gate dielectric layer covers the entire side surface of the channel region of the first sub-semiconductor pillar corresponding to a word line and the entire side surface of the channel region of the second sub-semiconductor pillar corresponding to another adjacent word line.

10. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; A semiconductor pillar is formed on the surface of the substrate, wherein the semiconductor pillar has a channel region and a first side surface, wherein at least a portion of the first side surface corresponding to the channel region is recessed toward a center of the semiconductor pillar; wherein the semiconductor pillar further has doped regions formed on both sides of the channel region, wherein the channel region and the doped regions are arranged in a direction perpendicular to the substrate surface, wherein a portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor pillar to form a first groove, wherein the first groove extends in a direction away from the substrate surface and spans the doped region and the channel region; A word line is formed, where the word line at least covers the first side surface corresponding to the channel region.

11. The method for preparing a semiconductor structure according to claim 10, wherein: The method of forming the semiconductor pillar includes: providing an initial substrate; etching a portion of the initial substrate to form semiconductor layers spaced apart along the second direction, with the remaining portion of the initial substrate serving as the substrate; forming a first pattern layer on a portion of the surface of the semiconductor layer, wherein the first pattern layer is used to define a cross-sectional shape of the semiconductor column parallel to the surface of the substrate; The semiconductor layer not covered by the first pattern layer is etched, and the remaining portion of the semiconductor layer forms the semiconductor pillar.

12. The method for preparing a semiconductor structure according to claim 11, wherein: The plurality of semiconductor pillars include: first sub-semiconductor pillars and second sub-semiconductor pillars alternately arranged along a first direction, wherein the first side surfaces of the first sub-semiconductor pillars and the first side surfaces of the second sub-semiconductor pillars are arranged opposite to each other along the first direction, and a word line covers the first side surfaces of the channel regions of the first sub-semiconductor pillars and the first side surfaces of the channel regions of the second sub-semiconductor pillars that are arranged opposite to each other. The method of forming the semiconductor pillars includes: forming a first patterned layer on a portion of the surface of the semiconductor layer, the first patterned layer comprising first sub-patterned layers and second sub-patterned layers alternately arranged along the first direction, the first sub-patterned layer comprising a first concave side having a first concave, the second sub-patterned layer comprising a second concave side having a second concave, the first concave side and the second concave side being arranged opposite to each other along the first direction; The semiconductor layer not covered by the first sub-pattern layer and the semiconductor layer not covered by the second sub-pattern layer are etched, and the remaining portion of the semiconductor layer forms the semiconductor pillar.

13. The method for preparing a semiconductor structure according to claim 12, wherein: The orthographic projection shape of the first sub-pattern layer on the surface of the base is a "concave" shape, and the orthographic projection shape of the second sub-pattern layer on the surface of the base is a "concave" shape.

14. The method for preparing a semiconductor structure according to claim 12 or 13, wherein: The first sub-pattern layer includes a first non-recessed side opposite to the first recessed side, and the second sub-pattern layer includes a second non-recessed side opposite to the second recessed side. The method for forming the word line includes: forming an isolation layer between adjacent semiconductor layers, wherein the isolation layer contacts the sidewalls of the semiconductor layer and the top surface of the isolation layer is flush with the top surface of the semiconductor layer; forming a plurality of second pattern layers spaced apart along a first direction on a top surface of the isolation layer, wherein the second pattern layers are directly opposite to the gap between the first non-recessed side and the second non-recessed side; Etching the semiconductor layer to a second preset thickness along the surface of the semiconductor layer not covered by the first patterned layer to form a first trench, and etching the isolation layer to a first preset thickness along the surface of the isolation layer not covered by the second patterned layer to form a second trench, wherein the first trench is connected to the second trench; forming a gate dielectric layer on the sidewall of the semiconductor pillar, wherein the gate dielectric layer also fills the gap between the first non-recessed side and the second non-recessed side; The word line is formed to fill the first trench and the second trench, and the word line covers the gate dielectric layer.

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