Semiconductor devices and their fabrication methods, storage systems

Abstract

This application provides a semiconductor device and a method for fabricating the same, as well as a memory system. The semiconductor device includes a stacked structure and a capacitive contact structure. The stacked structure includes alternating first dielectric layers and gate layers. The capacitive contact structure includes, from the outside in, a first conductive layer, a first insulating dielectric layer, and a second conductive layer, wherein the first conductive layer extends along the stacking direction in the stacked structure and is connected to the corresponding gate layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of a semiconductor device, a method for fabricating a semiconductor device, and a memory system. Background Technology

[0002] Taking 3D memory as an example, some semiconductor devices include stacked structures. As the number of stacked layers in the stacked structure increases, the etching depth required for the contact holes (CTs) extending to different word lines (WLs) becomes increasingly greater, placing higher demands on the CT etching process and the etching stop layer process. To reduce the process difficulty and simplify the process steps, the SCT (self-align contact) architecture has been proposed in related technologies. The SCT process uses a stair step (SS) cutting process to precisely stop the contact holes on each WL layer, thereby merging the SS process and the CT process.

[0003] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0004] The embodiments of this application provide semiconductor devices, methods for fabricating them, and storage systems that can at least partially solve the above-mentioned problems or other problems existing in the related technologies.

[0005] This application provides a semiconductor device comprising: a stacked structure including alternating stacked first dielectric layers and gate layers; and a capacitive contact structure including, from the outside in, a first conductive layer, a first insulating dielectric layer, and a second conductive layer, wherein the first conductive layer extends in the stacked structure along the stacking direction and is connected to the corresponding gate layer.

[0006] In one embodiment of this application, the capacitive contact structure further includes a third conductive layer and a second insulating dielectric layer located between the second conductive layer and the third conductive layer.

[0007] In one embodiment of this application, the first conductive layer includes a first portion and a second portion connected to each other, wherein the first portion extends in the stacked structure along the stacking direction; and the second portion extends in a plane perpendicular to the stacking direction and connects the first portion and the corresponding gate layer.

[0008] In one embodiment of this application, the capacitive contact structure further includes a sidewall barrier layer, which is located between the stacked structure and the first portion.

[0009] In one embodiment of this application, in a plane perpendicular to the stacking direction, the projection of the second portion overlaps the projection of the first portion.

[0010] In one embodiment of this application, the projection of the first portion is annular in a plane perpendicular to the stacking direction.

[0011] In one embodiment of this application, the first insulating dielectric layer covers the surface of the first conductive layer; and the second conductive layer covers the surface of the first insulating dielectric layer, wherein the extension length of the first conductive layer in the stacking direction is greater than the extension length of the second conductive layer in the stacking direction.

[0012] In one embodiment of this application, the third conductive layer includes a conductive material layer and an insulating filler layer surrounded by the conductive material layer.

[0013] In one embodiment of this application, the second conductive layer includes at least one of a semiconductor material layer and a metal material layer; and / or the third conductive layer includes at least one of a semiconductor material layer and a metal material layer.

[0014] In one embodiment of this application, the first conductive layer and the second conductive layer have the same thickness; and / or the second conductive layer and the third conductive layer have the same thickness.

[0015] In one embodiment of this application, the second conductive layer and the third conductive layer comprise the same material.

[0016] In one embodiment of this application, the stacked structure includes a memory region and a connection region adjacently distributed in a plane perpendicular to the stacking direction, wherein the gate layer extends from the memory region into the connection region, and the connection region further includes a second dielectric layer alternately stacked with the first dielectric layer, wherein the first conductive layer penetrates through a plurality of the second dielectric layers in the connection region along the stacking direction and is connected to the corresponding gate layer.

[0017] This application also provides a method for fabricating a semiconductor device, the method comprising:

[0018] In one embodiment of this application, a stacked structure is formed, the stacked structure including alternating stacked first dielectric layers and gate layers; and a capacitor contact structure is formed, wherein the capacitor contact structure includes, from the outside to the inside, a first conductive layer, a first insulating dielectric layer and a second conductive layer, the first conductive layer extending in the stacked structure along the stacking direction and connected to the corresponding gate layer.

[0019] In one embodiment of this application, forming a stacked structure includes: alternately stacking a first dielectric layer and a second dielectric layer to form a stacked structure; removing a portion of the second dielectric layer to form a sacrificial void; and forming the gate layer in the sacrificial void.

[0020] In one embodiment of this application, the stacked structure includes a predetermined storage area and a predetermined connection area distributed adjacent to each other in a plane perpendicular to the stacking direction. Forming the sacrificial void includes: forming a gate wire slot that penetrates the stacked structure along the stacking direction, wherein the gate wire slot includes a first gap located in the predetermined storage area and a second gap located in the predetermined connection area; filling the first gap and removing a portion of the second dielectric layer based on the second gap to form a first void; exposing the first gap and filling the second gap and the first void; and based on the exposed first gap, continuing to remove a portion of the second dielectric layer to form a second void, wherein the first void and the second void, which are interconnected, form the sacrificial void.

[0021] In one embodiment of this application, forming a capacitive contact structure includes: forming a first opening in a second dielectric layer extending along the stacking direction to a predetermined stacking height; forming a sidewall barrier layer on the sidewall of the first opening; removing a portion of the second dielectric layer that contacts the bottom of the first opening to form a second opening; and sequentially forming a first conductive layer, a first insulating dielectric layer, and a second conductive layer in the first opening and the second opening.

[0022] In one embodiment of this application, the method further includes: sequentially forming a second insulating dielectric layer and a third conductive layer on the surface of the second conductive layer.

[0023] In one embodiment of this application, the second conductive layer is formed using at least one of a semiconductor material and a metal material; and / or the third conductive layer is formed using at least one of a semiconductor material and a metal material.

[0024] In one embodiment of this application, forming the third conductive layer includes: forming a conductive material layer on the surface of the second insulating dielectric layer; and forming an insulating fill layer on the surface of the conductive material layer to fill the remaining space of the first opening.

[0025] In another aspect, this application provides a storage system comprising: a controller; and the semiconductor device provided in any one aspect of this application, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0026] In one embodiment of this application, the semiconductor device includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0027] The semiconductor device and its fabrication method, as well as the memory system provided according to at least one embodiment of this application, eliminate the need to form steps and word line contacts on the steps in the semiconductor device. Specifically, the semiconductor device may include a stacked structure and multiple capacitive contact structures disposed in the stacked structure. The first conductive layer of the capacitive contact structure enables electrical communication between the gate layer located at different stacking heights and the external circuit. Therefore, while simplifying the fabrication process and reducing production costs, it can improve the unit storage density, reliability, and overall performance of the semiconductor device.

[0028] Furthermore, the capacitive contact structure also includes a second conductive layer and a first insulating dielectric layer located between the first and second conductive layers. The first conductive layer, the second conductive layer, and the first insulating dielectric layer form a capacitor structure. Therefore, the capacitive contact structure not only enables electrical communication between the gate layer at different stack heights and external circuits, but also utilizes its internal space to form the capacitor structure required for semiconductor devices. This improves the overall performance of semiconductor devices while effectively increasing the unit storage density and reducing the price per unit storage cell. Attached Figure Description

[0029] Other features, objects, and beneficial effects of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings:

[0030] Figure 1 This is a partial cross-sectional schematic diagram of a semiconductor device according to one embodiment of this application;

[0031] Figure 2 yes Figure 1 A top view of a cross-section taken along line B-B' of a semiconductor device is shown.

[0032] Figure 3 yes Figure 2 The diagram shown is a top-view magnified schematic of the semiconductor device at point A;

[0033] Figure 4 This is a partial cross-sectional schematic diagram of a semiconductor device according to another embodiment of this application;

[0034] Figure 5 yes Figure 4 A top view of a semiconductor device taken along line D-D';

[0035] Figure 6 yes Figure 4 The diagram shows an enlarged cross-sectional view of the semiconductor device at point C;

[0036] Figure 7 This is a flowchart of a method for fabricating a semiconductor device according to one embodiment of this application;

[0037] Figures 8A-10 These are schematic diagrams illustrating a method for fabricating a semiconductor device according to one embodiment of this application; and

[0038] Figure 11 This is a schematic diagram of a storage system structure according to one embodiment of this application.

[0039] Specific methods

[0040] The present application will now be described in detail with reference to the accompanying drawings. The exemplary embodiments mentioned herein are for illustrative purposes only and are not intended to limit the scope of the application. Throughout the specification, the same reference numerals refer to the same elements.

[0041] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation rather than degree and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0042] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprising," "including," "having," "having," and / or "having have" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. When describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0043] In addition, when terms such as “connection,” “covering,” and / or “formed on” are used in this application, they may indicate that the corresponding components are in direct or indirect contact, unless there are other explicit limitations or can be inferred from the context.

[0044] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Furthermore, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formalized sense.

[0045] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0046] Figure 1 This is a partial cross-sectional schematic diagram of a semiconductor device 1000 according to one embodiment of this application. Figure 2 yes Figure 1 The diagram shows a top view of a cross-section of a semiconductor device taken along line B-B'. Figure 3 yes Figure 2 The diagram shows a magnified top view of the semiconductor device at point A. Figure 4 This is a partial cross-sectional schematic diagram of a semiconductor device 1000 according to another embodiment of this application. Figure 5 yes Figure 4 The diagram shows a top view of a cross-section of a semiconductor device taken along line D-D'. Figure 6 yes Figure 4 The diagram shows an enlarged cross-sectional view of the semiconductor device at point C.

[0047] like Figures 1-6 As shown, the semiconductor device 1000 may include a stacked structure 200 and a capacitor contact structure 500. The stacked structure 200 includes a plurality of alternately stacked first dielectric layers 210 and a plurality of gate layers 230. The capacitor contact structure 500 includes, from the outside in, a first conductive layer 530, a first insulating dielectric layer 34, and a second conductive layer 540. The first conductive layer 530 extends in the stacked structure 200 along the stacking direction (z-direction) and is electrically connected to the corresponding gate layer.

[0048] The semiconductor device provided according to at least one embodiment of this application eliminates the need to form steps and word line contacts on the steps within the semiconductor device. Specifically, the semiconductor device may include a stacked structure and multiple capacitive contact structures disposed within the stacked structure. The first conductive layer of the capacitive contact structure enables electrical communication between the gate layer located at different stack heights and external circuits. Therefore, while simplifying the fabrication process and reducing production costs, it can improve the unit storage density, reliability, and overall performance of the semiconductor device.

[0049] Furthermore, the capacitive contact structure also includes a second conductive layer and a first insulating dielectric layer located between the first and second conductive layers. The first conductive layer, the second conductive layer, and the first insulating dielectric layer form a capacitor structure. Therefore, the capacitive contact structure not only enables electrical communication between the gate layer at different stack heights and external circuits, but also utilizes its internal space to form the capacitor structure required for semiconductor devices. This improves the overall performance of semiconductor devices while effectively increasing the unit storage density and reducing the price per unit storage cell.

[0050] Specifically, the stacked structure 200 may be disposed on a substrate and includes a memory region 01 and a connection region 02 that are adjacently distributed in a plane parallel to the substrate (xy plane, where the x, y and z directions are perpendicular to each other). The memory region 01 includes a plurality of alternatingly stacked first dielectric layers 210 and a plurality of gate layers 230; the connection region 02 includes a plurality of alternatingly stacked first dielectric layers 210 and a plurality of second dielectric layers 220.

[0051] Gate layer 230 may include a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides. First dielectric layer 210 may be used as an isolation stack layer, including but not limited to an insulating dielectric material layer such as a silicon oxide layer. The first dielectric layer 210 and the second dielectric layer 220 may be two different insulating dielectric material layers; for example, the second dielectric layer 220 may include, but is not limited to, an insulating dielectric material layer such as a silicon nitride layer. Furthermore, the plurality of second dielectric layers 220 and the plurality of gate layers 230 may have the same stack height. Additionally, the number of layers in the stack structure 200 is not limited to the number shown in the figure and may be set as needed, such as 32 layers, 64 layers, 128 layers, etc.

[0052] In other words, the connection region 02 may include alternately stacked first dielectric layers 210 and composite layers, wherein each of the plurality of composite layers may include second dielectric layers 220 and gate layers 230 distributed and connected to each other in the xy plane. Each of the plurality of capacitive contact structures 500 extends in the connection region 02 along the z-direction in the stacked structure 200. The gate layer 230 extends from the storage region 01 into the connection region 02, and the first conductive layer 530 passes through the plurality of second dielectric layers 220 along the z-direction and is electrically connected to the corresponding gate layer.

[0053] Taking 3D memory as an example, semiconductor devices typically consist of a stacked structure formed by alternating gate and dielectric layers. Word line contacts located in the step regions of the stacked structure enable electrical communication between the gate layer and external circuitry. However, as the number of stacked layers increases, forming word line contacts in the step regions requires multiple processes such as photolithography and etching to create the stepped morphology of the steps, significantly increasing the manufacturing cost of semiconductor devices. Furthermore, the more steps there are, the larger the area of ​​the step regions needs to be, which is detrimental to improving the integration density of semiconductor devices. In addition, the more stacked layers there are, the more pronounced the wafer warpage becomes, making alignment between the word line contacts and the step surfaces in the step regions more difficult. This leads to decreased reliability or low electrical test yield, ultimately affecting the reliability and overall performance of the semiconductor device.

[0054] The semiconductor device provided in this application does not require the formation of steps and word line contacts on the steps. By providing multiple capacitive contact structures in the second region of the stacked structure, electrical communication between the gate layer at different stacking heights and the external circuit can be achieved. Therefore, while simplifying the fabrication process and reducing the production cost, the unit storage density, reliability and overall performance of the semiconductor device can be improved.

[0055] Furthermore, the capacitor contact structure also includes a second conductive layer and a first insulating dielectric layer located between the first and second conductive layers. The first conductive layer, the second conductive layer, and the first insulating dielectric layer form a capacitor structure. Therefore, the capacitor contact structure not only enables electrical communication between the gate layer at different stack heights and external circuits, but also utilizes its internal space to form the capacitor structure required for semiconductor devices. For example, the capacitor structure of this capacitor contact structure can be used in CMOS charge pump (Complementary Metal Oxide Semiconductor charge pump) circuits required for the peripheral circuits of semiconductor devices. Therefore, while improving the overall performance of semiconductor devices, it effectively increases the unit storage density and reduces the price per unit storage cell.

[0056] In addition, refer to Figure 1 and Figure 4 In one embodiment of this application, the capacitor contact structure 500 further includes a third conductive layer 550 and a second insulating dielectric layer 45 located between the second conductive layer 540 and the third conductive layer 550.

[0057] In other words, the capacitor contact structure 500 may include multiple capacitor structures, such as Figure 1 and Figure 4Capacitor contact structures 500 including two capacitor structures are shown, wherein a first conductive layer 530, a first insulating dielectric layer 34 and a second conductive layer 540 can form a first capacitor structure; and a second conductive layer 540, a second insulating dielectric layer 45 and a third conductive layer 550 can form a second capacitor structure.

[0058] Those skilled in the art will understand that the number of capacitor structures shown in the figures is for illustrative purposes only and is not a limitation of this application. The specific number of capacitor structures in the capacitor contact structure can be set according to actual needs. Alternatively, the multiple capacitor contact structures 500 may include the same number of capacitor structures; alternatively, the multiple capacitor contact structures 500 may include different numbers of capacitor structures. The specific number of capacitor structures included in the capacitor contact structure in the semiconductor device can be set according to actual needs.

[0059] Furthermore, with the increasing demand for storage capacity in semiconductor devices, the number of aforementioned memory stacks is gradually increasing. The stack structure 200 may include multiple sub-stack structures formed using techniques such as dual-stack or multi-stack. These multiple sub-stack structures may be stacked sequentially in the stacking direction to form the stack structure 200, wherein each sub-stack structure may include adjacent memory regions and interconnect regions distributed in a plane perpendicular to the stacking direction. The memory regions include a first dielectric layer and a gate layer stacked on top of each other, and the interconnect regions include a first dielectric layer and a second dielectric layer stacked on top of each other. The number of layers in each sub-stack structure may be the same or different. The content of a single stack structure described herein is wholly or partially applicable to stack structures formed by multiple sub-stack structures; therefore, related or similar content will not be repeated.

[0060] Refer again Figure 4 and Figure 6 Alternatively, in one embodiment of this application, the first conductive layer 530 includes a first portion 21 and a second portion 22 connected to each other, wherein the first portion 21 extends in the stacked structure 200 along a direction approximately z-direction, and the second portion 22 extends in the xy plane and connects the first portion 21 and the corresponding gate layer.

[0061] In addition, the conductive material forming the first conductive layer 530 may include any one or a combination of conductive metal materials and doped semiconductor materials. The conductive metal materials may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor materials may be, for example, doped crystalline silicon or silicides, etc. This application does not limit the specific materials used.

[0062] In one embodiment of this application, the capacitor contact structure 500 may further include a sidewall barrier layer 520, which is located between the stacked structure 200 and the first portion 530. The sidewall barrier layer 520 prevents the first portion 530 from forming a connection with the remaining gate layers in the stacked structure 200 except for the corresponding gate layer, thereby achieving electrical communication between the corresponding gate layer and the external circuit through the capacitor contact structure. Furthermore, as described above, the connection region 02 may include alternately stacked first dielectric layers 210 and composite layers, wherein each of the plurality of composite layers may include a second dielectric layer 220 and a gate layer 230 distributed and connected to each other in the xy plane. During the fabrication of the capacitor contact structure 500, under the protection of the sidewall barrier layer 520, by means of, for example, a dry etching process or a combination of dry and wet etching processes, only a portion of the second dielectric layer in the composite layer containing the corresponding gate layer can be removed, without removing a portion of the second dielectric layer in the remaining composite layers that have a different stacking height from the corresponding gate layer.

[0063] Refer again Figures 4-6 In one embodiment of this application, in the xy plane, the projection of the second part overlaps the projection of the first part.

[0064] In other words, the stacked structure 200 includes a storage region 01 and a connection region 02. The connection region 02 may include an insulating dielectric material stack layer formed by mutually stacked first dielectric layers 210 and second dielectric layers 220. A capacitor contact structure 500 is disposed in the connection region. A first portion 21 of the first conductive layer 530 extends along the z-direction in the insulating dielectric material stack layer and connects to a second portion 22 at the corresponding gate layer stack height. By setting the projection of the second portion 22 to cover the projection of the first portion 21, the second portion 22 can extend along the xy-direction and connect to the corresponding gate layer. While achieving electrical communication between the capacitor contact structure and the corresponding gate layer, short circuits between different gate layers can be prevented.

[0065] Furthermore, in the semiconductor device provided in at least one embodiment of this application, the projection of the first portion 21 of the first conductive layer 530 in the xy plane is annular.

[0066] The capacitive contact structure 500 can be accommodated in a pre-formed contact hole. Alternatively, the first conductive layer of a conventional contact structure can fill the contact hole, including the sidewall barrier layer 520. However, in the semiconductor device provided in at least one embodiment of this application, the projection of the first portion 21 of the first conductive layer 530 is annular. In other words, the first conductive layer 530 is located on the surface of the sidewall barrier layer 520 and on the sidewall of the contact hole, the first portion 21 of the first conductive layer 530 is located on the surface of the sidewall barrier layer 520, and the second portion 22 of the first conductive layer 530 is located on the sidewall of the contact hole.

[0067] Considering that the material forming the first conductive layer 530 typically includes any one or a combination of conductive metal materials and doped semiconductor materials, where the conductive metal material can be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor material can be, for example, doped crystalline silicon or silicides, setting the projection of the first portion 21 of the first conductive layer 530 as an annular shape can reduce the manufacturing cost of semiconductor devices and reduce the stress deformation of the stacked structure caused by the capacitor contact structure. Simultaneously, it allows for the formation of a capacitor structure in most of the remaining space on the inner wall of the capacitor contact structure 500. For example, by utilizing the internal space of the capacitor contact structure 500 itself to form the capacitor structure required for the semiconductor device, the overall performance of the semiconductor device can be improved while effectively increasing the unit storage density and reducing the price per unit storage cell.

[0068] In addition, such as Figure 1 and Figure 4 As shown, in one embodiment of this application, a first insulating dielectric layer 34 may cover the surface of a first conductive layer 530; and a second conductive layer 540 may cover the surface of a first insulating dielectric layer 34, wherein the extension length of the first conductive layer 530 in the z direction is greater than the extension length of the second conductive layer 540 in the z direction.

[0069] In addition, such as Figure 1 and Figure 3 As shown, in one embodiment of this application, the third conductive layer 550 may include a conductive material layer 550-2 and an insulating filler layer 550-1 surrounded by the conductive material layer 550-2.

[0070] In other words, the capacitor contact structure 500 may include multiple capacitor structures, such as Figure 1 A capacitor contact structure 500 including two capacitor structures is shown, wherein a first conductive layer 530, a first insulating dielectric layer 34, and a second conductive layer 540 can form a first capacitor structure; a second conductive layer 540, a second insulating dielectric layer 45, and a third conductive layer 550 can form a second capacitor structure. In a plurality of capacitor structures arranged sequentially from the outside in, the innermost conductive layer can be a composite structure. The innermost conductive layer may include a conductive material layer and an insulating filler layer surrounded by the conductive material layer. This configuration can reduce the manufacturing cost of semiconductor devices and reduce stress deformation of the stacked structure caused by the capacitor contact structure.

[0071] Optionally, in one embodiment of this application, the second conductive layer 540 may include any one or a combination of a conductive metal material layer and a semiconductor material layer, wherein the material used to form the conductive metal material layer may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the material used to form the semiconductor material layer may be, for example, crystalline silicon or silicides, etc.

[0072] Furthermore, the third conductive layer 550 may include any one or a combination of a conductive metal material layer and a semiconductor material layer, wherein the material used to form the conductive metal material layer may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the material used to form the semiconductor material layer may be, for example, crystalline silicon or silicides, etc.

[0073] In addition, to simplify the manufacturing process and save manufacturing costs, the same process and the same materials can be used to form multiple conductive layers, such as a second conductive layer, a third conductive layer, etc., included in the capacitor contact structure 500.

[0074] Optionally, the first conductive layer 530 and the second conductive layer 540 may have the same thickness. Alternatively, the second conductive layer 540 and the third conductive layer 550 may have the same thickness. Alternatively, the first conductive layer 530, the second conductive layer 540, and the third conductive layer 550 may all have the same thickness.

[0075] like Figure 1 and Figure 2 As shown, in one embodiment of this application, the semiconductor device 1000 may further include a gate line slot structure 400. The gate line slot structure 400 may pass through the storage region 01 in the z-direction and extend in the y-direction. Alternatively, the gate line slot structure 400 may pass through the connection region 02 in the z-direction and extend in the y-direction.

[0076] Furthermore, the semiconductor device 1000 also includes a channel structure 300 extending along the z-direction in the memory region 01 of the stacked structure 200. The channel structure 300 may include a semiconductor layer and a composite dielectric layer filled in the channel via, for example, a functional layer and a channel layer sequentially formed on the inner wall of the channel via. In addition, the channel structure 300 may also include a channel-filling dielectric layer that can fill the remaining space in the channel via after the functional layer and the channel layer have been formed.

[0077] The functional layer may include a barrier layer, a charge trapping layer, and a tunneling layer sequentially disposed on the inner wall of the channel aperture. Alternatively, the channel aperture may have a cylindrical or columnar shape extending along the z-direction in the stack structure 200. Similar to the channel aperture, the functional layer may also have a cylindrical or columnar shape extending along the z-direction in the stack structure 200.

[0078] The channel layer may be located on the surface of the tunneling layer and can be used to transport the required charge (electrons or holes). The channel layer may also have a cylindrical or columnar shape extending along the z-direction in the stack structure 200. The channel layer may be fabricated from a semiconductor material such as polycrystalline silicon or monocrystalline silicon and may contain conductive impurities. For example, the channel layer may be an N-type doped or P-type doped polycrystalline silicon layer.

[0079] Additionally, the semiconductor device 1000 may also include a virtual channel structure (not shown). Alternatively, the channel structure 300 and the virtual channel structure may have partially identical internal structures. For example, when forming the functional layer, channel layer, and channel-filling dielectric layer of the channel structure 300, the functional layer, channel layer, and channel-filling dielectric layer may also be filled in the virtual channel vias of the virtual channel junction.

[0080] In addition, as an alternative, since virtual channel structures do not have storage capabilities, insulating dielectric material layers such as silicon oxide layers can typically be filled into the virtual channel holes of the virtual channel structure.

[0081] Figure 7 This is a flowchart of a method for fabricating a semiconductor device according to one embodiment of this application, 2000. Figures 8A-10 These are schematic diagrams of a semiconductor device fabrication method 2000 according to one embodiment of this application.

[0082] like Figure 7 As shown, the semiconductor device fabrication method 2000 may include:

[0083] S1, forming a stacked structure, the stacked structure comprising alternating stacked first dielectric layers and gate layers.

[0084] S2, forming a capacitor contact structure, wherein the capacitor contact structure includes a first conductive layer, a first insulating dielectric layer and a second conductive layer from the outside to the inside, the first conductive layer extends in the stacked structure along the stacking direction and is connected to the corresponding gate layer.

[0085] The following will combine Figures 7 to 10 The specific process of each step of the above preparation method 2000 in one embodiment of this application is described in detail.

[0086] Step S1

[0087] Figure 8A This is a cross-sectional schematic diagram of the structure formed after forming a stacked structure 200' according to a preparation method of one embodiment of this application. Figure 8B This is a cross-sectional schematic diagram of the structure formed after forming the conductive layer 530 according to a preparation method of one embodiment of this application.

[0088] like Figure 7 and Figure 8A As shown, step S1 forms a stacked structure, which includes alternating stacked first dielectric layers and gate layers. For example, it may include: alternating stacking of first dielectric layer 210 and second dielectric layer 220 to form a stacked structure 200'; removing a portion of the second dielectric layer 220 to form a sacrificial void (not shown); and forming a gate layer 230 in the sacrificial void.

[0089] Specifically, in one embodiment of this application, step S1, forming the stacked structure, may further include providing an initial substrate. The material used to prepare the initial substrate can be any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide, or other group III-V compounds. Alternatively, the initial substrate may be single-crystal silicon.

[0090] In one embodiment of this application, the initial substrate may be, for example, a composite substrate, for supporting the device structure thereon. Multiple layers made of different materials may be sequentially deposited to form the initial substrate using thin film deposition processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

[0091] In one embodiment of this application, the initial substrate may include a substrate sacrificial layer for subsequent formation of a semiconductor interconnect layer of a connection channel structure. The substrate sacrificial layer may include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the substrate sacrificial layer may be a high-dielectric-constant dielectric layer. Alternatively, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer, and a dielectric layer sequentially disposed, wherein the dielectric layer may be a silicon nitride layer, and the sacrificial layer may be a silicon oxide layer. Yet another option is that the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer may be monocrystalline silicon or polycrystalline silicon. Specifically, in one embodiment of this application, an exemplary material for forming the sacrificial layer may be polycrystalline silicon.

[0092] A portion of the initial substrate may also form well regions doped with N-type or P-type dopants via ion implantation or diffusion processes. Dopants may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb); or any one or a combination of boron (B), gallium (Ga), or indium (In). In some embodiments of this application, the well regions may be prepared using the same or different dopants; furthermore, the doping concentration of the well regions may be the same or different, and this application does not limit this.

[0093] After the initial substrate is formed, a stacked structure 200' can be formed on the initial substrate by one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and this application does not limit them.

[0094] The stacked structure 200' may include multiple pairs of first dielectric layers 210 and second dielectric layers 220 that are stacked alternately with each other. For example, the stacked structure 200' may include 64 pairs, 128 pairs, or more than 128 pairs of first dielectric layers 210 and second dielectric layers 220.

[0095] In some embodiments, the first dielectric layer 210 and the second dielectric layer 220 may each comprise a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials used to form the first dielectric layer 210 and the second dielectric layer 220 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stack layer, while the silicon nitride layer may be used as a sacrificial stack layer. Subsequently, a portion of the sacrificial stack layer may be etched away, and the etched portion of the sacrificial stack layer may be replaced with a conductive layer comprising a conductive material to form the gate layer of the semiconductor device.

[0096] In addition, the stacked structure 200' may also include a capping layer located at the highest point of the stack. The capping layer includes, but is not limited to, an insulating dielectric material layer such as a silicon oxide layer.

[0097] The fabrication method for a single stacked structure has been described above. In fact, with the increasing demand for storage capacity in semiconductor devices, the size of storage stacks is gradually increasing. To overcome the limitations of traditional processes, dual-stack or multi-stack techniques can be used to form a stacked structure by sequentially stacking multiple sub-stacked structures along the thickness direction of the stacked structure. Each sub-stacked structure may include multiple alternating layers of first and second dielectric layers. The number of layers in each sub-stacked structure may be the same or different. Since the fabrication process and structure of the single stacked structure described above are fully or partially applicable to the stacked structure comprising multiple sub-stacked structures described herein, related or similar content will not be repeated. However, those skilled in the art will understand that subsequent fabrication processes can be performed based on multi-stacked or single-stacked structures.

[0098] Furthermore, in one embodiment of this application, step S1 forming the stacked structure may further include: forming a channel structure 300 and a virtual channel structure (not shown) in the stacked structure 200'; forming a gate line gap (not shown) in the stacked structure 200'; removing a portion of the second dielectric layer 220 via the gate line gap to form a gate layer 230; and forming a gate line gap structure 400, thereby forming the stacked structure 200.

[0099] In one embodiment of this application, a first region 01' and a second region 02' may be defined adjacently on the surface of an initial substrate. Subsequently, a stacked structure is formed on the surface of the initial substrate. The stacked structure may include storage regions and connection regions adjacently distributed in a plane parallel to the initial substrate (a plane perpendicular to the stacking direction), wherein the storage regions and connection regions may be formed in the first region 01' and the second region 02', respectively, and include stacked layers formed of different materials.

[0100] Specifically, in one embodiment of this application, a channel structure 300 and a virtual channel structure may be formed in the stacked structure 200'. Forming a plurality of channel structures 300 extending in the z-direction in the stacked structure 200' may include: forming a channel hole (not shown); and sequentially forming a functional layer 320 and a channel layer 330 on the inner wall of the channel hole.

[0101] The channel structure 300 may include a semiconductor layer and a composite dielectric layer filling the channel via. The functional layer 320 and the channel layer 330 may be formed on the inner wall of the channel via by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0102] Specifically, the channel vias can be formed by, for example, dry etching processes or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. The channel vias can have a cylindrical or columnar shape extending along the z-direction in the stacked structure 200'. Alternatively, the channel vias can extend into the initial substrate.

[0103] The functional layer 320 may include a barrier layer formed on the inner wall of the channel hole to prevent charge outflow, a charge trapping layer formed on the surface of the barrier layer to store charge during operation of the semiconductor device, and a tunneling layer formed on the surface of the charge trapping layer.

[0104] In some embodiments, functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in other embodiments, functional layer 320 may have a structure different from that of an ONO configuration. Channel layer 330 may be formed on the surface of tunneling layer and is capable of transporting the required charge (electrons or holes).

[0105] However, those skilled in the art should understand that, without departing from the teachings of this application, functional layers may be formed on the sidewalls and bottom surfaces of the channel hole, or on the sidewalls of the channel hole, depending on the different semiconductor device architectures, and this application does not limit this.

[0106] For example, as an alternative, according to one embodiment of this application, a functional layer 320 may be formed on the sidewalls and bottom surface of the channel hole, and a channel layer 330 may be formed on the surface of the tunneling layer of the functional layer 320 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0107] Alternatively, according to one embodiment of this application, an epitaxial layer (not shown) may be formed first on the bottom surface of the channel hole, and a functional layer 320 may be formed on the sidewall of the channel hole and the surface of the epitaxial layer. After removing the portion of the functional layer 320 located on the surface of the epitaxial layer, a channel layer 330 may be formed on the surface of the tunneling layer of the remaining functional layer 320 and the surface of the epitaxial layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0108] In some embodiments, the channel layer 330 may be fabricated from a semiconductor material such as polycrystalline silicon or monocrystalline silicon and may have conductive impurities. For example, the channel layer may be an N-type doped or P-type doped polycrystalline silicon layer. Similar to the channel via, the channel layer 330 may also have a cylindrical or columnar shape extending along the z-direction in the stacked structure 200'. Alternatively, the channel layer 330 may also extend into the initial substrate.

[0109] Furthermore, a channel plug can be formed at the end of the channel via furthest from the initial substrate (which can be understood as the top of the channel structure 300). Specifically, after forming the functional layer 320 and the channel layer 330, a channel-filling dielectric layer can be used to fill the channel via. The channel-filling dielectric layer may include an oxide dielectric layer, such as silicon oxide. Further, during the filling process, multiple insulating gaps can be formed in the channel-filling dielectric layer to reduce structural stress by controlling the channel filling process. Then, a channel plug is formed in the portion of the channel-filling dielectric layer located at the top of the channel via. The channel plug can be made of the same material as the channel layer 330, such as N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer 330.

[0110] After the channel structure 300 is formed, a virtual channel structure with a distance from the channel structure 300 in the first direction (x direction) can also be formed in the same way as described above. Therefore, related or similar content will not be described again.

[0111] Alternatively, since the virtual channel structure does not have storage functionality, it can typically be filled with only an insulating dielectric material layer, such as a silicon oxide layer, within the virtual channel holes (not shown) using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Similarly, by controlling the channel filling process, multiple insulating gaps can be formed within the insulating dielectric material layer to alleviate the structural stress of the virtual channel structure.

[0112] After forming the channel structure 300 and the virtual channel structure, multiple channel structures 300 can form a channel structure array, and multiple virtual channel structures can form a virtual channel structure array. Each array can be arranged in multiple rows and columns in the first direction and the second direction (y direction). The first region 01' may include at least the channel structure array.

[0113] After forming the channel structure 300 and the virtual channel structure, a gate line slot can be formed by, for example, a dry etching process or a combination of dry and wet etching processes, passing through the stacked structure 200' in the z-direction and extending in the y-direction. Alternatively, the gate line slot can pass through the stacked structure 200' in the z-direction and extend into the initial substrate. The gate line slot can serve as a pathway for providing etchant, and a portion of the second dielectric layer 220 in the stacked structure can be removed using, for example, a wet etching equivalent etching process, thereby forming the gate layer.

[0114] The stacked structure provided in this application includes a storage area 01 and a connection area 02 (see...). Figure 1 The storage area includes a channel structure and the connection area includes a contact structure. Therefore, the stacked structure 200' used to form the stacked structure also correspondingly includes a predetermined storage area and a predetermined connection area, which are formed in the first region 01' and the second region 02', respectively.

[0115] In one embodiment of this application, forming a sacrificial void for accommodating the gate layer 230 may include: forming a gate line slot extending through the stacked structure 200' along the z-direction, wherein the gate line slot includes a first gap (not shown) located in a predetermined memory region and a second gap (not shown) located in a predetermined interconnect region; filling the first gap and removing a portion of the second dielectric layer 230 based on the second gap to form the first void (not shown); exposing the first gap and filling the second gap and the first void; and continuing to remove a portion of the second dielectric layer based on the exposed first gap to form the second void (not shown), wherein the first void and the second void, which are interconnected, are formed as sacrificial voids.

[0116] Specifically, some of the multiple gate line slots extend in the y-direction and only in the storage region of the stacked structure 200'. Optionally, some of the multiple gate line slots extend in the y-direction and at least in the storage region and the interconnect region of the stacked structure 200'. The gate line slots enable the partial removal of the second dielectric layer 220 in the stacked structure 200' in subsequent steps.

[0117] Furthermore, after removing a portion of the second dielectric layer to form the gate layer, the connection region may include a stacked insulating dielectric material layer formed by mutually stacked first dielectric layers and the retained second dielectric layers. By placing a contact structure within this stacked insulating dielectric material, electrical communication between the contact structure and the corresponding gate layer can be achieved, while preventing short circuits between different gate layers. Therefore, to achieve the above effects, the semiconductor device fabrication method provided in this application removes only a portion of the second dielectric layer, and the shape and size of the final gate layer can be controlled by removing portions of the second dielectric layer in stages.

[0118] As an alternative, in one embodiment of this application, during the removal of a portion of the second dielectric layer using processes such as wet etching, process parameters such as the type of etchant in the gate gap, the concentration of the etchant, the etching time, and the etching rate can be adjusted to ensure that, during the etching of the portion of the second dielectric layer, both the portion of the second dielectric layer located in the storage region and the portion of the second dielectric layer located in the connection region and adjacent to the gate gap are sufficiently etched without any under-etching; and that the etching process accurately preserves a portion of the second dielectric layer in the connection region of the stacked structure, thus improving over-etching.

[0119] Alternatively, in one embodiment of this application, some of the plurality of gate line slots may define a first gap and a second gap in the y-direction, wherein the first gap may be located in a first region 01' and the second gap may be located in a second region 02'. Furthermore, some of the plurality of gate line slots may consist only of the first gap located in the first region 01'.

[0120] A first gap can be filled with a first filling sacrificial layer (not shown) and a portion of the second dielectric layer 220 can be removed based on the unfilled second gap using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0121] Optionally, the first filler sacrificial layer can be a polysilicon layer. The material of the first filler sacrificial layer is different from that of the second dielectric layer, so that the first filler sacrificial layer and the second dielectric layer 220 can have different etching rates for the same etchant, facilitating the removal of a portion of the second dielectric layer 220 in subsequent etching processes. Furthermore, since the first filler sacrificial layer needs to be removed in subsequent steps, a carbon layer, a polysilicon layer, or similar material can be used as the first filler sacrificial layer. This prevents damage to the stacked structure 200' during the subsequent removal process, while reducing the cost of fabricating the semiconductor device.

[0122] Optionally, the entire gate gap can be filled with a first filler sacrificial layer using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Then, the portion of the first filler sacrificial layer located in the second gap is removed using, for example, a dry etching process or a combination of dry and wet etching processes, exposing the second gap and leaving the remaining first filler sacrificial layer only in the first gap.

[0123] By filling the first gap with the remaining first filler sacrificial layer, the second gap can be exposed. The exposed second gap can serve as a pathway for providing etchant, and a portion of the second dielectric layer located in the second region 02' can be removed using an isotropic etching process, such as wet etching, to form the first void. In this process, by adjusting process parameters such as the type of etchant in the second gap, the concentration of the etchant, the etching time, and the etching rate, it can be ensured that during the etching of part of the second dielectric layer, the portion of the second dielectric layer located in the second region 02' and adjacent to the gate line gap can be sufficiently etched without under-etching, while also ensuring that the etching process accurately preserves a portion of the second dielectric layer in the second region 02' of the stacked structure, thereby improving over-etching.

[0124] Furthermore, after forming the first void, a first filling sacrificial layer in the first void can be removed using, for example, a dry etching process or a combination of dry and wet etching processes, or other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. Then, by means of the exposed first void, a portion of the second dielectric layer located in the first region 01' can be removed using, for example, wet etching or equivalent etching processes, to form the second void. This step may also include filling the formed first void with a second filling sacrificial layer (not shown). Optionally, a carbon layer, for example, can be used as the second filling sacrificial layer to fill the first void.

[0125] In some embodiments of this application, after the second void is formed, the connected first void and second void are formed as sacrificial voids. The gate layer 230 can be formed in the sacrificial voids using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The gate layer 230 may include a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides.

[0126] Furthermore, prior to forming the gate layer 230, the semiconductor device fabrication method 2000 according to one embodiment of this application further includes forming an isolation dielectric layer on the inner wall of the sacrificial void and on the inner sidewall of the gate line gap using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Alternatively, the isolation dielectric layer may be a high-dielectric-constant dielectric layer. Further, an adhesive layer may be formed between the first dielectric layer and the gate layer or between the isolation dielectric layer and the gate layer using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. For example, the adhesive layer may be, for example, a titanium nitride (TiN) layer.

[0127] In addition, such as Figure 8B As shown, in some embodiments of this application, after forming the gate layer 230, a gate line gap structure 400 can be formed by filling the gate line gaps. Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to sequentially fill the gate line gaps with a sidewall isolation layer and a dielectric filling layer to form the gate line gap structure 400. The dielectric filling layer can be an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride, or a semiconductor material such as polysilicon; this application does not limit this choice. After forming the gate line gap structure 400 and the gate layer 230 in the stacked structure 200', the stacked structure 200' is formed as a multilayer structure 200.

[0128] Step 2

[0129] Figure 9 This is a schematic cross-sectional view of the structure formed after forming the first insulating dielectric layer 34 according to a preparation method of one embodiment of this application. Figure 10 This is a cross-sectional schematic diagram of the structure formed after forming the second conductive layer 540 according to a preparation method of one embodiment of this application.

[0130] like Figure 1 , Figure 4 , Figures 8B-10As shown, step S2 forms a capacitor contact structure, wherein the capacitor contact structure includes a first conductive layer, a first insulating dielectric layer and a second conductive layer from the outside to the inside. The first conductive layer extends in the stacked structure along the stacking direction and is connected to the corresponding gate layer. This may include, for example, forming a first opening (not shown) of the second dielectric layer extending along the z-direction to a predetermined stacking height; forming a sidewall barrier layer 520 on the sidewall of the first opening; removing a portion of the second dielectric layer that contacts the bottom of the first opening to form a second opening (not shown); and sequentially forming a first conductive layer 530, a first insulating dielectric layer 34 and a second conductive layer 540 in the first opening and the second opening.

[0131] Specifically, such as Figure 1 , Figure 4 and Figure 8B As shown, multiple first openings extending along the z-direction and having different depths can be formed in the stacked structure 200 by, for example, dry etching processes or a combination of dry and wet etching processes, or by performing other manufacturing processes, such as patterning processes including photolithography, cleaning and chemical mechanical polishing.

[0132] After the first opening is formed, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to form an initial barrier layer (not shown) on the surface of the stacked structure 200 away from the initial substrate, the sidewalls of the first opening, and the bottom. The initial barrier layer can be prepared, for example, from dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, or from high dielectric materials such as alumina, and this application is not limited thereto.

[0133] After the initial barrier layer is formed, the portion of the initial barrier layer located on the surface of the stacked structure 200 is removed, and the bottom portion of the initial barrier layer located at the first opening is also removed to form a sidewall barrier layer 520. Protected by the sidewall barrier layer 520, a portion of the second dielectric layer 220 in contact with the bottom of the first opening, as well as a portion of the second dielectric layer 220 adjacent to this contact portion, is removed via the first opening using, for example, a dry etching process or a combination of dry and wet etching processes, thereby forming a second opening. The second opening and the first opening together form the contact hole of the capacitor contact structure 500.

[0134] Optionally, to reduce process complexity and simplify process steps, the contact holes of the capacitor contact structure 500 can be filled during the process of forming the gate line gaps. In this case, during the process of removing a portion of the second dielectric layer 220 to form the gate layer 230 as described in step S1 above, a third filler sacrificial layer (not shown) can be used to fill the contact holes of the capacitor contact structure 500. The third filler sacrificial layer can be selected as a carbon layer, which is convenient to remove in subsequent steps after the formation of the gate layer 230.

[0135] After the sidewall barrier layer 520 is formed, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to fill at least the surface of the sidewall barrier layer 520 and the second opening with conductive material to form a first conductive layer 530.

[0136] Alternatively, the conductive material forming the first conductive layer 530 may include any one or a combination of conductive metal materials and doped semiconductor materials, wherein the conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor material may be, for example, doped crystalline silicon or silicide, etc., and this application does not limit it.

[0137] Furthermore, in one embodiment of this application, the first conductive layer 530 does not completely fill the contact hole where the sidewall barrier layer 520 is formed. For example, a portion of the first conductive layer 530 fills the second opening, and a portion of the first conductive layer 530 is located on the surface of the sidewall barrier layer 520. The remaining space in the contact hole can be filled with an initial first insulating dielectric layer 34' using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the material forming the initial first insulating dielectric layer 34' can be a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0138] like Figure 1 , Figure 4 as well as Figures 8B-9 As shown, the first insulating dielectric layer 34' can be formed by removing a portion of the initial first insulating dielectric layer 34' through, for example, a dry etching process or a combination of dry and wet etching processes, or by performing other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. The first insulating dielectric layer 34 is located on the surface of the first conductive layer 530.

[0139] Optionally, such as Figure 1 , Figure 4 as well as Figures 9-10 As shown, a second conductive layer 540 can be formed on the surface of the first insulating dielectric layer 34 using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The conductive material forming the second conductive layer 540 can include any one or a combination of conductive metal materials and semiconductor materials. The conductive metal material can be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the semiconductor material can be, for example, doped crystalline silicon or silicides, etc., without limitation in this application. The second conductive layer 540 and the first conductive layer 530 form the first capacitor structure of the capacitor contact structure 500.

[0140] In addition, refer to again Figure 1 , Figure 4 as well as Figure 10 The semiconductor device fabrication method 2000 according to one embodiment of this application further includes: sequentially forming a second insulating dielectric layer 45 and a third conductive layer 550 on the surface of the second conductive layer 540.

[0141] Specifically, a second insulating dielectric layer 45 is formed on the surface of the second conductive layer 540 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the material forming the second insulating dielectric layer 45 may be a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0142] After the second insulating dielectric layer 45 is formed, a third conductive layer 550 may be formed on the surface of the second insulating dielectric layer 45 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0143] The conductive material forming the third conductive layer 550 may include any one or a combination of conductive metal materials and semiconductor materials. The conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the semiconductor material may be, for example, doped crystalline silicon or silicides, etc., and this application does not limit the specific materials used. The second conductive layer 540 and the third conductive layer 550 constitute the second capacitor structure of the capacitor contact structure 500.

[0144] Referring to the steps described above of forming a conductive layer (e.g., a second conductive layer 540 and a third conductive layer 550) and an insulating dielectric layer (e.g., a second insulating dielectric layer 45) in the contact hole of the capacitor contact structure 500, multiple capacitor structures can be formed in the contact hole as needed.

[0145] According to at least one embodiment of the semiconductor device fabrication method provided in this application, it is not necessary to form steps and word line contacts on the steps in the semiconductor device. Specifically, the semiconductor device may include a stacked structure and a plurality of capacitive contact structures disposed in the stacked structure. The first conductive layer of the capacitive contact structure can realize the electrical connection between the gate layer located at different stacking heights and the external circuit. Therefore, while simplifying the fabrication process and reducing the production cost, the unit storage density, reliability and overall performance of the semiconductor device can be improved.

[0146] Furthermore, the capacitive contact structure also includes a second conductive layer and a first insulating dielectric layer located between the first and second conductive layers. The first conductive layer, the second conductive layer, and the first insulating dielectric layer form a capacitor structure. Therefore, the capacitive contact structure not only enables electrical communication between the gate layer at different stack heights and external circuits, but also utilizes its internal space to form the capacitor structure required for semiconductor devices. This improves the overall performance of semiconductor devices while effectively increasing the unit storage density and reducing the price per unit storage cell.

[0147] In addition, refer to Figure 1 , Figure 3 and Figure 10 Forming the third conductive layer 550 may include: forming a conductive material layer 550-2 on the surface of the second insulating dielectric layer 45; and forming an insulating filler layer 550-1 on the surface of the conductive material layer 550-2 to fill the remaining space of the contact hole (or the first opening).

[0148] The final capacitor contact structure 500 may include multiple capacitor structures, such as Figure 1 A capacitor contact structure 500 including two capacitor structures is shown, wherein a first conductive layer 530, a first insulating dielectric layer 34, and a second conductive layer 540 can form a first capacitor structure; a second conductive layer 540, a second insulating dielectric layer 45, and a third conductive layer 550 can form a second capacitor structure. In a plurality of capacitor structures arranged sequentially from the outside in, the innermost conductive layer can be a composite structure. The innermost conductive layer may include a conductive material layer and an insulating filler layer surrounded by the conductive material layer. This configuration can reduce the manufacturing cost of semiconductor devices and reduce stress deformation of the stacked structure caused by the capacitor contact structure.

[0149] Optionally, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to sequentially form a conductive material layer 550-2 and an insulating filler layer 550-1 on the surface of the second insulating dielectric layer 45, wherein the insulating filler layer 550-1 fills the remaining space of the contact hole (or the first opening).

[0150] Alternatively, the conductive material forming the third conductive layer 550 may be the same as the conductive material forming the second conductive layer 540.

[0151] Furthermore, the material forming the insulating filler layer 550-1 can be a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. Optionally, the material of the insulating filler layer 550-1 is the same as the material of the second insulating dielectric layer 45; or the materials used to prepare the insulating filler layer 550-1, the first insulating dielectric layer 34, and the second insulating dielectric layer 45 are all the same.

[0152] Optionally, to simplify the fabrication process and save on fabrication costs, the same process and the same materials can be used to form multiple conductive layers, such as a second conductive layer, a third conductive layer, etc. Based on this, the first conductive layer 530 and the second conductive layer 540 can have the same thickness; or, the second conductive layer 540 and the third conductive layer 550 can have the same thickness; or, the first conductive layer 530, the second conductive layer 540, and the third conductive layer 550 can all have the same thickness.

[0153] Figure 11 This is a schematic diagram of the structure of a storage system 30000 according to one embodiment of this application.

[0154] like Figure 11 As shown, at least one embodiment of another aspect of this application also provides a storage system 30000. The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the embodiments above, and will not be repeated here. The semiconductor device 20000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. The following description will use a three-dimensional semiconductor device as an example.

[0155] Alternatively, a three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0156] The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the embodiments above, and will not be repeated here. The controller 32000 can control the semiconductor device 20000 via a channel CH, and the semiconductor device 20000 can perform operations based on the control of the controller 32000 in response to requests from the host 31000. The semiconductor device 20000 can receive commands CMD and addresses ADDR from the controller 32000 via the channel CH and access a region selected from the memory cell array in response to that address. In other words, the semiconductor device 20000 can perform internal operations corresponding to commands on the region selected by the address.

[0157] In some implementations, the three-dimensional storage system can be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc. The storage system provided in this application, due to the incorporation of the semiconductor device provided in this application, has the same beneficial effects as the described semiconductor device, and will not be elaborated upon here.

[0158] Although exemplary fabrication methods and structures of semiconductor devices are described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor device. Furthermore, the materials of the exemplified layers are merely exemplary.

[0159] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized by, include: A stacked structure comprising alternating stacked first dielectric layers and gate layers; as well as The capacitor contact structure, from the outside in, includes a first conductive layer, a first insulating dielectric layer, and a second conductive layer. The first conductive layer extends along the stacking direction in the stacked structure and is connected to the corresponding gate layer.

2. The semiconductor device according to claim 1, wherein, The capacitive contact structure further includes a third conductive layer and a second insulating dielectric layer located between the second conductive layer and the third conductive layer.

3. The semiconductor device according to claim 1, wherein, The first conductive layer includes a first portion and a second portion that are connected to each other. Wherein, the first portion extends in the stacked structure along the stacking direction; and The second portion extends in a plane perpendicular to the stacking direction and connects the first portion and the corresponding gate layer.

4. The semiconductor device according to claim 3, wherein, The capacitive contact structure further includes a sidewall barrier layer, which is located between the stacked structure and the first part.

5. The semiconductor device according to claim 3, wherein, In a plane perpendicular to the stacking direction, the projection of the second part overlaps the projection of the first part.

6. The semiconductor device according to claim 3, wherein, In a plane perpendicular to the stacking direction, the projection of the first portion is annular.

7. The semiconductor device according to claim 1, wherein, The first insulating dielectric layer covers the surface of the first conductive layer; as well as The second conductive layer covers the surface of the first insulating dielectric layer. Wherein, the extension length of the first conductive layer in the stacking direction is greater than the extension length of the second conductive layer in the stacking direction.

8. The semiconductor device according to claim 2, wherein, The third conductive layer includes a conductive material layer and an insulating filler layer surrounded by the conductive material layer.

9. The semiconductor device according to claim 2, wherein, The second conductive layer includes at least one of a semiconductor material layer and a metal material layer; and / or The third conductive layer includes at least one of a semiconductor material layer and a metal material layer.

10. The semiconductor device according to claim 2, wherein, The first conductive layer and the second conductive layer have the same thickness; and / or The second conductive layer and the third conductive layer have the same thickness.

11. The semiconductor device according to claim 2, wherein, The second conductive layer and the third conductive layer are made of the same material.

12. The semiconductor device according to claim 1, wherein, The stacked structure includes memory regions and interconnect regions adjacently distributed in a plane perpendicular to the stacking direction, wherein the gate layer extends from the memory region into the interconnect region, and the interconnect region further includes a second dielectric layer alternately stacked with the first dielectric layer. The first conductive layer penetrates multiple second dielectric layers along the stacking direction in the connection region and is connected to the corresponding gate layer.

13. A method for fabricating a semiconductor device, characterized in that, The method includes: A stacked structure is formed, the stacked structure comprising alternately stacked first dielectric layers and gate layers; and Forming a capacitor contact structure, The capacitor contact structure comprises, from the outside in, a first conductive layer, a first insulating dielectric layer, and a second conductive layer. The first conductive layer extends along the stacking direction in the stacked structure and is connected to the corresponding gate layer.

14. The method according to claim 13, wherein, The formation of a layered structure includes: The first dielectric layer and the second dielectric layer are alternately stacked to form a stacked structure; Remove a portion of the second dielectric layer to form sacrificial voids; and The gate layer is formed in the sacrificial void.

15. The method according to claim 14, wherein, The stacked structure includes predetermined storage areas and predetermined connection areas distributed adjacently in a plane perpendicular to the stacking direction, forming the sacrificial gap by: A gate wire slot is formed that extends through the stacking structure along the stacking direction, wherein the gate wire slot includes a first gap located in the predetermined storage area and a second gap located in the predetermined connection area; The first gap is filled, and a portion of the second dielectric layer is removed based on the second gap to form the first void; Expose the first gap and fill the second gap and the first void; and Based on the exposed first gap, a portion of the second dielectric layer is further removed to form a second void. The first gap and the second gap, which are interconnected, form the sacrificial gap.

16. The method of claim 14, wherein, The formation of the capacitor contact structure includes: A first opening is formed in the second dielectric layer extending along the stacking direction to a predetermined stacking height; A sidewall barrier layer is formed on the sidewall of the first opening; A portion of the second dielectric layer in contact with the bottom of the first opening is removed to form a second opening; and The first conductive layer, the first insulating dielectric layer, and the second conductive layer are sequentially formed in the first opening and the second opening.

17. The method according to claim 16, wherein, The method further includes: A second insulating dielectric layer and a third conductive layer are sequentially formed on the surface of the second conductive layer.

18. The method according to claim 17, wherein, The second conductive layer is formed using at least one of a semiconductor material and a metallic material; and / or The third conductive layer is formed using at least one of semiconductor materials and metallic materials.

19. The method according to claim 17, wherein, Forming the third conductive layer includes: A conductive material layer is formed on the surface of the second insulating dielectric layer; and An insulating filler layer is formed on the surface of the conductive material layer to fill the remaining space of the first opening.

20. A storage system, characterized in that, include: Controller; as well as The semiconductor device as claimed in any one of claims 1-12, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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