Semiconductor device and manufacturing method thereof, and electronic device

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, and an electronic device, the method comprising: providing a substrate, in which a body region and a drift region are formed; forming a liner layer and a mask layer on the surface of the substrate in sequence; patterning the liner layer and the mask layer to expose a portion of the drift region, and etching the substrate to form a groove in the drift region; performing an inclined ion implantation process to form a barrier layer at the bottom and sidewall of the groove; removing the barrier layer at the bottom of the groove; forming a field oxide layer, the field oxide layer filling the groove, wherein the top surface of the field oxide layer is higher than the surface of the substrate; removing the mask layer and the liner layer in sequence; forming a gate structure, the gate structure covering a portion of the field oxide layer and covering a portion of the body region and a portion of the drift region surface. The present invention forms a barrier layer on the sidewall of the groove, the barrier layer can avoid the generation of a bird's beak effect when forming the field oxide layer, thereby forming a nearly vertical field oxide layer, and improving the device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] There are two main types of DMOS (double-diffused MOSFET): VDMOS (vertical double-diffused MOSFET) and LDMOS (lateral double-diffused MOSFET). Among them, LDMOS is widely used in the industry because it is more compatible with CMOS (Complementary Metal Oxide Semiconductor) process and has advantages in voltage resistance, gain, linearity, switching performance, heat dissipation performance, etc.

[0003] Two important parameters of LDMOS are breakdown voltage and on-resistance. In order to improve the breakdown voltage of LDMOS, a gate field plate structure is usually adopted, that is, the gate is extended to the field oxide layer to form a gate field plate structure. The field oxide layer in the gate field plate structure is generally manufactured using the Local Oxidation of Silicon (LOCOS) process.

[0004] However, if Figure 1 As shown, the field oxide layer 110 obtained by the LOCOS process in the related art will form a "bird's beak" structure, which will cause the current path of the field oxide layer to become longer, resulting in a higher on-resistance of the device; and the "bird's beak" structure will also limit the thickness of the field oxide layer, making it impossible to form a thicker field oxide layer, thereby limiting the breakdown voltage of the device. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In view of the existing problems, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] Providing a substrate, wherein a body region and a drift region extending from a surface of the substrate into the substrate are formed in the substrate, the drift region has a first conductivity type, and the body region has a second conductivity type;

[0008] forming a liner layer and a mask layer in sequence on the surface of the substrate;

[0009] patterning the liner layer and the mask layer to expose a portion of the drift region, and etching the substrate to form a trench in the drift region;

[0010] Performing an inclined ion implantation process to form a barrier layer at the bottom and sidewalls of the trench;

[0011] removing the barrier layer at the bottom of the trench;

[0012] forming a field oxide layer, wherein the field oxide layer fills the trench, wherein a top surface of the field oxide layer is higher than a surface of the substrate;

[0013] removing the mask layer and the liner layer in sequence;

[0014] A gate structure is formed, wherein the gate structure covers a portion of the field oxide layer and covers a portion of the body region and a portion of the surface of the drift region.

[0015] Exemplarily, forming the gate structure includes:

[0016] forming a gate oxide layer, wherein the gate oxide layer covers a portion of the surface of the body region and a portion of the drift region, and a side wall of the gate oxide layer contacts the field oxide layer;

[0017] A gate electrode layer is formed, wherein the gate electrode layer covers a top surface of the gate oxide layer and a portion of the field oxide layer, wherein the gate structure includes the gate oxide layer and the gate electrode layer.

[0018] Exemplarily, a top surface of the field oxide layer is higher than a top surface of the gate oxide layer.

[0019] Exemplarily, after removing the mask layer and the liner layer in sequence, the method further includes:

[0020] A source region located in the body region and a drain region located in the drift region are formed, wherein the source region and the drain region are respectively located at two sides of the gate structure, and the source region and the drain region have a first conductivity type.

[0021] Exemplarily, a well region is further formed in the substrate, the body region and the drift region are located in the well region, and the well region has a first conductivity type.

[0022] Exemplarily, the implanted ions in the tilted ion implantation process include nitrogen ions; and / or,

[0023] The implantation ion dose of the inclined ion implantation process is greater than or equal to 10 15 / cm 2 and / or,

[0024] The tilted ion implantation process uses a bidirectional tilt angle to implant ions.

[0025] Exemplarily, the barrier layer located on the sidewall of the trench has a uniform thickness, or the thickness of the barrier layer located on the sidewall of the trench gradually decreases from top to bottom.

[0026] Exemplarily, when the inclined ion implantation process is performed to form the barrier layer, the barrier layer located on the sidewall of the trench also extends into the liner layer.

[0027] Another aspect of the present invention provides a semiconductor device, wherein the semiconductor device is manufactured by using the above method.

[0028] Another aspect of the present invention provides an electronic device, comprising the above-mentioned semiconductor device.

[0029] The semiconductor device and its manufacturing method and electronic device of the embodiments of the present invention form a barrier layer on the side wall of the groove, and the barrier layer can avoid the bird's beak effect when forming the field oxide layer, so as to form a nearly vertical field oxide layer, that is, the curvature of the field oxide layer is large enough, and there is almost no lateral diffusion, and the current path is shorter, thereby reducing the on-resistance of the device. At the same time, the thickness of the field oxide layer is not limited, and a thicker field oxide layer can be formed, thereby increasing the breakdown voltage of the device, and the process stability and feasibility are strong, thereby improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The following drawings of the present invention are used as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and their descriptions to explain the principles of the present invention. In the drawings:

[0031] Figure 1 A cross-sectional schematic diagram of a semiconductor device for obtaining a field oxide layer in a gate field plate structure by using a LOCOS process in the related art is shown;

[0032] Figure 2 A flowchart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown;

[0033] Figure 3A-3H A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. DETAILED DESCRIPTION

[0034] Next, the present invention will be more fully described in conjunction with the accompanying drawings, in which embodiments of the present invention are shown. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0035] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0036] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the present invention. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an ideal or overly formal sense unless expressly defined as such herein.

[0040] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0041] The field oxide layer in the gate field plate structure in the related art is generally manufactured by LOCOS process. Figure 1As shown, in the process of obtaining the field oxide layer 110 by adopting the LOCOS process, oxygen atoms will diffuse laterally to form a "bird's beak" structure. The "bird's beak" structure will cause the curvature of the field oxide layer to become smaller, thereby causing the current path of the field oxide layer to become longer, resulting in a higher on-resistance of the device; and the "bird's beak" structure will also limit the thickness of the field oxide layer, resulting in the inability to form a thicker field oxide layer. The thicker the field oxide layer, the higher the breakdown voltage of the device. The inability to form a thicker field oxide layer will result in the inability to obtain a higher breakdown voltage, thereby limiting the performance of the device.

[0042] Therefore, in view of the existence of the above-mentioned technical problems, the present invention proposes a method for manufacturing a semiconductor device, such as Figure 2 As shown, it mainly includes the following steps:

[0043] Step S1, providing a substrate, wherein a body region and a drift region extending from a surface of the substrate into the substrate are formed in the substrate, the drift region has a first conductivity type, and the body region has a second conductivity type;

[0044] Step S2, forming a liner layer and a mask layer in sequence on the surface of the substrate;

[0045] Step S3, patterning the liner layer and the mask layer to expose a portion of the drift region, and etching the substrate to form a trench in the drift region;

[0046] Step S4, performing an inclined ion implantation process to form a barrier layer at the bottom and sidewalls of the trench;

[0047] Step S5, removing the barrier layer at the bottom of the trench;

[0048] Step S6, forming a field oxide layer, wherein the field oxide layer fills the trench, wherein a top surface of the field oxide layer is higher than a surface of the substrate;

[0049] Step S7, removing the mask layer and the liner layer in sequence;

[0050] Step S8, forming a gate structure, wherein the gate structure covers a portion of the field oxide layer and covers a portion of the body region and a portion of the surface of the drift region.

[0051] The manufacturing method of the semiconductor device of the present invention forms a barrier layer on the side wall of the groove, and the barrier layer can avoid the bird's beak effect when forming the field oxide layer, so as to form a nearly vertical field oxide layer, that is, the curvature of the field oxide layer is large enough, and there is almost no lateral diffusion, and the current path is shorter, thereby reducing the on-resistance of the device. At the same time, the thickness of the field oxide layer is not limited, and a thicker field oxide layer can be formed, thereby increasing the breakdown voltage of the device, and the process stability and feasibility are strong, thereby improving the device performance.

[0052] Embodiment 1:

[0053] Below, reference Figures 2 to 3H The method for manufacturing a semiconductor device of the present invention is described in detail, wherein: Figure 2 A flowchart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. Figure 3A-3H A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown.

[0054] Exemplarily, the method for manufacturing a semiconductor device of the present invention comprises the following steps:

[0055] First, step S1 is performed to provide a substrate, wherein a body region and a drift region extending from a surface of the substrate into the substrate are formed in the substrate, the drift region has a first conductivity type, and the body region has a second conductivity type.

[0056] In one example, the substrate 300 is a bulk silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the substrate 300 may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) or germanium on insulator (GeOI), etc. Although several examples of materials that can form the substrate 300 are described herein, any material that can be used as the substrate 300 falls within the spirit and scope of the present invention.

[0057] In one example, if Figure 3A As shown, the drift region 302 has a first conductivity type, and the body region 301 has a second conductivity type, wherein the first conductivity type is an N-type conductivity type and the second conductivity type is a P-type conductivity type, or the first conductivity type is a P-type conductivity type and the second conductivity type is an N-type conductivity type.

[0058] In one example, if Figure 3AAs shown, a well region 303 is also formed in the substrate 300, the body region 301 and the drift region 302 are located in the well region 303, and the well region 303 has a first conductivity type. Optionally, a side surface 302 of the drift region is in lateral contact with the body region 301. Exemplarily, an ion implantation process may be performed on the substrate 300 to form the body region 301, the drift region 302, and the well region 303.

[0059] Next, step S2 is performed to sequentially form a liner layer and a mask layer on the surface of the substrate.

[0060] In one example, if Figure 3B As shown, the liner layer 304 and the mask layer 305 may be formed by various deposition methods commonly used in the art, for example, the liner layer 304 and the mask layer 305 may be formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or an atomic layer deposition (ALD) method. Exemplarily, the liner layer 304 includes an oxide layer (for example, silicon oxide, etc.), and the mask layer 305 includes a nitride layer (for example, silicon nitride, etc.), and the liner layer 304 is used to relieve the stress between the mask layer 305 and the substrate 300.

[0061] Next, step S3 is performed to pattern the liner layer and the mask layer to expose a portion of the drift region, and to etch the substrate to form a trench in the drift region.

[0062] In one example, if Figure 3C As shown, various etching processes commonly used in the art can be used to pattern the liner layer 304 and the mask layer 305 to expose part of the drift region 302, and the exposed drift region 302 is a region where a field oxide layer is predetermined to be formed; and various etching processes commonly used in the art can be used to etch the substrate 300 to form a groove 306 in the drift region 302. Among them, the etching process can include a traditional dry etching process and a wet etching process, such as reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods, and a single etching process can be used, or more than one etching process can be used. Exemplarily, the depth and width of the groove 306 should be reasonably set according to actual needs.

[0063] Next, step S4 is performed to perform an inclined ion implantation process to form a barrier layer at the bottom and sidewalls of the trench.

[0064] In one example, if Figure 3D As shown, a tilted ion implantation process is performed to form a barrier layer 307 at the bottom and sidewalls of the trench 306. It is worth noting that the formed barrier layer 307 is located in the drift region 302. Exemplarily, the implanted ions of the tilted ion implantation process include nitrogen ions, or other suitable implanted ions may also be used.

[0065] In one example, the implantation ion dose of the tilted ion implantation process is greater than or equal to 10 15 / cm 2 By implanting high-dose implantation ions such as N ions, a portion of the substrate at the bottom and sidewalls of the trench can be converted into a nitrogen-containing doped layer, which serves as a barrier layer 307 .

[0066] In one example, the tilted ion implantation process uses a bidirectional tilt angle to implant ions. The tilted ion implantation can well control the depth of ion implantation to form a barrier layer within a target depth range, thereby controlling the thickness and formation position of the barrier layer. Exemplarily, the tilt angle of the tilted ion implantation process should be appropriately set according to actual needs and is not specifically limited here.

[0067] Next, step S5 is performed to remove the barrier layer at the bottom of the trench. Figure 3E As shown, various etching processes commonly used in the art can be used to etch and remove the barrier layer 307 at the bottom of the trench 306. The etching process may include but is not limited to a dry etching process and a wet etching process. For example, the barrier layer 307 located on the sidewall of the trench 306 should be retained.

[0068] In one example, the barrier layer 307 located on the sidewall of the trench 306 has a uniform thickness, or the thickness of the barrier layer 307 located on the sidewall of the trench 306 gradually decreases from top to bottom. The thickness of the barrier layer 307 here refers to the thickness of the barrier layer 307 along the direction perpendicular to the sidewall of the trench 306. Taking the sidewall of the trench 306 arranged along the vertical direction as an example, the thickness of the barrier layer 307 here refers to the thickness of the trench 306 along the horizontal direction. Exemplarily, the blocking layer 307 is located in the drift region 302, and in order to increase the breakdown voltage of the device, the drift region 302 is generally a low-concentration doped region. When it is connected to high voltage, the drift region is high-resistance and can withstand higher voltage. In the present application, the blocking layer 307 formed by inclined ion implantation is implanted with N ions. If the implantation amount is too large, the doping concentration of the doped ions in the drift region 302 will increase, thereby reducing the breakdown voltage of the device. In the present application, the blocking layer 307 located on the side wall of the groove 306 is made to have a uniform thickness, or the thickness of the blocking layer 307 located on the side wall of 306 is gradually reduced from top to bottom, so as to minimize the influence of the implanted ions of the inclined ion implantation on the doping concentration of the drift region 302, thereby minimizing the influence on the breakdown voltage of the device.

[0069] In some examples, the barrier layer on the sidewall near the bottom may be removed simultaneously with the barrier layer on the bottom, so that the barrier layer finally remaining covers the upper portion of the sidewall of the trench.

[0070] Next, step S6 is performed to form a field oxide layer, wherein the field oxide layer fills the trench, wherein a top surface of the field oxide layer is higher than a surface of the substrate.

[0071] In one example, if Figure 3F As shown, a LOCOS process may be used to form a field oxide layer 308 filling the trench 306, and the top surface of the field oxide layer 308 is higher than the surface of the substrate 300. Specifically, a high-voltage oxide layer may be thermally grown through a furnace tube to form the field oxide layer 308. In this process, oxygen atoms react with silicon in the substrate 300 exposed at the bottom of the trench 306 to form an oxide layer. Since the formed oxide layer is thicker than the consumed silicon, the top surface of the formed field oxide layer 308 is lifted to be higher than the top surface of the substrate 300. At the same time, since a barrier layer 307 is formed on the side wall of the groove 306, the barrier layer 307 can block the lateral diffusion of oxygen atoms and avoid the bird's beak effect of the field oxide layer 308, thereby forming a nearly vertical field oxide layer 308, that is, the curvature of the field oxide layer is large enough, the current path is shorter, and the on-resistance of the device can be reduced. At the same time, the thickness of the field oxide layer 308 will not be limited, and a thicker field oxide layer 308 can be formed, which can increase the breakdown voltage of the device, and the process stability and feasibility are strong, thereby improving the device performance.

[0072] In one example, if Figures 3D to 3F As shown, when the inclined ion implantation process is performed to form the blocking layer 307, the blocking layer 307 located on the side wall of the groove 306 also extends into the liner layer 304. By extending the blocking layer 307 into the liner layer 304, the blocking layer 307 crosses the boundary between the liner layer 304 and the substrate surface on the side wall of the groove, thereby being able to better block the diffusion of oxygen atoms into the boundary between the liner layer 304 and the substrate surface during the process of forming the oxide layer 308, that is, being able to further enhance the blocking effect of the blocking layer 307 on oxygen atoms during the process of forming the field oxide layer 308, thereby being more conducive to avoiding the "bird's beak" effect.

[0073] Next, step S7 is performed to remove the mask layer and the liner layer in sequence. Figure 3F and Figure 3G As shown, various etching processes commonly used in the art can be used to remove the mask layer 305 and the liner layer 304. For example, a dry etching process can be used to remove the mask layer 305 first, and then a wet etching process can be used to remove the liner layer 304. Exemplarily, in the process of etching and removing the mask layer 305 and the liner layer 304, the field oxide layer 308 will also be partially etched, resulting in a reduction in thickness.

[0074] Finally, step S8 is performed to form a gate structure, which covers part of the field oxide layer and covers part of the surface of the body region and part of the surface of the drift region. For example, the gate structure covers part of the surface of the body region and extends to the field oxide layer on the drift region.

[0075] In one example, if Figure 3H As shown, a gate structure covering a portion of the field oxide layer 308 and a portion of the surface of the body region 301 and a portion of the drift region 302 can be formed by the following steps: Figure 3H As shown, a gate oxide layer 309 is formed, and the gate oxide layer 309 covers a portion of the surface of the body region 301 and a portion of the drift region 302, and a side wall of the gate oxide layer 309 contacts the field oxide layer 308, and the gate oxide layer 309 plays an isolation and protection role; then, as Figure 3H As shown, a gate electrode layer 310 is formed, and the gate electrode layer 310 covers the top surface of the gate oxide layer 309 and a portion of the field oxide layer 308, wherein the gate structure includes the gate oxide layer 309 and the gate electrode layer 310. Exemplarily, the gate oxide layer 309 can be formed by various deposition methods commonly used in the art, for example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). Exemplarily, the gate oxide layer 309 uses an oxide layer, such as silicon dioxide and other materials, but is not limited to the above examples. Exemplarily, the gate electrode layer 310 is composed of polysilicon material, and generally metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate layer. Exemplarily, the top surface of the field oxide layer 308 is higher than the top surface of the gate oxide layer 309. Exemplarily, the number of layers of the gate electrode layer 310 can be at least one layer, and the gate electrode layer 310 can be used as a field plate.

[0076] In one example, if Figure 3H As shown, the gate structure may further include sidewalls 311 located on both sides of the gate electrode layer 310, and the sidewalls 311 can increase the channel length of the device and reduce the short channel effect and the hot carrier effect caused by the short channel effect. The sidewalls 311 can be formed by various deposition methods commonly used in the art, for example, by chemical vapor deposition (CVD). Exemplarily, the sidewalls 311 can be a single-layer or multi-layer structure, for example, a single-layer silicon dioxide structure, or a double-layer structure of a single-layer silicon dioxide and a single-layer silicon nitride, or a triple-layer structure of a double-layer silicon dioxide and a single-layer silicon nitride, and the present application does not limit this.

[0077] In one example, if FIG. 3F to FIG. 3HAs shown, after removing the mask layer 305 and the liner layer 304 in sequence, the method of the present application further includes: forming a source region 312 located in the body region 301 and a drain region 313 located in the drift region 302, the source region 312 extending from the surface of the body region to the body region, and adjacent to the side of the gate structure close to the body region 301, the source region 312 and the drain region 313 are respectively located on both sides of the gate structure, the source region 312 and the drain region 313 have a first conductivity type, and the source region 312 and the drain region 313 can both be heavily doped regions. Exemplarily, the source region 312 and the drain region 313 can be formed by an ion implantation process, and then a rapid temperature rise annealing process is performed, using a high temperature of 900 degrees Celsius to 1050 degrees Celsius to activate the dopants in the source region 312 and the drain region 313, and at the same time repairing the lattice structure of the semiconductor substrate surface damaged in each ion implantation process. For example, the present application does not specifically limit the order of forming the gate structure, the source region 312 and the drain region 313. For example, FIG. 3F to FIG. 3H As shown, after removing the mask layer 305 and the liner layer 304 in sequence, the present application also includes the step of forming a body contact region 314 in the body region 301, the body contact region 314 has a second conductivity type, the doping concentration of the body contact region 314 is higher than the doping concentration of the body region 301, and the body contact region 314 can be used as a lead-out region of the body region 301. Exemplarily, a self-aligned silicide layer can also be formed on the gate electrode layer 310, the source region 312, and the drain region 313. Exemplarily, a shallow trench isolation (STI) structure can also be formed in the body region 301 and the drift region 302.

[0078] In one example, the gate structure and the field oxide layer 308 form a gate field plate structure, and the gate field plate structure can weaken the surface electric field of the drift region 302, which is beneficial to improving the breakdown voltage of the device.

[0079] In an example, taking the case where the first conductivity type is N-type and the second conductivity type is P-type, by applying voltage to the gate structure, free electrons in the body region 301 can be attracted to approach the gate structure, and holes in the body region 301 can be repelled, thereby forming an N channel in the body region 301. At this time, free electrons can move from the source region 312 to the drain region 313 through the N channel.

[0080] In some examples, the method of the present application further includes: forming a first conductive contact hole and a second conductive contact hole for respectively leading out the source region 312 and the drain region 313, wherein the first conductive contact hole is also electrically connected to the first metal layer as the source, and the second conductive contact hole is also electrically connected to the second metal layer as the drain. Optionally, a conductive contact hole electrically connected to the body contact region 314 may also be formed, and the conductive contact hole may also be electrically connected to the source. In some embodiments, the gate structure may be connected to the source.

[0081] In an example, the length direction of the body region 301 is the direction from the source region 312 to the drift region 302 , and the width direction of the body region 301 is the direction perpendicular to the length direction of the body region 301 .

[0082] In one example, along the width direction of the body region 301, the gate structure, the source region 312, the body region 301 and the drift region 302 all extend continuously, wherein the first conductive contact hole may include more than one and is selectively partially set in the source region 312, and the second conductive contact hole includes more than one and is selectively partially set in the drift region 301, for example, in the drain region 313 in the drift region 301.

[0083] So far, the description of the key steps of the method for manufacturing the semiconductor device of the present invention has been completed. The preparation of a complete semiconductor device may also include other steps, which will not be described one by one here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0084] In summary, the method for manufacturing a semiconductor device according to an embodiment of the present invention forms a barrier layer on the sidewall of the trench, and the barrier layer can avoid the bird's beak effect when forming the field oxide layer, thereby forming a nearly vertical field oxide layer, that is, the curvature of the field oxide layer is large enough, the lateral diffusion is almost non-existent, and the current path is shorter, thereby reducing the on-resistance of the device, and the thickness of the field oxide layer is not limited, and a thicker field oxide layer can be formed, thereby increasing the breakdown voltage of the device, and the process stability and feasibility are strong, thereby improving the device performance. For example, by making the barrier layer located on the sidewall of the trench have a uniform thickness, or by making the thickness of the barrier layer located on the sidewall gradually decrease from top to bottom, the influence on the doping concentration of the drift region is minimized, thereby minimizing the influence on the breakdown voltage of the device. For example, when performing an inclined ion implantation process to form a barrier layer, the barrier layer located on the sidewall of the trench 306 also extends into the liner layer, which can further enhance the barrier layer's blocking effect on oxygen atoms during the formation of the field oxide layer.

[0085] Embodiment 2:

[0086] The present invention further provides a semiconductor device, which is prepared by the method in the above-mentioned embodiment 1. Since the device of the present application is prepared by the above-mentioned method, it has the same advantages as the above-mentioned method.

[0087] In one example, if Figure 3HAs shown, the semiconductor device includes a substrate 300, in which a body region 301 and a drift region 302 are formed, the drift region 302 has a first conductivity type, and the body region 301 has a second conductivity type, wherein the first conductivity type is an N-type conductivity type and the second conductivity type is a P-type conductivity type, or the first conductivity type is a P-type conductivity type and the second conductivity type is an N-type conductivity type.

[0088] In one example, the substrate 300 is a bulk silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the substrate 300 may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) or germanium on insulator (GeOI), etc. Although several examples of materials that can form the substrate 300 are described herein, any material that can be used as the substrate 300 falls within the spirit and scope of the present invention.

[0089] In one example, if Figure 3H As shown, a well region 303 is formed in the substrate 300 , the body region 301 and the drift region 302 are located in the well region 303 , and the well region 303 has a first conductivity type. Exemplarily, an ion implantation process may be performed on the substrate 300 to form the body region 301 , the drift region 302 and the well region 303 .

[0090] In one example, a field oxide layer 308 is further included, which fills the trench 306 and has a top surface higher than the surface of the substrate 300 . A barrier layer 307 is also formed on the sidewall of the trench 306 . The barrier layer 307 is formed by an inclined ion implantation process into the trench 306 .

[0091] In one example, if Figure 3H As shown, the gate structure is also included, and the gate structure covers a portion of the field oxide layer 308 and covers a portion of the surface of the body region 301 and a portion of the drift region 302. Specifically, as Figure 3HAs shown, the gate structure may include a gate oxide layer 309 and a gate electrode layer 310, wherein: the gate oxide layer 309 covers a portion of the surface of the body region 301 and a portion of the drift region 302, and a side wall of the gate oxide layer 309 contacts the field oxide layer 308, and the gate oxide layer 309 plays an isolation and protection role; the gate electrode layer 310 covers the top surface of the gate oxide layer 309 and a portion of the field oxide layer 308. Exemplarily, the gate oxide layer 309 is an oxide layer, such as silicon dioxide and other materials, but is not limited to the above examples. Exemplarily, the gate electrode layer 310 is composed of polysilicon material, and generally metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate layer. Exemplarily, the top surface of the field oxide layer 308 is higher than the top surface of the gate oxide layer 309.

[0092] In one example, if Figure 3H As shown, it also includes a source region 312 located in the body region 301 and a drain region 313 located in the drift region 302, the source region 312 and the drain region 313 are respectively located on both sides of the gate structure, and the source region 312 and the drain region 313 have a first conductivity type. Exemplarily, it also includes a body contact region 314 located in the body region 301, the body contact region 314 has a second conductivity type, and the doping concentration of the body contact region 314 is higher than the doping concentration of the body region 301. Exemplarily, a self-aligned silicide layer can also be formed on the gate electrode layer 310, the source region 312 and the drain region 313. Exemplarily, an STI structure is also formed in the body region 301 and the drift region 302.

[0093] In one example, the gate structure and the field oxide layer 308 form a gate field plate structure, and the gate field plate structure can weaken the surface electric field of the drift region 302, which is beneficial to improving the breakdown voltage of the device.

[0094] In an example, taking the case where the first conductivity type is N-type and the second conductivity type is P-type, by applying voltage to the gate structure, free electrons in the body region 301 can be attracted to approach the gate structure, and holes in the body region 301 can be repelled, thereby forming an N channel in the body region 301. At this time, free electrons can move from the source region 312 to the drain region 313 through the N channel.

[0095] In some examples, the first conductive contact hole and the second conductive contact hole are respectively used to lead out the source region and the drain region, wherein the first conductive contact hole is also electrically connected to the first metal layer as the source, and the second conductive contact hole is also electrically connected to the second metal layer as the drain. Optionally, a conductive contact hole electrically connected to the body contact region 314 may also be included, and the conductive contact hole may also be electrically connected to the source.

[0096] The structure of the semiconductor device of the present invention has been introduced so far. The complete device may also include other component structures, which will not be described in detail here.

[0097] The semiconductor device of the embodiment of the present invention is manufactured by the above method, and a barrier layer is formed on the side wall of the groove. The barrier layer can avoid the bird's beak effect when forming the field oxide layer, thereby forming a nearly vertical field oxide layer, that is, the curvature of the field oxide layer is large enough, and there is almost no lateral diffusion, and the current path is shorter, thereby reducing the on-resistance of the device. At the same time, the thickness of the field oxide layer is not limited, and a thicker field oxide layer can be formed, thereby increasing the breakdown voltage of the device, and the process stability and feasibility are strong, thereby improving the device performance.

[0098] Embodiment three:

[0099] Another embodiment of the present invention provides an electronic device including the aforementioned semiconductor device.

[0100] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including the semiconductor device. The electronic device of the embodiment of the present invention has better performance due to the use of the semiconductor device.

[0101] Although multiple embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be conceived by those skilled in the art, all of which will fall within the spirit and scope of the concepts disclosed in the present invention. More particularly, various modifications and changes may be made to the arrangements and / or components of the combined arrangements of the subject matter within the scope of the present disclosure, the drawings, and the appended claims. In addition to modifications and changes to the components and / or arrangements, the use of alternatives is also an obvious option for those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Providing a substrate, wherein a body region and a drift region extending from a surface of the substrate into the substrate are formed in the substrate, the drift region has a first conductivity type, and the body region has a second conductivity type; forming a liner layer and a mask layer in sequence on the surface of the substrate, wherein the liner layer comprises an oxide layer; patterning the liner layer and the mask layer to expose a portion of the drift region, and etching the substrate to form a trench in the drift region; Performing an inclined ion implantation process to form a barrier layer at the bottom and sidewalls of the trench, wherein the thickness of the barrier layer located on the sidewalls of the trench gradually decreases from top to bottom; removing the barrier layer at the bottom of the trench; Thermally growing an oxide layer through a furnace tube to form a field oxide layer, wherein the field oxide layer fills the trench, wherein a top surface of the field oxide layer is higher than a surface of the substrate; removing the mask layer and the liner layer in sequence; forming a gate structure, wherein the gate structure covers a portion of the field oxide layer and covers a portion of the body region and a portion of the surface of the drift region; When the oblique ion implantation process is performed to form the barrier layer, the barrier layer located on the sidewall of the trench also extends into the liner layer and penetrates the liner layer.

2. The manufacturing method according to claim 1, characterized in that: Forming the gate structure includes: forming a gate oxide layer, wherein the gate oxide layer covers a portion of the surface of the body region and a portion of the drift region, and a side wall of the gate oxide layer contacts the field oxide layer; A gate electrode layer is formed, wherein the gate electrode layer covers a top surface of the gate oxide layer and a portion of the field oxide layer, wherein the gate structure includes the gate oxide layer and the gate electrode layer.

3. The manufacturing method according to claim 2, characterized in that: A top surface of the field oxide layer is higher than a top surface of the gate oxide layer.

4. The manufacturing method according to claim 1, characterized in that: After removing the mask layer and the liner layer in sequence, the method further includes: A source region located in the body region and a drain region located in the drift region are formed, wherein the source region and the drain region are respectively located at two sides of the gate structure, and the source region and the drain region have a first conductivity type.

5. The manufacturing method according to claim 1, characterized in that: A well region is also formed in the substrate, the body region and the drift region are located in the well region, and the well region has a first conductivity type.

6. The manufacturing method according to claim 1, characterized in that: The implanted ions in the tilted ion implantation process include nitrogen ions; and / or, The implantation ion dose of the inclined ion implantation process is greater than or equal to 10 15 / cm 2 and / or, The tilted ion implantation process uses a bidirectional tilt angle to implant ions.

7. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to any one of claims 1 to 6.

8. An electronic device, characterized in that: The electronic device includes the semiconductor device according to claim 7.

Images