Light emitting diode chip and preparation method thereof

Abstract

The invention provides a light emitting diode chip and a preparation method thereof, and belongs to the technical field of semiconductors. The light-emitting diode chip comprises a substrate, an epitaxial layer, a passivation layer, an N-type electrode and an N-type electrode wire; the epitaxial layer is located on one side of the substrate, the N-type electrode and the N-type electrode wire are located on the side, opposite to the substrate, of the epitaxial layer, and the N-type electrode is connected with the N-type electrode wire; the passivation layer comprises a first protection part and a second protection part which are spaced from each other, the first protection part covers between the outer edge of the substrate and the outer edge of the epitaxial layer, and the second protection part covers between the outer edge of the N-type electrode and the epitaxial layer and outside the N-type electrode wire. According to the invention, the routing reliability of the light-emitting diode chip can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a light emitting diode chip and a method for preparing the same. Background Art

[0002] A light emitting diode (LED) is a semiconductor diode that can convert electrical energy into light energy.

[0003] In the related art, the LED chip is the main component of the LED, which mainly includes an epitaxial layer, an N-type electrode and a P-type electrode, and the N-type electrode and the P-type electrode are respectively located on opposite sides of the epitaxial layer. Due to the shading of the N-type electrode, the brightness of the LED chip will be lost to a certain extent. In order to reduce the shading of the N-type electrode, the size of the N-type electrode is usually designed to be smaller.

[0004] However, as the size of the N-type electrode is reduced, its structural strength is also reduced, which can easily lead to reduced reliability of wire bonding. Summary of the invention

[0005] The embodiment of the present disclosure provides a light emitting diode chip and a method for manufacturing the same, which can effectively improve the wire bonding reliability of the light emitting diode chip. The technical solution is as follows:

[0006] On the one hand, the embodiments of the present disclosure provide a light-emitting diode chip, including a substrate, an epitaxial layer, a passivation layer, an N-type electrode, and an N-type electrode line;

[0007] The epitaxial layer is located on one side of the substrate, the N-type electrode and the N-type electrode line are located on a side of the epitaxial layer facing away from the substrate, and the N-type electrode and the N-type electrode line are connected;

[0008] The passivation layer includes a first protection portion and a second protection portion spaced apart from each other, wherein the first protection portion covers between the outer edge of the substrate and the outer edge of the epitaxial layer, and the second protection portion covers between the outer edge of the N-type electrode and the epitaxial layer and outside the N-type electrode line.

[0009] In one implementation of the present disclosure, the first protecting portion is located in the cutting path area, the first protecting portion at least partially covers the outer edge of the epitaxial layer, and extends along the side of the epitaxial layer to the substrate, so that the first protecting portion at least partially covers the outer edge of the substrate.

[0010] In another implementation of the present disclosure, a distance between an inner edge of the first protection portion and an outer edge of the epitaxial layer is 0.1 to 20 μm.

[0011] In yet another implementation of the present disclosure, the second protection portion includes a first sub-portion and a second sub-portion, and the first sub-portion and the second sub-portion are connected;

[0012] The first sub-portion covers between the outer edge of the N-type electrode and the epitaxial layer;

[0013] The second sub-portion covers the outside of the N-type electrode line.

[0014] In another implementation of the present disclosure, the first sub-portion at least partially covers the outer edge of the N-type electrode and extends along the side of the N-type electrode to the epitaxial layer, so that the first sub-portion at least partially covers the epitaxial layer.

[0015] In yet another implementation of the present disclosure, an extension direction of the second sub-portion is consistent with an extension direction of the N-type electrode line.

[0016] In yet another implementation of the present disclosure, the distance between the inner edge of the first sub-portion and the outer edge of the N-type electrode is 0.1 to 30 μm;

[0017] The distance between the outer edge of the first sub-portion and the outer edge of the N-type electrode is 0.1-20 μm.

[0018] In yet another implementation of the present disclosure, a distance between an outer edge of the second sub-portion and an outer edge of the N-type electrode line is 0.1-20 μm.

[0019] In yet another implementation of the present disclosure, the thickness of the passivation layer is 0.1-1000 μm.

[0020] On the other hand, an embodiment of the present disclosure provides a method for preparing a light-emitting diode chip, which is applicable to the light-emitting diode chip described in the above aspect, and comprises:

[0021] providing a substrate;

[0022] preparing an epitaxial layer on one side of the substrate;

[0023] Preparing an N-type electrode and an N-type electrode line on one side of the epitaxial layer;

[0024] A passivation layer is prepared on one side of the epitaxial layer, and the passivation layer is photolithographically processed to obtain a first protection portion and a second protection portion, wherein the first protection portion covers between the outer edge of the substrate and the outer edge of the epitaxial layer, and the second protection portion covers between the outer edge of the N-type electrode and the epitaxial layer and outside the N-type electrode line.

[0025] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0026] The light-emitting diode chip provided by the embodiment of the present disclosure includes a passivation layer, and the passivation layer includes a first protection part and a second protection part, wherein the first protection part covers between the outer edge of the substrate and the outer edge of the epitaxial layer, and is used to protect the outer edge of the epitaxial layer, and the second protection part covers between the outer edge of the N-type electrode and the epitaxial layer and outside the N-type electrode line, and is used to protect the outer edge of the N-type electrode and the N-type electrode line. In this way, under the protective effect of the passivation layer, the structural strength of the N-type electrode and the N-type electrode line can be improved, thereby effectively improving the wire bonding reliability of the light-emitting diode chip and avoiding the phenomenon of electrode digging. In addition, since the first protection part and the second protection part are spaced from each other and belong to two independent parts, there is a large gap between the two, which effectively reduces the shielding of the passivation layer to light, that is, reduces the influence of the passivation layer on the brightness of the light-emitting diode.

[0027] That is to say, by dividing the passivation layer into two parts, the first protection part and the second protection part, the N-type electrode and the N-type electrode line can be protected and reinforced, and the influence of the passivation layer on the brightness of the light-emitting diode can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 is a top view of a light emitting diode chip provided by an embodiment of the present disclosure;

[0030] Figure 2 The embodiment of the present disclosure provides Figure 1 AA direction cross-sectional view;

[0031] Figure 3 The embodiment of the present disclosure provides Figure 2 A magnified view of part A;

[0032] Figure 4 The embodiment of the present disclosure provides Figure 1 BB direction cross-sectional view;

[0033] Figure 5 It is a flow chart of a method for preparing a light-emitting diode chip provided in an embodiment of the present disclosure.

[0034] The symbols in the figure mean the following:

[0035] 10. Substrate;

[0036] 20. Epitaxial layer;

[0037] 30. Passivation layer;

[0038] 310, first protection part; 320, second protection part; 321, first sub-part; 322, second sub-part;

[0039] 40. N-type electrode;

[0040] 50. N-type electrode wire;

[0041] 60. P-type electrode.

[0042] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0044] The embodiment of the present disclosure provides a light emitting diode chip, Figure 1 A top view of a light emitting diode chip provided in an embodiment of the present disclosure, Figure 2 for Figure 1 AA direction section view, see Figure 1 and Figure 2 The light emitting diode chip includes a substrate 10 , an epitaxial layer 20 , a passivation layer 30 , an N-type electrode 40 , and an N-type electrode line 50 .

[0045] The epitaxial layer 20 is located on one side of the substrate 10, the N-type electrode 40 and the N-type electrode line 50 are located on the side of the epitaxial layer 20 facing away from the substrate 10, and the N-type electrode 40 and the N-type electrode line 50 are connected. The passivation layer 30 includes a first protection portion 310 and a second protection portion 320 spaced apart from each other, the first protection portion 310 covers between the outer edge of the substrate 10 and the outer edge of the epitaxial layer 20, and the second protection portion 320 covers between the outer edge of the N-type electrode 40 and the epitaxial layer 20 and outside the N-type electrode line 50.

[0046] The light-emitting diode chip provided by the embodiment of the present disclosure includes a passivation layer 30, and the passivation layer 30 includes a first protection portion 310 and a second protection portion 320, wherein the first protection portion 310 covers between the outer edge of the substrate 10 and the outer edge of the epitaxial layer 20, and is used to protect the outer edge of the epitaxial layer 20, and the second protection portion 320 covers between the outer edge of the N-type electrode 40 and the epitaxial layer 20 and outside the N-type electrode line 50, and is used to protect the outer edge of the N-type electrode 40 and the N-type electrode line 50. In this way, under the protection of the passivation layer 30, the structural strength of the N-type electrode 40 and the N-type electrode line 50 can be improved, thereby effectively improving the wire bonding reliability of the light-emitting diode chip and avoiding the electrode digging phenomenon. In addition, since the first protection portion 310 and the second protection portion 320 are spaced from each other and belong to two independent parts, there is a large gap between the two, which effectively reduces the blocking of light by the passivation layer 30, that is, reduces the influence of the passivation layer 30 on the brightness of the light-emitting diode.

[0047] That is, by dividing the passivation layer 30 into the first protection portion 310 and the second protection portion 320 , the N-type electrode 40 and the N-type electrode line 50 can be protected and reinforced, and the influence of the passivation layer 30 on the brightness of the light-emitting diode can be minimized.

[0048] In this embodiment, the thickness of the passivation layer 30 is 0.1-1000 μm.

[0049] In the above implementation, the thickness of the passivation layer 30 is designed to be the above value, which can prevent the passivation layer 30 from losing functionality due to being too thin, and can also prevent the passivation layer 30 from increasing the preparation cost due to being too thick.

[0050] For example, the passivation layer 30 is SiN x film.

[0051] Figure 3 for Figure 2 A magnified view of part A, combined with Figure 3 In this embodiment, the first protection portion 310 is located in the cutting path area, the first protection portion 310 at least partially covers the outer edge of the epitaxial layer 20, and extends along the side of the epitaxial layer 20 to the substrate 10, so that the first protection portion 310 at least partially covers the outer edge of the substrate 10.

[0052] In the above implementation, the first protection portion 310 is located in the cutting path area, and the first protection portion 310 covers the outer edge of the epitaxial layer 20 and the outer edge of the substrate 10, so as to seal the junction between the outer edge of the epitaxial layer 20 and the outer edge of the substrate 10 in the cutting path area, thereby effectively protecting the epitaxial layer 20 and preventing moisture from entering through the gap between the epitaxial layer 20 and the substrate 10.

[0053] Exemplarily, a distance a between an inner edge of the first protection portion 310 and an outer edge of the epitaxial layer 20 is 0.1-20 μm.

[0054] In the above implementation, the distance between the inner edge of the first protection portion 310 and the outer edge of the epitaxial layer 20 determines the coverage of the epitaxial layer 20 by the first protection portion 310. The larger the above distance, the greater the coverage of the epitaxial layer 20 by the first protection portion 310, and vice versa.

[0055] The distance between the inner edge of the first protection portion 310 and the outer edge of the epitaxial layer 20 is designed to be the above value, which can ensure the protection of the epitaxial layer 20 by the first protection portion 310 on the one hand, and minimize the impact of the first protection portion 310 on brightness on the other hand.

[0056] Continue to see Figure 3 In this embodiment, the second protection portion 320 includes a first sub-portion 321 and a second sub-portion 322, the first sub-portion 321 and the second sub-portion 322 are connected, the first sub-portion 321 covers between the outer edge of the N-type electrode 40 and the epitaxial layer 20, and the second sub-portion 322 covers outside the N-type electrode line 50.

[0057] In the above implementation, the first sub-portion 321 is used to seal the junction between the outer edge of the N-type electrode 40 and the epitaxial layer 20, and the second sub-portion 322 is used to seal the junction between the N-type electrode line 50 and the epitaxial layer 20. Through the first sub-portion 321 and the second sub-portion 322, on the one hand, the structural strength of the N-type electrode 40 and the N-type electrode line 50 can be improved to play a supporting role, and on the other hand, moisture can be prevented from entering through the gap between the N-type electrode 40 and the epitaxial layer 20, and the gap between the N-type electrode line 50 and the epitaxial layer 20.

[0058] Exemplarily, the first sub-portion 321 at least partially covers the outer edge of the N-type electrode 40 and extends along the side of the N-type electrode 40 to the epitaxial layer 20 , so that the first sub-portion 321 at least partially covers the epitaxial layer 20 .

[0059] The first sub-portion 321 covers the outer edge of the N-type electrode 40 and the epitaxial layer 20, so as to seal the interface between the outer edge of the N-type electrode 40 and the epitaxial layer 20, thereby effectively supporting the outer edge of the N-type electrode 40, improving the wire bonding reliability of the N-type electrode 40, and preventing moisture from entering through the gap between the N-type electrode 40 and the epitaxial layer 20.

[0060] Exemplarily, a distance b between an inner edge of the first sub-portion 321 and an outer edge of the N-type electrode 40 is 0.1-30 μm, and a distance c between an outer edge of the first sub-portion 321 and an outer edge of the N-type electrode 40 is 0.1-20 μm.

[0061] In the above implementation, the distance between the inner edge of the first sub-portion 321 and the outer edge of the N-type electrode 40 determines the coverage of the first sub-portion 321 on the N-type electrode 40. The larger the distance, the greater the coverage of the first sub-portion 321 on the N-type electrode 40, and vice versa. The distance between the outer edge of the first sub-portion 321 and the outer edge of the N-type electrode 40 determines the coverage of the first sub-portion 321 on the epitaxial layer 20. The larger the distance, the greater the coverage of the first sub-portion 321 on the epitaxial layer 20, and vice versa.

[0062] The distance between the inner edge of the first sub-portion 321 and the outer edge of the N-type electrode 40, and the distance between the outer edge of the first sub-portion 321 and the outer edge of the N-type electrode 40 are designed to be the above-mentioned values. On the one hand, it can ensure that the first sub-portion 321 protects the N-type electrode 40 and the epitaxial layer 20, and on the other hand, it can also minimize the impact of the first sub-portion 321 on the brightness.

[0063] See again Figure 1 , illustratively, the extension direction of the second sub-portion 322 is consistent with the extension direction of the N-type electrode line 50 .

[0064] The second sub-portion 322 extends along the length direction of the N-type electrode line 50 to ensure that the projection area of ​​the N-type electrode line 50 is reduced as much as possible on the basis of completely covering the N-type electrode line 50 , thereby reducing its influence on the brightness.

[0065] Figure 4 for Figure 1 BB direction cross-sectional view, combined with Figure 4 , exemplarily, a distance d between an outer edge of the second sub-portion 322 and an outer edge of the N-type electrode line 50 is 0.1-20 μm.

[0066] In the above implementation, the distance between the outer edge of the second sub-portion 322 and the outer edge of the N-type electrode line 50 determines the coverage of the second sub-portion 322 for the N-type electrode line 50. The larger the above distance, the greater the coverage of the first sub-portion 321 for the N-type electrode 40, and vice versa.

[0067] The distance between the outer edge of the second sub-portion 322 and the outer edge of the N-type electrode line 50 is designed to be the above value, which can ensure the protection of the N-type electrode line 50 by the second sub-portion 322 and minimize the impact of the second sub-portion 322 on brightness.

[0068] In this embodiment, the epitaxial layer 20 includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence.

[0069] In the above implementation, the first semiconductor layer has a first conductivity type, and the second semiconductor layer has a second conductivity type different from the first conductivity type. Energy transition occurs between the first semiconductor layer and the second semiconductor layer, so that the active layer emits light.

[0070] Exemplarily, the first semiconductor layer is a P-type aluminum indium phosphide layer, the active layer is a quantum well layer, and the second semiconductor layer is an N-type aluminum indium phosphide layer.

[0071] In this embodiment, the light emitting diode chip further includes a P-type electrode 60 . The P-type electrode 60 is located on a side of the substrate 10 facing away from the epitaxial layer 20 .

[0072] In the related art, there are two types of light emitting diode chips. The first type is that no passivation layer is provided at the N-type electrode, and the second type is that the passivation layer completely covers the outside of the epitaxial layer.

[0073] The first type of LED chip is used as a first control group, and a normal wire bonding test and a strict wire bonding test are performed on the LED chip provided by the embodiment of the present disclosure, and the data shown in Table 1 are obtained.

[0074]

[0075] Table 1

[0076] As shown in Table 1, 20 LED chips of each scheme were subjected to normal wire bonding test and strict wire bonding test. The data showed that 5 and 3 chips of the first control group had electrode digging abnormalities, while there was no electrode digging abnormality in the embodiment of the present disclosure, and the improvement ratio reached 25%.

[0077] The second light-emitting diode chip was used as a second control group and compared with the light-emitting diode chip provided in the embodiment of the present disclosure to perform a brightness test, and the data shown in Table 2 were obtained.

[0078]

[0079] Table 2

[0080] As can be seen from Table 2, four groups of brightness comparison tests were conducted on the LED chips of the two schemes, and it can be seen that the brightness of the LED chip provided by the embodiment of the present disclosure is improved by about 4-5% compared with the second control group.

[0081] Figure 5 A flowchart of a method for preparing a light emitting diode chip provided in an embodiment of the present disclosure, combined with Figure 5 In this embodiment, the preparation method includes:

[0082] Step 501: Provide a substrate 10.

[0083] Exemplarily, the substrate 10 is a silicon substrate 10, which has good thermal conductivity and thermal expansion coefficient matching. The substrate 10 provides a growth basis for the subsequent growth of the epitaxial layer 20, and can also provide a certain strength for the light-emitting diode chip to ensure that the chip will not break.

[0084] Step 502 : preparing an epitaxial layer 20 on one side of the substrate 10 .

[0085] Exemplarily, a metal-organic chemical vapor deposition (MOCVD) device is used to sequentially grow a first semiconductor layer, an active layer, and a second semiconductor layer. The first semiconductor layer has a first conductivity type, and the second semiconductor layer has a second conductivity type different from the first conductivity type. Energy transition occurs between the first semiconductor layer and the second semiconductor layer, and the active layer emits light.

[0086] Exemplarily, the first semiconductor layer is a P-type aluminum indium phosphide layer, the active layer is a quantum well layer, and the second semiconductor layer is an N-type aluminum indium phosphide layer.

[0087] Step 503 : preparing an N-type electrode 40 and an N-type electrode line 50 on one side of the epitaxial layer 20 .

[0088] Step 504 : preparing a passivation layer 30 on one side of the epitaxial layer 20 , and performing photolithography on the passivation layer 30 to obtain a first protection portion 310 and a second protection portion 320 .

[0089] The first protection portion 310 covers between the outer edge of the substrate 10 and the outer edge of the epitaxial layer 20 , and the second protection portion 320 covers between the outer edge of the N-type electrode 40 and the epitaxial layer 20 and outside the N-type electrode line 50 .

[0090] Exemplarily, step 504 includes the following steps:

[0091] Step 5041: Using a plasma enhanced chemical vapor deposition (PECVD) device, the growth temperature is set to 200-400° C. to prepare a passivation layer 30 with a thickness of 0.1-1000 μm.

[0092] Step 5042: Surface treatment.

[0093] Exemplarily, the surface treatment includes dehydration baking and coating of adhesive. The dehydration baking temperature is 140-200°C. At the same time, adhesive is used, and the adhesive component is hexamethyldisilazane. Hexamethyldisilazane is coated on the surface and heated to generate an organic compound with siloxane as the main body. The compound is a surfactant that can successfully change the wafer surface from hydrophilic to hydrophobic, so that the wafer and the photoresist can be better combined.

[0094] Step 5043: Spreading the glue.

[0095] Exemplarily, using positive photoresist, firstly, the photoresist is dripped on the surface of the wafer, and then spread by accelerated rotation at a speed of 1000 to 5000 rpm for 10 to 60 seconds.

[0096] Step 5044: Soft bake.

[0097] Exemplarily, the photoresist is baked to evaporate the solvent in the photoresist at a temperature of 80 to 120° C. for 60 to 180 seconds. The baked photoresist remains soft but is more firmly bonded to the wafer, thereby avoiding incomplete image formation during exposure and excess photoresist drift during etching.

[0098] Step 5045: Exposure.

[0099] For example, the wafer is exposed to ultraviolet light to transfer the pattern to the photoresist. The photoresist after exposure to light will undergo a degradation reaction, causing its solubility in the developer to be much greater than that of the unexposed photoresist.

[0100] Step 5046: Development.

[0101] Exemplarily, the unnecessary photoresist is dissolved with a developer, and the pattern on the photoresist is copied to the photoresist. The pattern on the positive photoresist is consistent with the pattern on the photoresist. Check whether there is any abnormality in the pattern after development, and ensure that the first sub-portion 321 of the passivation layer 30 covers the edge of the N-type electrode 40 and cannot deviate.

[0102] Step 5047: Hard bake.

[0103] For example, the heating oven makes the adhesive film adhere more firmly to the wafer surface, and the pit corrosion ability of the photoresist is also increased after the film is hardened. The temperature during the hardening process is higher than the temperature of the previous baking.

[0104] Step 5048: Etching.

[0105] Exemplarily, the passivation layer 30 is etched using an ammonium fluoride etching solution for 60 to 240 seconds. After etching, it is checked that the first sub-portion 321 of the passivation layer 30 covers the edge of the N-type electrode 40 and cannot deviate.

[0106] Step 5049: Remove glue.

[0107] Exemplarily, the photoresist on the surface of the wafer is removed by using a stripping solution to expose the passivation layer 30 structure.

[0108] A passivation layer 30 is prepared on one side of the epitaxial layer 20, and the passivation layer 30 is photolithographically processed to obtain a first protection portion 310 and a second protection portion 320. The first protection portion 310 covers between the outer edge of the substrate 10 and the outer edge of the epitaxial layer 20, and is used to protect the outer edge of the epitaxial layer 20. The second protection portion 320 covers between the outer edge of the N-type electrode 40 and the epitaxial layer 20 and outside the N-type electrode line 50, and is used to protect the outer edge of the N-type electrode 40 and the N-type electrode line 50. In this way, under the protective effect of the passivation layer 30, the structural strength of the N-type electrode 40 and the N-type electrode line 50 can be improved, thereby effectively improving the wire bonding reliability of the light-emitting diode chip and avoiding the digging electrode phenomenon. In addition, since the first protection portion 310 and the second protection portion 320 are spaced from each other and belong to two independent parts, there is a large gap between the two, which effectively reduces the blocking of light by the passivation layer 30, that is, reduces the influence of the passivation layer 30 on the brightness of the light-emitting diode.

[0109] That is to say, by preparing the passivation layer 30 and dividing the passivation layer 30 into two parts, namely the first protection part 310 and the second protection part 320, the N-type electrode 40 and the N-type electrode line 50 can be protected and reinforced, and the influence of the passivation layer 30 on the brightness of the light-emitting diode can be minimized.

[0110] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0111] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode chip, characterized in that: It comprises a substrate (10), an epitaxial layer (20), a passivation layer (30), an N-type electrode (40) and an N-type electrode line (50); The epitaxial layer (20) is located on one side of the substrate (10), the N-type electrode (40) and the N-type electrode line (50) are located on a side of the epitaxial layer (20) that is away from the substrate (10), and the N-type electrode (40) and the N-type electrode line (50) are connected; The passivation layer (30) comprises a first protection portion (310) and a second protection portion (320) which are spaced apart from each other, wherein the first protection portion (310) covers between the outer edge of the substrate (10) and the outer edge of the epitaxial layer (20), and the second protection portion (320) covers between the outer edge of the N-type electrode (40) and the epitaxial layer (20) and outside the N-type electrode line (50).

2. The light emitting diode chip according to claim 1, characterized in that: The first protection portion (310) is located in the cutting path area, the first protection portion (310) at least partially covers the outer edge of the epitaxial layer (20), and extends along the side of the epitaxial layer (20) to the substrate (10), so that the first protection portion (310) at least partially covers the outer edge of the substrate (10).

3. The light emitting diode chip according to claim 2, characterized in that: The distance between the inner edge of the first protection portion (310) and the outer edge of the epitaxial layer (20) is 0.1 to 20 μm.

4. The light emitting diode chip according to claim 1, characterized in that: The second protection portion (320) comprises a first sub-portion (321) and a second sub-portion (322), wherein the first sub-portion (321) and the second sub-portion (322) are connected; The first sub-portion (321) covers between the outer edge of the N-type electrode (40) and the epitaxial layer (20); The second sub-portion (322) covers the outside of the N-type electrode line (50).

5. The light emitting diode chip according to claim 4, characterized in that: The first sub-portion (321) at least partially covers the outer edge of the N-type electrode (40) and extends along the side of the N-type electrode (40) to the epitaxial layer (20), so that the first sub-portion (321) at least partially covers the epitaxial layer (20).

6. The light emitting diode chip according to claim 4, characterized in that: The extension direction of the second sub-portion (322) is consistent with the extension direction of the N-type electrode line (50).

7. The light emitting diode chip according to claim 4, characterized in that: The distance between the inner edge of the first sub-portion (321) and the outer edge of the N-type electrode (40) is 0.1 to 30 μm; The distance between the outer edge of the first sub-portion (321) and the outer edge of the N-type electrode (40) is 0.1-20 μm.

8. The light emitting diode chip according to claim 4, characterized in that: The distance between the outer edge of the second sub-portion (322) and the outer edge of the N-type electrode line (50) is 0.1-20 μm.

9. The light emitting diode chip according to any one of claims 1 to 8, characterized in that: The thickness of the passivation layer (30) is 0.1-1000 μm.

10. A method for preparing a light emitting diode chip, characterized in that: Suitable for preparing the light emitting diode chip according to claim 1, the preparation method comprising: Providing a substrate (10); Preparing an epitaxial layer (20) on one side of the substrate (10); Preparing an N-type electrode (40) and an N-type electrode line (50) on one side of the epitaxial layer (20); A passivation layer (30) is prepared on one side of the epitaxial layer (20), and the passivation layer (30) is subjected to photolithography to obtain a first protection portion (310) and a second protection portion (320), wherein the first protection portion (310) covers between the outer edge of the substrate (10) and the outer edge of the epitaxial layer (20), and the second protection portion (320) covers between the outer edge of the N-type electrode (40) and the epitaxial layer (20) and outside the N-type electrode line (50).

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