Display panel and method for manufacturing display panel

Abstract

The invention relates to a display panel and a method of manufacturing the same. A display panel according to one or more embodiments of the present disclosure may include a base layer, a pixel defining film over the base layer and defining an emission opening portion, a partition wall including: a first partition wall layer over the pixel defining film and defining an emission opening portion; a lower partition wall layer including an insulating material and an upper partition wall layer including a conductive material over the lower partition wall layer; and a second partition wall layer over the first partition wall layer and defining a partition wall opening portion overlapping the emission opening portion, the light emitting element including an anode, an intermediate layer over the anode in contact with the lower partition wall layer and spaced apart from the upper partition wall layer, and a cathode over the intermediate layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0091051 filed in the Korean Intellectual Property Office on July 13, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more aspects of the present disclosure relate to a display panel having improved display quality. Background Art

[0004] Display devices (such as televisions, monitors, smart phones, and tablet computers) that provide images to users include display panels that display images. Various display panels such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels are developed as display panels.

[0005] The organic light emitting display panel may include an anode, a cathode, and an emission pattern. The emission pattern may be separated in each of the emission regions, and the cathode may provide a common voltage to each of the emission regions. Summary of the invention

[0006] The present disclosure provides a display panel capable of preventing or reducing generation of leakage current to provide improved display quality and a method for manufacturing the display panel.

[0007] One or more embodiments of the present disclosure provide a display panel, which may include a base layer, a pixel defining film, a partition wall, and a light-emitting element, wherein the pixel defining film is above the base layer and defines an emission opening portion, the partition wall includes: a first partition wall layer, which is above the pixel defining film and includes a lower partition wall layer containing an insulating material and an upper partition wall layer containing a conductive material above the lower partition wall layer; and a second partition wall layer, which is above the first partition wall layer and defines a partition wall opening portion overlapping with the emission opening portion, the light-emitting element includes an anode, an intermediate layer above the anode that is in contact with the lower partition wall layer and spaced apart from the upper partition wall layer, and a cathode above the intermediate layer.

[0008] The lower partition wall layer may include amorphous silicon (a-Si), and the upper partition wall layer may include n- + Silicon (n + 4).

[0009] The intermediate layer may include at least one organic layer doped with a p-type dopant.

[0010] The intermediate layer may include: a hole transport region including an organic layer doped with a p-type dopant over the anode; an emission layer over the hole transport region; and an electron transport region over the emission layer.

[0011] The intermediate layer may include: an emission structure above the anode; and a charge generation layer between the emission structures and including an organic layer doped with a p-type dopant.

[0012] The thickness of the lower partition wall layer may be less than about 0.5 times the thickness of the first partition wall layer.

[0013] The cathode may contact the upper partition wall layer and may be electrically connected to the partition wall.

[0014] The second partition wall layer may include a tip portion protruding from the first partition wall layer toward the partition wall opening portion.

[0015] The second partition wall layer may include at least one of molybdenum and titanium.

[0016] The display panel may further include a thin film encapsulation layer including a thin film over the light emitting element and including a lower inorganic encapsulation pattern covering the light emitting element and contacting the partition wall.

[0017] The lower inorganic encapsulation pattern may include silicon nitride (SiN x ).

[0018] The partition wall opening portion may include a first region where the light emitting element is located and a second region having a width smaller than that of the first region, wherein the first partition wall layer has a first inner surface defining the first region, and wherein the second partition wall layer has a second inner surface defining the second region.

[0019] In one or more embodiments of the present disclosure, the display panel may include a base layer, a pixel defining film, a partition wall, and a light emitting element, wherein the pixel defining film is above the base layer and defines an emission opening portion, the partition wall is above the pixel defining film, defines a partition wall opening portion corresponding to the emission opening portion, and includes: a lower partition wall layer including amorphous silicon (a-Si); an upper partition wall layer above the lower partition wall layer and including n + Silicon (n + Si); and a second partition wall layer, above the upper partition wall layer, and including a tip portion protruding from the lower partition wall layer and the upper partition wall layer toward the partition wall opening portion, the light emitting element is in the partition wall opening portion in a plan view, and includes an anode, an intermediate layer above the anode, and a cathode above the intermediate layer.

[0020] The intermediate layer may contact the lower partition wall layer and may be spaced apart from the upper partition wall layer, and the cathode may contact the upper partition wall layer.

[0021] The display panel may further include a sacrificial pattern between the anode electrode and the pixel defining film, and define a sacrificial opening portion overlapping the emission opening portion.

[0022] The thickness of the lower partition wall layer is smaller than the thickness of the upper partition wall layer.

[0023] In one or more embodiments of the present disclosure, a method for manufacturing a display panel may include: providing an initial display panel, the initial display panel including a base layer, an anode above the base layer, and a pixel defining film above the base layer and covering the anode; forming a first initial partition wall layer by depositing an insulating material and a conductive material having substantially equal etching selectivity above the initial display panel; forming a second initial partition wall layer above the initial display panel; etching the first initial partition wall layer and the second initial partition wall layer to form a partition wall defining a partition wall opening portion; and forming an emission pattern and a cathode in the partition wall opening portion.

[0024] The insulating material may include amorphous silicon (a-Si), and the conductive material may include n + Silicon (n + 4).

[0025] The second preliminary partition wall layer may include a conductive material having a lower etch rate than the first preliminary partition wall layer.

[0026] The method of manufacturing a display panel according to one or more embodiments may further include substantially simultaneously etching the first preliminary partition wall layer and the second preliminary partition wall layer by dry etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain aspects of the present disclosure. In the accompanying drawings:

[0028] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0029] Figure 2 is an exploded perspective view of a display device according to one or more embodiments of the present disclosure;

[0030] Figure 3 is a cross-sectional view of a display module according to one or more embodiments of the present disclosure;

[0031] Figure 4 is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0032] Figure 5is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure;

[0033] Figure 6 is an enlarged plan view of a portion of a display area of ​​a display panel according to one or more embodiments of the present disclosure;

[0034] Figure 7 It is along Figure 4 A cross-sectional view of a display panel according to one or more embodiments of the present disclosure, taken along line II';

[0035] Fig. 8A and Figure 8B Each is shown Figure 7 A magnified view of area AA in FIG.

[0036] Fig. 9 It is along Figure 6 A cross-sectional view of a display panel according to one or more embodiments of the present disclosure, taken along line II-II′ in FIG.

[0037] FIG. 10A to FIG. 10I are cross-sectional views illustrating some of the operations of a method of manufacturing a display panel according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0038] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for implementing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects of the present disclosure will be fully conveyed to those skilled in the art. Therefore, processes, elements and techniques that are redundant, irrelevant or unrelated to the description of the embodiments, or are not necessary for a person of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise stated, in all drawings and written descriptions, the same figure numerals, reference numerals or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0039] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments described herein. The use of "may", "can" or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and substitutions within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various technical interconnections and drives are possible. Each embodiment may be implemented independently of one another, or may be implemented in association.

[0040] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0041] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. As such, variations in the shapes illustrated, such as due to manufacturing techniques and / or tolerances, should be expected. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the illustrated shapes of elements, layers, or regions, but should include deviations in shapes such as those caused by manufacturing.

[0042] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0043] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper side", etc. can be used in this article to describe the relationship between an element or feature and another element (multiple elements) or feature (multiple features) as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, the spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the elements described as "below", "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. The device can be oriented in addition (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged at the upper or lower side of the second part, without being limited to the upper side of the second part based on the direction of gravity.

[0044] In addition, the phrase "in a plan view" means when the object portion is observed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross section taken by vertically cutting the object portion is observed from the side. The term "overlap" or "overlapped" means that the first object can be above or below the second object, or on one side of the second object, and vice versa. In addition, the term "overlap" can include stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "not overlap" can include meanings such as "spaced apart from each other", "offset from each other" or "separated from each other" and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "face" and "facing" can mean that the first object can be directly opposite or indirectly opposite to the second object. In the case where a third object is inserted between the first object and the second object, the first object and the second object can be understood to be indirectly opposite to each other, although still facing each other.

[0045] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to, such that one or more intervening elements, layers, regions, or components may be present. Furthermore, this may collectively mean direct or indirect coupling or connection, as well as integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, capacitors, etc. When describing embodiments, unless explicitly described as being directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component, or is directly on another component, without the presence of intervening components.

[0046] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" another part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components (such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to...") can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0047] For the purposes of this disclosure, when following an element of a list, expressions such as "at least one of," "any of," or "one or more of," modify the elements of the entire list without modifying the individual elements of the list. For example, "at least one of X, Y, and Z," and "at least one selected from the group consisting of X, Y, and Z," may be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ), or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, when following an element of a list, expressions such as "at least one of," "a plurality of," "one of," and other prepositional phrases modify the elements of the entire list without modifying the individual elements of the list.

[0048] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first section described below can be referred to as the second element, second component, second area, second layer or second section. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish between elements of different categories or groups. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0049] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0050] The terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, and the plural forms are intended to also include the singular forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes" and "including" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0051] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in the reverse order of the described order.

[0052] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than as terms of degree, and are intended to allow for inherent deviations in measurements or calculations that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of +5% / -5% of the corresponding value. In view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "approximately" as used herein include the values ​​and mean within an acceptable deviation range for a particular value determined by those of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0054] Figure 1 is a perspective view of a display device DD according to one or more embodiments of the present disclosure. Figure 2 is an exploded perspective view of a display device DD according to one or more embodiments of the present disclosure.

[0055] In one or more embodiments, the display device DD may be a large display device, such as a television, a monitor, or an outdoor billboard. The display device DD may also be a small or medium-sized display device, such as a personal computer (e.g., a notebook computer, a tablet computer), a personal digital assistant, a vehicle navigation unit, a game console, a smart phone, or a camera. However, the above devices are examples, and unless departing from the present disclosure, the display device DD may also be used as another display device. Figure 1 and Figure 2 A smartphone is shown as an example of the display device DD.

[0056] refer to Figure 1 and Figure 2 , the display device DD can display an image IM in a third direction DR3 on a display surface FS parallel to each of the first direction DR1 and the second direction DR2. The third direction DR3 can be a direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2. The image IM can include not only dynamic images but also static images. Figure 1A clock window and application icons are shown as examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0057] In one or more embodiments, the front surface (or top surface) and the rear surface (or bottom surface) of each component are defined based on the direction of displaying the image IM. The front surface and the rear surface may be opposite to each other in a third direction DR3, and a direction perpendicular to each of the front surface and the rear surface may be parallel to the third direction DR3. The directions represented by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be changed to other directions. The phrase "on a plane" used herein may mean a state when observed in the third direction DR3.

[0058] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to constitute an appearance of the display device DD.

[0059] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0060] The frame area BZA may be an area having a relatively low light transmittance compared to the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and surround the transmission area TA. However, this is shown as an example, and the frame area BZA of the window WP may be omitted. The window WP may include at least one functional layer of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited to any one embodiment.

[0061] The display module DM may be located below the window WP. The display module DM may be a component that substantially generates an image IM. The image IM generated by the display module DM may be displayed on a display surface IS of the display module DM and may be externally visible to a user through the transmissive area TA.

[0062] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area activated in response to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be an area covered by a bezel area BZA and may not be visible from the outside.

[0063] The housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide a preset inner space. The display module DM may be accommodated in the inner space.

[0064] The housing HAU may include a material having relatively high rigidity. For example, the housing HAU may include a plurality of frames and / or plates, each of which includes glass, plastic, or metal, or a combination thereof. The housing HAU may stably protect the components of the display module DM accommodated in the internal space from external impacts.

[0065] Figure 3 is a cross-sectional view of a display module DM according to one or more embodiments of the present disclosure.

[0066] refer to Figure 3 The display module DM may include a display panel DP and an input sensor INS. The display device DD according to one or more embodiments of the present disclosure (see Figure 1 ) may further include a protection member on the bottom surface of the display panel DP or an anti-reflection member and / or a window member on the top surface of the input sensor INS.

[0067] The display panel DP may be a light-emitting display panel. However, this is an example, and the present disclosure is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The emission layer in the organic light-emitting display panel may include an organic light-emitting material. The emission layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0068] The display panel DP may include a base layer BL. The display panel DP may include a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE, each of which may be located on the base layer BL (as used herein, "on" may mean "above"). The input sensor INS may be located directly on the thin film encapsulation layer TFE. In the present disclosure, "component A is directly located on component B" means that an adhesive layer is not located between component A and component B.

[0069] The base layer BL may include at least one plastic film. The base layer BL may be a flexible substrate, and may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc. Figure 2 The described display area DA and non-display area NDA may be similarly defined in the base layer BL.

[0070] The circuit element layer DP-CL may include at least one insulating layer and a circuit element. The insulating layer may include at least one inorganic layer and at least one organic layer. The circuit element may include a signal line, a driving circuit of a pixel, and the like.

[0071] The display element layer DP-OLED may include partition walls and a light emitting element. The light emitting element may include an anode, an intermediate layer and a cathode.

[0072] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be positioned to improve optical efficiency, and some of which may be positioned to protect the organic light emitting diode.

[0073] The input sensor INS obtains coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a conductive layer having a single-layer structure or a multi-layer structure. In addition, the input sensor INS may include an insulating layer having a single-layer or multi-layer structure. The input sensor INS may detect the external input by using a capacitive method. However, this is an example, and the present disclosure is not limited thereto. For example, in one or more embodiments, the input sensor INS may detect the external input by using an electromagnetic induction method or a pressure detection method. In one or more other embodiments of the present disclosure, the input sensor INS may be omitted.

[0074] Figure 4 is a plan view of a display panel DP according to one or more embodiments of the present disclosure.

[0075] refer to Figure 4 , a display area DA and a non-display area NDA around the display area DA may be defined in the display panel DP. The display area DA and the non-display area NDA may be divided according to whether a pixel PX exists. The pixel PX may be located in the display area DA, and the pixel PX may not be located in the non-display area NDA.

[0076] The display panel DP may include pixels PX, initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, data lines DL1 to DLn, first control lines CSL1 and second control lines CSL2, driving voltage lines PL, scan drivers SDV, data drivers, emission drivers EDV, driving chips DIC, and pads PD. Here, m and n represent natural numbers of 2 or more. The data driver may be a circuit included in the driving chip DIC.

[0077] The pixels PX may be connected to initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, and data lines DL1 to DLn.

[0078] Initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, and black scan lines GBL1 to GBLm may extend in a first direction DR1 to be electrically connected to a scan driver SDV. Data lines DL1 to DLn may extend in a second direction DR2 to be electrically connected to a drive chip DIC. Emission control lines ECL1 to ECLm may extend in a first direction DR1 to be electrically connected to an emission driver EDV.

[0079] The driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be located on different layers. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0080] The first control line CSL1 may be connected to the scan driver SDV. The second control line CSL2 may be connected to the emission driver EDV.

[0081] The driving chip DIC, the driving voltage line PL, the first control line CSL1 and the second control line CSL2 may be electrically connected to the pad PD. The flexible circuit film FCB may be electrically connected to the pad PD through an anisotropic conductive adhesive layer. The pad PD may be a pad for connecting the flexible circuit film FCB to the display panel DP. The pad PD may be connected to the corresponding pixel PX through the driving voltage line PL, the first control line CSL1 and the second control line CSL2.

[0082] In addition, the pads PD may also include input pads. The input pads may be used to connect the flexible circuit film FCB to the input sensor INS (see Figure 3 However, the present disclosure is not limited thereto, and the input pad may be located at the input sensor INS (see Figure 3 ) and connected to a circuit board separate from the pad PD. Alternatively, the input sensor INS may be omitted, and the pad PD may not further include an input pad.

[0083] Figure 5 is an equivalent circuit diagram of a pixel PXij according to one or more embodiments of the present disclosure.

[0084] As an example, Figure 5 A plurality of pixels PX are shown (see Figure 4) is an equivalent circuit diagram of one pixel PXij in FIG. 4. Because a plurality of pixels PX have substantially the same circuit structure, the circuit structure of the pixel PXij will be described, and detailed descriptions of the other pixels PX will be omitted.

[0085] refer to Figure 4 and Figure 5 , the pixel PXij is connected to the i-th data line DLi among the data lines DL1 to DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, the j-th write scan line GWLj among the write scan lines GWL1 to GWLm, the j-th black scan line GBLj among the black scan lines GBL1 to GBLm, the j-th emission control line ECLj among the emission control lines ECL1 to ECLm, the first and second drive voltage lines VL1 and VL2, and the first and second initialization voltage lines VL3 and VL4. Here, i represents an integer from 1 to n, and j represents an integer from 1 to m.

[0086] The pixel PXij may include a light emitting element ED and a pixel circuit PDC. The light emitting element ED may be a light emitting diode. As an example of one or more embodiments of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic emission layer, but is not particularly limited thereto. The pixel circuit PDC may control the amount of current flowing through the light emitting element ED in response to the i-th data signal Di. The light emitting element ED may emit light at a predetermined brightness corresponding to the amount of current provided from the pixel circuit PDC.

[0087] The pixel circuit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a first capacitor Cst, a second capacitor Cbst, and a third capacitor Nbst. The configuration of the pixel circuit PDC according to one or more embodiments of the present disclosure is not limited to corresponding to Figure 5 One or more embodiments of the present invention. Figure 5 The pixel circuit PDC shown in FIG. 1 is merely an example, and the configuration of the pixel circuit PDC may be modified and implemented.

[0088] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor including a low temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor including an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be LTPS transistors.

[0089] For example, the first transistor T1 that directly affects the brightness of the light-emitting element ED can be configured to include a semiconductor layer made of polycrystalline silicon with high reliability, thereby realizing a display device with high resolution. Oxide semiconductors have high carrier mobility and low leakage current, and therefore no drastic voltage drop occurs even when the driving time is long. That is, since drastic color changes of the image due to voltage drop do not occur even during low-frequency driving, low-frequency driving can be achieved. As described above, the oxide semiconductor has a low leakage current, and therefore can be used as at least one of the third transistor T3 and the fourth transistor T4, each of which is connected to the gate electrode of the first transistor T1, thereby preventing or reducing leakage current that may flow to the gate electrode, and also reducing power consumption.

[0090] Some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be p-type transistors, and the other transistors may be n-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be p-type transistors, and the third transistor T3 and the fourth transistor T4 may be n-type transistors.

[0091] The configuration of the pixel circuit PDC according to the present disclosure is not limited to corresponding to Figure 5 One or more embodiments of the present invention. Figure 5The pixel circuit PDC shown in is only an example, and the configuration of the pixel circuit PDC may be modified and implemented. For example, all of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be p-type transistors or n-type transistors. Alternatively, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be p-type transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be n-type transistors.

[0092] The jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj can transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan line signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi can transmit the i-th data signal Di to the pixel PXij. The i-th data signal Di can have the same value as that input to the display device DD (see Figure 1 )’s image signal corresponding to the voltage level.

[0093] The first and second driving voltage lines VL1 and VL2 may transmit the first and second driving voltages ELVDD and ELVSS to the pixels PXij, respectively. In addition, the first and second initialization voltage lines VL3 and VL4 may transmit the first and second initialization voltages VINT and VAINT to the pixels PXij, respectively.

[0094] The first transistor T1 may be connected between a first driving voltage line VL1 receiving a first driving voltage ELVDD and the light emitting element ED. The first transistor T1 may include a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or referred to as an anode) of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the first capacitor Cst. The first transistor T1 may receive an i-th data signal Di transmitted by an i-th data line DLi according to a switching operation of the second transistor T2, and then transmit a driving current to the light emitting element ED.

[0095] The second transistor T2 may be connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 may include a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 may be turned on in response to the j-th write scan line signal GWj received through the j-th write scan line GWLj, and then transmit the i-th data signal Di received from the i-th data line DLi to the first electrode of the first transistor T1. The second capacitor Cbst may have one end connected to the third electrode of the second transistor T2 and the other end connected to the first node N1.

[0096] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the jth compensation scan line GCLj. The third transistor T3 may be turned on in response to the jth compensation scan signal GCj received through the jth compensation scan line GCLj, and then the third electrode of the first transistor T1 and the second electrode of the first transistor T1 are connected to each other so that the first transistor T1 is diode-connected. The third capacitor Nbst may have one end connected to the third electrode of the third transistor T3 and the other end connected to the first node N1.

[0097] The fourth transistor T4 may be connected between the first initialization voltage line VL3 to which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 may include a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line GILj. The fourth transistor T4 may be turned on in response to the jth initialization scan signal GIj received through the jth initialization scan line GILj. The turned-on fourth transistor T4 may transmit the first initialization voltage VINT to the first node N1 to initialize the potential of the third electrode of the first transistor T1 (e.g., the potential of the first node N1).

[0098] The fifth transistor T5 may include a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj. The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode (e.g., the second node N2) of the light emitting element ED, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj.

[0099] The fifth transistor T5 and the sixth transistor T6 may be turned on substantially simultaneously in response to the jth emission control signal EMj received through the jth emission control line ECLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 may be compensated by the diode-connected first transistor T1 and then transmitted to the light emitting element ED through the sixth transistor T6.

[0100] The seventh transistor T7 may include a first electrode connected to a second initialization voltage line VL4 to which the second initialization voltage VAINT is transmitted, a second electrode connected to the second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line GBLj. The second initialization voltage VAINT may have a voltage level less than or equal to a voltage level of the first initialization voltage VINT.

[0101] The first capacitor Cst may have one end connected to the third electrode of the first transistor T1 and the other end connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than that of the first driving voltage ELVDD.

[0102] Figure 6 is a display panel DP according to one or more embodiments of the present disclosure (see Figure 2 ) is an enlarged plan view of a portion of the display area DA. Figure 6 shows that when the display module DM (see Figure 2 ) of the display surface IS (see Figure 2 ) when viewed from above the display module DM (see Figure 3 ) plane, and shows the arrangement of emission areas PXA-R, PXA-G and PXA-B.

[0103] refer to Figure 6, the display area DA may include a first emission area PXA-R, a second emission area PXA-G, and a third emission area PXA-B and a peripheral area NPXA surrounding the first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B. The first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B may respectively correspond to areas from which light provided from the light emitting element is emitted. The first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B may be arranged according to the direction of the display module DM (see Figure 3 ) is divided by the color of the externally emitted light.

[0104] The first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may respectively provide light having first to third colors different from each other. For example, the light having the first color may be red light, the light having the second color may be green light, and the light having the third color may be blue light. However, examples of light having the first to third colors are not necessarily limited to the aforementioned examples.

[0105] Each of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may be defined as a region in which a top surface of the anode is partially exposed by an emission opening to be described later. The peripheral region NPXA may set a boundary of each of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B, and prevent or reduce mixing of colors between the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B.

[0106] Each of the first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B may be provided in plurality to have a preset arrangement shape, and may be repeatedly arranged in the display area DA. For example, the first emission area PXA-R and the third emission area PXA-B may be alternately arranged in the first direction DR1 and constitute a "first group". The second emission area PXA-G may be arranged in the first direction DR1 and constitute a "second group". Each of the "first group" and the "second group" may be provided in plurality, and the "first group" and the "second group" may be alternately arranged in the second direction DR2.

[0107] One second emission region PXA-G may be spaced apart from one first emission region PXA-R or one third emission region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0108] Figure 6The arrangement shapes of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B shown in FIG are examples and are not limited thereto. The first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may be arranged in various forms. In one or more embodiments, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have a shape such as Figure 6 As shown in Alternatively, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have a stripe arrangement shape or a diamond shape. )Layout Shape( and Diamond is a registered trademark of Samsung Display Co., Ltd. of South Korea).

[0109] Each of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have various shapes on a plane. For example, each of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have a shape such as a polygonal shape, a circular shape, or an elliptical shape. As an example, Figure 6 The first emission region PXA-R and the third emission region PXA-B each having a square (or diamond) shape on a plane and the second emission region PXA-G having an octagonal shape are shown.

[0110] The first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have substantially the same shape, or at least one of them may have a different shape on a plane. As an example, Figure 6 The first emission region PXA-R and the third emission region PXA-B having the same shape on a plane and the second emission region PXA-G having a shape different from the first emission region PXA-R and the third emission region PXA-B are shown.

[0111] At least some of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have different areas on a plane. In one or more embodiments, the area of ​​the first emission region PXA-R that emits red light may be larger than the area of ​​the second emission region PXA-G that emits green light, and may be smaller than the area of ​​the third emission region PXA-B that emits blue light. However, the large-small relationship of the areas of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B according to the color of the emitted light is not limited thereto, and may be selected according to the display module DM (see Figure 3However, the present disclosure is not limited thereto, and the respective areas of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may be the same on a plane / in a plan view.

[0112] The display module DM (see Figure 3 The shapes, areas, arrangements, etc. of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may be configured according to the color of the emitted light or the display module DM (see Figure 2 ) and may be variously designed in size or configuration, and is not limited to corresponding to Figure 6 One or more embodiments of the present invention.

[0113] Figure 7 It is along Figure 4 0 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure, taken along line II' in FIG. Fig. 8A and Figure 8B Each is shown Figure 7 A magnified view of region AA in Ref. Figure 7 , Fig. 8A and Figure 8B In the description of Figure 4 Redundant description of components having the same / similar reference numerals or numbers as those of the described components.

[0114] Figure 7 The display area DA is shown (see Figure 6 ), and Figure 7 The emission region PXA in may correspond to Figure 6 Any one of the first emission area PXA-R, the second emission area PXA-G and the third emission area PXA-B in the reference Figure 7 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0115] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers are formed by coating, deposition, etc. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by performing a photolithography process and an etching process. The semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL or the display element layer DP-OLED may be formed by these processes.

[0116] The circuit element layer DP-CL may be located on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, first, second, third, fourth, and fifth insulating layers 10, 20, 30, 40, and 50, an upper electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0117] The buffer layer BFL may be located on the base layer BL. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0118] The semiconductor pattern may be located on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the present disclosure is not limited thereto, and the semiconductor pattern may also include amorphous silicon or metal oxide. Figure 7 Only a portion of the semiconductor pattern is shown, and the semiconductor pattern may also be located in a plurality of emission regions PXA-R, PXA-G, and PXA-B (see Figure 6 ). The semiconductor pattern may be arranged according to a specific rule to cover a plurality of emission regions PXA-R, PXA-G, and PXA-B (see Figure 6 ). Depending on whether the semiconductor pattern is doped, the semiconductor pattern may have different electrical properties. The semiconductor pattern may include a first region having a high doping concentration and a second region having a low doping concentration. The first region may be doped with an n-type dopant or a p-type dopant. The p-type transistor may include a first region doped with a p-type dopant.

[0119] The first region may have a higher conductivity than the second region and may be substantially used as an electrode or a signal line. The second region may substantially correspond to an active portion (or channel) of a transistor. For example, a portion of the semiconductor pattern may be an active portion of a transistor, another portion may be a source or drain of the transistor, and another portion may be a conductive region.

[0120] The source S, the active portion A, and the drain D of the transistor TR1 may be formed of a semiconductor pattern. Figure 7 A portion of a signal transmission region SCL formed of a semiconductor pattern is shown. The signal transmission region SCL may be connected to a drain D of the transistor TR1 on a plane.

[0121] The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be located on the buffer layer BFL. Each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be an inorganic layer or an organic layer.

[0122] The first insulating layer 10 may be located on (e.g., above) the buffer layer BFL. The first insulating layer 10 may cover the source S, the active portion A, and the drain D of the transistor TR1 located on the buffer layer BFL, and the signal transmission region SCL. The gate G of the transistor TR1 may be located on the first insulating layer 10. The second insulating layer 20 may be located on the first insulating layer 10 to cover the gate G. The upper electrode EE may be located on the second insulating layer 20. The third insulating layer 30 may be located on the second insulating layer 20 to cover the upper electrode EE.

[0123] The first connection electrode CNE1 may be located on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The fourth insulating layer 40 may be located on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0124] The second connection electrode CNE2 may be located on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 may be located on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0125] The display element layer DP-OLED may be located on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a sacrificial pattern SP, a pixel defining film PDL, a partition wall PW, and a dummy pattern DMP.

[0126] The light emitting element ED may include an anode AE ​​(or a first electrode), an emission pattern EP, and a cathode CE (or a second electrode).

[0127] The anode AE ​​may be located on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 by passing through and defining a connection contact hole CNT-3 in the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and may be electrically connected to the corresponding circuit element. The anode AE ​​may have a single-layer structure or a multi-layer structure. The anode AE ​​may include a plurality of layers containing indium tin oxide (ITO) or Ag. For example, the anode AE ​​may include a layer containing ITO (hereinafter, referred to as a lower ITO layer), a layer located on the lower ITO layer and containing Ag (hereinafter, referred to as an Ag layer), and a layer located on the Ag layer and containing ITO (hereinafter, referred to as an upper ITO layer).

[0128] The sacrificial pattern SP may be located between the anode AE ​​and the pixel defining film PDL. A sacrificial opening portion OP-S exposing a portion of the top surface of the anode AE ​​may be defined in the sacrificial pattern SP. The sacrificial opening portion OP-S may overlap an emission opening portion OP-E to be described later on a plane.

[0129] The pixel defining film PDL may be located on the base layer BL. For example, the pixel defining film PDL may be located on the fifth insulating layer 50 of the circuit element layer DP-CL. The emission opening portion OP-E may be defined in the pixel defining film PDL. The emission opening portion OP-E may correspond to the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​through the emission opening portion OP-E.

[0130] In addition, the emission opening portion OP-E may correspond to the sacrificial opening portion OP-S of the sacrificial pattern SP. According to one or more embodiments of the present disclosure, in a cross-sectional view, the top surface of the anode AE ​​may be spaced apart from the pixel defining film PDL with the sacrificial pattern SP therebetween, and thus, the anode AE ​​may be protected from being damaged in the process of forming the emission opening portion OP-E.

[0131] On a plane, the area of ​​the emission opening portion OP-E may be smaller than the area of ​​the sacrificial opening portion OP-S. That is, the inner side surface of the pixel defining film PDL defining the emission opening portion OP-E may be closer to the center of the anode AE ​​than the inner side surface of the sacrificial pattern SP defining the sacrificial opening portion OP-S. However, the present disclosure is not limited thereto, and the inner side surface of the sacrificial pattern SP defining the sacrificial opening portion OP-S may be substantially aligned with the inner side surface of the pixel defining film PDL defining the emission opening portion OP-E.

[0132] The pixel definition film PDL may include an inorganic insulating material. The pixel definition film PDL may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiO x N y ). For example, the pixel definition film PDL may include silicon nitride (SiN x ). The pixel defining film PDL may be located between the anode AE ​​and the partition wall PW, and blocks electrical connection between the anode AE ​​and the partition wall PW.

[0133] The partition wall PW may be located on the pixel defining film PDL. A partition wall opening portion OP-P may be defined in the partition wall PW. The partition wall opening portion OP-P may overlap with the emission opening portion OP-E and may expose at least a portion of the anode AE.

[0134] The partition wall PW may have an undercut shape in a cross-sectional view. The partition wall PW may include a plurality of layers sequentially stacked, and at least one of the plurality of layers may be recessed from the other layers. Therefore, the partition wall PW may include a tip portion TP.

[0135] The partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be located on the pixel definition layer PDL, and the second partition wall layer L2 may be located on the first partition wall layer L1. Figure 7 As shown in FIG. 8 , the thickness of the first partition wall layer L1 may be greater than the thickness of the second partition wall layer L2 , but is not limited thereto.

[0136] The first partition wall layer L1 may be relatively recessed from the emission area PXA compared to the second partition wall layer L2. The first partition wall layer L1 may be undercut relative to the second partition wall layer L2. A portion of the second partition wall layer L2 protruding from the first partition wall layer L1 toward the emission area PXA may be defined as a tip portion TP in the partition wall PW. That is, the second partition wall layer L2 may include a tip portion TP protruding from the first partition wall layer L1 toward the partition wall opening portion OP-P. The tip portion TP of the second partition wall layer L2 may not overlap with the first partition wall layer L1 on a plane (for example, the edge / tip portion TP of the second partition wall layer L2 may not be aligned with the edge of the first partition wall layer L1).

[0137] The first partition wall layer L1 may include a lower partition wall layer L1-1 and an upper partition wall layer L1-2. The lower partition wall layer L1-1 may be located on the pixel definition film PDL, and the upper partition wall layer L1-2 may be located on the lower partition wall layer L1-1. The lower partition wall layer L1-1 may be directly located on the pixel definition film PDL, and the upper partition wall layer L1-2 may be directly located on the lower partition wall layer L1-1. Therefore, the lower partition wall layer L1-1 may have a bottom surface in contact with the top surface of the pixel definition film PDL and a top surface in contact with the bottom surface of the upper partition wall layer L1-2. The upper partition wall layer L1-2 may have a top surface in contact with the bottom surface of the second partition wall layer L2.

[0138] The lower partition wall layer L1-1 may be a substantially non-conductive high resistance layer. The lower partition wall layer L1-1 may include an insulating material. The lower partition wall layer L1-1 may include amorphous silicon (a-Si) as an insulating material. For example, the lower partition wall layer L1-1 may be made of amorphous silicon (a-Si).

[0139] The upper partition wall layer L1-2 may include a conductive layer. The upper partition wall layer L1-2 may include a conductive material. The upper partition wall layer L1-2 may include n + Silicon (n + Si) as a conductive material. For example, the upper partition wall layer L1-2 may be made of n+ Silicon (n + Si) is made.

[0140] refer to Fig. 8A and Figure 8B , the lower partition wall layer L1-1 may have a first thickness T1, and the upper partition wall layer L1-2 may have a second thickness T2. The first thickness T1 may be less than the second thickness T2. The first thickness T1 may be less than about 0.5 times the sum of the first thickness T1 and the second thickness T2. That is, the lower partition wall layer L1-1 may have a small thickness less than about 0.5 times the thickness of the first partition wall layer L1. For example, the first thickness T1 may be about 200 angstroms. And the second thickness T2 may be about 4000 angstroms However, one or more embodiments are not limited thereto. The ratio of the first thickness T1 to the second thickness T2 may be adjusted according to the structure of the light emitting element ED.

[0141] Reference again Figure 7 , the partition wall opening portion OP-P defined in the partition wall PW may include a first area A1 and a second area A2. The first partition wall layer L1 may have a first inner side surface S-L1 defining the first area A1 of the partition wall opening portion OP-P. The lower partition wall layer L1-1 and the upper partition wall layer L1-2 constituting the first partition wall layer L1 may share the first area A1 and the first inner side surface S-L1 defining the first area A1. The lower partition wall layer L1-1 and the upper partition wall layer L1-2 may include substantially the same amorphous silicon (a-Si) and n-Si. + Silicon (n + Si), and can be etched substantially simultaneously in a manufacturing process described later, so that the lower partition wall layer L1-1 and the upper partition wall layer L1-2 are substantially uniformly undercut relative to the second partition wall layer L2. Therefore, the inner side surface of the lower partition wall layer L1-1 and the inner side surface of the upper partition wall layer L1-2 can be aligned with each other in the third direction DR3, wherein each of the inner side surface of the lower partition wall layer L1-1 and the inner side surface of the upper partition wall layer L1-2 defines the first area A1.

[0142] The second partition wall layer L2 may have a second inner surface S-L2 defining the second area A2. In a cross-sectional view, the second inner surface S-L2 of the second partition wall layer L2 may be closer to the center of the anode AE ​​than the first inner surface S-L1 of the first partition wall layer L1. The first inner surface S-L1 may be recessed from the second inner surface S-L2 in a direction away from the center of the anode AE.

[0143] In the first direction DR1, the first area A1 may have a width different from that of the second area A2. In the first direction DR1, the width of the first area A1 may be greater than the width of the second area A2. In this case, the second area A2 of the partition wall opening portion OP-P may be a region defining the tip portion TP. Here, the emission area PXA may be considered as a region of the anode AE ​​exposed from the second area A2 of the partition wall PW corresponding thereto.

[0144] The second partition wall layer L2 may include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide. In one or more embodiments, the second partition wall layer L2 may include at least one of molybdenum (Mo) and titanium (Ti).

[0145] As an example, Figure 7 The first inner surface S-L1 and the second inner surface S-L2 are shown, each of which is substantially perpendicular to the top surface of the pixel definition film PDL, but the present disclosure is not limited thereto. For example, the partition wall PW may have a tapered shape or a reverse tapered shape.

[0146] The emission pattern EP may be located on the anode AE. The emission pattern EP may include at least one emission layer EML including a light emitting material (see Fig. 8A ). For example, the emission pattern EP may include an emission layer EML (see Fig. 8A ), and may include a hole transport region HTR (see Fig. 8A ) and the electron transport region ETR (see Fig. 8A ), hole transport region HTR (see Fig. 8A ) and the electron transport region ETR (see Fig. 8A ) is positioned so that the emission layer EML (see Fig. 8A ) therebetween. In addition, the emission pattern EP may include a plurality of emission structures, and the emission structures are arranged to be sequentially stacked on the anode AE ​​in the thickness direction. Each of the plurality of emission structures may include a hole transport region HTR (see Fig. 8A ) and the electron transport region ETR (see Fig. 8A ), hole transport region HTR (see Fig. 8A ) and the electron transport region ETR (see Fig. 8A ) is positioned so that the emission layer EML (see Fig. 8A ) therebetween. That is, the light emitting element ED including the emission pattern EP according to one or more embodiments may have an emission layer EML (see Fig. 8A ) structure, or has a column structure including a plurality of emission layers EML. The emission pattern EP may be referred to as an “intermediate layer”.

[0147] The emission pattern EP may be patterned by a tip portion TP defined in the partition wall PW. The emission pattern EP may be located inside (e.g., inside in a plan view) the sacrificial opening portion OP-S, the emission opening portion OP-E, and the partition wall opening portion OP-P. The emission pattern EP may be deposited on a portion of the top surface of the pixel defining film PDL exposed from the partition wall opening portion OP-P. That is, the emission pattern EP may have two end portions, each of which is disposed on the top surface of the pixel defining film PDL.

[0148] The emission pattern EP may contact the lower partition wall layer L1-1 and may not contact the upper partition wall layer L1-2. The emission pattern EP may include at least one organic layer containing a charge generating material. The charge generating material may be uniformly or non-uniformly dispersed in the organic layer. The charge generating material may be, for example, a p-type dopant. The emission pattern EP may include at least one organic layer doped with a p-type dopant. The p-type dopant may include at least one of a metal halide, a quinone derivative, a metal oxide, and a cyano-containing compound, but is not limited thereto. For example, the p-type dopant may include a metal halide such as CuI or RbI, a quinone derivative such as tetracyanoquinodimethane (TCNQ) or 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4-TCNQ), a metal oxide such as tungsten oxide or molybdenum oxide, or a cyano-containing compound such as dipyrazino[2,3-f:2',3'-h]quinoxaline-2,3,6,7,10,11-hexanitrile (HATCN) or 4-[[2,3-bis[cyano-(4-cyano-2,3,5,6-tetrafluorophenyl)methylethylidene]cyclopropylidene]-cyanomethyl]-2,3,5,6-tetrafluorobenzonitrile (NDP9). However, one or more embodiments are not limited thereto.

[0149] The organic layer doped with a p-type dopant may have conductivity. If the emission pattern EP including the organic layer doped with the p-type dopant contacts the upper partition wall layer L1-2 including a conductive material, the upper partition wall layer L1-2 and the emission pattern EP may be electrically connected to each other to generate leakage current. According to one or more embodiments of the present disclosure, since the emission pattern EP does not contact the upper partition wall layer L1-2 (for example, is separated from the upper partition wall layer L1-2 or is spaced apart from the upper partition wall layer L1-2) and contacts the lower partition wall layer L1-1, the leakage current may be reduced or prevented from being generated. For example, according to one or more embodiments of the present disclosure, the lower partition wall layer L1-1 contacting the emission pattern EP may be made of an insulating material such as amorphous silicon (a-Si), thereby reducing or preventing the leakage current from being generated even if a portion of the emission pattern EP (for example, a hole injection layer and / or a charge generation layer, each of which is doped with a p-type dopant) has conductivity.

[0150] The cathode CE may be located on the emission pattern EP. The cathode CE may be patterned by a tip portion TP defined in the partition wall PW. At least a portion of the cathode CE may be located in the partition wall opening portion OP-P. The cathode CE may be deposited on a portion of the top surface of the pixel defining film PDL that is exposed from the partition wall opening portion OP-P. That is, the cathode CE may have two ends, each of which is disposed on the pixel defining film PDL. The cathode CE may contact the first inner side surface S-L1 of the first partition wall layer L1. For example, at least a portion of the end of the cathode CE may contact the inner side surface of the lower partition wall layer L1-1, and the end of the cathode CE that does not contact the lower partition wall layer L1-1 may contact the inner side surface of the upper partition wall layer L1-2. Alternatively, the entire end of the cathode CE may contact the inner side surface of the upper partition wall layer L1-2.

[0151] The cathode CE may have electrical conductivity. The cathode CE may be made of various materials such as metal, transparent conductive oxide (TCO) or conductive polymer material, as long as the cathode CE can exhibit electrical conductivity. For example, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu) or a compound thereof.

[0152] The display element layer DP-OLED may further include a capping pattern CP. The capping pattern CP may be located in the partition wall opening portion OP-P. The capping pattern CP may be located on the cathode CE. The capping pattern CP may be patterned by a tip portion TP defined in the partition wall PW.

[0153] The dummy pattern DMP may be located on (e.g., above) the partition wall PW. The dummy pattern DMP may include a first dummy pattern D1, a second dummy pattern D2, and a third dummy pattern D3. Therefore, the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may be sequentially stacked on the top surface of the second partition wall layer L2 of the partition wall PW in the third direction DR3.

[0154] The first dummy pattern D1 may include an organic material. For example, the first dummy pattern D1 may include the same material as the emission pattern EP. The first dummy pattern D1 may be formed substantially simultaneously with the emission pattern EP through one process and then separated from the emission pattern EP by the undercut shape of the partition wall PW.

[0155] The second dummy pattern D2 may include a conductive material. For example, the second dummy pattern D2 may include the same material as the cathode CE. The second dummy pattern D2 may be formed substantially simultaneously with the cathode CE through one process and then separated from the cathode CE by the undercut shape of the partition wall PW.

[0156] The third dummy pattern D3 may include a conductive material. For example, the third dummy pattern D3 may include the same material as the capping pattern CP. The third dummy pattern D3 may be formed substantially simultaneously with the capping pattern CP through one process, and then separated from the capping pattern CP by the undercut shape of the partition wall PW.

[0157] The dummy opening portion OP-D may be defined in the dummy pattern DMP. The dummy opening portion OP-D may overlap the emission opening portion OP-E on a plane. The dummy opening portion OP-D may include first to third regions sequentially arranged in the third direction DR3. In the dummy opening portion OP-D, the first region AA1 (see Figure 10G ) may be defined by the inner surface of the first dummy pattern D1, and the second area AA2 (see Figure 10G ) may be defined by the inner side surface of the second dummy pattern D2, and the third area AA3 (see Figure 10G ) may be defined by an inner side surface of the third dummy pattern D3. Each of the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may have a closed line shape surrounding the emission area PXA on a plane.

[0158] As an example, Figure 7The corresponding inner surfaces of the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 aligned with the second inner surface S-L2 of the second partition wall layer L2 are shown. However, the present disclosure is not limited thereto, and the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may cover at least a portion of the second inner surface S-L2 of the second partition wall layer L2.

[0159] The thin film encapsulation layer TFE may be located on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower inorganic encapsulation pattern LIL, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL.

[0160] The lower inorganic encapsulation pattern LIL may be located on the light emitting element ED and the capping pattern CP. The lower inorganic encapsulation pattern LIL may correspond to the emission opening portion OP-E. The lower inorganic encapsulation pattern LIL may cover the light emitting element ED, the capping pattern CP, and the dummy pattern DMP, and have a portion located inside the partition wall opening portion OP-P. According to one or more embodiments, the lower inorganic encapsulation pattern LIL may contact each of the first inner surface S-L1 of the first partition wall layer L1 and the second inner surface S-L2 of the second partition wall layer L2. For example, the lower inorganic encapsulation pattern LIL may contact the inner surface S-L12 of the upper partition wall layer L1-2 (see Fig. 10E ) and each of the second inner side surfaces S-L2 of the second partition wall layer L2.

[0161] In one or more embodiments, the lower inorganic encapsulation pattern LIL may include an inorganic material. For example, the lower inorganic encapsulation pattern LIL may include silicon nitride (SiN x ). Therefore, the lower inorganic encapsulation pattern LIL may exhibit the same structure as the lower partition wall layer L1-1 including amorphous silicon (a-Si) and the lower inorganic encapsulation pattern LIL. + Silicon (n + The upper partition wall layer L1-2 including silicon nitride (SiN) has a suitable adhesion to each of the upper partition wall layers L1-2. x ) may be highly resistant to moisture due to a proper interface bonding force with the first partition wall layer L1.

[0162] The organic encapsulation film OL may cover the lower inorganic encapsulation pattern LIL and may provide a flat top surface. The upper inorganic encapsulation film UIL may be on the organic encapsulation film OL.

[0163] The lower inorganic encapsulation pattern LIL and the upper inorganic encapsulation film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the organic encapsulation film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0164] Fig. 8A and Figure 8B Each shows Figure 7 The structure of the light emitting element ED shown in FIG. Fig. 8A An example of an emission pattern EP including one emission layer EML in the light emitting element ED according to one or more embodiments is shown. Figure 8B An example of an emission pattern EP including a plurality of emission layers EML in a light emitting element ED according to one or more embodiments is shown.

[0165] refer to Fig. 8A The emission pattern EP may include an emission layer EML including a light emitting material. The emission pattern EP may include a hole transport region HTR between the anode AE ​​and the emission layer EML, and may include an electron transport region ETR between the emission layer EML and the cathode CE.

[0166] The hole transport region HTR may include at least one of a hole injection layer, a hole transport layer, an emission auxiliary layer, and an electron blocking layer. For example, the hole transport region HTR may include a hole injection layer and a hole transport layer sequentially stacked on the anode AE.

[0167] The hole transport region HTR may include a p-type dopant as a charge generating material. At least one of the hole injection layer, the hole transport layer, the emission auxiliary layer, and the electron blocking layer may include a p-type dopant. For example, the hole transport region HTR may include a hole injection layer including a p-type dopant. The hole injection layer may correspond to the aforementioned organic layer doped with a p-type dopant, but is not limited thereto.

[0168] The electron transport region ETR may include at least one of a hole blocking layer, an electron transport layer, and an electron injection layer. For example, the electron transport region ETR may include an electron transport layer and an electron injection layer located on the emission layer EML, but one or more embodiments are not limited thereto. The electron transport region ETR may include a single layer made of a single material or a single layer made of a plurality of different materials, or may have a multilayer structure including a plurality of layers made of a plurality of different materials.

[0169] refer to Figure 8B , the emission pattern EP according to one or more embodiments may include a plurality of emission structures EG1 and EG2. Each of the plurality of emission structures EG1 and EG2 may include an emission layer EML. Therefore, the emission pattern EP may include a plurality of emission layers EML. That is, the light emitting element ED according to one or more embodiments may be a light emitting element having a column structure including a plurality of emission layers EML.

[0170] The charge generation layer CGL may be located between the plurality of emission structures EG1 and EG2. The charge generation layer CGL may include a p-type dopant as a charge generation material. The charge generation layer CGL may correspond to the aforementioned organic layer doped with the p-type dopant. Fig. 8A What has been described can be similarly applied to p-type dopants.

[0171] exist Figure 8B In the light emitting element ED shown in FIG. 1 , the emission pattern EP may include two emission structures EG1 and EG2. However, one or more embodiments are not limited thereto, and the emission pattern EP may include three or four emission structures.

[0172] The emission pattern EP according to one or more embodiments may include a first emission structure EG1 and a second emission structure EG2, which are sequentially stacked in the thickness direction between the anode AE ​​and the cathode CE facing each other. The first emission structure EG1 may be located on the anode AE, and the second emission structure EG2 may be located on the charge generation layer CGL. That is, the light emitting element ED according to one or more embodiments may include the anode AE, the first emission structure EG1, the charge generation layer CGL, the second emission structure EG2, and the cathode CE stacked in sequence.

[0173] Each of the first emission structure EG1 and the second emission structure EG2 may include a hole transport region HTR, an emission layer EML, and an electron transport region ETR. In each of the first emission structure EG1 and the second emission structure EG2, the hole transport region HTR and the electron transport region ETR may be positioned so that the emission layer EML is therebetween. In the first emission structure EG1, the hole transport region HTR may be closer to the anode AE ​​than the electron transport region ETR. In the second emission structure EG2, the electron transport region ETR may be closer to the cathode CE than the hole transport region HTR.

[0174] At least one of the hole transport region HTR and the charge generation layer CGL included in each of the first and second emission structures EG1 and EG2 may include an organic layer doped with a p-type dopant, but one or more embodiments are not limited thereto.

[0175] Fig. 9 It is along Figure 6 A cross-sectional view taken along line II-II'. Fig. 9 is an enlarged view of a first emission area PXA-R, a second emission area PXA-G, and a third emission area PXA-B. Figure 7The description of one emission region PXA in FIG. 1 may be similarly applied to each of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B.

[0176] refer to Fig. 9 According to one or more embodiments, the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, a pixel defining film PDL, a partition wall PW, and a dummy pattern DMP.

[0177] The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3. The first light-emitting element ED1 may include a first anode AE1, a first emission pattern EP1, and a first cathode CE1. The second light-emitting element ED2 may include a second anode AE2, a second emission pattern EP2, and a second cathode CE2. The third light-emitting element ED3 may include a third anode AE3, a third emission pattern EP3, and a third cathode CE3. The first anode AE1, the second anode AE2, and the third anode AE3 may be arranged in a plurality of patterns. In one or more embodiments, the first emission pattern EP1 may provide red light, the second emission pattern EP2 may provide green light, and the third emission pattern EP3 may provide blue light.

[0178] The first emission opening portion OP1-E, the second emission opening portion OP2-E, and the third emission opening portion OP3-E may be defined in the pixel definition film PDL. The first emission opening portion OP1-E may expose at least a portion of the first anode AE1. The second emission opening portion OP2-E may expose at least a portion of the second anode AE2. The third emission opening portion OP3-E may expose at least a portion of the third anode AE3.

[0179] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3 may be located on top surfaces of the first anode AE1, the second anode AE2, and the third anode AE3, respectively. The first sacrificial opening portion OP1-S, the second sacrificial opening portion OP2-S, and the third sacrificial opening portion OP3-S overlapping the first emission opening portion OP1-E, the second emission opening portion OP2-E, and the third emission opening portion OP3-E may be defined in the first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3, respectively.

[0180] In one or more embodiments, the first partition wall opening portion OP1-P, the second partition wall opening portion OP2-P, and the third partition wall opening portion OP3-P respectively overlapping the first emission opening portion OP1-E, the second emission opening portion OP2-E, and the third emission opening portion OP3-E may be defined in the partition wall PW. The first emission region PXA-R may be defined as a region of the top surface of the first anode AE1 exposed by the first partition wall opening portion OP1-P. The second emission region PXA-G may be defined as a region of the top surface of the second anode AE2 exposed by the second partition wall opening portion OP2-P. The third emission region PXA-B may be defined as a region of the top surface of the third anode AE3 exposed by the third partition wall opening portion OP3-P.

[0181] Each of the first partition wall opening portion OP1-P, the second partition wall opening portion OP2-P, and the third partition wall opening portion OP3-P may include a reference Figure 7 The first area A1 described (see Figure 7 ) and the second area A2 (see Figure 7 The first partition wall layer L1 may have a first area A1 (see FIG. 1 ) that defines a first partition wall opening portion OP1 -P, a second partition wall opening portion OP2 -P, and a third partition wall opening portion OP3 -P, respectively. Figure 7 ) of the first inner side surface S-L1 (see Figure 7 ), and the second partition wall layer L2 may have a second area A2 (see Figure 7 ) of the second inner side surface S-L2 (see Figure 7 ).

[0182] The first emission pattern EP1 and the first cathode CE1 may be located in the first partition wall opening portion OP1-P, the second light emitting element ED2 and the second cathode CE2 may be located in the second partition wall opening portion OP2-P, and the third light emitting element ED3 and the third cathode CE3 may be located in the third partition wall opening portion OP3-P.

[0183] In one or more embodiments, the first emission pattern EP1, the second emission pattern EP2, and the third emission pattern EP3 and the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be physically separated by the second partition wall layer L2 defining the tip portion and defined in the emission opening portions OP1-E, OP2-E, and OP3-E and the partition wall opening portions OP1-P, OP2-P, and OP3-P, respectively. Each of the first emission pattern EP1, the second emission pattern EP2, and the third emission pattern EP3 and the first cathode CE1, the second cathode CE2, and the third cathode CE3 may contact at least a portion of the partition wall PW.

[0184] Each of the first emission pattern EP1, the second emission pattern EP2, and the third emission pattern EP3 may contact the lower partition wall layer L1-1, and may not contact the upper partition wall layer L1-2. Since the lower partition wall layer L1-1 corresponds to a substantially non-conductive high resistance layer, the first emission pattern EP1, the second emission pattern EP2, and the third emission pattern EP3 may contact only the lower partition wall layer L1-1 to prevent or reduce the generation of leakage current.

[0185] The first cathode CE1, the second cathode CE2, and the third cathode CE3 may each contact the upper partition wall layer L1-2, and thus be electrically connected to each other to receive a common voltage. The upper partition wall layer L1-2 may have high conductivity to reduce contact resistance with the first cathode CE1, the second cathode CE2, and the third cathode CE3. Therefore, the common cathode voltage may be substantially uniformly provided to the emission regions PXA-R, PXA-G, and PXA-B.

[0186] According to one or more embodiments of the present disclosure, a plurality of emission patterns EP1, EP2, and EP3 may be deposited by being patterned into pixel units by a tip portion defined in a partition wall PW. That is, a plurality of emission patterns EP1, EP2, and EP3 may be formed together using an open mask, but appropriately separated into pixel units by a partition wall PW.

[0187] On the contrary, if a fine metal mask (FMM) is used to pattern multiple emission patterns EP1, EP2 and EP3, a supporting spacer protruding from the conductive partition wall may be provided to support the fine metal mask. In addition, since the height of the partition wall and the spacer are separated from the base surface subjected to patterning by the fine metal mask, achieving high resolution may be limited. In addition, when the fine metal mask contacts the spacer, after the process of patterning the multiple emission patterns EP1, EP2 and EP3, foreign matter may remain on the spacer, or the spacer may be damaged due to the penetration of the fine metal mask. Therefore, a defective display panel may be provided.

[0188] According to one or more embodiments, when the partition wall PW is included, physical separation between the light emitting elements ED1, ED2, and ED3 can be achieved. Therefore, driving errors or current leakage between adjacent emission regions PXA-R, PXA-G, and PXA-B can be prevented or reduced, and the light emitting elements ED1, ED2, and ED3 can each be driven independently of each other.

[0189] For example, since the plurality of light emitting elements ED1, ED2 and ED3 can be arranged without contacting the display area DA (see Figure 2 ) is patterned without using a mask for internal elements in the display panel DP, so the defect rate can be reduced, thereby providing a display panel DP with improved process reliability. Since patterning can be performed even without providing a separate supporting spacer protruding from the partition wall PW, the corresponding areas of the emission regions PXA-R, PXA-G, and PXA-B can be reduced or miniaturized to provide a display panel DP implemented with a high resolution.

[0190] In addition, since manufacturing a mask having a large area is omitted in manufacturing a display panel DP having a large area, process costs can be reduced, and the display panel DP can be free from defects that may occur in a mask having a large area. Therefore, a display panel DP having improved process reliability can be provided. The description of the plurality of first emission patterns EP1 can be similarly applied to the plurality of second emission patterns EP2 and the third emission pattern EP3.

[0191] The capping patterns CP1, CP2, and CP3 may include a first capping pattern CP1, a second capping pattern CP2, and a third capping pattern CP3. The first capping pattern CP1, the second capping pattern CP2, and the third capping pattern CP3 may be located on the first cathode CE1, the second cathode CE2, and the third cathode CE3, respectively, and may be located in the first partition wall opening portion OP1-P, the second partition wall opening portion OP2-P, and the third partition wall opening portion OP3-P, respectively.

[0192] The dummy patterns DMP may include a plurality of first dummy patterns D1 , a plurality of second dummy patterns D2 , and a plurality of third dummy patterns D3 .

[0193] The first dummy pattern D1 may include a (1-1)th dummy pattern D11, a (1-2)th dummy pattern D12, and a (1-3)th dummy pattern D13 respectively surrounding the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B on a plane. The (1-1)th dummy pattern D11, the (1-2)th dummy pattern D12, and the (1-3)th dummy pattern D13 may respectively include the same materials as the first emission pattern EP1, the second emission pattern EP2, and the third emission pattern EP3, and may respectively be formed by the same processes as the first emission pattern EP1, the second emission pattern EP2, and the third emission pattern EP3.

[0194] The second dummy pattern D2 may include a (2-1)th dummy pattern D21, a (2-2)th dummy pattern D22, and a (2-3)th dummy pattern D23 respectively surrounding the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B on a plane. The (2-1)th dummy pattern D21, the (2-2)th dummy pattern D22, and the (2-3)th dummy pattern D23 may include the same materials as the first cathode CE1, the second cathode CE2, and the third cathode CE3, respectively, and may be formed by the same processes as the first cathode CE1, the second cathode CE2, and the third cathode CE3, respectively.

[0195] The third dummy pattern D3 may include a (3-1)th dummy pattern D31, a (3-2)th dummy pattern D32, and a (3-3)th dummy pattern D33 respectively surrounding the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B on a plane. The (3-1)th dummy pattern D31, the (3-2)th dummy pattern D32, and the (3-3)th dummy pattern D33 may respectively include the same materials as the first capping pattern CP1, the second capping pattern CP2, and the third capping pattern CP3, and may respectively be formed by the same processes as the first capping pattern CP1, the second capping pattern CP2, and the third capping pattern CP3.

[0196] The first dummy opening portion OP1-D, the second dummy opening portion OP2-D, and the third dummy opening portion OP3-D corresponding to the first emission opening portion OP1-E, the second emission opening portion OP2-E, and the third emission opening portion OP3-E may be defined in the dummy pattern DMP, respectively. Each of the first dummy opening portion OP1-D, the second dummy opening portion OP2-D, and the third dummy opening portion OP3-D may include a first area AA1, a second area AA2, and a third area AA3 sequentially arranged in the third direction DR3 (see Figure 10G). The first dummy opening portion OP1-D may be defined by the inner side surfaces of the (1-1)th dummy pattern D11, the (2-1)th dummy pattern D21, and the (3-1)th dummy pattern D31, the second dummy opening portion OP2-D may be defined by the inner side surfaces of the (1-2)th dummy pattern D12, the (2-2)th dummy pattern D22, and the (3-2)th dummy pattern D32, and the third dummy opening portion OP3-D may be defined by the inner side surfaces of the (1-3)th dummy pattern D13, the (2-3)th dummy pattern D23, and the (3-3)th dummy pattern D33.

[0197] The thin film encapsulation layer TFE may include lower inorganic encapsulation patterns LIL1, LIL2 and LIL3, an organic encapsulation film OL and an upper inorganic encapsulation film UIL. In one or more embodiments, the lower inorganic encapsulation patterns LIL1, LIL2 and LIL3 may include a first lower inorganic encapsulation pattern LIL1, a second lower inorganic encapsulation pattern LIL2 and a third lower inorganic encapsulation pattern LIL3. The first lower inorganic encapsulation pattern LIL1, the second lower inorganic encapsulation pattern LIL2 and the third lower inorganic encapsulation pattern LIL3 may overlap with the first emission opening portion OP1-E, the second emission opening portion OP2-E and the third emission opening portion OP3-E, respectively.

[0198] The first lower inorganic encapsulation pattern LIL1 may cover the first light emitting element ED1 and the (1-1)th dummy pattern D11, the (2-1)th dummy pattern D21, and the (3-1)th dummy pattern D31, and have a portion located inside the first partition wall opening portion OP1-P. The second lower inorganic encapsulation pattern LIL2 may cover the second light emitting element ED2 and the (1-2)th dummy pattern D12, the (2-2)th dummy pattern D22, and the (3-2)th dummy pattern D32, and have a portion located inside the second partition wall opening portion OP2-P. The third lower inorganic encapsulation pattern LIL3 may cover the third light emitting element ED3 and the (1-3)th dummy pattern D13, the (2-3)th dummy pattern D23, and the (3-3)th dummy pattern D33, and have a portion located inside the third partition wall opening portion OP3-P. The first lower inorganic encapsulation pattern LIL1 , the second lower inorganic encapsulation pattern LIL2 , and the third lower inorganic encapsulation pattern LIL3 may be disposed in the form of patterns spaced apart from each other.

[0199] FIG. 10A to FIG. 10I are cross-sectional views illustrating some of the operations of a method of manufacturing a display panel according to one or more embodiments of the present disclosure. FIG. 10A to FIG. 10I When describing, the same / similar reference numerals or signs are used to Figures 1 to 9 The elements described are the same / similar elements, and redundant description will be omitted.

[0200] The method of manufacturing a display panel according to one or more embodiments of the present disclosure may include providing an initial display panel DP-I, forming first and second initial partition walls L1-I and L2-I, forming partition walls PW, and forming an emission pattern EP and a cathode CE.

[0201] refer to Fig. 10A According to one or more embodiments, a method of manufacturing a display panel may include providing an initial display panel DP-I. The initial display panel DP-I provided in one or more embodiments may include a base layer BL, a circuit element layer DP-CL, an anode AE, an initial sacrificial pattern SP-I, and an initial pixel defining film PDL-I.

[0202] The circuit element layer DP-CL can be formed by a typical process for manufacturing circuit elements by coating, deposition, etc. to form an insulating layer, a semiconductor layer and a conductive layer, and then selectively patterning the insulating layer, the semiconductor layer and the conductive layer through a photolithography process and an etching process to form a semiconductor pattern, a conductive pattern, a signal line, etc.

[0203] The anode electrode AE ​​and the preliminary sacrificial pattern SP-I may be formed by substantially the same patterning process. The preliminary pixel defining film PDL-I may cover the anode electrode AE ​​and the preliminary sacrificial pattern SP-I.

[0204] Then, refer to Fig. 10B According to one or more embodiments, the method of manufacturing a display panel may include forming a preliminary partition wall PW-I on the preliminary display panel DP-I. Forming the preliminary partition wall PW-I may include forming a first preliminary partition wall layer L1-I and a second preliminary partition wall layer L2-I.

[0205] The first initial partition wall layer L1-I may be formed on the initial pixel definition film PDL-I. Forming the first initial partition wall layer L1-I may include forming an initial lower partition wall layer L1-1I and an initial upper partition wall layer L1-2I on the initial pixel definition film PDL-I. The initial lower partition wall layer L1-1I and the initial upper partition wall layer L1-2I may be formed by sequentially depositing materials having substantially the same etching selectivity on the initial pixel definition film PDL-I through a chemical vapor deposition (CVD) process.

[0206] The initial lower partition wall layer L1-1I may be formed by depositing an insulating material on the initial pixel definition film PDL-I. For example, the insulating material used to form the initial lower partition wall layer L1-1I may include amorphous silicon (a-Si). The initial lower partition wall layer L1-1I may be formed by depositing amorphous silicon (a-Si) on the initial pixel definition film PDL-I. The initial upper partition wall layer L1-2I may be formed by depositing a conductive material on the initial lower partition wall layer L1-1I. For example, the conductive material used to form the initial upper partition wall layer L1-2I may include n + Silicon (n + Si). The initial upper partition wall layer L1-2I may be formed by depositing n on the initial lower partition wall layer L1-1I. + Silicon (n + Si) to form.

[0207] The second initial partition wall layer L2-I may be formed on the first initial partition wall layer L1-I. For example, the second initial partition wall layer L2-I may be formed on the initial upper partition wall layer L1-2I. The second initial partition wall layer L2-I may be formed by a process of depositing a conductive material. In one or more embodiments, the conductive material used to form the second initial partition wall layer L2-I may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the conductive material used to form the second initial partition wall layer L2-I may be gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide used to form the second initial partition wall layer L2-I may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide. The conductive material used to form the second initial partition wall layer L2-I may be different from the conductive material used to form the initial upper partition wall layer L1-2I. The conductive material used to form the second preliminary partition wall layer L2-I may include at least one of molybdenum (Mo) and titanium (Ti). In one or more embodiments, the second preliminary partition wall layer L2-I may be formed of molybdenum (Mo).

[0208] Thereafter, the method of manufacturing a display panel according to one or more embodiments may include forming a first photoresist layer PR1 (see Fig. 10C ).

[0209] refer to Fig. 10CThe first photoresist layer PR1 may be formed by forming an initial photoresist layer on the initial partition wall PW-1 and then patterning the initial photoresist layer by using a photomask. An optical opening portion OP-PR may be formed in the first photoresist layer PR1 by a patterning process. The optical opening portion OP-PR may overlap the anode AE ​​on a plane.

[0210] Then, refer to Fig. 10D and Fig. 10E According to one or more embodiments, the method of manufacturing a display panel may include etching a first preliminary partition wall layer L1-I and a second preliminary partition wall layer L2-I to form a first partition wall layer L1 and a second partition wall layer L2 having a partition wall opening portion OP-P defined therein, thereby forming a partition wall PW from the preliminary partition wall PW-I.

[0211] First, if Fig. 10D As shown in, the initial etching of the first initial partition wall layer L1-I and the second initial partition wall layer L2-I may include forming an initial partition wall opening portion OP-PI in the initial partition wall PW-I by using the first photoresist layer PR1 as a mask and dry etching the first initial partition wall layer L1-I and the second initial partition wall layer L2-I. The first initial partition wall layer L1-I and the second initial partition wall layer L2-I may be etched substantially simultaneously by an initial dry etching process. The initial partition wall opening portion OP-PI may overlap the anode AE.

[0212] The initial dry etching process according to one or more embodiments may be performed in an etching environment in which the etching selectivities of the first initial partition wall layer L1-I and the second initial partition wall layer L2-I are substantially the same. Therefore, the inner side surface of the first initial partition wall layer L1-I and the inner side surface of the second initial partition wall layer L2-I may be substantially aligned with each other, and each of the inner side surfaces of the first initial partition wall layer L1-I and the second initial partition wall layer L2-I defines the initial partition wall opening portion OP-PI.

[0213] Then, if Fig. 10E As shown in FIG. 1 , the secondary etching of the first preliminary partition wall layer L1-I may include etching the first preliminary partition wall layer L1-I from the preliminary partition wall opening portion OP-PI (see FIG. 1 ). Fig. 10D ) forms a partition wall opening portion OP-P. The partition wall opening portion OP-P may overlap the first anode AE1. In the present disclosure, the secondary etching of the first preliminary partition wall layer L1-I may be referred to as an "undercut etching process".

[0214] In the undercut etching process, the initial lower partition wall layer L1-1I and the initial upper partition wall layer L1-2I may be etched substantially simultaneously. In addition, the undercut etching process may be performed in an etching environment in which the etching selectivities of the initial lower partition wall layer L1-1I and the initial upper partition wall layer L1-2I are substantially the same. Therefore, the inner side surface of the lower partition wall layer L1-1 and the inner side surface of the upper partition wall layer L1-2 may be substantially aligned with each other, wherein each of the inner side surface of the lower partition wall layer L1-1 and the inner side surface of the upper partition wall layer L1-2 defines a partition wall opening portion OP-P.

[0215] The partition wall opening portion OP-P may include a first area A1 and a second area A2 positioned sequentially in the thickness direction (e.g., the third direction DR3). The first partition wall layer L1 may have a first inner surface S-L1 defining the first area A1 of the partition wall opening portion OP-P. The first inner surface S-L1 may be divided into an inner surface S-L11 of the lower partition wall layer L1-1 and an inner surface S-L12 of the upper partition wall layer L1-2. The second partition wall layer L2 may have a second inner surface S-L2 defining the second area A2.

[0216] The undercut etching process according to one or more embodiments may be performed in an etching environment in which the difference in etching selectivity between the first initial partition wall layer L1-I and the second initial partition wall layer L2-I is appropriately large. Therefore, the inner surface of the partition wall PW defining the partition wall opening portion OP-P may have an undercut shape in cross section. In one or more embodiments, the etching rate of the first initial partition wall layer L1-I may be higher than the etching rate of the second initial partition wall layer L2-I. The etching rate of each of the initial lower partition wall layer L1-1I and the initial upper partition wall layer L1-2I may be higher than the etching rate of the second initial partition wall layer L2-I. That is, the second initial partition wall layer L2-I may include a material having an etching rate lower than the etching rate of the first initial partition wall layer L1-I. Therefore, the first initial partition wall layer L1-I may be etched more than the second initial partition wall layer L2-I, and the first inner surface S-L1 of the first partition wall layer L1 may be recessed from the second inner surface S-L2 of the second partition wall layer L2. A tip portion may be formed in the partition wall PW by a portion of the second partition wall layer L2 protruding (eg, in a plan view) from the first partition wall layer L1 toward the center of the anode AE.

[0217] Afterwards, refer to Fig.10F The method of manufacturing a display panel according to one or more embodiments may include etching an initial pixel definition film PDL-I (see Fig. 10E ), thereby forming a pixel definition film PDL. The etching of the initial pixel definition film PDL-I may be performed using a dry etching method (see Fig. 10E), and the initial pixel definition film PDL-I may be etched using the first photoresist layer PR1 and a portion of the partition wall PW (eg, the second partition wall layer L2) as a mask (see Fig. 10E ). An emission opening portion OP-E corresponding to the partition wall opening portion OP-P may be formed in the pixel defining film PDL.

[0218] In addition, the method of manufacturing a display panel according to one or more embodiments may include etching the initial sacrificial pattern SP-I. For example, the etching of the initial sacrificial pattern SP-I may be performed using a wet etching method, and the initial sacrificial pattern SP-I may be etched using the first photoresist layer PR1 and a portion of the partition wall PW (e.g., the second partition wall layer L2) as a mask.

[0219] refer to Figure 10G , a sacrificial opening portion OP-S overlapping the emission opening portion OP-E may be formed in the sacrificial pattern SP formed by etching the initial sacrificial pattern SP-I. At least a portion of the anode AE ​​may be exposed from the sacrificial pattern SP and the pixel defining film PDL through the sacrificial opening portion OP-S and the emission opening portion OP-E. The sacrificial pattern SP may include an amorphous transparent conductive oxide. For example, the sacrificial pattern SP may be zinc oxide (ZnO) doped with aluminum (Al). x ).

[0220] The etching of the sacrificial pattern SP may be performed in an etching environment in which the difference in etching selectivity between the sacrificial pattern SP and the anode AE ​​is appropriately large, and thus the anode AE ​​may be prevented from being etched together. That is, the sacrificial pattern SP having a higher etching rate than the anode AE ​​may be located between the pixel defining film PDL and the anode AE, thereby preventing the anode AE ​​from being etched together and damaged during etching.

[0221] In addition, etching of the sacrificial pattern SP may be performed in an etching environment in which a difference in etching selectivity between the sacrificial pattern SP and the first and second partition wall layers L1 and L2 of the partition wall PW is relatively large, and thus, the possibility of the first and second partition wall layers L1 and L2 being etched together may be reduced or prevented.

[0222] The method of manufacturing a display panel according to one or more embodiments may include forming an emission pattern EP in a partition wall opening portion OP-P, forming a cathode CE, and removing a first photoresist layer PR1 (see Fig.10F ) and then form a capping pattern CP.

[0223] Forming the emission pattern EP, forming the cathode CE, and forming the capping pattern CP may each be performed by a deposition process. In one or more embodiments, the emission pattern EP may be formed by a thermal evaporation process, the cathode CE may be formed by a sputtering process, and the capping pattern CP may be formed by a thermal evaporation process. However, one or more embodiments of the present disclosure are not limited thereto.

[0224] When forming the emission pattern EP, the emission pattern EP may be separated by a tip portion formed in the partition wall PW and may be located inside the emission opening portion OP-E and the partition wall opening portion OP-P. When forming the emission pattern EP, a first initial dummy pattern D1-I spaced apart from the emission pattern EP may be formed together on the partition wall PW.

[0225] In one or more embodiments, the emission pattern EP may contact the lower partition wall layer L1-1 and not contact the upper partition wall layer L1-2. Fig. 9 ) can prevent or reduce leakage current between adjacent pixels.

[0226] When forming the cathode CE, the cathode CE may be separated by a tip portion formed in the partition wall PW and may be located inside the partition wall opening portion OP-P. The cathode CE may be provided at a higher incident angle than the emission pattern EP so that the cathode CE contacts the first inner side surface S-L1 of the first partition wall layer L1 (see Fig. 10E ). For example, the cathode CE contacts the inner side surface S-L11 of the lower partition wall layer L1-1 (see Fig. 10E ). In addition, at least a portion of the cathode CE contacts the inner side surface S-L12 of the upper partition wall layer L1-2 (see Fig. 10E ). When forming the cathode CE, a second preliminary dummy pattern D2-I spaced apart from the cathode CE may be formed together on the partition wall PW. The anode AE, the emission pattern EP, and the cathode CE may constitute a light emitting element ED.

[0227] When forming the capping pattern CP, the capping pattern CP may be separated by a tip portion formed in the partition wall PW and may be located inside the partition wall opening portion OP-P. When forming the capping pattern CP, a third initial dummy pattern D3-I spaced apart from the capping pattern CP may be formed together on the partition wall PW. According to another embodiment of the present disclosure, the formation of the capping pattern CP may be omitted.

[0228] The first initial dummy pattern D1-I, the second initial dummy pattern D2-I, and the third initial dummy pattern D3-I may form an initial dummy pattern DMP-I, and the dummy opening portion OP-D may be defined in the initial dummy pattern DMP-I. The dummy opening portion OP-D may include a first area AA1, a second area AA2, and a third area AA3 sequentially positioned in a thickness direction (e.g., a third direction DR3). In the dummy opening portion OP-D, the first area AA1 may be defined by the inner side surface of the first initial dummy pattern D1-I, the second area AA2 may be defined by the inner side surface of the second initial dummy pattern D2-I, and the third area AA3 may be defined by the inner side surface of the third initial dummy pattern D3-I.

[0229] Afterwards, refer to Fig. 10H According to one or more embodiments, the method of manufacturing a display panel may include forming an initial lower inorganic encapsulation pattern LIL-1. The initial lower inorganic encapsulation pattern LIL-1 may be formed by a deposition process. In one or more embodiments, the initial lower inorganic encapsulation pattern LIL-1 may be formed by a chemical vapor deposition (CVD) process. The initial lower inorganic encapsulation pattern LIL-1 may be formed by depositing silicon nitride (SiN) on the partition wall PW and the cathode CE. x ) is formed, and a portion of the initial lower inorganic encapsulation pattern LIL-1 may be formed inside the partition wall opening portion OP-P. In one or more embodiments, the silicon nitride (SiN x ) formed by the lower inorganic packaging pattern LIL (see Figure 7 ) can be due to the first partition wall layer L1 (see Figure 10G ) has a very moisture-resistant property due to the high bonding force between the lower partition wall layer L1-1 and the upper partition wall layer L1-2.

[0230] Then, refer to Fig.10I The method of manufacturing a display panel according to one or more embodiments may include forming a second photoresist layer PR2, forming an initial lower inorganic encapsulation pattern LIL-1 (see Fig. 10H ) is patterned to form the lower inorganic encapsulation pattern LIL and the initial dummy pattern DMP-I (see Fig. 10H ) is patterned to form a dummy pattern DMP.

[0231] When forming the second photoresist layer PR2, the second photoresist layer PR2 may be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer by using a photomask. The second photoresist layer PR2 has a pattern shape corresponding to the emission opening portion OP-E through a patterning process.

[0232] Reference again Fig. 10H, when patterning the initial lower inorganic encapsulation pattern LIL-1, the initial lower inorganic encapsulation pattern LIL-1 may be patterned by dry etching to remove a portion of the initial lower inorganic encapsulation pattern LIL-1 overlapping with the remaining anodes other than the corresponding anode AE. For example, if the initial lower inorganic encapsulation pattern LIL-1 corresponds to the first anode AE1 (see Fig. 9 ), the initial lower inorganic encapsulation pattern LIL-1 and the second anode AE2 and the third anode AE3 (see Fig. 9 ) overlapping part.

[0233] The lower inorganic encapsulation pattern LIL overlapping the corresponding emission opening portion OP-E may be formed by a patterned initial lower inorganic encapsulation pattern LIL-1. A portion of the lower inorganic encapsulation pattern LIL may be located in the partition wall opening portion OP-P to cover the light emitting element ED, and another portion of the lower inorganic encapsulation pattern LIL may be located on the partition wall PW.

[0234] When patterning the initial dummy pattern DMP-I, the first initial dummy pattern D1-I, the second initial dummy pattern D2-I, and the third initial dummy pattern D3-I may be patterned by dry etching so that a portion of each of the first initial dummy pattern D1-I, the second initial dummy pattern D2-I, and the third initial dummy pattern D3-I that overlaps with the remaining anodes other than the corresponding anode AE ​​is removed. For example, when the first initial dummy pattern D1-I, the second initial dummy pattern D2-I, and the third initial dummy pattern D3-I correspond to the first anode AE1 (see Fig. 9 ), each of the first initial dummy pattern D1-I, the second initial dummy pattern D2-I, and the third initial dummy pattern D3-I is connected to the second anode AE2 and the third anode AE3 (see Fig. 9 )The overlapping part can be removed.

[0235] The first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 overlapped with the corresponding emission opening portion OP-E may be formed by patterning the first initial dummy pattern D1-I, the second initial dummy pattern D2-I, and the third initial dummy pattern D3-I, respectively, and form a dummy pattern DMP, each of which may include the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3. Each of the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may have a surrounding emission area PXA (see FIG. 1 ) on a plane. Figure 7 ) of the closed line shape.

[0236] After that, refer to Figure 7 and Fig.10I, the method of manufacturing a display panel according to one or more embodiments may include, after removing the second photoresist layer PR2, forming an organic encapsulation film OL and an upper inorganic encapsulation film UIL to complete the display panel DP. The organic encapsulation film OL may be formed by applying an organic material through an inkjet process, but is not limited thereto. The organic encapsulation film OL provides a planarized top surface. Thereafter, an inorganic material may be deposited to form an upper inorganic encapsulation film UIL. Thus, a display panel DP that may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE may be formed.

[0237] Forming a partition wall opening portion and an emission opening portion (each of the partition wall opening portion and the emission opening portion corresponds to an emission area having a different color) in the partition wall PW and the pixel definition film PDL, forming light emitting elements ED1, ED2, and ED3 providing different colors, and forming the lower inorganic encapsulation pattern LIL covering the light emitting elements ED1, ED2, and ED3 providing different colors may be further performed between forming the lower inorganic encapsulation pattern LIL and completing the display panel DP. Thus, the following may be formed: Fig. 9 The display panel DP shown in the figure may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3, a first capping pattern CP1, a second capping pattern CP2, and a third capping pattern CP3, a (1-1)th dummy pattern D11, a (1-2)th dummy pattern D12, and a (1-3)th dummy pattern D13, a (2-1)th dummy pattern D21, a (2-2)th dummy pattern D22, a (2-3)th dummy pattern D23, a (3-1)th dummy pattern D31, a (3-2)th dummy pattern D32, a (3-3)th dummy pattern D33, and a first lower inorganic encapsulation pattern LIL1, a second lower inorganic encapsulation pattern LIL2, and a third lower inorganic encapsulation pattern LIL3.

[0238] The display panel according to one or more embodiments may include a partition wall PW including a first partition wall layer L1 including an insulating material and a second partition wall layer L2 including a conductive material. Here, the emission pattern EP included in the light emitting element ED may contact only the first partition wall layer L1. Therefore, even if a portion of the emission pattern EP (e.g., an organic layer doped with a p-type dopant) has conductivity, leakage current may be prevented or reduced.

[0239] According to the method of manufacturing a display panel according to one or more embodiments, leakage current between adjacent pixels may be prevented or reduced, thereby manufacturing a display panel having suitable display quality.

[0240] Although one or more embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these embodiments, but various changes and modifications can be made by those skilled in the art within the spirit and scope of the present disclosure as claimed in the attached claims and their functional equivalents included therein. Therefore, the technical scope of the present disclosure is not limited to the contents described in the detailed description of the specification, but should be determined by the claims.

Claims

1. Display panel, including: Base layer; a pixel defining film over the base layer and defining an emission opening portion; Partition wall, comprising: a first partition wall layer over the pixel definition film and including a lower partition wall layer including an insulating material and an upper partition wall layer including a conductive material over the lower partition wall layer; and a second partition wall layer over the first partition wall layer and defining a partition wall opening portion overlapping the emission opening portion; and A light emitting element includes an anode, an intermediate layer above the anode, contacting the lower partition wall layer and spaced apart from the upper partition wall layer, and a cathode above the intermediate layer.

2. The display panel according to claim 1, wherein: The lower partition wall layer includes amorphous silicon, and Wherein, the upper partition wall layer includes n + silicon.

3. The display panel according to claim 1, wherein: The intermediate layer includes at least one organic layer doped with a p-type dopant.

4. The display panel according to claim 3, wherein: The intermediate layer comprises: a hole transport region including the organic layer doped with the p-type dopant above the anode; an emissive layer over the hole transport region; and An electron transport region is above the emission layer.

5. The display panel according to claim 3, wherein: The intermediate layer comprises: an emitting structure over the anode; and The charge generation layer is between the emission structures and includes the organic layer doped with the p-type dopant.

6. The display panel according to claim 1, wherein: The cathode contacts the upper partition wall layer and is electrically connected to the partition wall.

7. The display panel according to claim 1, wherein: The second partition wall layer includes at least one of molybdenum and titanium.

8. The display panel according to claim 1 , further comprising a thin film encapsulation layer, the thin film encapsulation layer comprising a thin film, the thin film being above the light emitting element and including a lower inorganic encapsulation pattern covering the light emitting element and contacting the partition wall, and in, The lower inorganic encapsulation pattern includes silicon nitride.

9. Display panel, including: Base layer; a pixel defining film over the base layer and defining an emission opening portion; A partition wall, over the pixel definition film, defines a partition wall opening portion corresponding to the emission opening portion, and includes: a lower partition wall layer including amorphous silicon; an upper partition wall layer, above the lower partition wall layer, and comprising n + Silicon; and a second partition wall layer above the upper partition wall layer and including a tip portion protruding from the lower partition wall layer and the upper partition wall layer toward the partition wall opening portion; and The light emitting element is in the partition wall opening portion in a plan view and includes an anode, an intermediate layer over the anode, and a cathode over the intermediate layer.

10. The display panel according to claim 9, wherein: The intermediate layer contacts the lower partition wall layer and is spaced apart from the upper partition wall layer, and Wherein, the cathode contacts the upper partition wall layer.

11. A method for manufacturing a display panel, the method comprising: Providing an initial display panel, the initial display panel comprising a base layer, an anode over the base layer, and a pixel defining film over the base layer and covering the anode; forming a first preliminary partition wall layer by depositing an insulating material and a conductive material having equal etching selectivity over the preliminary display panel; forming a second initial partition wall layer above the initial display panel; etching the first preliminary partition wall layer and the second preliminary partition wall layer to form a partition wall defining a partition wall opening portion; as well as An emission pattern and a cathode are formed in the partition wall opening portion.

12. The method according to claim 11, wherein: The insulating material includes amorphous silicon, and the conductive material includes n + silicon.

13. The method according to claim 11, wherein: The second preliminary partition wall layer includes a conductive material having a lower etching rate than the first preliminary partition wall layer.

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