A bottom electrode-insulating layer-top electrode structure, a method of manufacturing the same, and a microelectronic device

Abstract

The application relates to the field of microelectronic devices, in particular to a bottom electrode-insulating layer-top electrode structure and a preparation method thereof and a microelectronic device. The preparation method comprises the following steps: providing a substrate, forming a bottom electrode on the surface of the substrate; forming an insulating layer on the bottom electrode, the material of the insulating layer being a metal oxide; sequentially forming a buffer layer and a top electrode on the insulating layer, the material of the buffer layer being a selenium material or a tellurium material; removing the buffer layer through an annealing process, so that the insulating layer and the top electrode are in non-damage contact, and a bottom electrode-insulating layer-top electrode structure is obtained. According to the method, the buffer layer is introduced between the insulating layer and the top electrode, non-damage and stress-free contact between the insulating layer and the top electrode is realized, local stress and damage introduced in the insulating layer in the process of direct deposition of the top electrode are reduced, the yield of the device is improved, the fluctuation of the device is reduced, and large-scale device integration can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronic devices, in particular to a bottom electrode-insulating layer-top electrode structure, a preparation method thereof and a microelectronic device. BACKGROUND

[0002] The bottom electrode-insulating layer-top electrode structure can realize functional devices such as memristors and neuromorphic devices. By applying a voltage between the two electrodes, the resistance state in the insulating layer is changed, thereby realizing information storage and neuromorphic computing functions. The quality of the insulating layer has a great influence on the devices based on the structure. If there are defects and stress in the insulating layer, it will affect the change of the resistance state in the insulating layer, and then affect the yield of the device, cause large fluctuation of the device, and limit the application of related devices. It is found that damage and stress may be introduced in the insulating layer during the deposition of the top electrode, which may reduce the yield of the device and increase the fluctuation of the device. Some studies have proposed a mechanical transfer method of the top electrode to reduce the damage and stress introduced in the insulating layer (Highly Reliable Low-Voltage Memristive Switching and Artificial Synapse Enabled by van der Waals Integration. Matter 2020, 2, 965-976. DOI: 10.1016 / j.matt.2020.01.011. and Highly Stable HfO2 Memristors through van der Waals Electrode Lamination and Delamination. Nano Lett. 2023, 23, 9928-9935. DOI: 10.1021 / acs.nanolett.3c02888), but this mechanical transfer method is easy to produce cracks and wrinkles, introduce bubbles and impurities at the interface, and is difficult to achieve large-scale consistency, so it is difficult to realize large-scale device integration.

[0003] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0004] In view of the deficiencies of the prior art described above, the purpose of the present application is to provide a bottom electrode-insulating layer-top electrode structure, a preparation method thereof and a microelectronic device, aiming to solve the problems that the existing method may bring new problems when reducing the damage and stress introduced by the top electrode to the insulating layer, and the problem that it is difficult to realize large-scale device integration.

[0005] Specifically, the technical solutions of the present application are as follows:

[0006] In a first aspect, the present application provides a preparation method of a bottom electrode-insulating layer-top electrode structure, comprising the following steps:

[0007] providing a substrate, and forming a bottom electrode on a surface of the substrate;

[0008] forming an insulating layer on the bottom electrode, wherein a material of the insulating layer comprises a metal oxide;

[0009] sequentially forming a buffer layer and a top electrode on the insulating layer, wherein a material of the buffer layer is a selenium material or a tellurium material;

[0010] removing the buffer layer by an annealing process to make the insulating layer and the top electrode have no damage contact, and obtaining the bottom electrode-insulating layer-top electrode structure.

[0011] In a second aspect, the present application provides a bottom electrode-insulating layer-top electrode structure prepared by the preparation method of the present application.

[0012] In a third aspect, the present application provides a microelectronic device comprising the bottom electrode-insulating layer-top electrode structure of the present application.

[0013] The present application introduces a buffer layer between the insulating layer and the top electrode, realizes no damage and no stress contact between the insulating layer and the top electrode, reduces the local stress and damage introduced in the insulating layer during the deposition of the top electrode, improves the yield of the device, and reduces the fluctuation of the device. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 The preparation method of the bottom electrode-insulating layer-top electrode structure provided by the present application is shown in the flowchart.

[0015] Figure 2 The preparation process flowchart of the bottom electrode-insulating layer-top electrode structure provided by the embodiment 1 is shown. DETAILED DESCRIPTION

[0016] The present application provides a bottom electrode-insulating layer-top electrode structure, a preparation method thereof, and a microelectronic device. To make the purpose, technical scheme and effects of the present application more clear and explicit, the present application is further described in detail. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0017] The application proposes a new preparation method for the "bottom electrode-insulating layer-top electrode" basic structure in microelectronic devices such as memristors and neuromorphic devices, and the basic idea is: a buffer layer is introduced between the insulating layer and the top electrode, the buffer layer material has a low deposition temperature and a suitable evaporation temperature, so it will not damage the insulating layer during the deposition process, reducing the damage and stress of the insulating layer during the direct deposition of the top electrode, and the buffer layer can be removed by a simple annealing process at a suitable temperature, achieving damage-free and stress-free contact between the insulating layer and the top electrode, thereby improving the yield of the device and reducing the volatility of the device.

[0018] According to one embodiment of the application, a preparation method of a bottom electrode-insulating layer-top electrode structure is provided, comprising the steps of:

[0019] S1, providing a substrate, and forming a bottom electrode on the surface of the substrate;

[0020] S2, forming an insulating layer on the bottom electrode, the material of the insulating layer comprising a metal oxide;

[0021] S3, sequentially forming a buffer layer and a top electrode on the insulating layer, the material of the buffer layer being selenium material or tellurium material;

[0022] S4, removing the buffer layer by an annealing process to achieve damage-free contact between the insulating layer and the top electrode, and obtaining the bottom electrode-insulating layer-top electrode structure.

[0023] In the embodiment of the application, a buffer layer is introduced between the insulating layer and the top electrode, and the buffer layer material is selected from selenium material or tellurium material with a low deposition temperature and a suitable evaporation temperature. Since the buffer layer material has a low deposition temperature, it will not damage the insulating layer during the deposition process, reducing the damage and stress to the surface of the insulating layer during the direct deposition of the top electrode. Moreover, the buffer layer material has a suitable evaporation temperature and can be removed by a simple annealing process at a suitable temperature, achieving damage-free and stress-free contact between the insulating layer and the top electrode, thereby improving the yield of the device and reducing the volatility of the device. The method proposed in the embodiment of the application is simple and efficient, and avoids the defects such as cracks, wrinkles, introduction of bubbles and impurities at the interface, etc. by mechanical transfer, and can realize large-scale consistency and device integration.

[0024] In step S1, in one embodiment, the step of forming a bottom electrode on the surface of the substrate specifically comprises:

[0025] S11, applying photoresist on the surface of the substrate, and performing a preset bottom electrode patterning process on the substrate by a photolithography process;

[0026] S12, depositing a bottom electrode material, removing the photoresist on the substrate to form a patterned bottom electrode on the surface of the substrate.

[0027] In one embodiment, the step S11 specifically comprises: applying the photoresist on the surface of the substrate by spin coating, pre-baking the substrate, exposing the substrate to a preset bottom electrode pattern by a laser direct writing lithography machine, and developing to obtain a patterned substrate.

[0028] In one embodiment, the step S12 specifically comprises: depositing a bottom electrode material on the patterned substrate, removing the photoresist on the substrate by a lift-off process to obtain a patterned bottom electrode on the surface of the substrate.

[0029] In the present application, the material and shape of the substrate are both conventional substrates in the prior art, which are not limited herein.

[0030] In the present application, a preset lithography pattern can be formed on a specific position of the substrate by using the photoresist and the lithography process according to specific needs. The specific shape of the lithography pattern can be set according to actual needs, which is not limited herein. After depositing the bottom electrode material, the photoresist on the substrate needs to be removed to form a predetermined patterned bottom electrode structure. The use of the photoresist and the lithography process to pattern the substrate, and the subsequent removal of the photoresist are all conventional techniques in the art, which are not limited herein.

[0031] In step S2, in one embodiment, forming an insulating layer on the bottom electrode means forming the insulating layer on the patterned bottom electrode and on the substrate not covered by the bottom electrode.

[0032] In one embodiment, the insulating layer is selected from metal oxides without conductivity, preferably HfO2, Al2O3 or VO2.

[0033] In one embodiment, the thickness of the insulating layer is 0.5 nm to 50 nm. For example, the thickness of the insulating layer can be 0.5 nm, 1 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm. Within this thickness range, the device has a lower operating voltage and energy consumption.

[0034] In step S3, in one embodiment, the thickness of the buffer layer is 2 nm to 50 nm. For example, the thickness of the buffer layer can be 2 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm. Within this thickness range, the buffer layer can be removed more easily by an annealing process.

[0035] In step S4, in an embodiment, the annealing process is an atmosphere annealing process or a vacuum annealing process, which can be selected according to the buffer layer material used. In the present application, an atmosphere annealing process is preferably selected, in which the gas used is one or more of hydrogen, argon and nitrogen, the annealing temperature is 120-200℃, and the annealing time is 0.5-2h. For example, the annealing temperature can be 120℃, 130℃, 140℃, 150℃, 160℃, 170℃, 180℃, 190℃, 200℃; and the annealing time can be 0.5h, 1h, 1.5h, 2h.

[0036] In this embodiment, the buffer layer is removed by the annealing process, so that the insulating layer and the top electrode are in contact without damage, avoiding the problem of damage and stress to the surface of the insulating layer when the top electrode is directly deposited on the insulating layer.

[0037] According to an embodiment of the present application, the material of the bottom electrode is the same as or different from that of the top electrode. The material can be selected according to the working mechanism of the device.

[0038] In the present application, the material of the bottom electrode and the material of the top electrode can be selected from existing electrode materials, which are not limited herein.

[0039] According to an embodiment of the present application, the preparation method further comprises, before the step of sequentially forming a buffer layer and a top electrode on the insulating layer, applying a photoresist on the insulating layer, and performing a preset top electrode patterning process on the insulating layer by a photolithography process; and before the step of removing the buffer layer by the annealing process, removing the photoresist on the insulating layer. At this time, an intermediate structure of bottom electrode-insulating layer-buffer layer-top electrode is prepared.

[0040] In the present application, each layer in the bottom electrode-insulating layer-top electrode structure can be prepared by a method including a magnetron sputtering technique, a thermal evaporation technique, an electron beam evaporation technique or a vacuum arc evaporation technique, etc. The related film plating techniques are all conventional techniques in the art, which are not limited herein.

[0041] According to an embodiment of the present application, a bottom electrode-insulating layer-top electrode structure prepared by the preparation method of the present application is also provided.

[0042] According to an embodiment of the present application, a microelectronic device is also provided, which comprises the bottom electrode-insulating layer-top electrode structure of the present application.

[0043] According to an embodiment of the present application, the microelectronic device is a memristor, a neuromorphic device, etc.

[0044] As Figure 1As shown, the preparation method of the bottom electrode-insulating layer-top electrode structure provided by the present application comprises the following steps:

[0045] A substrate is provided, and a bottom electrode is formed on the surface of the substrate. An insulating layer (a metal oxide thin film) is deposited on the bottom electrode. A buffer layer material is deposited on the insulating layer to form a buffer layer, and a top electrode material is deposited to form a top electrode. The buffer layer is removed through an annealing process, thereby obtaining the bottom electrode-insulating layer-top electrode structure of the present application.

[0046] The present application will be further described below through specific examples.

[0047] Example 1

[0048] The present example provides a preparation method of a bottom electrode-insulating layer-top electrode structure, which specifically comprises the following steps:

[0049] The SiO2 / Si (285 nm SiO2) substrate is ultrasonically cleaned with acetone, anhydrous ethanol and deionized water respectively, and the cleaning time is 5 min. After being dried by a nitrogen gun, the residual water and oxygen on the surface of the substrate are removed by plasma cleaning. On the substrate, a photoresist with a thickness of 1 μm is applied by spin coating. The substrate is pre-baked to evaporate the solvent in the photoresist and dry the photoresist film. The substrate is exposed to a preset bottom electrode pattern by a laser direct writing photoetching machine, and after development, a patterned substrate is obtained. The bottom electrode material Ti (5 nm) / Pt (30 nm) film is deposited under a vacuum degree less than 10 -4 Pa by using an electron beam evaporation coating machine, and then the photoresist is removed by a lift-off process, thereby obtaining the bottom electrode structure on the substrate. The 5 nm thick HfO2 film is deposited as the insulating layer by using an atomic layer deposition process. On the substrate with the insulating layer, a photoresist with a thickness of 1 μm is applied by spin coating. The substrate is pre-baked to evaporate the solvent in the photoresist and dry the photoresist film. The substrate is exposed to a preset top electrode pattern by a laser direct writing photoetching machine, and after development, a patterned substrate is obtained. The buffer layer material Se (10 nm) film is first deposited as a buffer layer, and then the top electrode material Ag (30 nm) film is deposited as a top electrode under a vacuum degree less than 10 -4 Pa by using an electron beam evaporation coating machine. Then the photoresist is removed by a lift-off process, thereby obtaining the bottom electrode-insulating layer-buffer layer-top electrode structure on the substrate. Then the structure is placed in an annealing furnace, argon gas is introduced at a gas flow rate of 200 standard cubic centimeters per minute (SCCM), the annealing temperature is 150℃, and the annealing time is 4 h, so that the Se material of the buffer layer is removed, thereby obtaining the Pt-HfO2-Ag structure. Figure 2 The preparation process flow diagram of the bottom electrode-insulating layer-top electrode structure provided by the present example is shown in the figure.

[0050] Example 2

[0051] This embodiment provides a preparation method of a bottom electrode-insulating layer-top electrode structure, which is specifically as follows:

[0052] The SiO2 / Si (285 nm SiO2) substrate is ultrasonically cleaned with acetone, anhydrous ethanol and deionized water respectively, and the cleaning time is 5 min. After being dried by a nitrogen gun, the residual water and oxygen on the surface of the substrate are removed by using a plasma cleaning. On the substrate, a photoresist with a thickness of 1 μm is coated by using a spin coating method. The substrate is pre-baked to evaporate the solvent in the photoresist and dry the photo film. The substrate is exposed to a preset bottom electrode pattern on the substrate by using a laser direct writing photoetching machine, and a patterned substrate is obtained after development. A Ti (5 nm) / Pt (30 nm) film is deposited under a vacuum degree less than 10 -4 Pa by using an electron beam evaporation coating machine. The photoresist is removed by a lift-off process to obtain a bottom electrode structure on the substrate. A 5 nm thick Al2O3 film is deposited as an insulating layer by using an atomic layer deposition process. A photoresist with a thickness of 1 μm is coated on the substrate with the prepared insulating layer by using a spin coating method. The substrate is pre-baked to evaporate the solvent in the photoresist and dry the photo film. The substrate is exposed to a preset top electrode pattern on the substrate by using a laser direct writing photoetching machine, and a patterned substrate is obtained after development. A Se (10 nm) film is first deposited as a buffer layer and then an Ag (30 nm) film is deposited as a top electrode under a vacuum degree less than 10 -4 Pa by using an electron beam evaporation coating machine. The photoresist is removed by a lift-off process to obtain a bottom electrode-insulating layer-buffer layer-top electrode structure on the substrate. Then, the structure is placed in an annealing furnace, argon gas is introduced at a gas flow rate of 200 standard cubic centimeters per minute (SCCM), the annealing temperature is 150°C, and the annealing time is 4 h, so that the Se material of the buffer layer is removed to obtain a Pt-Al2O3-Ag structure.

[0053] Example 3

[0054] This embodiment provides a preparation method of a bottom electrode-insulating layer-top electrode structure, which is specifically as follows:

[0055] The SiO2 / Si (285 nm SiO2) substrate is ultrasonically cleaned with acetone, anhydrous ethanol and deionized water respectively, and the cleaning time is 5 min. After being dried by a nitrogen gun, the residual water and oxygen on the surface of the substrate are removed by using a plasma cleaning. On the substrate, a photoresist with a thickness of 1 μm is coated by using a spin coating method. The substrate is pre-baked to evaporate the solvent in the photoresist and dry the photo film. The substrate is exposed to a preset bottom electrode pattern on the substrate by using a laser direct writing photoetching machine, and a patterned substrate is obtained after development. A Ti (5 nm) / Pt (30 nm) film is deposited under a vacuum degree less than 10 -4Ti(5nm) / Pt(30nm) films were deposited under vacuum of Pa. The photoresist was removed by lift-off process to obtain the bottom electrode structure on the substrate. A 5nm thick VO2 film was deposited as an insulating layer using a magnetron sputtering process. A 1 μm thick photoresist was coated on the substrate with the insulating layer using a spin coating method. The substrate was pre-baked to evaporate the solvent in the photoresist and dry the photoresist film. The substrate was exposed to a preset top electrode pattern by a laser direct writing photoetching machine. After development, a patterned substrate was obtained. An electron beam evaporation film coater was used to deposit a 30nm thick Pt film as a top electrode under a vacuum of less than 10 -4 Ti(5nm) / Pt(30nm) films were deposited under vacuum of Pa. The photoresist was removed by lift-off process to obtain the bottom electrode structure on the substrate. A 5nm thick VO2 film was deposited as an insulating layer using a magnetron sputtering process. A 1 μm thick photoresist was coated on the substrate with the insulating layer using a spin coating method. The substrate was pre-baked to evaporate the solvent in the photoresist and dry the photoresist film. The substrate was exposed to a preset top electrode pattern by a laser direct writing photoetching machine. After development, a patterned substrate was obtained. An electron beam evaporation film coater was used to deposit a 30nm thick Pt film as a top electrode under a vacuum of less than 10

[0056] Example 4

[0057] The present embodiment provides a method for preparing a bottom electrode-insulating layer-top electrode structure, which is specifically as follows:

[0058] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol and deionized water for 5 minutes. After being blown dry with a nitrogen gun, the substrate was cleaned by plasma to remove residual water and oxygen on the surface of the substrate. A 1 μm thick photoresist was coated on the substrate using a spin coating method. The substrate was pre-baked to evaporate the solvent in the photoresist and dry the photoresist film. The substrate was exposed to a preset bottom electrode pattern by a laser direct writing photoetching machine. After development, a patterned substrate was obtained. An electron beam evaporation film coater was used to deposit a 5nm thick VO2 film as an insulating layer under a vacuum of less than 10 -4 Ti(5nm) / Pt(30nm) films were deposited under vacuum of Pa. The photoresist was removed by lift-off process to obtain the bottom electrode structure on the substrate. A 5nm thick VO2 film was deposited as an insulating layer using a magnetron sputtering process. A 1 μm thick photoresist was coated on the substrate with the insulating layer using a spin coating method. The substrate was pre-baked to evaporate the solvent in the photoresist and dry the photoresist film. The substrate was exposed to a preset top electrode pattern by a laser direct writing photoetching machine. After development, a patterned substrate was obtained. An electron beam evaporation film coater was used to deposit a 30nm thick Pt film as a top electrode under a vacuum of less than 10 -4At the vacuum degree of Pa, a Se (5 nm) film is first deposited as a buffer layer, and then a Ti (5 nm) / Pt (30 nm) film is deposited as a top electrode. The photoresist is removed by a lift-off process to obtain a bottom electrode-insulating layer-buffer layer-top electrode structure on the substrate. Then it is placed in an annealing furnace, argon gas is introduced at a gas flow rate of 200 standard cubic centimeters per minute (SCCM), the annealing temperature is 150°C, and the annealing time is 4 h, the Se material of the buffer layer is removed, and a Ti / Pt-VO2-Ti / Pt structure is obtained.

[0059] It should be understood that the application of the present application is not limited to the above examples, and can be improved or changed by those of ordinary skill in the art according to the above description, and all these improvements and changes shall belong to the protection scope of the appended claims of the present application.

Claims

1. A method of producing a bottom electrode-insulating layer-top electrode structure, characterized by, The method comprises the steps of: providing a substrate and forming a bottom electrode on the surface of the substrate; forming an insulating layer on the bottom electrode, the material of the insulating layer comprising a metal oxide; forming a buffer layer and a top electrode on the insulating layer in sequence, the material of the buffer layer being selenium or tellurium; removing the buffer layer by an annealing process so that the insulating layer and the top electrode are in contact without damage, thereby obtaining the bottom electrode-insulating layer-top electrode structure.

2. The method of claim 1, wherein the method further comprises: The thickness of the buffer layer is 2-50 nm.

3. The method of claim 1, wherein the method further comprises: The metal oxide is HfO2, Al2O3 or VO2.

4. The method of claim 1, wherein the method further comprises: The thickness of the insulating layer is 0.5-50 nm.

5. The method of claim 1, wherein the method further comprises: The annealing process is an atmosphere annealing process, the gas used is one or more of hydrogen, argon and nitrogen, the annealing temperature is 120-200℃, and the annealing time is 0.5-2 h.

6. The method of claim 1, wherein the method further comprises: The material of the bottom electrode is the same as or different from that of the top electrode.

7. The method of claim 1, wherein the method further comprises: The step of forming a bottom electrode on the surface of the substrate specifically comprises: applying photoresist on the surface of the substrate and performing preset bottom electrode patterning treatment on the substrate by using a photolithography process; depositing a bottom electrode material and removing the photoresist on the substrate to form a patterned bottom electrode on the surface of the substrate.

8. The method of claim 1, wherein the method further comprises: The preparation method further comprises: before the step of forming a buffer layer and a top electrode on the insulating layer in sequence, applying photoresist on the insulating layer and performing preset top electrode patterning treatment on the insulating layer by using a photolithography process; before the step of removing the buffer layer by an annealing process, removing the photoresist on the insulating layer.

9. A bottom electrode-insulating layer-top electrode structure prepared by the preparation method according to any one of claims 1-8.

10. A microelectronic device, comprising: The bottom electrode-insulating layer-top electrode structure according to claim 9.

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