Mask pattern correction method and device, equipment, medium and product

Abstract

The invention provides a mask pattern correction method and device, equipment, a medium and a product, and the method comprises the steps: correcting a first mask plate corresponding to a to-be-corrected design layout, and obtaining a second mask plate; defect detection is carried out on the simulation pattern contour corresponding to the second mask plate to obtain a detection result, and the detection result comprises a plurality of defect patterns with defects in the second mask plate and a defect type corresponding to each defect pattern; for a plurality of defect patterns belonging to the same defect type, obtaining at least one pattern group with the same shape in the plurality of defect patterns; obtaining a correction graph corresponding to the defect graph in the at least one graph group; and for any defect pattern in the second mask plate, replacing the defect pattern with the correction pattern corresponding to the pattern group with the same shape as the defect pattern to obtain a target mask plate. According to the embodiment of the invention, the mask pattern correction efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a mask pattern correction method, device, equipment, medium and product. Background Art

[0002] In the field of semiconductor manufacturing, lithography is one of the key processes, and its accuracy and efficiency directly determine the performance and cost of the chip. With the continuous reduction of the feature size of integrated circuits, lithography rule check (LRC) and optical proximity correction (OPC) have become important links to ensure the accurate transfer of patterns to silicon wafers. However, in the face of increasingly complex chip designs, the LRC and OPC processes under the existing technology system face severe challenges. In particular, after OPC correction, the traditional LRC method needs to verify the quality of the mask graphics through detailed simulation and full-layout hotspot detection. In this process, for mask graphics with poor correction effects, multiple iterations of correction and inspection are often required, resulting in a time-consuming and inefficient overall process. Summary of the invention

[0003] The present application provides a mask pattern correction method, device, equipment, medium and product, which can improve the efficiency of mask pattern correction.

[0004] In a first aspect, an embodiment of the present application provides a mask pattern correction method, the method comprising:

[0005] Correcting the first mask corresponding to the design layout to be corrected to obtain a second mask;

[0006] Performing defect detection on the simulated pattern contour corresponding to the second mask plate to obtain a detection result, wherein the detection result includes a plurality of defect patterns having defects in the second mask plate and a defect type corresponding to each defect pattern;

[0007] For a plurality of defect graphics belonging to the same defect type, obtaining at least one group of graphics having the same shape among the plurality of defect graphics;

[0008] Obtaining a correction pattern corresponding to a defective pattern in at least one pattern group;

[0009] For any defective pattern in the second mask, the defective pattern is replaced by a correction pattern corresponding to a pattern group having the same shape as the defective pattern, to obtain a target mask.

[0010] In a second aspect, the present application provides a mask pattern correction device, the device comprising:

[0011] A correction module, used for correcting the first mask corresponding to the design layout to be corrected to obtain a second mask;

[0012] A detection module, used to perform defect detection on the simulated pattern contour corresponding to the second mask plate to obtain a detection result, wherein the detection result includes a plurality of defective patterns with defects in the second mask plate and a defect type corresponding to each defective pattern;

[0013] A first acquisition module is used to acquire, for a plurality of defect patterns belonging to the same defect type, at least one group of patterns having the same shape among the plurality of defect patterns;

[0014] A second acquisition module, used for acquiring a correction pattern corresponding to a defective pattern in the at least one pattern group;

[0015] The replacement module is used to replace any defective pattern in the second mask plate with a correction pattern corresponding to a pattern group with the same shape as the defective pattern to obtain a target mask plate.

[0016] In a third aspect, an embodiment of the present application provides an electronic device, the electronic device comprising: a processor and a memory storing computer program instructions;

[0017] When the processor executes the computer program instructions, the mask pattern correction method in any one of the embodiments of the first aspect is implemented.

[0018] In a fourth aspect, an embodiment of the present application provides a computer storage medium having computer program instructions stored thereon, and when the computer program instructions are executed by a processor, a mask graphic correction method as in any one of the embodiments in the first aspect is implemented.

[0019] In a fifth aspect, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes a mask graphic correction method as in any one of the embodiments in the first aspect above.

[0020] In a mask pattern correction method, device, equipment, medium and product provided in an embodiment of the present application, the first mask plate is first corrected to obtain a second mask plate, and then the simulated pattern contour of the second mask plate is subjected to defect detection, and the defect type of each defect pattern is accurately classified. For defect patterns of the same defect type and shape, the correction pattern is designed and matched in units of pattern groups, avoiding the tedious process of correcting one by one in the traditional method. In the correction implementation stage, it is only necessary to replace each defect pattern with a correction pattern that matches its shape to quickly complete the optimization of the entire mask pattern. This technical solution not only reduces the number of unnecessary comprehensive simulations and repeated corrections, but also greatly shortens the overall correction cycle and improves the correction efficiency of the mask pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 It is a flowchart of a mask pattern correction method provided by an embodiment of the present application;

[0023] Figure 2 This is one of the principle schematic diagrams of a mask pattern correction method provided by an embodiment of the present application;

[0024] Figure 3 This is the second principle schematic diagram of a mask pattern correction method provided by an embodiment of the present application;

[0025] Figure 4 This is the third principle schematic diagram of a mask pattern correction method provided by an embodiment of the present application;

[0026] Figure 5 This is the fourth principle schematic diagram of the mask pattern correction method provided by an embodiment of the present application;

[0027] Figure 6 It is a structural schematic diagram of a mask pattern correction device provided in an embodiment of the present application;

[0028] Figure 7 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0030] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0031] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0032] In the field of semiconductor manufacturing, lithography rule checking is a key step in ensuring that patterns are accurately transferred to silicon wafers. Traditional methods rely on comparing simulated exposure profiles after optical proximity correction with preset target patterns, and identifying and correcting potential bad spots through a series of manually defined lithography rules. However, this method has significant drawbacks: in the face of complex and changing chip designs, when the OPC correction effect is not ideal, it is often necessary to go through multiple iterations of lithography rule checking and OPC correction cycles, which is not only time-consuming and lengthy, but also greatly reduces production efficiency. In addition, different layout designs often require customized lithography rules. This lack of flexibility further increases the difficulty of process optimization.

[0033] In order to solve the problems existing in the prior art, the embodiments of the present application provide a mask pattern correction method, device, equipment, medium and product.

[0034] The present application embodiment provides a mask pattern correction method, device, equipment, medium and product. The following first introduces the mask pattern correction method provided by the present application embodiment. Figure 1 As shown, the method specifically comprises the following steps:

[0035] S100, modifying a first mask corresponding to the design layout to be modified to obtain a second mask.

[0036] Optionally, in an embodiment of the present application, the design layout to be corrected exists in the form of an electronic file, which contains the geometry, layout and connection relationship between all circuit elements on the chip. The design layout is one of the most basic and important files in the chip manufacturing process, which directly determines the function and performance of the chip. However, due to physical limitations and uncertainties in the manufacturing process (such as optical diffraction, process deviations, etc. in the lithography process), the graphics on the design layout are often not perfectly reproduced when transferred to the silicon wafer, so corrections are required to optimize the final product quality. The "design layout to be corrected" here refers to the design layout that needs to be optimized.

[0037] The mask (also called a photomask or reticle) is a key tool used in the photolithography process in semiconductor manufacturing. It is a light-shielding layer coated with a specific pattern on a transparent substrate, and these patterns correspond one-to-one to the circuit elements on the chip to be manufactured. During the photolithography process, light is irradiated onto the silicon wafer through the transparent area on the mask, while the light-shielding area blocks the light, thereby forming a pattern on the silicon wafer that corresponds to the design layout. However, due to the difference between the actual pattern on the silicon wafer and the design layout, the mask generated directly using the design layout (i.e., the first mask) often cannot directly meet the manufacturing requirements, so it needs to be corrected.

[0038] Optionally, in a feasible implementation of the present application, first, a professional electronic design automation (EDA) tool can be used to read and analyze the design layout to be corrected to identify key features, such as line width, spacing, corner shape, etc. These features are easily affected by physical effects such as optical diffraction and interference during the photolithography process, resulting in deviations between the final graphics on the silicon wafer and the design intent. In order to compensate for these deviations, OPC technology will be applied next. This technology pre-calculates and adjusts the shape of the graphics on the mask plate to "reverse" offset the influence of these physical effects during the photolithography process, thereby ensuring that the graphics formed on the silicon wafer are as close to the design layout as possible.

[0039] Specifically, the OPC correction process includes multiple sub-steps, such as rule checking (ensuring that the graphics comply with established manufacturing rules), model building (building an optical model of the lithography process), simulation (simulating the interaction between light and mask graphics during the lithography process), and graphic optimization (adjusting the mask graphics based on the simulation results). In this series of steps, advanced algorithms and huge computing resources are used to carefully evaluate and adjust each feature in the design layout to ensure that each graphic on the final mask is carefully designed to achieve the expected imaging effect during the lithography process.

[0040] The first correction is usually based on a series of preset algorithms and models, which are designed to predict the pattern deformation that may occur during the lithography process and adjust the pattern on the mask accordingly. However, due to various uncertainties and complexities in the actual manufacturing process (such as performance fluctuations of the lithography machine, changes in material properties, slight differences in process parameters, etc.), the second mask (i.e., the second mask) obtained after the first correction may still not fully meet the manufacturing requirements.

[0041] S200, performing defect detection on the simulated pattern contour corresponding to the second mask plate to obtain a detection result, wherein the detection result includes a plurality of defective patterns having defects in the second mask plate and a defect type corresponding to each defective pattern.

[0042] Optionally, in an embodiment of the present application, the second mask is a mask that has been preliminarily corrected to reduce pattern distortion caused by physical effects (such as diffraction and interference) during the photolithography process. In order to evaluate the performance of the second mask in actual photolithography, simulation software is used to simulate the photolithography process and simulate the graphic profile formed on the silicon wafer. This is the simulated graphic profile corresponding to the second mask. This profile is calculated based on factors such as optical models, photolithography process parameters, and mask patterns, and is used to predict actual photolithography results.

[0043] In the simulated graphic outline, if some parts of the graphics do not conform to the design layout or manufacturing specifications, they may be considered defective graphics. These defects may be caused by insufficient OPC correction, mask manufacturing errors, photolithography process fluctuations, etc. Defective graphics may appear in the form of changes in line width, distortion of shapes, insufficient coverage or bridging of through holes, and disconnections.

[0044] Defective graphics can be classified into different defect types according to their specific characteristics and impacts. Including but not limited to the following: Critical dimension deformation: Critical dimensions such as width and length of lines or graphics do not match the design values. Line end deformation: The shape of the line end is distorted or deformed. Through-hole coverage problems: The coverage area of ​​through-holes (such as contact holes and vias) is insufficient or too large, resulting in poor connection or short circuit. Open circuits and bridges: Lines are broken or parts that should not be connected are accidentally connected. Auxiliary graphic imaging problems: Graphics used to assist in lithography alignment or measurement (such as alignment marks) are not clearly imaged or are offset. Process window problems: Within a certain range of process parameters, defective graphics cannot be effectively controlled.

[0045] Optionally, in a feasible implementation of the present application, the optical model is first used to perform a high-precision simulated lithography process on the second mask to predict the imaging effect of the mask pattern on the silicon wafer under real lithography conditions. This simulation process takes into account multiple factors such as the light source characteristics of the lithography machine, the aberration of the lens system, the photosensitivity characteristics of the photoresist, and the reflection and scattering of the silicon wafer surface, thereby generating a simulated pattern profile that is as close to the actual situation as possible.

[0046] Next, the simulated graphic outlines are analyzed and compared in detail by automated detection algorithms. Based on preset lithography rules and design specifications, these algorithms identify areas in the simulated graphic outline that do not conform to the design intent or may cause manufacturing problems, the so-called "defective graphics". At the same time, the algorithms will classify the defects according to their specific characteristics and determine the defect type corresponding to each defective graphic, such as critical dimension deformation, line end deformation, through-hole coverage problems, open circuits and bridges.

[0047] In order to more accurately locate and describe these defects, the algorithm also calculates the specific location and size information of the defective pattern and associates it with the corresponding part in the design layout. In this way, the pattern in the second mask is associated with the design layout with defects, so that in the subsequent correction process, these defective patterns can be processed in a targeted manner instead of indiscriminately modifying the entire mask.

[0048] The entire defect detection process is a highly automated and intelligent process that can comprehensively analyze and evaluate complex mask patterns in a short period of time and quickly and accurately identify potential manufacturing problems. This not only greatly improves the efficiency and accuracy of mask correction, but also provides strong data support for subsequent correction work.

[0049] S300 , for a plurality of defect patterns belonging to the same defect type, obtaining at least one group of patterns having the same shape among the plurality of defect patterns.

[0050] Optionally, in a feasible implementation of the present application, all defect graphics and their corresponding defect types are first traversed, and defect graphics of the same defect type are classified into one category. The purpose of this is to centrally process graphics with similar characteristics and correction requirements, thereby improving correction efficiency and accuracy.

[0051] Next, for each type of defective graphics, the shape features of these graphics are further analyzed to identify groups of graphics with the same shape. This step can rely on advanced graphics matching algorithms that can accurately compare the geometric shape, size ratio and other features of the graphics to determine whether they belong to the same group. During the graphics matching process, some preprocessing steps can be used to simplify the graphics structure, remove noise or perform normalization to improve the accuracy and robustness of the matching.

[0052] Once groups of graphics with the same shape are identified, they are recorded and a unique identifier or label is assigned to each group. This identifier or label will be used to reference and replace the corresponding defective graphics in the subsequent correction process. At the same time, in order to ensure the accuracy of the correction, the specific location information of the defective graphics in each group of graphics, such as coordinate position, rotation angle, etc., can also be recorded so that these graphics can be accurately located and replaced during the correction process.

[0053] It is worth noting that the implementation of step S300 also involves some optimization strategies. For example, in order to improve processing efficiency, parallel processing or distributed computing technology can be used to process multiple graphic groups at the same time; in order to reduce the amount of calculation, some heuristic algorithms or approximate matching methods can be used to quickly identify graphic groups with similar shapes. In addition, in order to ensure the quality and consistency of the correction graphics, a correction graphic library can be established, which contains correction graphic templates for various common defect types. In S400, the correction graphic template that matches the current graphic group can be retrieved from this library for subsequent replacement operations.

[0054] In summary, S300 organizes graphics with the same defect type and shape into groups by classifying and matching defect graphics, and assigns a unique identifier and location information to each graphic group. This step provides an important data foundation and organizational framework for subsequent correction work, making the correction process more efficient, accurate and controllable.

[0055] S400, obtaining a correction pattern corresponding to a defective pattern in the at least one pattern group.

[0056] Optionally, in a feasible implementation of the present application, for each group of defective patterns with the same shape identified in S300, one defective pattern in the group is selected as a representative for real-time correction attempts. The advantage of this method is that the correction strategy can be adjusted in real time according to the specific defect situation to achieve higher correction accuracy.

[0057] Next, the selected defective pattern is simulated and corrected using a lithography simulation tool or a physical model. During the correction process, various parameters can be adjusted, such as the size, position, shape, etc. of the corrected pattern, to observe the impact of these changes on the final pattern profile. The goal of the correction is to make the corrected pattern profile as close to the design layout requirements as possible and meet the preset accuracy requirements.

[0058] In order to achieve real-time correction, an iterative optimization algorithm can be designed. In each iteration, the algorithm will automatically adjust the correction parameters according to the current correction results and the preset accuracy requirements, and re-simulate the correction. This process will be repeated until the corrected graphic contour meets the preset accuracy requirements. In order to ensure the stability and reliability of the correction results, some verification steps can also be set. For example, during the correction process, the corrected graphic contour can be compared with the design layout regularly to verify whether the correction effect meets expectations. If it is found that the correction result deviates greatly from expectations, the algorithm can automatically adjust the correction strategy or select other defective graphics for trial.

[0059] Finally, when the representative defective pattern in a group meets the preset accuracy requirement through real-time correction, the correction strategy or correction pattern can be applied to other defective patterns of the same shape in the group, thereby achieving correction of the entire pattern group.

[0060] S500: For any defective pattern in the second mask, replace the defective pattern with a correction pattern corresponding to a pattern group having the same shape as the defective pattern, to obtain a target mask.

[0061] Optionally, in a feasible implementation of the present application, a mapping relationship may be established first, which associates each group of defective patterns with the same shape identified in S300 with their corresponding correction patterns. This mapping relationship may be a table, a database, or any form of data structure, as long as it can be efficiently queried and retrieved.

[0062] Next, for each defect pattern detected in the second mask, S500 first determines its shape and defect type. Then, based on this information, the correction pattern corresponding to the pattern group with the same shape and matching defect type as the defect pattern is searched in the previously established mapping relationship. Once a matching correction pattern is found, S500 performs a replacement operation, that is, replacing the defect pattern in the second mask with the found correction pattern.

[0063] During the replacement process, it is necessary to ensure that the size, position, direction and other parameters of the corrected graphics match those of the defective graphics to ensure that the contour of the replaced graphics meets the design requirements. Specifically, it is required to accurately calculate the placement parameters of the corrected graphics, and some fine-tuning is required to ensure that the replaced graphics maintain the correct relative position relationship with the surrounding graphics.

[0064] In addition, S500 also needs to consider the manufacturability of the modified pattern. That is, the modified pattern must not only meet the design requirements, but also meet the constraints of the manufacturing process, such as the minimum line width, spacing rules, etc. Therefore, during the replacement process, some additional verification steps may be required to ensure that the modified pattern will not introduce new defects during the manufacturing process.

[0065] Finally, when all defective patterns are replaced with corresponding corrected patterns, S500 generates a new mask data file, namely the target mask, which contains the corrected mask pattern information and can be directly used in subsequent manufacturing processes.

[0066] In a mask pattern correction method, device, equipment, medium and product provided in an embodiment of the present application, the first mask plate is first corrected to obtain a second mask plate, and then the simulated pattern contour of the second mask plate is subjected to defect detection, and the defect type of each defect pattern is accurately classified. For defect patterns of the same defect type and shape, the correction pattern is designed and matched in units of pattern groups, avoiding the tedious process of correcting one by one in the traditional method. In the correction implementation stage, it is only necessary to replace each defect pattern with a correction pattern that matches its shape to quickly complete the optimization of the entire mask pattern. This technical solution not only reduces the number of unnecessary comprehensive simulations and repeated corrections, but also greatly shortens the overall correction cycle and improves the correction efficiency of the mask pattern.

[0067] In one embodiment, the step of performing defect detection on the simulated pattern contour corresponding to the second mask plate to obtain a detection result includes:

[0068] Performing a lithography rule check on the simulated pattern profile corresponding to the second mask plate to obtain defect point information, wherein the defect point information includes the corresponding coordinate positions of multiple defect points on the design layout to be corrected, and the defect type of each defect point;

[0069] Determining a plurality of defective patterns having defects in the second mask plate according to the coordinate positions corresponding to each of the plurality of defective points on the design layout to be corrected;

[0070] According to the defect type of each defect point, determine the defect type corresponding to each defect graph;

[0071] A plurality of defective patterns having defects in the second mask plate and a defect type corresponding to each defective pattern are determined as the detection result.

[0072] Optionally, in a feasible implementation of the present application, first, the simulated graphic contour can be analyzed in detail through the lithography rule checking technology to identify any areas that violate the lithography process rules or design specifications, which are defect points. During the lithography rule checking process, every detail of the simulated graphic contour will be traversed, compared with the pre-set lithography rule library, and all coordinate positions that do not meet the rules and the corresponding defect types, such as line width too narrow, insufficient spacing, etc., will be recorded to form defect point information.

[0073] Next, based on the defect point information, the coordinate position of each defect point on the design layout to be corrected can be reversely mapped to the graphic structure of the second mask, so as to accurately locate the actual defective graphic area in the mask, that is, the defective graphic. This process requires a deep understanding of the correspondence between the design layout and the mask graphic, and the use of efficient graphic processing algorithms to achieve coordinate conversion and graphic matching.

[0074] Subsequently, the defect type of each defect point is further determined based on the defect type of each defect pattern. Since a defect pattern may contain multiple defect points, and these defect points may belong to different defect types, it is necessary to comprehensively consider the types of these defect points and assign a defect type label that best matches its overall characteristics to each defect pattern through methods such as logical judgment or statistical analysis.

[0075] Finally, the multiple defective patterns with defects in the second mask and the defect types corresponding to each defective pattern are compiled into a complete test result report. This report not only records the specific location, shape and size of the defective patterns, but also clarifies their defect types, providing detailed data support for subsequent pattern correction work. Through this series of steps, this embodiment successfully achieves accurate defect detection of the contour of the simulated pattern of the second mask, laying a solid foundation for subsequent pattern correction and optimization.

[0076] In these optional embodiments, through precise lithography rule inspection, defect points are accurately located and their types are identified, and then the defect pattern and its type are determined, thereby ensuring the comprehensiveness and accuracy of defect detection, providing strong support for subsequent pattern correction, and improving the success rate of chip manufacturing and product quality.

[0077] In one embodiment, the determining of a plurality of defective patterns having defects in the second mask plate according to the coordinate positions corresponding to each of the plurality of defective points on the design layout to be corrected includes:

[0078] Determine, according to the coordinate position corresponding to the first defect point on the design layout to be corrected, a design pattern corresponding to the first defect point in the design layout to be corrected, wherein the first defect point is any one of the multiple defect points;

[0079] A pattern in the second mask plate corresponding to the design pattern is determined as a defective pattern.

[0080] Optionally, in a feasible implementation of the present application, first, any one of the multiple defect points is selected as the first defect point. This selection is arbitrary because the processing flow of each defect point is the same and will eventually contribute to the identification of the defective pattern. Then, according to the coordinate position corresponding to the first defect point on the design layout to be corrected, the design pattern corresponding to this coordinate position on the design layout is accurately located through an efficient coordinate mapping mechanism.

[0081] In the coordinate system, each graphic element (such as lines, polygons, etc.) on the design layout is assigned one or more coordinate points, which define the position and shape of the graphic element. Similarly, the graphics on the mask are also described by a similar coordinate system. Therefore, when the coordinate position of the defect point on the design layout is known, the corresponding graphic area on the mask can be found through coordinate mapping.

[0082] In these optional embodiments, through precise coordinate mapping, the defect points on the design layout are mapped to specific patterns on the second mask plate, and the defective patterns are quickly and accurately identified, thereby improving the efficiency and accuracy of defect detection, providing precise target positioning for subsequent pattern correction, and helping to improve chip manufacturing quality and yield.

[0083] In one embodiment, the defect point information further includes a defect value corresponding to each defect point;

[0084] The step of determining the defect type corresponding to each defect pattern according to the defect type of each defect point includes:

[0085] For any first graphic among the plurality of defective graphics, obtaining a second graphic corresponding to the first graphic in the to-be-corrected design layout;

[0086] In the case where there are at least two defect points of at least two defect types on the second figure, the defect type of the defect point corresponding to the maximum defect value among the at least two defect points is determined as the defect type of the first figure.

[0087] In one embodiment, determining the defect type corresponding to each defect pattern according to the defect type of each defect point further includes:

[0088] In the case that there is a defect point of a defect type on the second graphic, the defect type is determined as the defect type of the first graphic.

[0089] Optionally, in a feasible implementation method of the present application, first, the defect point information not only includes the coordinate position and defect type, but also adds the defect value corresponding to each defect point. This defect value is used to quantify the severity of the defect or the scope of influence, such as the specific value of the line width deviation, the specific distance of insufficient spacing, etc.

[0090] For any first graphic among multiple defective graphics, first find the corresponding second graphic in the design layout to be corrected by coordinate mapping and other methods. Next, when there are at least two defect points of at least two defect types on the second graphic, it is necessary to determine which defect type can better represent the overall defect condition of this graphic. To this end, the defect values ​​corresponding to these defect points are compared, and the defect type of the defect point corresponding to the maximum defect value is selected as the defect type of the graphic. The larger the defect value, the greater its impact on the graphic performance or chip manufacturing quality may be, so it should be given priority.

[0091] However, in another case, if there is only one defect point of defect type on the second graph, then determining the defect type of the graph becomes relatively simple and direct. It is only necessary to directly determine this unique defect type as the defect type of the graph.

[0092] In these optional embodiments, through such a processing flow, not only can the defective patterns on the mask be identified, but also the defect types of these patterns can be more finely classified. This classification not only takes into account the type of defect, but also the severity or impact range of the defect, thereby providing more comprehensive and accurate information for subsequent pattern correction work. At the same time, this classification method based on defect values ​​also helps to better understand the relative importance of different defect types, so as to make more reasonable decisions during the correction process.

[0093] In one embodiment, obtaining a correction pattern corresponding to a defective pattern in the at least one pattern group includes:

[0094] Acquire a third pattern with the largest degree of defect among defective patterns in a target pattern group, wherein the target pattern group is any one of the at least one pattern group;

[0095] The third pattern is corrected based on a preset correction method to obtain a corrected pattern corresponding to the target pattern group, wherein the preset correction method corresponds to the defect type of the defect pattern in the target pattern group.

[0096] Optionally, in a feasible implementation of the present application, first, a target graphic group is selected from at least one group of graphic groups as the object of current processing, and this selection can be based on a preset sorting rule (such as the number of defects, the severity of defects, etc.) or can be manually specified by the user. After the target graphic group is selected, the defective graphics in the group are further identified, and special attention is paid to the third graphic with the largest defect degree.

[0097] The evaluation of defect severity depends on multiple factors, including but not limited to defect type, defect value (as mentioned above, used to quantify the severity or impact range of the defect), potential impact of the defect on pattern performance or chip manufacturing quality, etc. Defective patterns can be comprehensively scored based on these factors to determine which pattern has the greatest degree of defect.

[0098] Once the third pattern is determined, it will be corrected according to the preset correction method. The preset correction method here is closely related to the defect type of the defective pattern in the target pattern group, which means that different defect types will have different correction strategies. For example, for defects with too narrow line width, the correction method can be to increase the width of the line; for defects with insufficient spacing, the correction method can be to adjust the distance between patterns. These correction methods are based on long-term design experience and process knowledge accumulation, aiming to restore the original design intent of the pattern to the greatest extent, while ensuring that the corrected pattern meets the requirements of the lithography process.

[0099] During the correction process, a variety of graphics processing techniques can be used, such as shape recognition, size adjustment, position movement, etc., to ensure the accuracy and efficiency of the correction. After the correction is completed, the corrected graphics will be saved as the corrected graphics corresponding to the target graphics group for use in subsequent steps.

[0100] In these optional embodiments, through such a processing flow, the pattern with the most serious defects in the pattern group can be efficiently identified, and the corresponding correction method can be used to correct it based on its defect type. This targeted correction strategy not only improves the efficiency and accuracy of the correction, but also helps to reduce unnecessary correction work, thereby reducing the cost and time of chip manufacturing. At the same time, because the correction method is carefully designed according to the defect type, the corrected pattern is more likely to meet the design requirements, improving the success rate of chip manufacturing and product quality.

[0101] In one embodiment, for any defective pattern in the second mask, replacing the defective pattern with a correction pattern corresponding to a pattern group having the same shape as the defective pattern to obtain a target mask comprises:

[0102] For any defective pattern in the second mask plate, if the correction pattern corresponding to the pattern group with the same shape as the defective pattern meets the lithography rules of the design layout to be corrected, the defective pattern is replaced with the correction pattern corresponding to the pattern group with the same shape as the defective pattern to obtain the target mask plate.

[0103] Optionally, in a feasible implementation of the present application, first, it should be clear that each defective pattern exists in a pattern group with the same shape, which means that although the patterns in the same group may be in different positions or have different sizes, their basic shapes are consistent. Such a grouping strategy helps to manage and correct defects more effectively.

[0104] In the specific implementation, all defective patterns in the second mask are first traversed, and for each defective pattern, a pattern group with the same shape is found. Next, check whether the correction pattern corresponding to the pattern group meets the lithography rules of the design layout to be corrected. This step is crucial because it ensures that no new violations of design rules are introduced when replacing the defective pattern. Lithography rules include a series of geometric and physical constraints to ensure that the pattern transfer and replication during the chip manufacturing process can achieve the expected results.

[0105] If the correction pattern corresponding to the pattern group is found to conform to the lithography rules, a replacement operation will be performed, that is, the original defective pattern is replaced with the corresponding correction pattern. This replacement process needs to ensure that the replaced pattern is consistent with the original defective pattern in position, size and shape, but the defects are eliminated through correction. After the replacement is completed, a target mask that is closer to the design layout to be corrected is obtained.

[0106] It is worth noting that the replacement operation here is conditional, that is, it will only be performed when the correction pattern meets the lithography rules. This conditional replacement strategy not only improves the accuracy of the correction, but also avoids unnecessary error correction and duplication of work. At the same time, it also reflects the strict compliance with the requirements of the lithography process, ensuring that the corrected mask can meet the high-precision requirements of chip manufacturing.

[0107] In these optional embodiments, through such a processing flow, the defective pattern in the second mask can be effectively replaced with a corrected pattern that meets the design rules, thereby obtaining a more perfect target mask. This process not only improves the quality of the mask, but also provides a reliable guarantee for subsequent chip manufacturing work.

[0108] In one embodiment, the method further comprises:

[0109] According to a preset correction pattern library, defect detection is performed on the second mask to determine a defective area in the second mask where defects exist, wherein the defective area includes at least one defective pattern;

[0110] For any one of the at least one defect pattern, obtaining a correction pattern corresponding to the defect type of the defect pattern and the shape of the defect pattern from the preset correction pattern library;

[0111] For any one defect pattern among the at least one defect pattern, the defect pattern is replaced by a correction pattern corresponding to the defect pattern.

[0112] Optionally, in the embodiment of the present application, the preset correction graphic library refers to a database specifically used to store and manage various common defect graphic samples, which are continuously collected and sorted during the usual defect repair process. Specifically, the preset correction graphic library contains defect graphic samples of various defect types, and each defect graphic sample records in detail the type, shape, size, and location of the defect. This information is obtained through professional testing and analysis equipment to ensure the accuracy and reliability of the data.

[0113] Optionally, in a feasible implementation of the present application, a preset correction graphic library is first constructed, which is gradually formed by continuously collecting and sorting various common defect graphic samples in long-term defect repair practice. The preset correction graphic library not only provides a wealth of experience accumulation and reference basis for subsequent mask defect repair, but more importantly, the preset correction graphic library can also be used as a prediction tool. Before the OPC process, through in-depth analysis of the mask graphics, it can accurately identify those areas with higher defect risks, so as to carry out targeted key inspections and repairs on these areas.

[0114] In specific implementation, the second mask can be comprehensively inspected for defects based on the defect pattern samples stored in the preset correction pattern library. Once defective areas are found, these defective areas will be immediately analyzed in detail to determine the specific types and shapes of the defective patterns contained therein. Then, the preset correction pattern library is searched for correction patterns that completely match the defect types and defect shapes of these defective patterns. Once a matching correction pattern is found, a replacement operation can be performed to replace the original defective pattern with the corresponding correction pattern selected from the database. In these optional embodiments, by using the preset correction pattern library to perform efficient and accurate defect detection and repair on the second mask, the defective pattern on the mask can be quickly located and replaced, thereby significantly improving the quality and production efficiency of the mask. In addition, the establishment of the preset correction pattern library has also accumulated valuable experience and data for subsequent defect repair work, providing strong support for the continuous improvement and optimization of semiconductor production.

[0115] It should be noted that the various optional implementation modes introduced in the embodiments of the present application can be implemented in combination with each other or separately if they do not conflict with each other, and the embodiments of the present application are not limited to this.

[0116] In order to facilitate understanding of the information display method provided by the above embodiment, the above mask pattern correction method is described below using a specific scenario embodiment.

[0117] First, the first mask corresponding to the original design pattern (i.e., the design layout to be corrected) is corrected by OPC to obtain the second mask. The purpose of OPC is to pre-adjust the pattern size and shape to compensate for the pattern distortion caused by optical diffraction and process changes during the lithography process. After completing OPC, the exposure profile of the corrected mask (i.e., the second mask) is simulated using a high-precision lithography simulation model. This step generates the expected shape of the pattern after exposure, providing basic data for subsequent rule checking.

[0118] Subsequently, the simulated exposure profile is subjected to LRC to identify areas that do not conform to the lithography rules, especially those recurring defective patterns. The LRC tool analyzes every detail in the exposure profile and compares it with the preset lithography rules, such as Figure 2 As shown in Figure 2, a data file containing defect point information is generated. At the same time, through the graphic matching algorithm, as shown in Figure 2 Figure 3 As shown, it is possible to find all repeated graphics with the same shape features and record their coordinates and layer information. Figure 2'defect-count' is the number of defects, 'worst-size' is the maximum defect value in defect-count, 'category-id' is the defect type, 'check-id' is the defect detection algorithm, 'size' is the defect value, and 'patch-id' is the label of the corresponding mask pattern.

[0119] Subsequently, in-depth OPC optimization is performed for the defect types in the identified repetitive patterns. Figure 4 As shown, it can be seen Figure 4 The exposure profile in the figure has a very obvious terminal shrinkage effect, which can be inferred to be caused by insufficient variables in the optimization process. Therefore, it is necessary to re-interrupt the original design graphic (i.e., the design layout to be revised), add more variables, and place evaluation points at appropriate locations for optimization, such as Figure 5 As shown, the optimized result (i.e., the corrected graph) is obtained. Compared with the original result, the shrinkage effect at the end is greatly improved. If the result at this time meets the requirements, the optimization is stopped and the result is saved.

[0120] Finally, the intelligent pattern replacement function is used to replace all repeated and poorly performing patterns in the original layout with optimized and corrected patterns. Since the exposure profiles of patterns of the same shape are the same under the same mask, this step greatly improves the repair efficiency and avoids duplication of work. After the replacement is completed, a new optimized mask design is output, which contains defect-free and finely adjusted patterns.

[0121] Optionally, in the embodiments of the present application, the rapid repair of repeated graphic defect points in the lithography process is achieved through intelligent detection and optimization technology, which greatly reduces the complexity and difficulty of OPC correction. The present application can also establish a database, which not only accumulates valuable experience data in daily defect repair, but also predicts and identifies potential high-risk defect areas before OPC, so as to implement precise repair. Its highly automated script processing flow can quickly capture and process repeated graphics, greatly simplifying user operations and meeting the high-efficiency requirements in the production environment.

[0122] In addition, this application has significantly improved the efficiency of layout correction by uniformly outputting the graphics of the same type of defect points and replacing them as a whole after OPC correction, avoiding the inefficient method of repairing them one by one. At the same time, the constructed defect point information library provides OPC engineers with a wealth of reference cases, which helps to quickly accumulate and apply repair experience. When faced with similar layouts, relevant files can be quickly retrieved to achieve efficient reference and repair.

[0123] It is worth noting that this application has a wide range of applications and can be easily applied to various types of layouts, such as metal layers, hole layers, etc., demonstrating its strong versatility and flexibility. Ultimately, by reducing the complex steps and time-consuming OPC corrections, this application effectively reduces the overall optimization cost, bringing significant efficiency improvements and cost savings to the chip manufacturing industry.

[0124] Figure 6 A schematic structural diagram of a mask pattern correction device provided in another embodiment of the present application is shown. For ease of explanation, only the portion related to the embodiment of the present application is shown.

[0125] Reference Figure 6 , the mask pattern correction device may include:

[0126] A correction module 601 is used to correct a first mask corresponding to the design layout to be corrected to obtain a second mask;

[0127] A detection module 602 is used to perform defect detection on the simulated pattern contour corresponding to the second mask plate to obtain a detection result, wherein the detection result includes a plurality of defective patterns with defects in the second mask plate and a defect type corresponding to each defective pattern;

[0128] A first acquisition module 603 is used to acquire, for a plurality of defect patterns belonging to the same defect type, at least one group of patterns having the same shape among the plurality of defect patterns;

[0129] A second acquisition module 604 is used to acquire a correction pattern corresponding to the defective pattern in the at least one pattern group;

[0130] The replacement module 605 is used to replace any defective pattern in the second mask plate with a correction pattern corresponding to a pattern group with the same shape as the defective pattern, so as to obtain a target mask plate.

[0131] In one embodiment, the detection module 602 may include:

[0132] A first inspection submodule is used to perform a lithography rule inspection on the simulated pattern profile corresponding to the second mask plate to obtain defect point information, wherein the defect point information includes the corresponding coordinate positions of multiple defect points on the design layout to be corrected, and the defect type of each defect point;

[0133] A first determination submodule is used to determine a plurality of defective patterns having defects in the second mask plate according to the coordinate positions corresponding to each of the plurality of defect points on the design layout to be corrected;

[0134] The second determination submodule is used to determine the defect type corresponding to each defect pattern according to the defect type of each defect point;

[0135] The third determination submodule is used to determine a plurality of defective patterns having defects in the second mask plate and a defect type corresponding to each defective pattern as the detection result.

[0136] In one embodiment, the first determining submodule may include:

[0137] A first determining unit is used to determine a design pattern corresponding to the first defect point in the design layout to be corrected according to a coordinate position corresponding to the first defect point in the design layout to be corrected, wherein the first defect point is any one of the multiple defect points;

[0138] The second determining unit is used to determine the pattern in the second mask plate corresponding to the design pattern as a defective pattern.

[0139] In one embodiment, the defect point information further includes a defect value corresponding to each defect point; and the second determination submodule may include:

[0140] A first acquisition unit is used to acquire, for any first graphic among the plurality of defective graphics, a second graphic corresponding to the first graphic in the design layout to be corrected;

[0141] The third determining unit is used to determine the defect type of the defect point corresponding to the maximum defect value among the at least two defect points as the defect type of the first figure when there are at least two defect points of at least two defect types on the second figure.

[0142] In one embodiment, the second determining submodule may further include:

[0143] The fourth determining unit is used to determine, when there is a defect point of a defect type on the second graphic, the defect type as the defect type of the first graphic.

[0144] In one embodiment, the second acquisition module 604 may include:

[0145] A first acquisition submodule is used to acquire a third pattern with the largest degree of defect among defective patterns in a target pattern group, wherein the target pattern group is any one of the at least one pattern group;

[0146] The correction submodule is used to correct the third pattern based on a preset correction method to obtain a corrected pattern corresponding to the target pattern group, wherein the preset correction method corresponds to the defect type of the defect pattern in the target pattern group.

[0147] In one embodiment, the replacement module 605 may include:

[0148] The replacement submodule is used to replace any defective pattern in the second mask plate with a correction pattern corresponding to a pattern group with the same shape as the defective pattern, so as to obtain the target mask plate, if the correction pattern corresponding to the pattern group with the same shape as the defective pattern meets the lithography rules of the design layout to be corrected.

[0149] In one embodiment, the mask pattern correction device may further include:

[0150] A second detection module, configured to perform defect detection on the second mask plate according to a preset correction pattern library, and determine a defective area in the second mask plate where defects exist, wherein the defective area includes at least one defective pattern;

[0151] A third acquisition module is used to acquire, for any one of the at least one defect pattern, a correction pattern corresponding to the defect type of the defect pattern and the shape of the defect pattern from the preset correction pattern library;

[0152] The second replacement module is used to replace any one defect pattern among the at least one defect pattern with a correction pattern corresponding to the defect pattern.

[0153] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application, and are devices corresponding to the above-mentioned methods. All implementation methods in the above-mentioned method embodiment are applicable to the embodiments of the device. Its specific functions and technical effects brought about can be found in the method embodiment part, and will not be repeated here.

[0154] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0155] Figure 7 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application is shown.

[0156] The device may include a processor 701 and a memory 702 storing program instructions.

[0157] When the processor 701 executes the program, the steps in any of the above method embodiments are implemented.

[0158] Exemplarily, the program may be divided into one or more modules / units, one or more modules / units are stored in the memory 702 and executed by the processor 701 to complete the present application. One or more modules / units may be a series of program instruction segments capable of completing a specific function, and the instruction segments are used to describe the execution process of the program in the device.

[0159] Specifically, the processor 701 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0160] The memory 702 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 702 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 702 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 702 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 702 is a non-volatile solid-state memory.

[0161] The memory may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical or other physical / tangible memory storage devices. Thus, typically, the memory includes one or more tangible (non-transitory) readable storage media (e.g., memory devices) encoded with software including computer executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to an aspect of the present disclosure.

[0162] The processor 701 implements any one of the methods in the above embodiments by reading and executing program instructions stored in the memory 702 .

[0163] In one example, the electronic device may further include a communication interface 703 and a bus 710. The processor 701, the memory 702, and the communication interface 703 are connected via the bus 710 and communicate with each other.

[0164] The communication interface 703 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0165] Bus 710 includes hardware, software or both, and the parts of online data flow billing equipment are coupled to each other. For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front-end bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 710 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the present application considers any suitable bus or interconnection.

[0166] In addition, in combination with the method in the above embodiment, the embodiment of the present application can provide a storage medium for implementation. The storage medium stores program instructions; when the program instructions are executed by a processor, any one of the methods in the above embodiment is implemented.

[0167] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0168] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0169] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0170] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0171] The functional modules shown in the above block diagram can be implemented as hardware, software, firmware or their combination. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), suitable firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. Programs or code segments can be stored in machine-readable media, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable media" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. Code segments can be downloaded via computer grids such as the Internet, intranets, etc.

[0172] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0173] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0174] The above are only specific implementation methods of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A mask pattern correction method, characterized in that: The method comprises: Correcting the first mask corresponding to the design layout to be corrected to obtain a second mask; Performing defect detection on the simulated pattern contour corresponding to the second mask plate to obtain a detection result, wherein the detection result includes a plurality of defect patterns having defects in the second mask plate and a defect type corresponding to each defect pattern; For a plurality of defect patterns belonging to the same defect type, obtaining at least one group of patterns having the same shape among the plurality of defect patterns; Obtaining a correction pattern corresponding to a defective pattern in the at least one pattern group; For any defective pattern in the second mask plate, the defective pattern is replaced by a correction pattern corresponding to a pattern group having the same shape as the defective pattern, so as to obtain a target mask plate.

2. The mask pattern correction method according to claim 1, characterized in that: The step of performing defect detection on the simulated pattern contour corresponding to the second mask plate to obtain a detection result includes: Performing a lithography rule check on the simulated pattern profile corresponding to the second mask plate to obtain defect point information, wherein the defect point information includes the corresponding coordinate positions of multiple defect points on the design layout to be corrected, and the defect type of each defect point; Determining a plurality of defective patterns having defects in the second mask plate according to the coordinate positions corresponding to each of the plurality of defective points on the design layout to be corrected; According to the defect type of each defect point, determine the defect type corresponding to each defect graph; A plurality of defective patterns having defects in the second mask plate and a defect type corresponding to each defective pattern are determined as the detection result.

3. The mask pattern correction method according to claim 2, characterized in that: The step of determining a plurality of defective patterns having defects in the second mask plate according to the coordinate positions of the plurality of defective points on the design layout to be corrected includes: Determine, according to the coordinate position corresponding to the first defect point on the design layout to be corrected, a design pattern corresponding to the first defect point in the design layout to be corrected, wherein the first defect point is any one of the multiple defect points; A pattern in the second mask plate corresponding to the design pattern is determined as a defective pattern.

4. The mask pattern correction method according to claim 2, characterized in that: The defect point information also includes a defect value corresponding to each defect point; The step of determining the defect type corresponding to each defect pattern according to the defect type of each defect point includes: For any first graphic among the plurality of defective graphics, obtaining a second graphic corresponding to the first graphic in the to-be-corrected design layout; In the case where there are at least two defect points of at least two defect types on the second figure, the defect type of the defect point corresponding to the maximum defect value among the at least two defect points is determined as the defect type of the first figure.

5. The mask pattern correction method according to claim 4, characterized in that: The step of determining the defect type corresponding to each defect pattern according to the defect type of each defect point further includes: In the case that there is a defect point of a defect type on the second graphic, the defect type is determined as the defect type of the first graphic.

6. The mask pattern correction method according to claim 1, characterized in that: The obtaining of the correction pattern corresponding to the defective pattern in the at least one pattern group includes: Acquire a third pattern with the largest degree of defect among defective patterns in a target pattern group, wherein the target pattern group is any one of the at least one pattern group; The third pattern is corrected based on a preset correction method to obtain a corrected pattern corresponding to the target pattern group, wherein the preset correction method corresponds to the defect type of the defect pattern in the target pattern group.

7. The mask pattern correction method according to claim 1, characterized in that: The method of replacing any defective pattern in the second mask plate with a correction pattern corresponding to a pattern group having the same shape as the defective pattern to obtain a target mask plate comprises: For any defective pattern in the second mask plate, if the correction pattern corresponding to the pattern group with the same shape as the defective pattern meets the lithography rules of the design layout to be corrected, the defective pattern is replaced with the correction pattern corresponding to the pattern group with the same shape as the defective pattern to obtain the target mask plate.

8. The mask pattern correction method according to claim 1, characterized in that: The method further comprises: According to a preset correction pattern library, defect detection is performed on the second mask to determine a defective area in the second mask where defects exist, wherein the defective area includes at least one defective pattern; For any one of the at least one defect pattern, obtaining a correction pattern corresponding to the defect type of the defect pattern and the shape of the defect pattern from the preset correction pattern library; For any one defect pattern among the at least one defect pattern, the defect pattern is replaced by a correction pattern corresponding to the defect pattern.

9. An electronic device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the mask pattern correction method according to any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the mask pattern correction method according to any one of claims 1 to 8 is implemented.

11. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the mask pattern correction method as described in any one of claims 1 to 8.

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