PCIe and SRIO interface channel data conversion system and method based on FPGA

Abstract

The invention relates to a PCIe and SRIO interface channel data conversion system and method based on an FPGA, and belongs to the technical field of data conversion. The method is compatible with various data transmission formats, so that the data transmission formats do not depend on message formats in transmission data; according to the method and the device, a transmission header is established, and user-defined first packet, middle packet and tail packet marks are added to reserved fields in the transmission header, so that various data transmission formats are supported, analysis of message information in an original message is omitted, time loss in data transmission is reduced, and the transmission rate can reach 80% of the maximum link supportable rate; and the SRIO channel is flexible and can support a plurality of single-path SRIO interface channels.

Description

Technical Field

[0001] The present invention belongs to the technical field of data conversion, and in particular relates to a PCIe and SRIO interface channel data conversion system and method based on FPGA. Background Art

[0002] At present, in the main technologies for FPGA-based PCIe interface and SRIO interface channel data conversion, data conversion depends on parsing information such as the length of the transmission data message format. When data in a new message format needs to be converted in the channel, the FPGA program needs to be redesigned, which complicates the design and increases resource usage. Summary of the invention

[0003] 1. Technical issues to be resolved

[0004] In order to solve the problems caused by the conversion of multiple message formats, the present invention provides a processing and implementation scheme for PCIe and SRIO interface channel data conversion based on FPGA.

[0005] (II) Technical solution

[0006] In order to solve the above technical problems, the present invention provides a PCIe and SRIO interface channel data conversion system based on FPGA, including a sending module and a receiving module;

[0007] Wherein, the sending module includes:

[0008] A PCIe interface data receiving module is used to receive data transmitted to the FPGA through the PCIe interface protocol and convert the data into an internal data stream of the FPGA;

[0009] A receiving data buffer module is used to buffer a whole packet of complete data from the PCIe interface data receiving module;

[0010] The data subpacketization module is used to subpacket the complete data cached by the receiving data cache module into multiple data packets suitable for sending by the SRIO interface data sending module, add the SRIO transmission header during the subpacketization process, and add the packet marks of the first packet, the middle packet, and the last packet in the SRIO transmission header;

[0011] The SRIO interface data sending module is used to receive the data stream obtained after the data subpacketization module, convert it into data that complies with the SRIO interface protocol, and send it to the SRIO interface;

[0012] The receiving module comprises:

[0013] The SRIO interface data receiving module is used to receive data transmitted to the FPGA through the SRIO interface protocol from the SRIO interface and convert it into the SRIO interface data stream inside the FPGA;

[0014] A data packetization module is used to parse the packet flags of the first packet, the middle packet, and the last packet in the SRIO transmission header of the SRIO interface data stream, delete the SRIO transmission header from the SRIO interface data stream, and then combine the data stream into a complete packet of complete data according to the packet flags of the first packet, the middle packet, and the last packet in the SRIO transmission header;

[0015] A sending data buffer module is used to buffer a whole packet of complete data from the data packaging module;

[0016] The PCIe interface data sending module is used to receive a whole package of complete data from the sending data buffer module, convert it into data that complies with the PCIe interface protocol, and send it to the PCIe interface.

[0017] The present invention also provides a PCIe and SRIO interface channel data conversion method implemented based on the system.

[0018] Preferably, the implementation process of PCIe to SRIO end in this method is as follows:

[0019] PCIe to SRIO:

[0020] The PCIe interface data receiving module waits to receive data from the PCIe interface, and the receiving data buffer module buffers a whole packet of complete data Data_P2S from the PCIe interface data receiving module;

[0021] The data packetization module receives the data Data_P2S from the receiving data buffer module, and packets it into multiple data packets and form a data stream to send to the SRIO interface data sending module; when the packetization starts, the first packet Data_P2S_0 is first packetized and an SRIO transmission header with a first packet mark is added to generate a data stream SRIO_HEAD+Data_P2S_0, and then the middle packet is packetized and an SRIO transmission header with a middle packet mark is added. When the packetization ends, the tail packet Data_P2S_n is packetized and an SRIO transmission header with a tail packet mark is added to generate a data stream SRIO_HEAD+Data_P2S_n;

[0022] The SRIO interface data sending module receives the data stream SRIO_HEAD+Data_P2S_n and sends it to the SRIO interface.

[0023] Preferably, standard AXI-Stream transmission is adopted during PICe forwarding, and can be routed and distributed to multiple single-channel SRIO interface channels.

[0024] Preferably, the implementation process of SRIO to PCIe end in this method is as follows:

[0025] The SRIO interface data receiving module waits to receive data from the SRIO interface, and sends the received data stream SRIO_HEAD+Data_P2S_n to the data packaging module;

[0026] The data packetization module first parses the first packet, middle packet, and last packet flags in the SRIO transmission header SRIO_HEAD, then deletes the SRIO transmission header SRIO_HEAD, and finally combines the sub-packet data stream Data_P2S_n into a complete data packet Data_P2S and sends it to the sending data buffer module;

[0027] The sending data buffer module buffers the complete data packet Data_P2S and sends it to the PCIe interface data sending module, and the PCIe interface data sending module sends the complete data packet Data_P2S to the PCIe interface.

[0028] Preferably, the method completes data conversion from PCIe to SRIO and then to PCIe.

[0029] Preferably, the SWRITE message type in the HELLO FTYPE Packet Format is used during SRIO forwarding, and the SRIO transmission header is the SWRITE message transmission header.

[0030] The present invention also provides a system on chip based on FPGA implemented based on the system.

[0031] The invention also provides an application of the system in the field of data conversion.

[0032] The invention also provides an application of the method in the field of data conversion.

[0033] (III) Beneficial effects

[0034] The present invention provides a processing and implementation scheme for PCIe and SRIO interface channel data conversion based on FPGA, which is compatible with multiple data transmission formats and is independent of the message format in the transmission data; and supports multiple data transmission formats by adding customized first packet, middle packet and tail packet flags to the reserved fields in the transmission header, omits parsing the message information in the original message, reduces the time loss in data transmission, and the transmission rate can reach 80% of the maximum link supportable rate; and the SRIO channel is flexible and can support multiple single-channel SRIO interface channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1It is a system module composition diagram of the present invention;

[0036] Figure 2 is the interface flow chart of the present invention;

[0037] Figure 3 This is a schematic diagram of the SRIO SWRITE format. DETAILED DESCRIPTION

[0038] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0039] In order to solve the problems caused by the conversion of multiple message formats, the present invention provides a processing and implementation scheme for PCIe and SRIO interface channel data conversion based on FPGA, which is compatible with multiple message formats and does not depend on the message format in the transmitted data.

[0040] refer to Figure 1 , a PCIe and SRIO interface channel data conversion system based on FPGA provided by the present invention includes a sending module and a receiving module;

[0041] Wherein, the sending module includes:

[0042] A PCIe interface data receiving module is used to receive data transmitted to the FPGA through the PCIe interface protocol and convert the data into an internal data stream of the FPGA;

[0043] A receiving data buffer module is used to buffer a whole packet of complete data from the PCIe interface data receiving module;

[0044] The data subpacketization module is used to subpacket the complete data cached by the receiving data cache module into multiple data packets suitable for sending by the SRIO interface data sending module, add the SRIO transmission header during the subpacketization process, and add the packet marks of the first packet, the middle packet, and the last packet in the SRIO transmission header;

[0045] The SRIO interface data sending module is used to receive the data stream obtained after the data subpacketization module, convert it into data that complies with the SRIO interface protocol, and send it to the SRIO interface.

[0046] The receiving module comprises:

[0047] The SRIO interface data receiving module is used to receive data transmitted to the FPGA through the SRIO interface protocol from the SRIO interface and convert it into the SRIO interface data stream inside the FPGA;

[0048] A data packetization module is used to parse the packet flags of the first packet, the middle packet, and the last packet in the SRIO transmission header of the SRIO interface data stream, delete the SRIO transmission header from the SRIO interface data stream, and then combine the data stream into a complete packet of complete data according to the packet flags of the first packet, the middle packet, and the last packet in the SRIO transmission header;

[0049] A sending data buffer module is used to buffer a whole packet of complete data from the data packaging module;

[0050] The PCIe interface data sending module is used to receive a whole package of complete data from the sending data buffer module, convert it into data that complies with the PCIe interface protocol, and send it to the PCIe interface.

[0051] refer to Figure 2 The PCIe and SRIO interface channel data conversion implementation process based on the system is as follows:

[0052] PCIe to SRIO:

[0053] The PCIe interface data receiving module waits to receive data from the PCIe interface, and the receiving data buffer module buffers a whole packet of complete data Data_P2S from the PCIe interface data receiving module;

[0054] The data packetization module receives the data Data_P2S from the receiving data buffer module, and packets it into multiple data packets and form a data stream to send to the SRIO interface data sending module; when the packetization starts, the first packet Data_P2S_0 is first packetized and an SRIO transmission header with a first packet mark is added to generate a data stream SRIO_HEAD+Data_P2S_0, and then the middle packet is packetized and an SRIO transmission header with a middle packet mark is added. When the packetization ends, the tail packet Data_P2S_n is packetized and an SRIO transmission header with a tail packet mark is added to generate a data stream SRIO_HEAD+Data_P2S_n;

[0055] The SRIO interface data sending module receives (packetizes) the data stream SRIO_HEAD+Data_P2S_n and sends it to the SRIO interface.

[0056] In the present invention, standard AXI-Stream transmission is adopted during PICe forwarding, and routing distribution to multiple single-channel SRIO interface channels is possible. The present invention only describes the forwarding process of a single SRIO interface channel.

[0057] SRIO to PCIe:

[0058] The SRIO interface data receiving module waits to receive data from the SRIO interface, and sends the received data stream SRIO_HEAD+Data_P2S_n to the data packaging module;

[0059] The data packetization module first parses the first packet, middle packet, and last packet flags in the SRIO transmission header SRIO_HEAD, then deletes the SRIO transmission header SRIO_HEAD, and finally combines the sub-packet data stream Data_P2S_n into a complete data packet Data_P2S and sends it to the sending data buffer module;

[0060] The sending data buffer module buffers the complete data packet Data_P2S and sends it to the PCIe interface data sending module, and the PCIe interface data sending module sends the complete data packet Data_P2S to the PCIe interface.

[0061] At this point, the data conversion from PCIe to SRIO and then to PCIe is completed.

[0062] In the present invention, the SWRITE message type in the HELLO FTYPE Packet Format is used during SRIO forwarding (SRIO to PCIe end), and the SWRITE message transmission header (SRIO transmission header) is as follows: Figure 3 By adding customized first packet, middle packet, and last packet flags to the reserved fields in the transmission header, support for multiple data transmission formats is achieved, parsing of the message information in the original message is omitted, time loss in data transmission is reduced, and the transmission rate can reach 80% of the maximum link rate.

[0063] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A PCIe and SRIO interface channel data conversion system based on FPGA, characterized in that: It includes a sending module and a receiving module; Wherein, the sending module includes: A PCIe interface data receiving module is used to receive data transmitted to the FPGA through the PCIe interface protocol and convert the data into an internal data stream of the FPGA; A receiving data buffer module is used to buffer a whole packet of complete data from the PCIe interface data receiving module; The data subpacketization module is used to subpacket the complete data cached by the receiving data cache module into multiple data packets suitable for sending by the SRIO interface data sending module, add the SRIO transmission header during the subpacketization process, and add the packet marks of the first packet, the middle packet, and the last packet in the SRIO transmission header; The SRIO interface data sending module is used to receive the data stream obtained after the data subpacketization module, convert it into data that complies with the SRIO interface protocol, and send it to the SRIO interface; The receiving module comprises: The SRIO interface data receiving module is used to receive data transmitted to the FPGA through the SRIO interface protocol from the SRIO interface and convert it into the SRIO interface data stream inside the FPGA; A data packetization module is used to parse the packet flags of the first packet, the middle packet, and the last packet in the SRIO transmission header of the SRIO interface data stream, delete the SRIO transmission header from the SRIO interface data stream, and then combine the data stream into a complete packet of complete data according to the packet flags of the first packet, the middle packet, and the last packet in the SRIO transmission header; A sending data buffer module is used to buffer a whole packet of complete data from the data packaging module; The PCIe interface data sending module is used to receive a whole package of complete data from the sending data buffer module, convert it into data that complies with the PCIe interface protocol, and send it to the PCIe interface.

2. A method for converting PCIe and SRIO interface channel data based on the system as claimed in claim 1.

3. The method according to claim 2, characterized in that The implementation process of PCIe to SRIO in this method is as follows: PCIe to SRIO: The PCIe interface data receiving module waits to receive data from the PCIe interface, and the receiving data buffer module buffers a whole packet of complete data Data_P2S from the PCIe interface data receiving module; The data packetization module receives the data Data_P2S from the receiving data buffer module, and packets it into multiple data packets and form a data stream to send to the SRIO interface data sending module; when the packetization starts, the first packet Data_P2S_0 is first packetized and an SRIO transmission header with a first packet mark is added to generate a data stream SRIO_HEAD+Data_P2S_0, and then the middle packet is packetized and an SRIO transmission header with a middle packet mark is added. When the packetization ends, the tail packet Data_P2S_n is packetized and an SRIO transmission header with a tail packet mark is added to generate a data stream SRIO_HEAD+Data_P2S_n; The SRIO interface data sending module receives the data stream SRIO_HEAD+Data_P2S_n and sends it to the SRIO interface.

4. The method according to claim 3, characterized in that Standard AXI-Stream transmission is used during PICe forwarding, and it can be routed and distributed to multiple single-channel SRIO interface channels.

5. The method according to claim 3, characterized in that The implementation process of SRIO to PCIe in this method is as follows: The SRIO interface data receiving module waits to receive data from the SRIO interface, and sends the received data stream SRIO_HEAD+Data_P2S_n to the data packaging module; The data packetization module first parses the first packet, middle packet, and last packet flags in the SRIO transmission header SRIO_HEAD, then deletes the SRIO transmission header SRIO_HEAD, and finally combines the sub-packet data stream Data_P2S_n into a complete data packet Data_P2S and sends it to the sending data buffer module; The sending data buffer module buffers the complete data packet Data_P2S and sends it to the PCIe interface data sending module, and the PCIe interface data sending module sends the complete data packet Data_P2S to the PCIe interface.

6. The method according to claim 5, characterized in that The method completes the data conversion from PCIe to SRIO and then to PCIe.

7. The method according to claim 5, characterized in that During SRIO forwarding, the SWRITE message type in the HELLO FTYPE PacketFormat is used, and the SRIO transmission header is the SWRITE message transmission header.

8. A system on chip based on FPGA implemented based on the system as claimed in claim 1.

9. An application of the system according to claim 1 in the field of data conversion.

10. An application of the method according to any one of claims 2 to 7 in the field of data conversion.

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