A security assessment method and system for logic-locked encryption circuits

Abstract

The present invention relates to the field of circuit security technology and proposes a security assessment method and system for a logic-locked encryption circuit, comprising: extracting key bits, logic gates, and logic cone sets in the logic-locked encryption circuit; searching for logically blockable key bits in the key bits; obtaining an X-state fill object in an automatic test vector generation algorithm based on the logically blockable key bits; traversing the logic cone set, generating a first test vector for the key bits in the logic cone based on the automatic test vector generation algorithm to obtain an ideal response; assuming a stuck-at fault for the current key bit, regenerating a second test vector based on the automatic test vector generation algorithm to obtain an actual response; comparing the actual response with the ideal response to obtain an inferable key; and calculating the proportion of inferable key bits in the key bits and comparing it with a preset threshold to obtain a security assessment result. The present invention significantly improves the efficiency of security assessment of logic-locked circuits.

Description

Technical Field

[0001] The present invention relates to the field of circuit security technology, and in particular to a security assessment method and system for a logic-locked encryption circuit. Background Art

[0002] The globalization of integrated circuit (IC) design and manufacturing has driven the rapid development of electronic products, but it has also created significant challenges for intellectual property protection. In this global supply chain environment, IC design and manufacturing often involve multiple manufacturers, increasing the risk of design leaks and intellectual property theft. To address these challenges, logic lockout technology has emerged. This technology embeds key-controlled logic gates within IC circuits, ensuring that the circuits function properly only when the correct key is input, thereby encrypting and protecting chip functionality. However, with the continuous advancement of attack methods, existing logic lockout technology faces severe security threats. Attackers can exploit the lockout mechanism through various methods, including path-sensitization attacks, SAT attacks, and fault injection attacks based on automatic test pattern generation (ATPG). These attack methods often bypass the lockout mechanism by obtaining circuit keys or injecting faults, thereby compromising the overall security of the circuit and posing a serious challenge to intellectual property protection.

[0003] Existing evaluation methods for logic-locked encryption circuits struggle to adapt to the increasing number of keys and increasingly complex lock logic required for complex and high-security lock circuits, resulting in inefficient security assessments. For example, assessing the risk of attacks based on fault injection requires significant computing resources to simulate and implement. This can require numerous fault injection assumptions and variables, especially when dealing with multiple keys and multi-level lock logic. This not only increases the difficulty of implementation and reduces evaluation efficiency, but can also impact the accuracy and reliability of the results. Summary of the Invention

[0004] In order to overcome the above-mentioned defect of low efficiency in security assessment of logic lock circuits in the prior art, the present invention provides a security assessment method and system for logic lock encryption circuits.

[0005] In order to achieve the above technical effects, the technical solutions of the present invention are as follows:

[0006] A security assessment method for a logic-locked encryption circuit comprises the following steps:

[0007] S1, extracting key bits and logic gates in the logic-locked encryption circuit; dividing the logic cone based on the output nodes in the logic-locked encryption circuit to obtain a logic cone set;

[0008] S2. Dividing the key bits into logically blockable key bits and non-logically blockable key bits; obtaining an X-state filling object in an automatic test vector generation algorithm based on the logically blockable key bits;

[0009] S3. Find the logic cone with the least key bits in the logic cone set;

[0010] S4. Traverse the key bit set in the current logic cone to find the key bit with the most X-state filled objects, generate a first test vector for this key bit based on an automatic test vector generation algorithm, input the first test vector into the logic-locked encryption circuit to obtain an ideal response, assume a stuck-at fault exists for this key bit, regenerate a second test vector based on the automatic test vector generation algorithm, input the second test vector into the logic-locked encryption circuit to obtain an actual response, and delete this key bit from the key bit set.

[0011] S5. Compare the actual response with the ideal response to obtain an inferred value of the key bit; take the key bit whose inferred value is the same as the correct value of the key bit as the inferred key bit, and repeat steps S4 to S5 until the key bit set is empty;

[0012] S6, deleting the current logic cone from the logic cone set, and repeating steps S3 to S6 until the logic cone set is empty;

[0013] S7. Calculate the proportion of the inferable key bits in the key bits, and compare it with a preset threshold to obtain a security assessment result.

[0014] The present invention also provides a security assessment system for a logic-locked encryption circuit, the system comprising:

[0015] Key bit division module: used to extract key bits and logic gates in the logic lock encryption circuit; divide the key bits into logically blockable key bits and non-logically blockable key bits;

[0016] The automatic test vector generation test module uses the logically blockable key bit as an X-state fill object in the automatic test vector generation algorithm; generates a first test vector for any key bit based on the automatic test vector generation algorithm, and inputs the first test vector into the logic-locked encryption circuit to obtain an ideal response; embeds a stuck-at fault in the current key bit, regenerates a second test vector based on the automatic test vector generation algorithm, and inputs the second test vector into the logic-locked encryption circuit to obtain an actual response;

[0017] Key bit inference module: compares the actual response with the ideal response to obtain an inferred value for any key bit, and makes a judgment based on the inferred value and the true value of the key bit. If the comparison results are the same, the key bit is considered to be an inferred key. Otherwise, the next key bit is judged until all key bits are traversed;

[0018] Logic lock encryption circuit security assessment module: calculates the proportion of inferable key bits in the key bits and compares it with a preset threshold to obtain a security assessment result.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The present invention improves the automatic test vector generation algorithm based on key invalidation. When generating test vectors using the automatic test vector generation algorithm, the X state of unspecified bits is induced to occur at logically blocked key bits. The number of fault injection points is greatly reduced, unnecessary global scans are avoided, and evaluation efficiency is improved. Subsequently, a pseudo-fault sensitization attack is implemented. By assuming a fault at each key bit, an actual response is obtained, and an inferred value is obtained by comparing it with an ideal response. If the inferred value is the same as the actual key value, the key bit is considered to be high-risk. The injection of pseudo-faults reduces unnecessary fault location, can quickly screen out potential high-risk key bits, avoids redundant calculation steps, improves the speed of overall test vector generation and analysis, and makes the security analysis of the entire encryption system more complete and targeted. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a flow chart of a security assessment method for a logic-locked encryption circuit according to Example 1.

[0022] Figure 2 This is the logic blocking schematic diagram of the AND gate.

[0023] Figure 3 This is the logic blocking principle diagram of the OR gate.

[0024] Figure 4 This is the logic blocking schematic diagram of the NAND gate.

[0025] Figure 5 This is the logic blocking schematic diagram of the NOR gate.

[0026] Figure 6 This is a flow chart of a security assessment system for a logic-locked encryption circuit according to Example 2. DETAILED DESCRIPTION

[0027] The accompanying drawings are for illustrative purposes only and are not to be construed as limiting the present invention;

[0028] It is understandable to those skilled in the art that some well-known descriptions may be omitted in the drawings.

[0029] The technical solution of the present invention is further described below with reference to the accompanying drawings and embodiments.

[0030] Example 1

[0031] This embodiment provides a security assessment method for a logic-locked encryption circuit, including the following steps:

[0032] S1, extracting key bits and logic gates in the logic-locked encryption circuit; dividing the logic cone based on the output nodes in the logic-locked encryption circuit to obtain a logic cone set;

[0033] S2. Dividing the key bits into logically blockable key bits and non-logically blockable key bits; obtaining an X-state filling object in an automatic test vector generation algorithm based on the logically blockable key bits;

[0034] S3. Find the logic cone with the least key bits in the logic cone set;

[0035] S4. Traverse the key bit set in the current logic cone to find the key bit with the most X-state filled objects, generate a first test vector for this key bit based on an automatic test vector generation algorithm, input the first test vector into the logic-locked encryption circuit to obtain an ideal response, assume a stuck-at fault exists for this key bit, regenerate a second test vector based on the automatic test vector generation algorithm, input the second test vector into the logic-locked encryption circuit to obtain an actual response, and delete this key bit from the key bit set.

[0036] S5. Compare the actual response with the ideal response to obtain an inferred value of the key bit; take the key bit whose inferred value is the same as the correct value of the key bit as the inferred key bit, and repeat steps S4 to S5 until the key bit set is empty;

[0037] S6, deleting the current logic cone from the logic cone set, and repeating steps S3 to S6 until the logic cone set is empty;

[0038] S7. Calculate the proportion of the inferable key bits in the key bits, and compare it with a preset threshold to obtain a security assessment result.

[0039] This embodiment improves the efficiency of key analysis by classifying key bits into logically blockable and non-logically blockable key bits. The X-state filling strategy of the subsequent test vector generation algorithm is optimized, implementing a key-nullification ATPG algorithm (KN-ATPG). By logically blocking logically blockable key bits, the proportion of uncertain bits in the circuit is reduced, thereby reducing the number of test vectors and generation time, improving the efficiency of the overall test process. Subsequently, the ideal response of any key is compared with the actual response obtained by a pseudo-fault, implementing a pseudo-fault sensitization attack (PFSA). This allows the inferability of each key bit to be determined, weak key bits to be identified, and the security of each key bit to be accurately assessed. Finally, by calculating the ratio of the number of inferable key bits to the total number of key bits, the security of the logic-locked encryption circuit can be objectively quantified, and the circuit's protection can be targeted. Furthermore, the significantly reduced fault injection requirements reduce physical damage to the device.

[0040] As an exemplary illustration, a graph analysis is performed on the logic lock encryption circuit to obtain the logic gates and key bits in the logic lock encryption circuit.

[0041] In an optional embodiment, the step of dividing the key bits into logically blockable key bits and logically non-blockable key bits includes:

[0042] Searching for a logic gate directly connected to an output node of the logic lock encryption circuit in the output path of any key bit as the final logic gate, and taking the node connected to the output path of the current key bit and the final logic gate as the key bit node, and the remaining input nodes of the final logic gate as blocking enable nodes;

[0043] Determine the original input with the blocking enable node as the cone top of the logic cone;

[0044] If the original input does not contain other key bits, then the key bit is a logically blockable key bit; otherwise, it is a non-logically blockable key bit.

[0045] In this embodiment, by combining the logical properties of the key bits with the circuit structure, by determining the blocking enable node and its original input, and searching for other key bits in the original input to determine whether it is a logically blockable key bit, this hierarchical analysis method makes the classification of key bits more detailed and accurate, and improves the reliability of subsequent analysis and testing.

[0046] In an optional embodiment, the step of obtaining a set of X-state fill objects in an automatic test vector generation algorithm based on the logically blockable key bits includes:

[0047] For any key bit node in the final logic gate that can logically block the key bit, the original input is determined as the cone top of the logic cone, and the original input is used as an X-state filling object in the automatic test vector generation algorithm.

[0048] In this embodiment, the original input in the same final logic gate as the key bit is also used as an X-state filling object, which expands the scope of X filling and reduces the number of subsequent fault injections.

[0049] In an optional embodiment, the stuck-at fault includes a set-0 fault and a set-1 fault.

[0050] In this embodiment, a fault is injected into the current key bit by setting a fault to 0 or setting a fault to 1 before generating the second test vector. This allows targeted detection of response changes caused by the fault during the generation of the second test vector.

[0051] In an optional embodiment, the step of inputting the first test vector into the logic lock encryption circuit to obtain an ideal response includes:

[0052] Forcibly constraining the key bits in the first test vector that cannot be logically blocked by changing the value of the key bits; logically blocking the key bits of the X state fill bits; and then inputting the first test vector into the logic lock encryption circuit to obtain an ideal response;

[0053] The step of inputting the second test vector into the logic lock encryption circuit to obtain an actual response comprises:

[0054] The key bits in the second test vector that cannot be logically blocked are forced to be constrained by changing the value of the key bits; the key bits of the X state filling bits are logically blocked; and the second test vector is input into the logic locking encryption circuit to obtain an ideal response.

[0055] As an exemplary embodiment, the step of enforcing the constraint includes changing the value of the key bits using laser injection.

[0056] In this embodiment, by enforcing constraints on key bits that cannot be logically blocked, the test vectors accurately reflect the circuit's true logical state, eliminating unnecessary variable interference and improving the validity of the test results. By logically blocking the X-state fill bits, the uncertainty of the input state is reduced, lowering computational complexity. Furthermore, laser injection is a high-precision operation that ensures precise manipulation of the key bit values ​​during testing, thus avoiding errors caused by randomness or uncontrollable factors and improving test accuracy and reliability.

[0057] In an optional embodiment, the step of logically blocking includes:

[0058] According to the type of the second logic gate, the original input of the blocking enable node is changed.

[0059] Further optionally, the step of changing the original input of the blocking enable node according to the type of the second logic gate includes:

[0060] If the second logic gate is an AND gate, adjusting the original input to set the blocking enable node value to 0;

[0061] If the second logic gate is an OR gate, adjusting the original input to set the blocking enable node value to 1;

[0062] If the second logic gate is a NAND gate, adjusting the original input to set the blocking enable node value to 0;

[0063] If the second logic gate is a NOR gate, the original input is adjusted to set the blocking enable node value to 1.

[0064] Specifically, if Figure 2 As shown in the figure, it is the logic blocking principle diagram of the AND gate, where Key represents the key bit, x2 and x3 are the original inputs of the blocking enable node, and the inputs of x2 and x3 are constrained to 0, so that the blocking enable node value is 0, the output of the G3 logic gate is 0, and the key bit is logically blocked.

[0065] like Figure 3 As shown in the figure, it is the logic blocking principle diagram of the OR gate, where Key represents the key bit, x2 and x3 are the original inputs of the blocking enable node, and the inputs of x2 and x3 are constrained to 1, so that the blocking enable node value is 1, the output of the G3 logic gate is 1, and the key bit is logically blocked.

[0066] like Figure 4 As shown in the figure, it is the logic blocking principle diagram of the NAND gate, where Key represents the key bit, x2 and x3 are the original inputs of the blocking enable node, and the inputs of x2 and x3 are constrained to 0, so that the blocking enable node value is 0, the output of the G3 logic gate is 1, and the key bit is logically blocked.

[0067] like Figure 5 As shown in the figure, it is the logic blocking principle diagram of the AND gate, where Key represents the key bit, x2 and x3 are the original inputs of the blocking enable node, and the inputs of x2 and x3 are constrained to 0, so that the blocking enable node value is 0, the output of the G3 logic gate is 1, and the key bit is logically blocked.

[0068] In this embodiment, a logic blocking method is used to make the input of key bits invalid in the subsequent automatic test vector generation test process, thereby simplifying the complexity of security testing, reducing dependence on key bits, and improving test efficiency.

[0069] In an optional embodiment, the step of comparing the actual response with the ideal response to obtain the inferred value of the key bit includes: if the actual response is different from the ideal response, then using the value of the stuck-at fault as the inferred value of the key bit; otherwise, using the complementary value of the value of the stuck-at fault as the inferred value of the key bit.

[0070] In this embodiment, the actual response is compared with the ideal response. If there is a difference between the actual response and the ideal response, indicating that the hypothetical stuck-at fault has been successfully transmitted, the fault value is used as the inferred value for that key bit. Otherwise, indicating that the hypothetical stuck-at fault has not been successfully transmitted, the complementary value of the fault value is used as the inferred value for that key bit. Inferring the key directly based on the actual response changes caused by the fault can more quickly infer key information, reducing the time and resources required.

[0071] In an optional embodiment, the step of calculating the proportion of inferable key bits in the key bits and comparing it with a preset threshold to obtain a security assessment result includes: if the proportion of inferable key bits in the key bits is greater than the preset threshold, then the security assessment result of the logic-locked encryption circuit is determined to be high risk; otherwise, the security assessment result of the logic-locked encryption circuit is determined to be low risk.

[0072] In this embodiment, setting a threshold provides a quantitative standard for security assessment, making the assessment process more objective and standardized. In addition, by inferring the key bits, the encryption algorithm can be optimized or adjusted for these specific key bits.

[0073] Example 2

[0074] This embodiment proposes a security assessment system for a logic-locked encryption circuit, and applies a security assessment method for a logic-locked encryption circuit proposed in Example 1. Figure 6 FIG. 1 is an architecture diagram of a security assessment system for a logic-locked encryption circuit according to an embodiment of the present invention.

[0075] This embodiment provides a security assessment system for a logic-locked encryption circuit, including:

[0076] Key bit division module: used to extract key bits and logic gates in the logic lock encryption circuit; divide the key bits into logically blockable key bits and non-logically blockable key bits;

[0077] The automatic test vector generation test module uses the logically blockable key bit as an X-state fill object in the automatic test vector generation algorithm; generates a first test vector for any key bit based on the automatic test vector generation algorithm, and inputs the first test vector into the logic-locked encryption circuit to obtain an ideal response; embeds a stuck-at fault in the current key bit, regenerates a second test vector based on the automatic test vector generation algorithm, and inputs the second test vector into the logic-locked encryption circuit to obtain an actual response;

[0078] Key bit inference module: compares the actual response with the ideal response to obtain an inferred value for any key bit, and makes a judgment based on the inferred value and the true value of the key bit. If the comparison results are the same, the key bit is considered to be an inferred key. Otherwise, the next key bit is judged until all key bits are traversed;

[0079] Logic lock encryption circuit security assessment module: calculates the proportion of inferable key bits in the key bits and compares it with a preset threshold to obtain a security assessment result.

[0080] It can be understood that the system of this embodiment corresponds to the method of the above-mentioned embodiment 1, and the options in the above-mentioned embodiment 1 are also applicable to this embodiment, so they will not be described again here.

[0081] The terms used in the drawings are for illustrative purposes only and should not be construed as limiting this patent;

[0082] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A security assessment method for a logic-locked encryption circuit, characterized in that: The following steps are involved: S1, extracting key bits and logic gates in the logic-locked encryption circuit; dividing the logic cone based on the output nodes in the logic-locked encryption circuit to obtain a logic cone set; S2. Dividing the key bits into logically blockable key bits and non-logically blockable key bits; obtaining an X-state filling object in an automatic test vector generation algorithm based on the logically blockable key bits; S3. Find the logic cone with the least key bits in the logic cone set; S4. Traverse the key bit set in the current logic cone to find the key bit with the most X-state filled objects, generate a first test vector for this key bit based on an automatic test vector generation algorithm, input the first test vector into the logic-locked encryption circuit to obtain an ideal response, embed an assumption that a stuck-at fault exists in this key bit, regenerate a second test vector based on the automatic test vector generation algorithm, input the second test vector into the logic-locked encryption circuit to obtain an actual response, and delete this key bit from the key bit set. S5. Compare the actual response with the ideal response to obtain an inferred value of the key bit; take the key bit whose inferred value is the same as the correct value of the key bit as the inferred key bit, and repeat steps S4 to S5 until the key bit set is empty; S6, deleting the current logic cone from the logic cone set, and repeating steps S3 to S6 until the logic cone set is empty; S7. Calculate the proportion of the inferable key bits in the key bits, and compare it with a preset threshold to obtain a security assessment result.

2. The security assessment method for a logic-locked encryption circuit according to claim 1, wherein: The step of dividing the key bits into logically blockable key bits and non-logically blockable key bits comprises: Searching for a logic gate directly connected to an output node of the logic lock encryption circuit in the output path of any key bit as the final logic gate, and taking the node connected to the output path of the current key bit and the final logic gate as the key bit node, and the remaining input nodes of the final logic gate as blocking enable nodes; Determine the original input with the blocking enable node as the cone top of the logic cone; If the original input does not contain other key bits, then the key bit is a logically blockable key bit; otherwise, it is a non-logically blockable key bit.

3. The security assessment method for a logic-locked encryption circuit according to claim 2, wherein: The step of obtaining an X-state filling object set in an automatic test vector generation algorithm based on the logically blockable key bit comprises: For any key bit node in the final logic gate that can logically block the key bit, the original input is determined as the cone top of the logic cone, and the original input is used as an X-state filling object in the automatic test vector generation algorithm.

4. The security assessment method for a logic-locked encryption circuit according to claim 1, wherein: The stuck-at fault includes a set-0 fault and a set-1 fault.

5. The security assessment method for a logic-locked encryption circuit according to claim 1, wherein: The step of inputting the first test vector into the logic lock encryption circuit to obtain an ideal response includes: Forcibly constraining the key bits in the first test vector that cannot be logically blocked by changing the value of the key bits; logically blocking the key bits of the X state fill bits; and then inputting the first test vector into the logic lock encryption circuit to obtain an ideal response; The step of inputting the second test vector into the logic lock encryption circuit to obtain an actual response comprises: The key bits in the second test vector that cannot be logically blocked are forced to be constrained by changing the value of the key bits; the key bits of the X state filling bits are logically blocked; and the second test vector is input into the logic locking encryption circuit to obtain an ideal response.

6. The security assessment method for a logic-locked encryption circuit according to claim 5, characterized in that: The steps of logic blocking include: According to the type of the second logic gate, the original input of the blocking enable node is changed.

7. The security assessment method for a logic-locked encryption circuit according to claim 6, wherein: The step of changing the original input of the blocking enable node according to the type of the second logic gate includes: If the second logic gate is an AND gate, adjusting the original input to set the blocking enable node value to 0; If the second logic gate is an OR gate, adjusting the original input to set the blocking enable node value to 1; If the second logic gate is a NAND gate, adjusting the original input to set the blocking enable node value to 0; If the second logic gate is a NOR gate, the original input is adjusted to set the blocking enable node value to 1.

8. The security assessment method for a logic-locked encryption circuit according to claim 1, wherein: The step of comparing the actual response with the ideal response to obtain the inferred value of the key bit includes: if the actual response is different from the ideal response, then using the value of the stuck-at fault as the inferred value of the key bit; otherwise, using the complementary value of the value of the stuck-at fault as the inferred value of the key bit.

9. The security assessment method for a logic-locked encryption circuit according to claim 1, wherein: The step of calculating the proportion of the inferable key bits in the key bits and comparing it with a preset threshold to obtain a security assessment result includes: if the proportion of the inferable key bits in the key bits is greater than the preset threshold, then the security assessment result of the logic-locked encryption circuit is determined to be high risk; otherwise, the security assessment result of the logic-locked encryption circuit is determined to be low risk.

10. A security assessment system for a logic-locked encryption circuit, applied to the security assessment method for a logic-locked encryption circuit according to any one of claims 1 to 9, characterized in that: The system comprises: Key bit division module: used to extract key bits and logic gates in the logic lock encryption circuit; divide the key bits into logically blockable key bits and non-logically blockable key bits; The automatic test vector generation test module uses the logically blockable key bit as an X-state fill object in the automatic test vector generation algorithm; generates a first test vector for any key bit based on the automatic test vector generation algorithm, and inputs the first test vector into the logic-locked encryption circuit to obtain an ideal response; embeds a stuck-at fault in the current key bit, regenerates a second test vector based on the automatic test vector generation algorithm, and inputs the second test vector into the logic-locked encryption circuit to obtain an actual response; Key bit inference module: compares the actual response with the ideal response to obtain an inferred value of any key bit, and makes a judgment based on the inferred value and the true value of the key bit. If the comparison result is the same, the key bit is considered to be an inferred key bit. Otherwise, the next key bit is judged until all key bits are traversed; Logic lock encryption circuit security assessment module: calculates the proportion of inferable key bits in the key bits and compares it with a preset threshold to obtain a security assessment result.

Images