System for integrated circuit design, semiconductor packaging method and computer program product

Abstract

An integrated circuit design implementation system, a method of semiconductor package and a computer program product are provided. The integrated circuit design implementation system includes a die-to-die (D2D) compiler to receive a configuration of the semiconductor package. The semiconductor package includes a first semiconductor die and a second semiconductor die bonded to each other. The D2D compiler is configured to generate a first bump map and a second bump map for the first semiconductor die and the second semiconductor die, respectively, based on a configuration of the semiconductor package. The first bump map indicates individual locations of a plurality of first bump structures in the first semiconductor die, and the second bump map indicates individual locations of a plurality of second bump structures in the second semiconductor die.

Description

Technical Field

[0001] An embodiment of the present disclosure is directed to an integrated circuit design implementation system, and more particularly to an integrated circuit design implementation system using a die-to-die compiler. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density comes from the continuous reduction of the minimum feature size (e.g., the shrinking of semiconductor process nodes towards sub-nanometer nodes), which allows more components to be integrated into a given area. With the recent growing demand for miniaturization, higher speed, greater bandwidth, and lower power consumption and latency, the demand for advanced packaging technology for semiconductor die is also growing. Summary of the invention

[0003] In some embodiments, an integrated circuit design implementation system is provided, which includes a die-to-die compiler. The die-to-die compiler is used to: receive a configuration of a semiconductor package, the semiconductor package at least including a first semiconductor die and a second semiconductor die bonded to each other; and based on the configuration of the semiconductor package, generate a first bump map and a second bump map for the first semiconductor die and the second semiconductor die, respectively. The first bump map indicates the individual positions of a plurality of first bump structures in the first semiconductor die, and the second bump map indicates the individual positions of a plurality of second bump structures in the second semiconductor die. In the first bump map, a first subset of some first bump structures configured to transmit a plurality of signals to the second semiconductor die and a second subset of some first bump structures configured to receive a plurality of signals from the second semiconductor die are arranged symmetrically with respect to an X-axis or a Y-axis of the first bump map. In the second bump mapping, a first subset of second bump structures configured to transmit multiple signals to the first semiconductor die and a second subset of second bump structures configured to receive multiple signals from the first semiconductor die are arranged symmetrically with respect to an X-axis or a Y-axis of the second bump mapping.

[0004] In some embodiments, a method for simulating a semiconductor package is provided, comprising the following steps: receiving a configuration of a semiconductor package, the semiconductor package comprising at least a first semiconductor die and a second semiconductor die bonded to each other; and generating a first bump map and a second bump map for the first semiconductor die and the second semiconductor die, respectively, based on the configuration of the semiconductor package; the first bump map indicates individual positions of a plurality of first bump structures in the first semiconductor die, and the second bump map indicates individual positions of a plurality of second bump structures in the second semiconductor die. In the first bump map, a first subset of the first bump structures configured to transmit a plurality of signals to the second semiconductor die and a second subset of the first bump structures configured to receive a plurality of signals from the second semiconductor die are symmetrically arranged relative to an X-axis or a Y-axis of the first bump map. In the second bump map, a first subset of the second bump structures configured to transmit a plurality of signals to the first semiconductor die and a second subset of the second bump structures configured to receive a plurality of signals from the first semiconductor die are symmetrically arranged relative to an X-axis or a Y-axis of the second bump map.

[0005] In some embodiments, a computer program product is provided, comprising a computer-readable medium program code stored thereon, wherein the computer-readable medium program code, when executed by a processor, causes the processor to implement a method, the method comprising the following steps: receiving a configuration of a semiconductor package, the semiconductor package at least comprising a first semiconductor die and a second semiconductor die bonded to each other, wherein the first semiconductor die and the second semiconductor die are bonded so that the first semiconductor die and the second semiconductor die are arranged side by side or vertically stacked with each other; and based on the configuration of the semiconductor package, generating a first bump map and a second bump map for the first semiconductor die and the second semiconductor die, respectively; wherein the first bump map indicates a plurality of first bumps in the first semiconductor die. The individual positions of the block structures, the second bump mapping indicates the individual positions of the plurality of second bump structures in the second semiconductor die; in the first bump mapping, a first subset of these first bump structures configured to transmit a plurality of signals to the second semiconductor die and a second subset of these first bump structures configured to receive a plurality of signals from the second semiconductor die are symmetrically arranged with respect to an X-axis or a Y-axis of the first bump mapping; and in the second bump mapping, a first subset of these second bump structures configured to transmit a plurality of signals to the first semiconductor die and a second subset of these second bump structures configured to receive a plurality of signals from the first semiconductor die are symmetrically arranged with respect to an X-axis or a Y-axis of the second bump mapping. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] An aspect of an embodiment of the present disclosure is in accordance with the accompanying Figure 1The following detailed description is best understood when read together. It should be noted that, in accordance with the standard specification in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 illustrates a block diagram of a processing system according to various embodiments of the present disclosure;

[0008] Figure 2 illustrates a flow of an example method used by electronic design automation (EDA) according to some embodiments;

[0009] Figure 3 illustrates a flow of an example method used by an EDA according to some embodiments;

[0010] Figure 4 illustrates a flow of an example method used by an EDA according to some embodiments;

[0011] Figure 5 FIG. 1 shows a method for performing a multi-step process according to some embodiments. Figures 2 to 4 The method shown in is based on the configuration of the semiconductor package to generate an example bump map;

[0012] Figure 6 illustrates an example configuration of a semiconductor die of a semiconductor package for which a bump map is generated according to some embodiments;

[0013] Figure 7 illustrates an example configuration of a semiconductor die and corresponding bump mapping of a semiconductor package according to some embodiments;

[0014] Figure 8 illustrates an example configuration of a semiconductor die and corresponding bump mapping of a semiconductor package according to some embodiments;

[0015] Fig. 9 illustrates a flow of an example method for configuring bump mapping according to some embodiments;

[0016] Fig.10 illustrates example operations for configuring bump mapping according to some embodiments;

[0017] Fig.11 illustrates example operations for configuring bump mapping according to some embodiments;

[0018] Fig.12 illustrates example operations for configuring bump mapping according to some embodiments;

[0019] Fig.13 illustrates example operations for configuring bump mapping according to some embodiments;

[0020] Fig.14 illustrates example operations for configuring bump mapping according to some embodiments;

[0021] Fig.15 illustrates an example bump map and corresponding bit map according to some embodiments;

[0022] Fig.16 Illustrated are example operations for designing a solid bump map in accordance with some embodiments.

[0023]

Explanation of symbols

[0024] 100: Processing system

[0025] 110: Processing Tools

[0026] 112: Input / output device

[0027] 114: Display

[0028] 116:LAN / WAN

[0029] 120:CPU

[0030] 122: Memory

[0031] 124:Mass storage device

[0032] 126: Video Adapter

[0033] 128: I / O interface

[0034] 130: Bus

[0035] 140: Network interface

[0036] 200: Method

[0037] 201: Behavioral / functional design

[0038] 203: Connection information

[0039] 210:Synthesis Tools

[0040] 211: Second network connection table

[0041] 220: Placement and Routing Tools

[0042] 230: Verification Tools

[0043] 240: Manufacturing Tools

[0044] 300: Methods

[0045] 310: Configuration

[0046] 320:D2D Compiler

[0047] 330: Recipe

[0048] 340: Bump Mapping

[0049] 345: Bump structure

[0050] 400: Method

[0051] 410:RTL description

[0052] 415: Synthesis

[0053] 420:DFT Insertion

[0054] 425: Gate level network connection table

[0055] 430: Bump Map Description

[0056] 435: Floor plan

[0057] 440:Key instance preset script

[0058] 445: Placement

[0059] 450:CTS Formula

[0060] 455:CTS

[0061] 460: Routing

[0062] 500: Bump Mapping

[0063] 505: Legend

[0064] 510:TX / RX

[0065] 520:TX / RX RP

[0066] 530:VDD / VSS

[0067] 540:WE / RVALID D2D

[0068] 550:TX / RX DFT

[0069] 560: Fake

[0070] 570:TX / RX D2D clk

[0071] 580:TX / RX D2D reset

[0072] 590:Connect

[0073] 592: District 1

[0074] 594: District 2

[0075] 596: District 3

[0076] 598: District 4

[0077] 610~660: Configuration

[0078] 710-1~710-2: Bump Mapping

[0079] 740-1~740-2: Bump Mapping

[0080] 820-1~820-2: Bump Mapping

[0081] 830-1~830-2: Bump Mapping

[0082] 850-1~850-2: Bump Mapping

[0083] 860-1~860-2: Bump Mapping

[0084] 900: Method

[0085] 910: Configuration

[0086] 920:D2D Compiler

[0087] 930: Recipe

[0088] 940: Initial bump mapping

[0089] 950: Extended Bump Mapping

[0090] 960: Extension

[0091] 1000:Instance operation

[0092] 1010: Operation

[0093] 1012:TX structure

[0094] 1014: RX structure

[0095] 1020: Operation

[0096] 1022: Repair Chain

[0097] 1030~1040: Operation

[0098] 1100:Instance operation

[0099] 1110~1130: Operation

[0100] 1200:Instance operation

[0101] 1210~1220: Operation

[0102] 1300:Instance operation

[0103] 1310: Bidirectional LITEIO

[0104] 1310R:RX LIO

[0105] 1310T:TX LIO

[0106] 1320:TX FF

[0107] 1330:TX bump structure

[0108] 1340:RX FF

[0109] 1350: RX bump structure

[0110] 1400: Operation

[0111] 1410: Bidirectional LITEIO

[0112] 1410R:RX LIO

[0113] 1410T:TX LIO

[0114] 1420: RX reverse FF

[0115] 1430:TX bump structure

[0116] 1440:Tx reverse FF

[0117] 1450: RX bump structure

[0118] 1510: Bump Mapping

[0119] 1520: Bitmap

[0120] 1530A: Sorting of bump structures

[0121] 1530B: Bit Order

[0122] 1600:Instance operation

[0123] 1610: Bump Mapping

[0124] 1620:TSV related components

[0125] 1630:DCDL

[0126] 1640: Border

[0127] 1650: Duty Cycle Corrector DETAILED DESCRIPTION

[0128] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify an embodiment of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0129] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," "top," "bottom," and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature(s). The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0130] Modern semiconductor devices may be formed as semiconductor packages including a plurality of semiconductor dies (e.g., semiconductor chips, integrated circuit (IC) chips, etc.) operatively and physically coupled to each other. A plurality of IC dies / chips are integrated into a single semiconductor package using various techniques. Examples of semiconductor packages include chip on wafer on substrate (CoWoS) packaging, integrated fan-out (InFo) packaging, three-dimensional integrated circuit (3D IC) packaging, or the like. In a semiconductor package, different IC dies / chips (e.g., having logic functionality) are typically coupled to each other via one or more connection structures (e.g., without logic functionality). In existing techniques, simulation and / or verification of such semiconductor packages typically requires a large amount of manpower. For example, after separately synthesizing lower-level circuit descriptions for different IC dies / chips, the connection structures are manually configured (e.g., inserted therein) with respect to the physical configuration and operational connection of the IC dies / chips for the synthesized lower-level circuit descriptions. This manual work disadvantageously complicates the design and corresponding verification of semiconductor packages. Therefore, existing techniques for designing semiconductor packages are not entirely satisfactory in some aspects.

[0131] One embodiment of the present disclosure provides various embodiments of an integrated circuit design implementation system and an operation method thereof that can automatically generate a design recipe based on a semiconductor package. For example, the system can generate a design recipe (e.g., register-transfer level (RTL) mapping, physical design (PD) mapping, die-to-die (D2D) bump mapping) in a configurable manner by, for example, placing a multi-stack compatible bump structure of a 3D IC (e.g., a small outline integrated circuit (SoIC), InFO, 3DInFO, etc.), a preset clock structure script, etc. The integrated circuit design implementation system described herein may include a D2D compiler. The D2D compiler may receive a configuration of a semiconductor package, the semiconductor package at least including a first semiconductor die and a second semiconductor die bonded to each other. The D2D compiler may generate a first bump mapping and a second bump mapping for the first semiconductor die and the second semiconductor die respectively based on the configuration of the semiconductor package. The first bump mapping may indicate individual positions of a plurality of first bump structures in the first semiconductor die, and the second bump mapping may indicate individual positions of a plurality of second bump structures in the second semiconductor die. In the first bump mapping, a first subset of first bump structures configured for transmitting signals to the second semiconductor die and a second subset of first bump structures configured for receiving signals from the second semiconductor die are symmetrically arranged with respect to an X-axis or a Y-axis of the first bump mapping. In the second bump mapping, a first subset of second bump structures configured for transmitting signals to the first semiconductor die and a second subset of second bump structures configured for receiving signals from the first semiconductor die are symmetrically arranged with respect to an X-axis or a Y-axis of the second bump mapping.

[0132] As disclosed herein, a system can automatically generate RTL descriptions, bump mapping, physical design layout, etc. by automatically generating recipes for D2D blocks based on different design specifications / configurations (e.g., bump pitch, array size, etc.). This facilitates the design flow of 3D IC D2D interface blocks, thereby significantly helping to reduce the time and effort of designing semiconductor packages. As disclosed herein, a system can generate front-end (FE) RTL and back-end (BE) design recipes, for example, 2.5D compatible bump mapping, 3D (front-to-front or face-to-face, F2F) / front-to-back (F2B)) compatible bump mapping, etc., as one of the system outputs supporting multi-stack designs. Such bump mapping can support 3D IC multi-stack partitioning (F2F, F2B, etc.) in a configurable / compatible manner. This provides design flexibility, allowing configurability and multi-stack compatibility.

[0133] Figure 1 A block diagram of a processing system 100 is shown in accordance with various embodiments of the present disclosure. The processing system 100 may be used to implement any or all of the processes, steps, or operations discussed herein. The processing system 100 may include a processing tool 110, such as a desktop computer, a workstation, a laptop computer, or a dedicated unit customized for a particular application. The processing system 100 may be equipped with a display 114 and one or more input / output devices 112, such as a mouse, a keyboard, or a printer. The processing tool 110 may include a central processing unit (CPU) 120, a memory 122, a mass storage device 124, a video adapter 126, and an I / O interface 128 connected to a bus 130.

[0134] Bus 130 may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or a video bus. CPU 120 may include any type of electronic data processor, and memory 122 may include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).

[0135] Mass storage device 124 may include any type of storage device for storing data, programs, and other information and making the data, programs, and other information accessible via bus 130. Mass storage device 124 may include, for example, one or more of a hard drive, a magnetic disk drive, an optical disk drive, or the like.

[0136] Video adapter 126 and I / O interface 128 provide interfaces for coupling external input and output devices to processing tool 110. Figure 1 As shown in , examples of input and output devices include a display 114 coupled to a video adapter 126 and an I / O device 112 coupled to an I / O interface 128, such as a mouse, keyboard, printer, and the like. Other devices may be coupled to the processing tool 110, and additional or fewer interface cards may be utilized. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The processing tool 110 may also include a network interface 140, which may be a wired link and / or a wireless link to a local area network (LAN) or a wide area network (WAN) 116.

[0137] It should be noted that the processing system 100 may include other components. For example, the processing system 100 may include a power supply, cables, a motherboard, a removable storage medium, a housing, and the like. Although these other components are not shown, they may be considered part of the processing system 100.

[0138] In various embodiments of the present disclosure, electronic design automation (EDA) is a program code executed by CPU 120 for automatically generating a network connection table based on the design of a semiconductor package (hereinafter referred to as Figure 2 130 ). In addition, during the execution of the EDA, the EDA may provide various analyses and / or verifications of the semiconductor package based on the layout of the automatically generated netlist. The program code may be accessed by the CPU 120 from the memory 122 , the mass storage device 124 , or the like via the bus 130 , or remotely accessed via the network interface 140 .

[0139] Figure 2The flowchart of an example method 200 of an EDA disclosed in the present disclosure for automatically generating or updating a netlist based on a design of a semiconductor package and a user-supplied / specified behavior / function design 201 and connection information 203 is shown. In various embodiments of the present disclosure, a semiconductor package includes a plurality of IC chips (hereinafter referred to as "logic chips") and a plurality of connection structures ("non-logic structures"). Specifically, the logic chips may each present one or more logic and / or analog functions, and the non-logic structures may each provide one or more electrical connection functions for the corresponding ones in the logic chips.

[0140] For example, the behavioral / functional design 201 may specify the desired behavior or function of the logic chip based on various signals or stimuli applied to the input of the overall design, and may be written in a suitable language, such as a hardware description language (HDL). The behavioral / functional design 201 may be uploaded to the processing tool 110 (see FIG. 1 ) via the I / O interface 128. Figure 1 ), such as by a user creating a file when executing the EDA. Alternatively, the behavior / function design 201 may be uploaded and / or stored in the memory 122 or mass storage device 124, or the behavior / function design 201 may be downloaded from a remote user via the network interface 140 (see Figure 1 ) upload. In these cases, CPU 120 will access behavioral / functional design 201 during execution of EDA.

[0141] According to various embodiments of the present disclosure, the connection information 203 may specify the physical configuration and connections in the logic chips and non-logic structures. For example, the connection information 203 may include how the logic chips are physically configured with each other, such as side by side, stacked, or a combination thereof. In another example, the connection information 203 may include how different ones of the logic chips are electrically coupled to each other. Based on the technology used to form the semiconductor package, the non-logic structure may include any of a variety of structures that can provide electrical connection functions and / or mechanical support. Examples of non-logic structures include a physical substrate (e.g., a printed circuit board (PCB), a chip scale package (CSP) substrate), a physical redistribution layer (RDL), and a physical interposer (e.g., a silicon interposer, an organic interposer, etc.). Similar to the behavioral / functional design 201, the connection information 203 may be uploaded to the processing tool 110 via the I / O interface 128 (see Figure 1), such as by a user creating a file when executing the EDA. Alternatively, the connection information 203 may be uploaded and / or stored in the memory 122 or mass storage device 124, or the behavior / function design 201 may be downloaded from a remote user via the network interface 140 (see Figure 1 ) upload. In these cases, CPU 120 will access connection information 203 during execution of EDA.

[0142] The EDA may obtain the behavioral / functional design 201 and the connection information 203, and perform synthesis, for example, through a synthesis tool 210, to generate a netlist, for example, 211. In a brief overview, the synthesis tool 210 may first form a plurality of functionally equivalent logic gate level circuit descriptions (hereinafter referred to as "first netlists") corresponding to logic chips, respectively, based on the behavioral / functional design 201. It should be noted that such first netlists may each represent a gate level description corresponding to a separate logic chip. Next, the synthesis tool 210 may convert the first netlist into a netlist 211 (hereinafter referred to as "second netlist") based on the connection information 203, which includes how the logic chips are physically configured and operationally communicate with each other via non-logical structures. The synthesis tool 210 may generate the second netlist based on a graph, the graph including a plurality of vertices connected to each other via counterparts in edges, which will be discussed below.

[0143] According to various embodiments of the present disclosure, while generating a first network connection table (for a logic chip), the synthesis tool 210 may convert the logic chip into a plurality of first vertices respectively. Next, upon receiving the connection information 203 (specifying a non-logical structure), the synthesis tool 210 may convert the non-logical structure into a plurality of second vertices respectively. For example, the synthesis tool 210 may configure the second vertex and the first vertex according to the physical configuration specified in the connection information 203. Next, the synthesis tool 210 may generate a plurality of third vertices, each of which corresponds to a virtual interface between any two of the logic chip and the non-logical structure. Next, the synthesis tool 210 may connect two of the first vertex, the second vertex, and / or the third vertex via a plurality of edges. For example, the synthesis tool 210 may generate or otherwise configure such edges according to the connection (in the logic chip and the non-logical structure) specified in the connection information 203. As a result, a graph consisting of a first vertex, a second vertex, a third vertex, and an edge may be formed. The synthesis tool 210 may determine this graph that uniquely corresponds to the semiconductor package. As a result, the synthesis tool 210 may automatically transform the first netlist into the second netlist 211 .

[0144] In some embodiments, the synthesis tool 210 may provide the second net connection table 211 to the placement and routing tool 220. Based on the second net connection table 211, the placement and routing tool 220 may establish an actual physical design for the overall structure (e.g., a semiconductor package) and / or a bump map for the semiconductor die of the semiconductor package. The placement and routing tool 220 may form a physical design by acquiring selected cells from a cell library and placing them into cell rows to establish the bump map. These cell rows generally have a row height similar to the height of most individual cells located in the cell row, so that power rails, implants, and wells can be aligned between individual cells. The placement of each individual cell within the cell row and the placement of each cell row relative to other cell rows can be guided by a cost function to minimize the wiring length and area requirements of the resulting integrated circuit. This placement can be performed automatically by the placement and routing tool 220, or it can also be partially performed through a manual process, whereby a user can manually insert one or more cells into a row.

[0145] Once the placement and routing tool 220 has completed generating the actual physical design of the overall structure, the verification tool 230 may provide physical verification of the semiconductor package. Physical verification generally includes timing verification, design rule check (DRC), layout versus schematic (LVS) analysis, and electrical rule check (ERC). Once physical verification is completed with satisfactory results, the design of the semiconductor package may be sent to the manufacturing tool 240 to generate, for example, a photolithography mask that may be used for physical fabrication of the desired design. The design may be transmitted to the manufacturing tool 240 via the LAN / WAN 116 ( Figure 1 ) or other suitable transmission form from the EDA to the manufacturing tool 240 is sent to the manufacturing tool 240.

[0146] Figure 3 The flow of an example method 300 for automatically generating a bump map 340 of a semiconductor package based on a configuration 310 (e.g., a user-supplied / specified behavior / functional design 201 and connection information 203, etc.) by an EDA according to some embodiments of the present disclosure is illustrated. The configuration 310 includes information or a specification file for designing an overall structure of a semiconductor package and / or a bump map for a semiconductor die in the semiconductor package. In some examples, the configuration 310 may include various information of the semiconductor die, including but not limited to the number of data bits, the size of the bump matrix, the repair data ratio, the dynamic bus inversion (DBI) data ratio, the power ground (PG) ratio, etc.

[0147] Configuration 310 may be uploaded to processing tool 110 via I / O interface 128 (see Figure 1 ), such as by a user creating a file when executing EDA. In response to uploading (or receiving) configuration 310, processing tool 110 and / or a die-to-die (D2D) compiler 320 located thereon may generate recipe 330. D2D compiler may be operably coupled to synthesis tool 210 and placement and routing tool 220 to generate recipe 330. Based on recipe 330, processing tool 110 and / or D2D compiler 320 may generate register-transfer level (RTL) mapping, physical design (PD) mapping, D2D bump mapping, etc. Bump mapping 340 is shown as a non-limiting example of a bump mapping that may be generated by the D2D compiler.

[0148] As shown in the bump map 340, cells are selected to form different subsets of bump structures 345, each of which may have different functions (e.g., transmitting signals, receiving signals, etc.). Bump structures 345 filled with different patterns indicate bump structures with different functions. Although briefly described herein as examples, different bump maps and structures will be described in more detail below.

[0149] Figure 4 The flowchart of an example method 400 for using an EDA to automatically design a recipe (eg, recipe 330 ) based on a configuration 310 (eg, user-supplied / specified behavior / functional design 201 and connection information 203 , etc.) according to some embodiments of the present disclosure is illustrated.

[0150] Configuration 310 may include various information of the semiconductor die, including but not limited to data bit ratio, number of data bits, size of bump matrix, repair data ratio, dynamic bus inversion (DBI) data ratio, power ground (PG) ratio, etc. Non-limiting examples of configuration 310 may include a data bit ratio of 32, a DBI data ratio of 1 / 8, and a repair data ratio of 1 / 32, etc.

[0151] The D2D compiler 320 may receive the configuration 310 and perform synthesis 415 based on the configuration 310 (e.g., by the synthesis tool 210). The configuration 310 may include a library package file (e.g., library exchange format (LEF), gds (graphic data stream), etc.) and configurable design specifications (e.g., FP dimensions, bump array matrix (e.g., its size), bump X / Y pitch, power ground (PG) ratio, dynamic bus inversion (DBI) data ratio, repair data bit ratio, design for testing (DFT) data, data bit (e.g., a number of data bits), 3D port, LITEIO, FF name, etc.). The synthesis tool 210 and / or the D2D compiler 320 operatively coupled thereto may generate a gate level net connection table 425 based on the RTL description 410 (e.g., generated by the D2D compiler 320 or included in the configuration 310). In some examples, the configuration 310 may include DFT data, and the synthesis tool 210 and / or D2D compiler 320 operatively coupled thereto may perform DFT insertion 420 to add additional logic processes to improve the testability of the recipe design. In some examples, the RTL description 410 may include a LITEIO module (which includes LITEIO cells and transmits and receives clock / control / data IO), a RP_REG module (which calculates repair / DBI cells), and a DESKEW-FIFO module (which handles clock domain crossing in stack level timing). In some examples, the D2D compiler 320 may generate the RTL description based on at least the number of data bits, the DBI data ratio, and the repair data ratio.

[0152] Based on the gate-level netlist 425 and the bump mapping description 430, the D2D compiler 320 may create a floorplan 435. The bump mapping description 430 may include, but is not limited to, a bump array matrix, its dimensions, bump X / Y pitch, etc., and the D2D compiler may generate an actual physical design for the overall structure of a semiconductor package and / or a floorplan 435 for bump mapping of a semiconductor die.

[0153] Based on the key example preset script 440 and the floor plan 435, the placement and routing tool (e.g., 220) and / or the D2D compiler 320 operatively coupled thereto may establish (place 445 and route 460) an actual physical design of an overall structure (e.g., a semiconductor package) and / or a bump map for a semiconductor die included in the semiconductor package. The placement and routing tool (e.g., 220) may form a physical design by acquiring selected cells from a cell library and placing them into cell rows, thereby establishing a bump structure. As discussed in more detail below, the bump structure may include various subsets of bump structures (e.g., a bump structure for transmitting signals, a bump structure for receiving signals, etc.). The placement and routing tool 220 (e.g., automatic place & route (APR)) and / or the D2D compiler 320 operably coupled thereto may perform specific standard cell placement according to key instance preset scripts and perform clock tree allocation according to a clock tree synthesis (CTS) recipe.

[0154] This placement and routing may be done automatically by a placement and routing tool (eg, 220), or may be performed in part via a manual process whereby a user manually inserts one or more cells into a row.

[0155] Figure 5 FIG. 1 shows a method for performing a multi-step process according to some embodiments. Figures 2 to 4 The method shown in is based on an example bump map 500 generated by the configuration of a semiconductor package. A D2D compiler (e.g., 320) can receive a configuration of a semiconductor package, the semiconductor package comprising at least a first semiconductor die and a second semiconductor die bonded to each other. The D2D compiler (e.g., 320) can generate a bump map 500 (e.g., a first bump map for the first semiconductor die, a second bump map for the second semiconductor die, etc.) based on the configuration of the semiconductor package. The bump map 500 indicates individual locations of various bump structures in the semiconductor die. Figure 5 As shown in , the various bump structures can be configured in various ways. In some examples, the subset of bump structures can be arranged symmetrically with respect to the X-axis or Y-axis of the bump map 500. In some examples, the subset of bump structures can be arranged parallel to the X-axis of the bump map 500, wherein the bump structures are spaced apart from each other by a predetermined distance in a plurality of predetermined different distances (e.g., a first distance, a second distance, etc.). In some examples, the subset of bump structures can be arranged on the X-axis or the Y-axis of the bump map 500.

[0156] Bump map 500 includes various subsets of bump structures, each of which includes bump structures for different functions, as shown in legend 505. TX / RX 510 is a bump structure for transmitting a signal to / receiving a signal from another bump structure. For example, a TX bump structure can transmit a signal to an RX bump structure. TX / RX RP 520 is a bump structure for repair. VDD / VSS 530 is a bump structure for supply / receive / ground voltage. TX / RX D2D clk 570 is a bump structure for transferring a clock signal between dies. TX / RX D2D reset 580 is a bump structure for resetting a device or circuit to its preset state or initial condition. WE / RVALID D2D 540 is a bump structure for ensuring that data is correctly written to and read from a memory or register. TX / RX DFT 550 is a bump structure that facilitates testing of an integrated circuit. Dummy 560 is a dummy bump structure.

[0157] In some instances, such as Figure 5 As shown in , multiple subsets of bump structures may be configured as multiple repair chains disposed in corresponding areas in the bump map 500. Each area may occupy M times the area unit of the bump map 500, where M is a positive integer. In some examples, different bump structures may form different subsets of bump structures. For example, a first subset of first bump structures configured as multiple first repair chains are each disposed in a corresponding first area 592 of the first bump map, and a second subset of first bump structures further configured as multiple second repair chains are each disposed in a corresponding second area 594 of the first bump map. The first area 592 and the second area 594 may each occupy M times the area unit of the first bump map, where M is a positive integer. In some examples, a first subset of second bump structures configured as multiple third repair chains are each disposed in a corresponding third area 596 of the second bump map, and a second subset of second bump structures further configured as multiple fourth repair chains are each disposed in a corresponding fourth area 598 of the second bump map. The third region 596 and the fourth region 598 may each occupy N times the area unit of the second bump map, where N is a positive integer. In some examples, the integers M and N may be 24, 16, 8, etc.

[0158] Figure 6An example configuration 600 of a semiconductor die of a semiconductor package for which a bump map is generated according to some embodiments is illustrated. A D2D compiler (e.g., 320) described herein may output a bump map for a semiconductor die in various configurations 600. In some examples, a D2D compiler (e.g., 320) described herein may generate a bump map for a semiconductor die having a multi-stack configuration. Configuration 600 is merely a non-limiting example, and a D2D compiler (e.g., 320) described herein may output a bump map for a semiconductor die having other configurations.

[0159] Configurations 610, 620, and 630 show full stack configurations, where the first die and the second die are arranged along an axis. In configuration 610, the first die and the second die are arranged side by side (e.g., 2.5D full stacking). In configuration 620, the first die and the second die are stacked vertically with each other, such that the front side of the first die faces the back side of the second die (e.g., 3D F2B full stacking). In configuration 630, the first die and the second die are stacked vertically with each other, such that the front side of the first die faces the front side of the second die (e.g., 3D F2F full stacking).

[0160] Configurations 640, 650, and 660 show partially stacked configurations where the first die and the second die are in an off-axis configuration. In configuration 640, the first die and the second die are configured side by side (e.g., 2.5D partial stacking). In configuration 650, the first die and the second die are perpendicular to each other but partially stacked so that the front side of the first die faces the back side of the second die (e.g., 3D F2B partial stacking). In configuration 660, the first die and the second die are perpendicular to each other but partially stacked so that the front side of the first die faces the front side of the second die (e.g., 3D F2F partial stacking).

[0161] Although configuration 600 shows two semiconductor dies, in some examples, a D2D compiler (eg, 320 ) described herein may generate a bump map that is compatible with more than two semiconductor dies.

[0162] Figure 7 610, 640 (eg, Figure 6 ) and corresponding bump maps 710 (710-1 and 710-2), 740 (740-1 and 740-2). Bump map 710-1 is a bump map corresponding to the first semiconductor die in configuration 610, and bump map 710-2 is a bump map corresponding to the second semiconductor die in configuration 610. Bump map 740-1 is a bump map corresponding to the first semiconductor die in configuration 640, and bump map 740-2 is a bump map corresponding to the second semiconductor die in configuration 640.

[0163] The D2D compiler (e.g., 320) can automatically generate a bump map 710 based on the configuration 610 and generate a bump map 740 based on the configuration 640. As shown in the bump map 740, the RX structure and the TX structure in the bump map 740-1 will be connected to the TX structure and the RX structure in the bump map 740-2, respectively, to communicate signals therebetween. As shown in the bump map 710, the bump map 710 can be generated using "reverse" logic, so that the RX structure and the TX structure in the bump map 710-1 will be connected to the RX structure and the TX structure in the bump map 710-2, respectively, to communicate signals therebetween. The "reverse" logic will refer to Fig.14 A more detailed discussion is given.

[0164] As described herein, a bump map (e.g., 710-1, 710-2, 740-1, 740-2, etc.) can be configured according to a corresponding configuration (e.g., 610, 640, etc.). The bump map can be generated without changing the position of the individual bump structures. Instead, the relative configuration (e.g., orientation, symmetry, etc.) of the bump map can be changed (e.g., rotated, flipped, etc.) according to the corresponding configuration.

[0165] Figure 8 620, 650, 630, 660 (eg, Figure 6 ) and corresponding bump maps 820 (820-1 and 820-2), 850 (850-1 and 850-2), 830 (830-1 and 830-2), 860 (860-1 and 860-2). Bump map 820-1 is a bump map corresponding to the first semiconductor die in configuration 620, and bump map 820-2 is a bump map corresponding to the second semiconductor die in configuration 620. Bump map 850-1 is a bump map corresponding to the first semiconductor die in configuration 650, and bump map 850-2 is a bump map corresponding to the second semiconductor die in configuration 650. Bump map 830-1 is a bump map corresponding to the first semiconductor die in configuration 630, and bump map 830-2 is a bump map corresponding to the second semiconductor die in configuration 630. Bump map 860 - 1 is a bump map corresponding to a first semiconductor die in configuration 660 , and bump map 860 - 2 is a bump map corresponding to a second semiconductor die in configuration 660 .

[0166] The D2D compiler (e.g., 320) may automatically generate bump maps 820, 850, 830, 860 based on the configurations 620, 650, 630, 660, respectively. In the configuration 620, the bump map 820-1 corresponds to the second semiconductor die in the configuration 620, and the bump map 820-2 corresponds to the first semiconductor die in the configuration 620. Since the configuration 620 is a front-to-back (F2B) configuration (e.g., the front surface of the first semiconductor die faces the back surface of the second semiconductor die), the bump map 820-2 reflects the front surface of the first semiconductor die, and the bump map 820-1 reflects the back surface of the second semiconductor die. Since the configuration 620 is a fully stacked configuration in which two semiconductor dies are arranged along an axis, the bump structures in the bump map 820-1 are positioned according to the positions of the bump structures in the bump map 820-2. That is, the bump structures in bump map 820-2 are located at positions corresponding to the positions of the bump structures in bump map 820-1. In configuration 620, "reverse" logic is used so that the RX structures and TX structures in bump map 820-1 will be connected to the RX structures and TX structures in bump map 820-2, respectively, to communicate signals therebetween.

[0167] In configuration 630, bump map 830-1 corresponds to the second semiconductor die in configuration 630, and bump map 830-2 corresponds to the first semiconductor die in configuration 630. Since configuration 630 is a front-to-front (F2F) configuration, bump map 830-2 reflects the front surface of the first semiconductor die, and bump map 830-1 reflects the front surface of the second semiconductor die. Since configuration 630 is a fully stacked configuration, in which two semiconductor dies are arranged along an axis (here, a vertical axis), the bump structures in bump map 830-1 are positioned according to the positions of corresponding bump structures in bump map 830-2. That is, the bump structures in bump map 830-2 are located at the same positions as the positions of corresponding bump structures in bump map 830-1. In configuration 630, "reverse" logic is not used, so that the RX structure and TX structure in bump map 830-1 will be connected to the TX structure and RX structure in bump map 830-2, respectively, to communicate signals therebetween.

[0168] In configuration 650, bump map 850-1 corresponds to the second semiconductor die in configuration 650, and bump map 850-2 corresponds to the first semiconductor die in configuration 650. Because configuration 650 is a front-to-back (F2B) configuration, bump map 850-2 reflects the front surface of the first semiconductor die, and bump map 850-1 reflects the back surface of the second semiconductor die. Because configuration 650 is a partially stacked configuration, in which the two semiconductor dies are off-axis, the bump structures in bump map 850-1 are positioned according to the corresponding positions of the bump structures in bump map 850-2. For example, as shown, bump map 850-2 can be rotated so that the bump structures in bump map 850-1 are positioned according to the corresponding positions of the bump structures in bump map 850-2. In configuration 650, "reverse" logic is not used, so the RX structure and TX structure in bump map 850-1 will be connected to the TX structure and RX structure in bump map 850-2, respectively, to communicate signals therebetween.

[0169] In configuration 660, bump map 860-1 corresponds to the second semiconductor die in configuration 660, and bump map 860-2 corresponds to the first semiconductor die in configuration 660. Since configuration 660 is a front-to-front (F2F) configuration, bump map 860-2 reflects the front surface of the first semiconductor die, and bump map 860-1 reflects the front surface of the second semiconductor die. Since configuration 660 is a partially stacked configuration, in which the two semiconductor dies are off-axis, the bump structures in bump map 860-1 are positioned according to the corresponding positions of the bump structures in bump map 860-2. For example, as shown, bump map 860-2 can be rotated so that the bump structures in bump map 860-1 are positioned according to the corresponding positions of the bump structures in bump map 860-2. In configuration 660, "reverse" logic is used so that the RX structure and TX structure in bump map 860-1 will be connected to the RX structure and TX structure in bump map 860-2, respectively, to communicate signals therebetween.

[0170] As described herein, bump maps (e.g., 820-1, 820-2, 850-1, 850-2, 830-1, 830-2, 860-1, 860-2, etc.) can be configured according to corresponding configurations (e.g., 620, 650, 630, 660, etc.). Bump maps can be generated without changing the positions of individual bump structures. Instead, the relative configuration (e.g., orientation, symmetry, etc.) of the bump maps can be changed (e.g., rotated, flipped, etc.) according to the corresponding configuration.

[0171] Fig. 9Flow of an example method 900 for configuring a bump map according to some embodiments is illustrated. Method 900 can be substantially similar or identical to method 300. Configuration 910 can be substantially similar or identical to configuration 310. D2D compiler 920 can be substantially similar or identical to D2D compiler 320. Recipe 930 can be substantially similar or identical to recipe 330.

[0172] Method 900 may include configuring or reconfiguring an initial bump map 940. Configuring 910 may include extending 960 the initial bump map 940 into an extended bump map 950. Fig. 9 As shown in , the initial bump map 940 is generated based on a configuration including: 128TX+128RX data bits, a 17×21 bump array matrix, a repair data bit ratio of 1 / 32, a DBI data bit ratio of 1 / 8, and a PG ratio of 10.6%. The D2D compiler 920 may reconfigure (e.g., expand 960) the initial bump map 940 based on an updated configuration (e.g., an extended configuration) to generate an extended bump map 950. For example, the extended bump map 950 is generated based on an updated configuration including: 160TX+160RX data bits, a 21×21 bump array matrix, a repair data bit ratio of 1 / 40, a DBI data bit ratio of 1 / 8, and a PG ratio of 11.3%. In order to achieve the reconfiguration (e.g., expansion), various operations may be performed on the bump structure. For example, as Fig. 9 As shown in , different subsets of the bump structures may be staggered, grouped, symmetrically arranged, etc.

[0173] Fig.10 An example operation 1000 for configuring a bump map according to some embodiments is illustrated. A D2D compiler (e.g., 320) may perform at least one of the operations 1000 to configure (e.g., generate a bump map) or reconfigure (e.g., extend) a bump map. In operation 1010, bump structures may be paired. As a non-limiting example, operation 1010 is shown as pairing TX / RX bump structures 1012, 1014 so that the bump structures 1012, 1014 are positioned symmetrically with respect to the Y-axis and the X-axis. More specifically, the TX structure 1012 is located on the left side of the bump map and the RX structure 1014 is located on the right side of the bump map, wherein the TX and RX structures 1012, 1014 are symmetrical with respect to the Y-axis. On the X-axis and the Y-axis, bump structures (e.g., TX / RX D2D-clk, TX / RX D2D reset, TX / RX DFT, etc.) for transmitting / receiving control signals, operating voltage / ground voltage (VDD / VSS), etc. are positioned.

[0174] In operation 1020, the bump structures for staggered VDD / VSS may be positioned to form a balanced staggered multiple power supply. This allows for a stable and reliable power grid and improved IR performance (eg, reduced voltage drop, IR drop, etc.).

[0175] In operation 1030 and operation 1040, bump structures that are highly correlated bits may be grouped. In operation 1030, bump structures that share the same repair chain 1022 (and / or share the same bus encoding) may be grouped. Fig.10 As shown in , operation 1030 can group the bump structures into a plurality of groups. In operation 1040, the bump structures can be grouped so that N (e.g., N=8, 10, ...) data in a square configuration share a DBI with a short physical distance. As described herein, the symmetrical bump structure allows for flexible configuration / configuration / reconfiguration (e.g., rotation, flipping, etc.) of bump mapping, thereby saving time and manpower in the overall process of 3D IC stacking.

[0176] Fig.11 An example operation 1100 for configuring a bump map according to some embodiments is illustrated. A D2D compiler (e.g., 320) may perform at least one of the operations 1100 to configure (e.g., generate a bump map) or reconfigure (e.g., expand) a bump map. In operation 1110, bump structures for VDD / VSS may be placed based on a power ground (PG) ratio. The bump structures for VDD / VSS may be placed within a sub-grid (N×M, where N and M are integers; for example, N=4, M=4) of a predetermined size to satisfy the PG ratio. Fig.11 The operation 1110 shown in FIG. 1 is a non-limiting example, and any PG ratio can also be achieved by placing the bump structures for VDD / VSS in sub-grids of different sizes. Fig.11 As shown in , the bump structures for VDD / VSS may be positioned symmetrically with respect to the X-axis and / or Y-axis of the bump map.

[0177] In operation 1120, the bump structure for repair may be placed in a predetermined position of the bump map. Fig.11 As shown in operation 1120 of , the bump structure for repair can be placed in the quadrant. In some examples, the bump structure for repair can be placed in a predetermined position of the bump map to meet a predetermined repair data ratio. For example, the bump structure for repair can be placed close to the corresponding repair chain to improve the efficiency of the repair process. The bump structure for repair can be positioned symmetrically with respect to the X-axis and / or Y-axis of the bump map.

[0178] In operation 1130, the bump structures in the predetermined area of ​​the bump map may form a sequence for dynamic bus inversion (DBI). Fig.11 As shown in operation 1130, for DBI, the bump structures located on the left side of the bump map form a sequence starting from the bottom portion of the bump map and ending at the top portion of the bump map. In some examples, for DBI, a predetermined number of bump structures can be sorted to meet a predetermined DBI data ratio. In some examples, the first subset and the second subset of the bump structures can be further configured as a plurality of first DBI signals, and can each be set in a corresponding first region of the bump map. In some examples, each of the first regions occupies M times the area unit of the first bump map, where M is a positive integer.

[0179] Fig.12 An example operation 1200 for configuring a bump map is shown in accordance with some embodiments. A D2D compiler (e.g., 320) may perform at least one of the operations 1200 to configure (e.g., generate a bump map) or reconfigure (e.g., expand) a bump map. In operation 1210, the D2D compiler may configure an N×M bump map, where N and M are odd numbers. This allows the bump structure for control signal pairing to be placed at the center row (e.g., the X-axis of the bump map) and / or the center column (e.g., the Y-axis of the bump map) of the bump map. For example, if Fig.12 As shown in , the bump structures for control signal pairing can be placed on the X-axis of the bump map. In operation 1210, subsets of different bump structures (eg, TX / RX, etc.) can be arranged symmetrically with respect to the X-axis and / or Y-axis of the bump map.

[0180] In operation 1220, the D2D compiler (eg, 320) may symmetrically place subsets of different bump structures (eg, TX / RX, TX / RX RP, TX / RX-D2D-clk, etc.) on the bump map. Fig.12 As shown in , the bump structure for TX can be arranged symmetrically with the bump structure for RX with respect to the Y axis of the bump mapping. Fig.12 The operation 1220 shown in FIG. 1 is a non-limiting example, and any bump structure may be symmetrically arranged.

[0181] Fig.13 Illustrated is an example operation 1300 for configuring a bump map in accordance with some embodiments. A D2D compiler (eg, 320) may use different logic configurations to connect different bump structures. Fig.131340. In some examples, the RX LIO 1310R may provide the signal to the RX FF 1340 via a multiplexer.

[0182] Fig.14 Illustrated is an example operation 1400 for configuring a bump map in accordance with some embodiments. A D2D compiler (eg, 320) may use different logic configurations to connect different bump structures. Fig.14 Operation 1400 is a configuration with "reverse" logic for connecting bump structures for transmitting / receiving signals (e.g., TX / RX). The TX bump structure 1430 generated based on the configuration with "reverse" logic can receive signals, and the RX bump structure 1450 generated based on the configuration with "reverse" logic can transmit signals. In the configuration with "reverse" logic, the TX bump structure 1430 can provide the received signal to the TX LIO 1410T of the bidirectional LITEIO 1410, which can provide the signal to the RX reverse FF 1420. In the configuration with "reverse" logic, the Tx reverse FF 1440 can provide the signal to the RX bump structure 1450 through the RX LIO 1410R of the bidirectional LITEIO 1410, and the RX bump structure 1450 can transmit the signal. As described above with respect to Figure 6 and Figure 7 As discussed, different logics (eg, "direct" logic, "inverse" logic, etc.) may be used to generate bump maps having different configurations.

[0183] Fig.15 An example bump map 1510 and corresponding bit map 1520 are shown according to some embodiments. Figures 7 to 14The various operations discussed are used to generate the bump map 1510. The bit map 1520 shows bits, each of which corresponds to each bump structure in the bump map 1510. In this non-limiting example, the bump map 1510 includes 357 bump structures (17×21), of which 256 bump structures are used for TX / RX, 32 bump structures are used for DBI, 8 bump structures are used for TX / RX RP, 2 bump structures are used for reset, 2 bump structures are used for WE / RVALID, 2 bump structures are used for TX / RXD2D clk, 18 bump structures are used for VDD, 18 bump structures are used for VSS, 8 bump structures are used for TX / RX DFT, and 11 dummy bump structures are included.

[0184] Generating the configuration (eg, 310) of the bump map 1510 may include an ordering 1530A of the bump structures. The bits in the bitmap 1520 may be ordered based on the ordering 1530A of the bump structures. Fig.15 As shown in , the order 1530B of the bits in the bitmap 1520 can be generated based on the order 1530A to arrange the bump structures (eg, from T0 to T31, from T32 to T63, ...). Similarly, the bump structures for RX can be arranged based on the order.

[0185] Fig.16 An example operation 1600 for designing a physical bump map according to some embodiments is illustrated. A D2D compiler (e.g., 320) and / or a placement and routing tool operatively coupled thereto may generate a recipe (e.g., 330) for a physical layout design for a semiconductor package (e.g., a D2D interface block) based on a configuration, a netlist, a bump map, etc. The D2D compiler and / or a placement and routing tool operatively coupled thereto may place or pre-place different components on the bump map 1610 and / or include a clock tree synthesis (CTS) recipe for D2D timing closure to generate a physical layout design for a semiconductor package (e.g., a D2D interface block).

[0186] In operation 1600, the D2D compiler (e.g., 320) may place or preset through-silicon via (TSV) related components 1620, including LITEIO, ESD, and TX / RX flip-flops. Examples of TSV related components 1620 include, but are not limited to, RX TSV, RX LITEIO, RX direct flip-flops, TX reverse flip-flops, etc. In operation 1600, the D2D compiler (e.g., 320) may place or preset clock components (e.g., H-tree clock roots, arch clock multiplexers, etc.). All D2Ds and flip-flops may be balanced together. In operation 1600, the D2D compiler (e.g., 320) may place or preset digital-controlled delay lines (DCDL) 1630 according to the closest logical connection sequence. In operation 1600, the D2D compiler (e.g., 320) may place or preset boundaries 1640 for RX pipeline flip-flops to guide R2R timing. In operation 1600 , a D2D compiler (eg, 320 ) may place or preset a duty cycle corrector 1650 to restore duty cycle performance to increase the clock frequency at double data rate.

[0187] In one aspect of an embodiment of the present disclosure, an integrated circuit design implementation system is disclosed. The system includes a die-to-die (D2D) compiler, which is used to receive a configuration of a semiconductor package, the semiconductor package at least including a first semiconductor die and a second semiconductor die bonded to each other; and based on the configuration of the semiconductor package, generate a first bump map and a second bump map for the first semiconductor die and the second semiconductor die, respectively. The first bump map indicates the individual positions of a plurality of first bump structures in the first semiconductor die, and the second bump map indicates the individual positions of a plurality of second bump structures in the second semiconductor die. In the first bump map, a first subset of first bump structures configured for transmitting signals to the second semiconductor die and a second subset of first bump structures configured for receiving signals from the second semiconductor die are arranged symmetrically with respect to an X-axis or a Y-axis of the first bump map. In the second bump map, a first subset of second bump structures configured to transmit signals to the first semiconductor die and a second subset of second bump structures configured to receive signals from the first semiconductor die are symmetrically arranged relative to an X axis or a Y axis of the second bump map.

[0188] In some embodiments, in the first bump mapping, a third subset of the first bump structures configured for transmitting / receiving a plurality of first control signals is disposed on the X-axis or Y-axis of the first bump mapping. In the second bump mapping, a third subset of the second bump structures configured for transmitting / receiving a plurality of second control signals is disposed on the X-axis or Y-axis of the second bump mapping.

[0189] In some embodiments, in the first bump map, a fourth subset of the first bump structures configured to receive the first supply voltage is disposed parallel to the X-axis of the first bump map, wherein the fourth subset of the first bump structures are spaced apart from each other by a first distance. In the second bump map, a fourth subset of the second bump structures configured to receive the first supply voltage is disposed parallel to the X-axis of the second bump map, wherein the fourth subset of the second bump structures are spaced apart from each other by the first distance.

[0190] In some embodiments, in the first bump map, a fifth subset of the first bump structures configured to receive a second supply voltage is disposed parallel to the X-axis of the first bump map, wherein the fifth subset of the first bump structures are spaced apart from each other by a second distance. In the second bump map, a fifth subset of the second bump structures configured to receive the second supply voltage is disposed parallel to the X-axis of the second bump map, wherein the fifth subset of the second bump structures are spaced apart from each other by a second distance.

[0191] In some embodiments, the first distance is different from the second distance.

[0192] In some embodiments, the first supply voltage is a working voltage and the second supply voltage is a ground voltage.

[0193] In some embodiments, the first subsets of the first bump structures of the multiple first repair chains are further configured to be each disposed in the corresponding first area of ​​the first bump map, and the second subsets of the first bump structures of the multiple second repair chains are further configured to be each disposed in the corresponding second area of ​​the first bump map, and the first area and the second area each occupy M times the area unit of the first bump map, where M is a positive integer. The first subsets of the second bump structures of the multiple third repair chains are further configured to be each disposed in the corresponding third area of ​​the second bump map, and the second subsets of the second bump structures of the multiple fourth repair chains are further configured to be each disposed in the corresponding fourth area of ​​the second bump map, and the third area and the fourth area each occupy N times an area unit of the second bump map, where N is a positive integer.

[0194] In some embodiments, the first subset and the second subset of the first bump structures further configured as a plurality of first dynamic bus reverse signals are each disposed in a corresponding first region of the first bump map, and the first region each occupies M times the area unit of the first bump map, where M is a positive integer. The first subset and the second subset of the second bump structures further configured as a plurality of second dynamic bus reverse signals are each disposed in a corresponding second region of the second bump map, and the second region each occupies N times the area unit of the second bump map, where N is a positive integer.

[0195] In some embodiments, the configuration of the semiconductor package includes the following information for each of the first semiconductor die and the second semiconductor die: number of data bits; size of bump matrix; repair data ratio; dynamic bus reverse data ratio; or power to ground ratio.

[0196] In some embodiments, the system further includes a synthesis tool operably coupled to the die-to-die compiler and configured to generate a netlist based on the register transfer level description.

[0197] In some embodiments, the die-to-die compiler further generates the register transfer level description based on at least the number of data bits, the dynamic bus reverse data ratio, and the repair data ratio.

[0198] In some embodiments, the system further includes a placement and routing tool operably coupled to the die-to-die compiler and configured to generate a physical layout design for the semiconductor package based on the first bump map, the second bump map, and the netlist.

[0199] In another aspect of an embodiment of the present disclosure, a method for simulating a semiconductor package is disclosed. The method includes receiving a configuration of a semiconductor package, the semiconductor package including at least a first semiconductor die and a second semiconductor die bonded to each other; and generating a first bump map and a second bump map for the first semiconductor die and the second semiconductor die respectively based on the configuration of the semiconductor package. The first bump map indicates the individual positions of a plurality of first bump structures in the first semiconductor die, and the second bump map indicates the individual positions of a plurality of second bump structures in the second semiconductor die. In the first bump map, a first subset of first bump structures configured to transmit signals to the second semiconductor die and a second subset of first bump structures configured to receive signals from the second semiconductor die are symmetrically arranged relative to an X-axis or a Y-axis of the first bump map. In the second bump map, a first subset of second bump structures configured to transmit signals to the first semiconductor die and a second subset of second bump structures configured to receive signals from the first semiconductor die are symmetrically arranged relative to an X-axis or a Y-axis of the second bump map.

[0200] In some embodiments, the first semiconductor die and the second semiconductor die are bonded such that the first semiconductor die and the second semiconductor die are arranged side by side.

[0201] In some embodiments, the first semiconductor die and the second semiconductor die are bonded such that the first semiconductor die is vertically stacked on the second semiconductor die.

[0202] In yet another aspect of an embodiment of the present disclosure, a computer program product is disclosed. The computer program product includes a computer-readable medium program code stored thereon, which, when executed by a processor, causes the processor to implement a method. The method includes receiving a configuration of a semiconductor package, the semiconductor package at least including a first semiconductor die and a second semiconductor die bonded to each other, wherein the first semiconductor die and the second semiconductor die are bonded so that the first semiconductor die and the second semiconductor die are arranged side by side or vertically stacked with each other; and generating a first bump map and a second bump map for the first semiconductor die and the second semiconductor die respectively based on the configuration of the semiconductor package. The first bump map indicates the individual positions of a plurality of first bump structures in the first semiconductor die, and the second bump map indicates the individual positions of a plurality of second bump structures in the second semiconductor die. In the first bump map, a first subset of the first bump structures configured for transmitting a signal to the second semiconductor die and a second subset of the first bump structures configured for receiving a signal from the second semiconductor die are arranged symmetrically with respect to an X-axis or a Y-axis of the first bump map. In the second bump map, a first subset of second bump structures configured to transmit signals to the first semiconductor die and a second subset of second bump structures configured to receive signals from the first semiconductor die are symmetrically arranged relative to an X axis or a Y axis of the second bump map.

[0203] In some embodiments, in the first bump mapping, a third subset of these first bump structures configured for transmitting / receiving multiple first control signals is disposed on the X-axis or Y-axis of the first bump mapping; in the second bump mapping, a third subset of these second bump structures configured for transmitting / receiving multiple second control signals is disposed on the X-axis or Y-axis of the second bump mapping.

[0204] In some embodiments, in the first bump map, a fourth subset of the first bump structures configured to receive the first supply voltage is disposed parallel to the X-axis of the first bump map, wherein the fourth subset of the first bump structures are spaced apart from each other by a first distance. In the second bump map, a fourth subset of the second bump structures configured to receive the first supply voltage is disposed parallel to the X-axis of the second bump map, wherein the fourth subset of the second bump structures are spaced apart from each other by the first distance.

[0205] In some embodiments, in the first bump map, a fifth subset of the first bump structures configured to receive the second supply voltage is disposed parallel to the X-axis of the first bump map, wherein the fifth subset of the first bump structures are spaced apart from each other by the second distance. In the second bump map, a fifth subset of the second bump structures configured to receive the second supply voltage is disposed parallel to the X-axis of the second bump map, wherein the fifth subset of the second bump structures are spaced apart from each other by the second distance.

[0206] In some embodiments, the semiconductor package further includes a third semiconductor die. The first semiconductor die, the second semiconductor die, and the third semiconductor die are stacked vertically with each other. The processor implements the method, which includes the step of generating a third bump map for the third semiconductor die based on the configuration of the semiconductor package.

[0207] As used herein, the terms "about" and "approximately" generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0208] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of an embodiment of the present disclosure. Those skilled in the art will appreciate that they may readily use an embodiment of the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of an embodiment of the present disclosure.

Claims

1. A system for implementing integrated circuit design, characterized in that: Include: A die-to-die compiler for: receiving a configuration of a semiconductor package, the semiconductor package comprising at least a first semiconductor die and a second semiconductor die bonded to each other; and Based on the configuration of the semiconductor package, generating a first bump map and a second bump map for the first semiconductor die and the second semiconductor die, respectively; wherein the first bump map indicates individual locations of a plurality of first bump structures in the first semiconductor die, and the second bump map indicates individual locations of a plurality of second bump structures in the second semiconductor die; wherein, in the first bump mapping, a first subset of the plurality of first bump structures configured to transmit a plurality of signals to the second semiconductor die and a second subset of the plurality of first bump structures configured to receive a plurality of signals from the second semiconductor die are symmetrically arranged with respect to an X-axis or a Y-axis of the first bump mapping; and In the second bump mapping, a first subset of the plurality of second bump structures configured to transmit a plurality of signals to the first semiconductor die and a second subset of the plurality of second bump structures configured to receive a plurality of signals from the first semiconductor die are symmetrically arranged with respect to an X-axis or a Y-axis of the second bump mapping.

2. The system according to claim 1, characterized in that in, In the first bump map, a third subset of the plurality of first bump structures configured for transmitting / receiving a plurality of first control signals is disposed on the X-axis or the Y-axis of the first bump map; and Wherein, in the second bump mapping, a third subset of the plurality of second bump structures configured for transmitting / receiving a plurality of second control signals is disposed on the X-axis or the Y-axis of the second bump mapping.

3. The system according to claim 1, characterized in that in, In the first bump map, a fourth subset of the plurality of first bump structures configured to receive a first supply voltage is disposed parallel to the X-axis of the first bump map, wherein the fourth subset of first bump structures are spaced apart from each other by a first distance; wherein, in the second bump map, a fourth subset of the plurality of second bump structures configured to receive the first supply voltage is disposed parallel to the X-axis of the second bump map, wherein the fourth subset of second bump structures are spaced apart from each other by the first distance, wherein, in the first bump map, a fifth subset of the plurality of first bump structures configured to receive a second supply voltage is disposed parallel to the X-axis of the first bump map, wherein the fifth subset of first bump structures are spaced apart from each other by a second distance; and In the second bump map, a fifth subset of the plurality of second bump structures configured to receive the second supply voltage is disposed parallel to the X-axis of the second bump map, wherein the fifth subset of second bump structures are spaced apart from each other by the second distance.

4. The system according to claim 1, characterized in that wherein the first subset of the plurality of first bump structures further configured as a plurality of first repair chains are each disposed in a corresponding first region of the first bump map, and the second subset of the plurality of first bump structures further configured as a plurality of second repair chains are each disposed in a corresponding second region of the first bump map, and the first region and the second region each occupy M times an area unit of the first bump map, where M is a positive integer; and The first subset of the plurality of second bump structures further configured as a plurality of third repair chains is each arranged in a corresponding third area of ​​the second bump map, and the second subset of the plurality of second bump structures further configured as a plurality of fourth repair chains is each arranged in a corresponding fourth area of ​​the second bump map, and the third area and the fourth area each occupy N times an area unit of the second bump map, where N is a positive integer.

5. The system according to claim 1, wherein: wherein the first subset and the second subset of the plurality of first bump structures further configured as a plurality of first dynamic bus reverse signals are each disposed in a corresponding first region of the first bump map, the first region each occupying M times an area unit of the first bump map, M being a positive integer; and The first subset and the second subset of the plurality of second bump structures further configured as a plurality of second dynamic bus reverse signals are each arranged in a corresponding second area of ​​the second bump map, and each of the second areas occupies N times an area unit of the second bump map, where N is a positive integer.

6. The system according to claim 1, wherein: It further comprises: a synthesis tool operably coupled to the die-to-die compiler and configured to generate a netlist based on a register transfer level description, The configuration of the semiconductor package includes the following information for each of the first semiconductor die and the second semiconductor die: a number of data bits; a size of a bump matrix; a repair data ratio; a dynamic bus reverse data ratio; or a power to ground ratio.

7. The system according to claim 6, characterized in that The die-to-die compiler is further configured to generate the register transfer level description based at least on the number of data bits, the dynamic bus reverse data ratio, and the repair data ratio.

8. The system according to claim 6, characterized in that It further comprises: A placement and routing tool is operably coupled to the die-to-die compiler and is used to generate a physical layout design for the semiconductor package based on the first bump map, the second bump map, and the netlist.

9. A method for simulating a semiconductor package, characterized in that: The following steps are involved: receiving a configuration of a semiconductor package, the semiconductor package comprising at least a first semiconductor die and a second semiconductor die bonded to each other; and Based on the configuration of the semiconductor package, generating a first bump map and a second bump map for the first semiconductor die and the second semiconductor die, respectively; wherein the first bump map indicates individual locations of a plurality of first bump structures in the first semiconductor die, and the second bump map indicates individual locations of a plurality of second bump structures in the second semiconductor die; wherein, in the first bump mapping, a first subset of the plurality of first bump structures configured to transmit a plurality of signals to the second semiconductor die and a second subset of the plurality of first bump structures configured to receive a plurality of signals from the second semiconductor die are symmetrically arranged with respect to an X-axis or a Y-axis of the first bump mapping; and In the second bump mapping, a first subset of the plurality of second bump structures configured to transmit a plurality of signals to the first semiconductor die and a second subset of the plurality of second bump structures configured to receive a plurality of signals from the first semiconductor die are symmetrically arranged with respect to an X-axis or a Y-axis of the second bump mapping.

10. A computer program product, characterized in that A computer readable medium having program code stored thereon, wherein the computer readable medium program code, when executed by a processor, causes the processor to implement a method, the method comprising the following steps: Receive a configuration of a semiconductor package, the semiconductor package comprising at least a first semiconductor die and a second semiconductor die bonded to each other, wherein the first semiconductor die and the second semiconductor die are bonded so that the first semiconductor die and the second semiconductor die are arranged side by side or vertically stacked with each other; and Based on the configuration of the semiconductor package, generating a first bump map and a second bump map for the first semiconductor die and the second semiconductor die, respectively; wherein the first bump map indicates individual locations of a plurality of first bump structures in the first semiconductor die, and the second bump map indicates individual locations of a plurality of second bump structures in the second semiconductor die; wherein in the first bump map, a first subset of the plurality of first bump structures configured to transmit a plurality of signals to the second semiconductor die and a second subset of the plurality of first bump structures configured to receive a plurality of signals from the second semiconductor die are symmetrically arranged relative to an X-axis or a Y-axis of the first bump map; and Wherein, in the second bump mapping, a first subset of the plurality of second bump structures configured for transmitting a plurality of signals to the first semiconductor die and a second subset of the plurality of second bump structures configured for receiving a plurality of signals from the first semiconductor die are symmetrically arranged with respect to an X-axis or a Y-axis of the second bump mapping.

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