A static switch control circuit for an industrial frequency inverter power supply

Abstract

The present invention discloses a static switch control circuit for a power-frequency inverter power supply. The control circuit is used to control a power-frequency inverter power supply comprising at least two inverters and at least one static switch. The control circuit has inputs connected to a main inverter and a sub-inverter, respectively, and an output connected to the static switch. The control circuit includes a first connector and a second connector. The static switch control circuit of the present invention can be controlled in parallel by two inverters, and when either inverter fails, switching is performed without delay. Communication between the two inverters is not required, thus avoiding voltage fluctuations caused by communication delays in dual-inverter control circuits.

Description

Technical Field

[0001] The present invention relates to the field of uninterruptible power supplies, and in particular to a static switch control circuit of an industrial frequency inverter power supply. Background Art

[0002] A power frequency inverter consists of an inverter and a static switch. The inverter converts the battery pack's DC input into AC power, providing AC power to the load. The static switch collects AC and DC input information, along with inverter data, to determine input and inversion status and control the inverter output.

[0003] When DC input is used, the inverter converts the DC input from the battery pack into AC power, providing AC power to the load. Usually, a bypass AC input is also provided to ensure the stability of the power frequency inverter power supply.

[0004] Traditional power frequency inverters consist of a set of inverters and a set of static switches. To increase power supply reliability by connecting the inverters in parallel, two sets of power frequency inverters are required. This solution requires a large space for two sets of power frequency inverters, and the wiring between the two sets is complex and external to the power supply, making them susceptible to interference from the ambient magnetic field. A communication failure between the two sets of power frequency inverters can easily cause the power sources to interact with each other, generating circulating currents that can damage the inverters and affect the downstream load. Summary of the Invention

[0005] The purpose of the present invention is to address the problem of parallel connection of industrial frequency inverter power supplies and propose a static switch control circuit for the inverter power supply. The control circuit can adapt to two scenarios: shared bypass and separate bypass of the inverter power supplies. It is simple to use and can improve system reliability. When the bypass input is abnormal or an inverter fails, the static switch is guaranteed to work normally. In addition, when one of the inverters fails, even if the communication fails, smooth switching can still be guaranteed.

[0006] Principle Description

[0007] For two or more power-frequency inverters, or a power-frequency inverter with a common bypass and multiple inverters, the most important issue is controlling the static switch output. For a single inverter, the control signals for the inverter output and bypass output are interlocked: only one control signal is sent to the static switch, while the other is blocked. For multiple inverters connected in parallel, the control signals for all static switches are consistent. If the static switch control signal of one inverter fails, both control signals will be blocked. Due to the delay in signal interaction, if the master inverter fails, there may be a delay in the standby inverter switching to master control, resulting in a power outage at the load end.

[0008] In response to the above problems, the present invention provides a static switch control circuit for an industrial frequency inverter power supply, wherein the control circuit is used to control an industrial frequency inverter power supply comprising at least two inverters and at least one static switch, wherein the input of the control circuit is connected to a main inverter and a sub-inverter respectively, and the output of the control circuit is connected to the static switch, wherein the control circuit comprises a first connector and a second connector, wherein the first connector is powered by a first inverter, and the second connector is powered by a second inverter, and the DC power supply of the first inverter is divided into two branches, wherein the first branch is input to the first input of the controlled connector via a diode D1, and the second branch is input to the second input of the controlled connector via a diode D3. Input, the DC power supply of the second inverter is divided into two branches. The third branch is connected in parallel with the first branch through diode D4 and then input to the first input of the controlled connector. The fourth branch is connected in parallel with the second branch through diode D6 and then input to the second input of the controlled connector. The first connector has a first main control inverter signal output and a first bypass control signal output; the second connector has a second main control inverter signal output and a second bypass control signal output; the first main control inverter signal output and the second main control inverter signal output are respectively connected in parallel through diodes to form an inverter control signal; the first bypass control signal output and the second bypass control signal output are respectively connected in parallel through diodes to form a bypass control signal.

[0009] The inverter control signal is input to the base of transistor Q4, the collector of transistor Q4 is connected to the base of transistor Q5 via a diode, the collector of transistor Q5 is powered by a low-voltage power supply via a voltage divider resistor and connected to the second input of NAND gate U2A, the first input of NAND gate U2A is connected to the periodically changing PWM drive signal, and the output of NAND gate U2A is used as the output of the inverter control signal.

[0010] The bypass control signal is input to the base of the transistor Q7, the collector of the transistor Q7 is connected to the base of the transistor Q6 via a diode, the collector of the transistor Q6 is powered by a low-voltage power supply via a voltage divider resistor and is connected to the second input of the NAND gate U2B, the first input of the NAND gate U2B is connected to the periodically changing PWM drive signal, the output of the NAND gate U2A serves as the output of the bypass control signal, and the collector of the transistor Q5 is connected to the base of the transistor Q6 via a diode.

[0011] Furthermore, the output of the controlled connector is connected to a static switch, and the controlled connector controls the static switch to switch between the bypass input and the inverter input.

[0012] Furthermore, a chip UC3845 is included for generating a PWM drive signal with the same period as the inverter.

[0013] Furthermore, the bypass input is connected to the mains, and the first inverter and the second inverter are respectively connected to respective battery packs.

[0014] Furthermore, the number of the controlled static switches is one or two.

[0015] The present invention can achieve effective control of the static switch during the control process of two or more sets of industrial frequency inverter power supplies, even if the main inverter fails and the inverter communication is delayed, thereby avoiding power outages at the back end. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of a framework of the static switch control circuit of the present invention when applied to static switch control;

[0017] Figure 2 1 is an internal circuit diagram of the static switch control circuit of the present invention.

[0018] Figure 3 The present invention is applied to a controlled static switch in the present invention.

[0019] Figure 4 This is a diagram showing the actual application effect of the circuit described in the invention. Channel 1 (yellow) is the sampling of the total output voltage of the inverter power supply, channel 2 (green) is the sampling of the BAPASS signal, and channel 3 (purple) is the sampling of the INVERNT signal. It simulates when one of the inverter power supplies fails. Combined with the analysis and control of the working process, the BAPASS signal of channel 2 changes from a low level to a high level. During this fault process, it can be observed that the total output voltage sampling of the inverter power supply on channel 1 has no abnormal conditions such as fluctuations, spikes, and faults, and the output is stable. DETAILED DESCRIPTION

[0020] The present invention will be described in further detail below with reference to the embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0021] like Figure 1 The figure shows a circuit diagram of an application scenario of the control circuit of the present invention. The circuit of the present invention is applied in the case of controlling a static switch using a dual inverter. In order to avoid irreparable losses caused by inverter failure when two static switches are controlled by a single inverter, a dual inverter is used for redundancy. However, considering that the traditional dual inverter control process requires coordination between the dual inverters based on communication between the dual inverters, if the communication between the two is delayed or fails, when one inverter fails, the control signal output to the static switch will be disordered.

[0022] In order to avoid the above-mentioned control signal disorder problem, such as Figure 1As shown, in this embodiment, two inverters, inverter No. 1 and inverter No. 2, are used to jointly control the two static switches, and the two inverters are powered by their own battery packs. That is, the present invention adds an additional coordination control circuit, which is subsequently referred to as a static switch control circuit.

[0023] The static switch control circuit of this embodiment is used to control an industrial frequency inverter power supply including two inverters and two static switches. The inputs of the control circuit are connected to inverter No. 1 and inverter No. 2 respectively.

[0024] like Figure 2 As shown, the control circuit includes a first connector CN1 (FKV10VR) and a second connector CN2 (FKV10VR). The first connector is powered by the first inverter (inverter 1 in the figure), which generates a 12V DC signal to power the corresponding connector. Inverter 1 outputs a first main control inverter signal and a first bypass control signal to the first connector CN1. Similarly, the second inverter (inverter 2 in the figure) outputs a second main control inverter signal and a second bypass control signal to the second connector CN2, which is powered by inverter 2.

[0025] The first connector CN1 is connected to the static switch control signal of inverter No. 1, and the second connector CN2 is connected to the static switch control signal of inverter No. 2. +12B and +12B' are isolated by diodes D1 and D4, respectively, to prevent backflow. In the figure, INV CTRL and INV CTRL' are the control signals of the inverter outputs of the two sets of inverters, respectively. They are output through two connectors and isolated by diode D2 to prevent backflow. R1 is the signal grounding resistor to prevent the signal from being left floating and generating a virtual voltage.

[0026] In the figure, BY CTRL and BY CTRL' are the control signals for the bypass outputs of the two inverters, respectively. They are output via two connectors and isolated by diode D5 to prevent backflow. R2 is a signal ground resistor to prevent floating signals from generating pseudo voltage. GND is the signal ground. +12 and +12' are isolated by diodes D3 and D6, respectively, to prevent backflow. Pins 1 and 2 of the first connector CN1 are the 12V power supply, pins 9 and 10 are the 12VB power supply, and pins 3 and 4 are the power ground. These two power supplies jointly provide power to the static switch. Pins 5 and 6 are the control signals for the bypass output, and pins 7 and 8 are the control signals for the forwarding inverter output. Within a single connector, the control signals are interlocked. When pins 5 and 6 are outputting control signals, pins 7 and 8 are not, and the inverter static switch is in the bypass output state. When pins 7 and 8 are outputting control signals, pins 5 and 6 are not, and the inverter static switch is in the inverter output state.

[0027] After the DC power supply input of inverter No. 1 is supplied to connector CN1, it is divided into two branches. The first branch is input to the first input of controlled connector CN1 via diode D1, and the second branch is input to the second input of controlled connector CN3 via diode D3. After the DC power supply input of inverter No. 2 is supplied to connector CN2, it is divided into two branches. The third branch is connected in parallel with the first branch via diode D4 and is input to the first input of controlled connector CN3. The fourth branch is connected in parallel with the second branch via diode D6 and is input to the second input of controlled connector CN3. The first connector CN1 has a first main control inverter signal output and a first bypass control signal output, which are mutually inverse. That is, when the first main control inverter signal output is high, the first bypass control signal output must be low, and vice versa.

[0028] The second connector has a second main control inverter signal output and a second bypass control signal output, which are mutually opposite, that is, when the second main control inverter signal output is high, the second bypass control signal output must be low, and vice versa; the first main control inverter signal output and the second main control inverter signal output are respectively connected in parallel through diodes to form an inverter control signal; the first bypass control signal output and the second bypass control signal output are respectively connected in parallel through diodes to form a bypass control signal.

[0029] The combined inverter control signal is input to the base of transistor Q4. The collector of transistor Q4 is connected to the base of transistor Q5 via a diode, with the emitter of transistor Q4 connected to ground. The collector of transistor Q5 is powered by a low-voltage power supply via a voltage divider resistor and connected to the second input of NAND gate U2A. The emitter of transistor Q5 is grounded. The first input of NAND gate U2A is connected to the periodically varying PWM drive signal, and the output of NAND gate U2A serves as the inverter control signal.

[0030] The combined bypass control signal is input to the base of the transistor Q7, the collector of the transistor Q7 is connected to the base of the transistor Q6 via a diode, the emitter of the transistor Q7 is grounded, the collector of the transistor Q6 is powered by a low-voltage power supply via a voltage divider resistor and is connected to the second input of the NAND gate U2B, the first input of the NAND gate U2B is connected to a periodically changing PWM drive signal, the output of the NAND gate U2B serves as the output of the bypass control signal, and the collector of the transistor Q5 is connected to the base of the transistor Q6 via a diode.

[0031] The periodically changing PWM drive signal is generated by the independent UC3845 chip, which generates a PWM signal with a corresponding duty cycle based on the static switch control requirements. The PWM signal here uses a 50Hz alternating pulse signal to match the inverter output, with both period and phase matching.

[0032] In this circuit, the CD40107 operates as follows: Pin 3 of the CD40107 outputs the INV STS DRV signal, which controls the inverter output function of the static switch. If the INV STSDRV signal is high, the inverter output function is disabled. If the INV STSDRV signal alternates between high and low levels, the inverter output function is enabled. Pin 5 of the CD40107 outputs the BYSTSDRV signal, which controls the bypass output function of the static switch. If the BY STSDRV signal is high, the bypass output function is disabled. If the INV STSDRV signal alternates between high and low levels, the bypass output function is enabled.

[0033] The control process of the static switch is as follows:

[0034] To set the static switches of the two inverters to bypass mode, they send high-level signals to BY CTRL and BY CTRL', respectively (the connector forwards these signals through the corresponding ports). To set the static switches to inverter mode, they send high-level signals to INV CTRL and INV CTRL', respectively (the connector forwards these signals through the corresponding ports, the same applies below). Under normal circumstances, the signals sent by the two inverters are consistent, resulting in only one of the BYPASS and INVERNT signals being high. In this case, the inverter outputs in the bypass or inverter state according to normal control requirements. If one inverter fails or information exchange between the two inverters fails, the signals sent by the two inverters will become inconsistent, resulting in both BYPASS and INVERNT signals being high. In this case, after passing through the circuit of the present invention, the inverter output will be in the inverter state.

[0035] The following is a further detailed explanation of the working process of the inverter power supply:

[0036] When both inverters are operating normally, the main control signals (INV CTRL) output by inverters 1 and 2 to the corresponding connectors are both high, and the bypass control signals (BY CTRL) are both low. The corresponding interfaces in CN1 and CN2 output high, turning D2 on and outputting a high level to the base of transistor Q4. This turns Q4 on and Q5 off. Pin 2 of NAND gate U2A (CD40107) is high, and the PWM signal on pin 1 of U2A alternates between high and low levels. Pin 3 of U2A also outputs an alternating high and low signal. Q7 is off, Q6 is on, and pin 6 of U2B is low. The PWM signal on pin 7 of U2B alternates between high and low levels, and pin 5 of U2B outputs a high signal. Because the bypass input and the inverter main control input require alternating signals, the bypass input is non-conductive when it is continuously high. The two static switches are controlled by the inverter output under the main control signal.

[0037] When inverter No. 1 or inverter No. 2 fails, the following description takes inverter No. 1 failure as an example. The main control signal output (INV CTRL) of connector CN1 connected to inverter No. 1 is low, and the main control signal of connector CN2 connected to inverter No. 2 is high. The main control signal output and bypass signal output in the connector are opposite to each other. The bypass signal output of CN2 is low, and the bypass output of CN1 is high. The two are high when connected in parallel. The INVERNT signal is high, the BAPASS signal is high, Q4 is turned on, Q5 is cut off, pin 2 of NAND gate U2A is high, and the PWM signal of pin 1 of NAND gate U2A is a high-low alternating level signal. Pin 3 of NAND gate U2A will output a high-low alternating level signal; Q7 is turned on, Q6 is turned on, pin 6 of NAND gate U2B is low, and the PWM signal of pin 7 of NAND gate U2B is a high-low alternating level signal. Pin 5 of NAND gate U2B will output a high-level signal. The static switch is controlled solely by inverter 2, and there will be no control disorder.

[0038] When both inverters fail, the main control signal output (INVCTRL) of the connector connected to inverter 1 is low, and the main control signal of the connector connected to inverter 2 is also low. The main control signal output and the bypass signal output in the connector are mutually inverse. The bypass signal output of the connectors connected to inverters 1 and 2 is high, the INVERNT signal is low, and the BAPASS signal is high. Q4 is turned off, Q5 is turned on, pin 2 of NAND gate U2A is low, the PWM signal on pin 1 of NAND gate U2A is alternating high and low, and pin 3 of NAND gate U2A outputs a high signal. Q7 is turned on, Q6 is turned off, pin 6 of NAND gate U2B is high, the PWM signal on pin 7 of NAND gate U2B is alternating high and low, and pin 5 of NAND gate U2B is alternating high and low. This achieves a smooth transition from inverter power supply to bypass power supply.

[0039] When the circuit of the present invention is used for control, the circuit simulation after encountering a fault is as follows Figure 4 Among them, channel 1 (yellow) is the total output voltage sampling of the inverter power supply, channel 2 (green) is the BAPASS signal sampling, and channel 3 (purple) is the INVERNT signal sampling. When one of the inverter power supplies fails, combined with the working process analysis and control, the BAPASS signal of channel 2 changes from a low level to a high level. During this fault process, it can be observed that the total output voltage sampling of the inverter power supply in channel 1 has no abnormal conditions such as fluctuations, spikes, and faults, and the output is stable.

[0040] Although the principles of the present invention have been described in detail above in conjunction with the preferred embodiments of the present invention, those skilled in the art should understand that the above embodiments are merely illustrative of the present invention and are not intended to limit the scope of the present invention. The details in the embodiments do not constitute a limitation on the scope of the present invention. Without departing from the spirit and scope of the present invention, any obvious changes such as equivalent transformations and simple substitutions based on the technical solution of the present invention fall within the scope of protection of the present invention.

Claims

1. A static switch control circuit for an industrial frequency inverter power supply, characterized in that: The control circuit is used to control an industrial frequency inverter power supply including at least two inverters and at least one static switch. The input of the control circuit is connected to the main inverter and the auxiliary inverter respectively, and the output of the control circuit is connected to the static switch. The control circuit includes a first connector and a second connector. The first connector is powered by the first inverter, and the second connector is powered by the second inverter. The DC power supply of the first inverter is divided into two branches. The first branch is input to the first input of the controlled connector via a diode D1, and the second branch is input to the second input of the controlled connector via a diode D3. The DC power supply of the second inverter is divided into Two branches, the third branch is connected in parallel with the first branch through a diode D4 and then input to the first input of the controlled connector, the fourth branch is connected in parallel with the second branch through a diode D6 and then input to the second input of the controlled connector, the first connector has a first main control inverter signal output and a first bypass control signal output; the second connector has a second main control inverter signal output and a second bypass control signal output; the first main control inverter signal output and the second main control inverter signal output are respectively connected in parallel through diodes to form an inverter control signal; the first bypass control signal output and the second bypass control signal output are respectively connected in parallel through diodes to form a bypass control signal. The inverter control signal is input to the base of transistor Q4, the collector of transistor Q4 is connected to the base of transistor Q5 via a diode, the collector of transistor Q5 is powered by a low-voltage power supply via a voltage divider resistor and is connected to the second input of NAND gate U2A, the first input of NAND gate U2A is connected to the periodically changing PWM drive signal, the output of NAND gate U2A serves as the output of the inverter control signal, the emitters of Q4, Q5, Q6 and Q7 are grounded respectively, the collector of Q4 is powered by a 12V power supply via resistor R20, the collector of Q7 is powered by a 12V power supply via resistor R37, The bypass control signal is input to the base of the transistor Q7, the collector of the transistor Q7 is connected to the base of the transistor Q6 via a diode, the collector of the transistor Q6 is powered by a low-voltage power supply via a voltage divider resistor and is connected to the second input of the NAND gate U2B, the first input of the NAND gate U2B is connected to the periodically changing PWM drive signal, the output of the NAND gate U2A serves as the output of the bypass control signal, and the collector of the transistor Q5 is connected to the base of the transistor Q6 via a diode.

2. The static switch control circuit according to claim 1, characterized in that: The output of the controlled connector is connected to the static switch, and the controlled connector controls the static switch to switch between the bypass input and the inverter input.

3. The static switch control circuit according to claim 1, characterized in that: The chip UC3845 is also included to generate a PWM drive signal with the same cycle as the inverter.

4. The static switch control circuit according to claim 1, characterized in that: The bypass input is connected to the mains, and the first inverter and the second inverter are respectively connected to their own battery packs.

5. The static switch control circuit according to claim 1, wherein: The number of controlled static switches is one or two.

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