A dual-stage amplification dynamic amplifier and its application

Abstract

The present invention discloses a dual-stage amplified dynamic amplifier, including a power supply capacitor network, a common-source common-gate common-source dual-stage inverter and a dual-stage output network, which is suitable for high-precision switched capacitor circuits. The amplification working stage of the dynamic amplifier of the present invention is divided into two parts: coarse quantization and level shift. In the coarse quantization stage, the power supply capacitor supplies power to the common-source common-gate inverter, and the output result is stored on the auxiliary capacitor; in the level conversion stage, the transistor is configured as an ordinary common-source inverter, and the power supply capacitor can use the remaining charge in the coarse quantization stage to power the inverter, and the output auxiliary capacitor is reversely connected to the output end of the inverter to achieve level shift and promote charge transfer. The dual-stage amplified dynamic amplifier of the present invention can achieve an equivalent DC gain of 72.5dB without adding additional power supply capacitors and other overheads, and can maintain the stability of gain under multiple different process angles.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a dual-stage amplification dynamic amplifier and applications thereof. Background Art

[0002] In recent years, dynamic amplifiers have attracted extensive attention from researchers due to their characteristic of no quiescent current during reset, which means that the power consumption of dynamic amplifiers is positively correlated with the operating frequency, and there is almost no power consumption in standby mode; therefore, dynamic amplifiers have broad application prospects in low-power sensor chips, especially battery-powered chips. Currently, a widely used architecture is to use pre-charged capacitors to power the inverter, that is, to charge the capacitor at the reset time, and use the charge stored on the capacitor to power the inverter during amplification. This amplifier has the advantages of no quiescent current, current reuse, and no need for common-mode feedback. However, the DC gain of this amplifier is small, and it is still a long way from being directly applied to systems such as high-precision analog-to-digital converters.

[0003] One existing method for improving the DC gain of a dynamic amplifier is the Correlated Level Shifting (CLS) technology, as described in the literature [Chen Junsheng. Research and Design of Readout Circuits for CMOS Image Sensors [D]. Zhejiang: Zhejiang University, 2023]. The application premise of this technology is a closed-loop amplification structure of switched capacitors. The principle is to promote the charge transfer of closed-loop amplification, thereby improving the equivalent DC gain of the dynamic amplifier. The circuit cost of this technology is only an additional pair of capacitors and two sets of switches, and it has been widely used in switched capacitor delta-sigma modulators and pipelined successive approximation analog-to-digital converters, achieving extremely high energy efficiency. However, in the closed-loop amplification structure using CLS technology, the entire amplification stage is divided into sub-stage 1 (coarse amplification) and sub-stage 2 (level shift); for the dynamic amplifier, at the end of the coarse amplification stage, the capacitor that supplies power has been discharged and cannot support the level shift operation of sub-stage 2.

[0004] There are currently two methods to solve the power supply problem in the level shift stage: one is to use a new pre-charged capacitor for power supply in the level shift stage (such as the Chinese patent technology with publication number CN115051663A), but this will increase the size of the overall capacitor and reduce the area efficiency of the entire chip; the other method is to control the body potential of the transistor to eliminate the body effect of the transistor in the level shift stage to reduce the threshold voltage (such as the literature [Hu Yaopeng. Research and Design of Low-Power 2-0 MASH ADC [D]. Zhejiang: Zhejiang University, 2022]), so that the amplifier can use the residual charge on the power supply capacitor to complete the level shift operation, but this operation is very sensitive to the process parameters of the transistor and the consistency is not high under different process corners. Summary of the invention

[0005] In view of the above, the present invention provides a dual-stage amplification dynamic amplifier, which can achieve an improvement in DC gain with a lower circuit cost and maintain gain stability under different process angles.

[0006] A dual-stage amplification dynamic amplifier includes a power supply capacitor network, a fully differential common-source common-gate-common-source dual-stage inverter, and a fully differential dual-stage output network, wherein:

[0007] The power supply capacitor network is charged in the reset phase and supplies power to the common-source common-gate-common-source dual-stage inverter in the amplification phase;

[0008] The common-source common-gate-common-source dual-stage inverter is used to generate a set of differential signals after amplifying the input signal;

[0009] The dual-stage output network is used to perform a level shift operation on a differential signal.

[0010] Furthermore, the operation of the dynamic amplifier is divided into a reset stage and an amplification stage, and the amplification stage is further divided into a coarse quantization stage and a level shift stage; in the coarse quantization stage, the two-stage output network directly uses the differential signal generated by the common-source common-gate-common-source two-stage inverter as the final output of the dynamic amplifier; in the level shift stage, the two-stage output network uses the differential signal generated by the common-source common-gate-common-source two-stage inverter superimposed with the output result of the coarse quantization stage as the final output of the dynamic amplifier.

[0011] Furthermore, the power supply capacitor network includes a capacitor C RES And four switches S1~S4, one end of S1 is connected to the power supply voltage VDD, the other end of S1 is connected to one end of S2 and C RES One end of S2 is connected to the common source and common gate-common source double-stage inverter, C RESThe other end of is connected to one end of S3 and one end of S4, the other end of S3 is grounded to VSS, and the other end of S4 is connected to the common-source common-gate-common-source double-stage inverter.

[0012] Furthermore, in the reset phase, S1 and S3 are closed, S2 and S4 are open, and capacitor C RES During the amplification phase, S1 and S3 are disconnected, S2 and S4 are closed, and the capacitor C RES Power is supplied to the cascode-common-source two-stage inverter.

[0013] Further, the common-source common-gate-common-source two-stage inverter includes four PMOS tubes M3, M4, M7, M8, four NMOS tubes M1, M2, M5, M6 and eight switches S5~S12, wherein the source of M3 is connected to the source of M4 and the other end of S2, the drain of M3 is connected to the source of M7, the drain of M7 is connected to the drain of M5 and serves as the inverting output end of the common-source common-gate-common-source two-stage inverter, the source of M5 is connected to the drain of M1, the gate of M3 is connected to one end of S7, one end of S5 and the gate of M1 and serves as the non-inverting input end of the dynamic amplifier, the other end of S7 is connected to the gate of M7 and one end of S11, the other end of S11 is grounded VSS, the other end of S5 is connected to the gate of M5 and one end of S9, and S The other end of 9 is connected to the power supply voltage VDD, the drain of M4 is connected to the source of M8, the drain of M8 is connected to the drain of M6 and serves as the non-inverting output end of the common-source common-gate-common-source two-stage inverter, the source of M6 is connected to the drain of M2, the gate of M4 is connected to one end of S8, one end of S6 and the gate of M2 and serves as the inverting input end of the dynamic amplifier, the other end of S8 is connected to the gate of M8 and one end of S12, the other end of S12 is grounded to VSS, the other end of S6 is connected to the gate of M6 and one end of S10, the other end of S10 is connected to the power supply voltage VDD, the source of M1 is connected to the source of M2 and the other end of S4; the body potential of M1, M2, M5 and M6 is grounded to VSS, and the body potential of M3, M4, M7 and M8 is connected to the power supply voltage VDD.

[0014] Furthermore, in the coarse quantization stage, S5 to S8 are closed and S9 to S12 are opened; in the level shifting stage, S5 to S8 are opened and S9 to S12 are closed.

[0015] Furthermore, the two-stage output network includes two auxiliary capacitors C LSP and C LSN And six switches S13~S18, one end of S13 is connected to one end of S17 and connected to the inverting output end of the common source common gate-common source double stage inverter, and the other end of S13 is connected to C LSN One end of the dynamic amplifier is connected to the inverting output terminal, C LSNThe other end of S14 is connected to the other end of S17 and one end of S15. The other end of S15 is connected to the common mode voltage VCM. One end of S14 is connected to one end of S18 and connected to the positive phase output end of the common source and common gate-common source two-stage inverter. The other end of S14 is connected to C LSP One end of the dynamic amplifier is connected to the positive output terminal, C LSP The other end of is connected to the other end of S18 and one end of S16, and the other end of S16 is connected to the common mode voltage VCM.

[0016] Furthermore, in the reset phase, S13~S18 are all closed, and the auxiliary capacitor C LSP and C LSN Both ends of the common-source common-gate-common-source dual-stage inverter are connected to the common-mode voltage VCM at the same time to complete the zeroing of the amplification result of the common-source common-gate-common-source dual-stage inverter; in the coarse quantization stage, S13~S16 are closed, S17 and S18 are disconnected, and the output signal of the common-source common-gate-common-source dual-stage inverter has an auxiliary capacitor C LSP and C LSN In the level shift stage, S13~S16 are disconnected, S17 and S18 are closed, and the auxiliary capacitor C LSP and C LSN The drain voltage of M5~M8 is shifted to the common mode voltage to facilitate closed-loop charge transfer.

[0017] A fully differential switched capacitor closed-loop amplifier circuit includes a sampling switched capacitor circuit, an integrating switched capacitor circuit and a dynamic amplifier. The sampling switched capacitor circuit is connected to the dynamic amplifier. The integrating switched capacitor circuit is connected across the input and output ends of the dynamic amplifier. The dynamic amplifier adopts the above-mentioned dual-stage amplification dynamic amplifier.

[0018] The dual-stage amplification dynamic amplifier of the present invention can solve the power supply problem in the CLS technology to improve the equivalent DC gain of the dynamic amplifier, avoid the increase of the capacitor area, and improve the process robustness of the amplifier. Experimental results show that the present invention can achieve an equivalent DC gain of 72.5dB, and does not require additional power supply capacitors in the level shift stage, nor does it require control of the body potential of the transistor, so that the dynamic amplifier can achieve an increase in DC gain with a lower circuit cost and maintain the stability of the gain under multiple different process angles. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural block diagram of the dynamic amplifier of the present invention.

[0020] Figure 2 The figure is a schematic diagram of a circuit structure of a dynamic amplifier according to the present invention.

[0021] Figure 3 It is a circuit connection diagram of the dynamic amplifier of the present invention in the coarse quantization stage.

[0022] Figure 4 It is a circuit connection diagram of the dynamic amplifier of the present invention in the level shift stage.

[0023] Figure 5 The figure is a schematic diagram of the structure of a switched capacitor closed-loop amplifier circuit using the dynamic amplifier of the present invention.

[0024] Figure 6 The figure is a timing diagram of a switched capacitor closed-loop amplifier circuit using the dynamic amplifier of the present invention.

[0025] Figure 7 It is a schematic diagram of the gain simulation results of the dynamic amplifier of the present invention. DETAILED DESCRIPTION

[0026] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0027] like Figure 1 As shown, the high-gain low-cost dynamic amplifier of the present invention comprises a power supply capacitor network (C RES ), a fully differential common-source common-gate-common-source two-stage inverter, and a fully differential two-stage output network, a total of three parts.

[0028] Figure 2 The figure shows an implementation circuit structure of a high-gain and low-cost dynamic amplifier of the present invention, wherein the power supply capacitor network includes a capacitor C RES And switches S1, S2, S3, and S4 that control the charging and discharging of the capacitor.

[0029] The cascode-common-source dual-stage inverter includes input NMOS transistors M1 and M2, input PMOS transistors M3 and M4, NMOS cascode transistors M5 and M6, PMOS cascode transistors M7 and M8, switches S5, S6, S9 and S10 for controlling M5 and M6, and switches S7, S8, S11 and S12 for controlling M7 and M8.

[0030] The dual-stage output network includes two auxiliary capacitors C LSP , C LSN And switches S13, S14, S15, S16, S17, and S18 connected to the control auxiliary capacitor.

[0031] Capacitor C RES The upper plate is connected to one end of S1 and S2 at the same time, the other end of S1 is connected to the power supply voltage VDD, and the other end of S2 is connected to the source of M3 and M4. RES The lower plate is connected to one end of S3 and S4 at the same time, the other end of S3 is grounded to VSS, and the other end of S4 is connected to the source of M1 and M2.

[0032] The gate of NMOS transistor M1 is connected to the amplifier input V IP The drain is connected to the source of M5; the gate of NMOS transistor M2 is connected to the amplifier input V IN The drain is connected to the source of M6; the gate of PMOS transistor M3 is connected to the amplifier input V IP The drain is connected to the source of M7; the gate of PMOS transistor M4 is connected to the amplifier input V IN The drain is connected to the source of M8; the gate of the common-source common-gate tube M5 is connected to one end of S5 and S9, and the other end of S5 is connected to the amplifier input V IP The other end of S9 is connected to VDD, the drain of M5 is connected to the drain of M7; the gate of the common-source common-gate tube M6 is connected to one end of S6 and S10, and the other end of S6 is connected to the amplifier input V IN The other end of S10 is connected to VDD, the drain of M6 is connected to the drain of M8; the gate of the common-source common-gate tube M7 is connected to one end of S7 and S11, and the other end of S7 is connected to the amplifier input V IP The other end of S11 is connected to VSS, the drain of M7 is connected to the drain of M5; the gate of the common-source common-gate tube M8 is connected to one end of S8 and S12, and the other end of S8 is connected to the amplifier input V IN The other end of S12 is connected to VSS, the drain of M8 is connected to the drain of M6; the body potentials of all NMOS transistors are connected to VSS, and the body potentials of all PMOS transistors are connected to VDD.

[0033] Auxiliary capacitor C LSN The upper plate is connected to the amplifier output V ON , the lower plate is connected to one end of S15, and the other end of S15 is connected to the common mode voltage VCM; C LSN The lower plate is connected to one end of S17, and the other end is connected to the drain of M5 and M7; the auxiliary capacitor C LSP The upper plate is connected to the amplifier output V OP , the lower plate is connected to one end of S16, and the other end of S16 is connected to the common mode voltage VCM; C LSP The lower plate is connected to one end of S18, and the other end is connected to the drain of M6 and M8; one end of S13 is connected to the output V ON , the other end is connected to the drain of M5 and M7, and one end of S14 is connected to the output V OP , and the other end is connected to the drain of M6 and M8.

[0034] The circuit connection of the dynamic amplifier in the sub-stage 1-coarse quantization stage of this embodiment is as follows Figure 3 As shown, C RESThe upper plate is connected to the source of M3 and M4 through S2, C RES The lower plate is connected to the source of M1 and M2 through S4, C RES The transistors are configured as a cascode inverter, with the gates of M1, M3, M5, and M7 connected to the amplifier input V IP Connect the gates of M2, M4, M6, and M8 to the amplifier input V IN Connection; the drain of the transistor is connected to V through S13, S14 ON 、V OP Connected, auxiliary capacitor C LSN , C LSP The lower plate of is connected to VCM through S15 and S16. After the coarse quantization is completed, the amplification result is stored in the auxiliary capacitor C LSN , C LSP superior.

[0035] The circuit connection of the dynamic amplifier in the sub-stage 2 - level shift stage of this embodiment is as follows Figure 4 As shown, C RES The upper plate is connected to the source of M3 and M4 through S2, C RES The lower plate is connected to the source of M1 and M2 through S4, C RES The charge stored after the coarse quantization stage is used to continue to supply power to the common-source inverter. The transistors are configured as common-source inverters, and the gates of M1 and M3 continue to be connected to the amplifier input V IP The gate of M5 is connected to VDD, and the gate of M7 is connected to VSS. M5 and M7 work as two conducting switches at this time; the gates of M2 and M4 continue to be connected to the amplifier input V IN The gate of M6 is connected to VDD, and the gate of M8 is connected to VSS. M6 and M8 work as two conducting switches at this time. The drain of the transistor is connected to the auxiliary capacitor C through S17 and S18 respectively. LSN , C LSP The lower plate is connected to the auxiliary capacitor C LSN , C LSP The upper plate of the amplifier is connected to the output V ON 、V OP In this operation, the coarse quantization result is from V ON 、V OP By subtracting the upper phase, the level of the transistor drain is shifted to VCM, realizing the level shift operation.

[0036] like Figure 5 As shown, the dynamic amplifier of this embodiment can be successfully applied to a fully differential switched capacitor amplifier circuit. The fully differential amplifier circuit includes a sampling switch, an integrating switch, a sampling capacitor C SP and C SN, Integral capacitor C INTP and C INTN The dual-stage dynamic amplifier of the present invention and the operating timing of the switched capacitor amplifier are as follows: Figure 6 As shown:

[0037] φ1 switching clock stage, the switched capacitor circuit is sampling, the input signal V IP 、V IN is sampled to C SP , C SN The dual-stage dynamic amplifier performs a reset operation, C RES Complete charging. φ2 switching clock phase, complete from C SP , C SN to C INTP , C INTN The charge transfer, the switched capacitor circuit completes the amplification function, and the amplification stage is divided into two sub-stages φ 21 Coarse Quantization and φ 22 Level shift. φ 21 The switching clock is the coarse quantization stage. The circuit is as follows Figure 3 The connection shown in the figure obtains the coarse quantization result. The gain of the amplifier in the coarse quantization stage is the DC gain of the common source and common gate inverter; φ 22 The switching clock is the level shift stage, and the circuit is as follows Figure 4 The connection shown here completes the level shift operation and the output signal V OP 、V ON The drain level of the transistor is shifted to the common-mode voltage VCM. Through the DC gain of the common-source inverter, the virtual ground point of the switched capacitor amplifier is shifted further toward VCM, promoting the SP , C SN to C INTP , C INTN The charge transfer makes the closed-loop amplification process more accurate and improves the equivalent gain of the switched capacitor amplifier.

[0038] like Figure 7 As shown, this embodiment implements a dual-stage amplification dynamic amplifier through a power supply capacitor and 8 transistors under a power supply voltage of 1.2V, and the equivalent DC gain is increased from 52.9dB to 72.5dB; this proves that the dual-stage dynamic amplifier designed in the present invention effectively solves the power supply problem in the level shift stage, without the need to introduce additional power supply capacitors, and without the need to control the body potential of the transistor, etc., effectively saving area and other circuit expenses.

[0039] The above description of the embodiments is to facilitate the understanding and application of the present invention by those skilled in the art. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative work. Therefore, the present invention is not limited to the above embodiments. Improvements and modifications made by those skilled in the art to the present invention based on the disclosure of the present invention should be within the protection scope of the present invention.

Claims

1. A dual-stage amplification dynamic amplifier, characterized in that: It includes a power supply capacitor network, a fully differential common-source common-gate-common-source two-stage inverter, and a fully differential two-stage output network, wherein: The power supply capacitor network is charged in the reset phase and supplies power to the common-source common-gate-common-source dual-stage inverter in the amplification phase; The common-source common-gate-common-source dual-stage inverter is used to generate a set of differential signals after amplifying the input signal; The dual-stage output network is used to perform a level shift operation on the differential signal; The operation of the dynamic amplifier is divided into a reset stage and an amplification stage, and the amplification stage is further divided into a coarse quantization stage and a level shift stage; in the coarse quantization stage, the two-stage output network directly uses the differential signal generated by the common-source common-gate-common-source two-stage inverter as the final output of the dynamic amplifier; in the level shift stage, the two-stage output network uses the differential signal generated by the common-source common-gate-common-source two-stage inverter superimposed with the output result of the coarse quantization stage as the final output of the dynamic amplifier; The power supply capacitor network includes a capacitor C RES And four switches S1~S4, one end of S1 is connected to the power supply voltage VDD, the other end of S1 is connected to one end of S2 and C RES One end of S2 is connected to the common source and common gate-common source double-stage inverter, C RES The other end of is connected to one end of S3 and one end of S4, the other end of S3 is grounded to VSS, and the other end of S4 is connected to a common-source common-gate-common-source dual-stage inverter; The common-source common-gate-common-source dual-stage inverter comprises four PMOS tubes M3, M4, M7, and M8, four NMOS tubes M1, M2, M5, and M6, and eight switches S5 to S12, wherein the source of M3 is connected to the source of M4 and the other end of S2, the drain of M3 is connected to the source of M7, the drain of M7 is connected to the drain of M5 and serves as the inverting output end of the common-source common-gate-common-source dual-stage inverter, the source of M5 is connected to the drain of M1, the gate of M3 is connected to one end of S7, one end of S5, and the gate of M1 and serves as the non-inverting input end of the dynamic amplifier, the other end of S7 is connected to the gate of M7 and one end of S11, the other end of S11 is grounded VSS, the other end of S5 is connected to the gate of M5 and one end of S9, the other end of S9 is grounded VSS, the other end of S5 is connected to the gate of M5 and one end of S9, and the other end of S9 is grounded VSS. One end is connected to the power supply voltage VDD, the drain of M4 is connected to the source of M8, the drain of M8 is connected to the drain of M6 and serves as the non-inverting output end of the common-source common-gate-common-source two-stage inverter, the source of M6 is connected to the drain of M2, the gate of M4 is connected to one end of S8, one end of S6 and the gate of M2 and serves as the inverting input end of the dynamic amplifier, the other end of S8 is connected to the gate of M8 and one end of S12, the other end of S12 is grounded to VSS, the other end of S6 is connected to the gate of M6 and one end of S10, the other end of S10 is connected to the power supply voltage VDD, the source of M1 is connected to the source of M2 and the other end of S4; the body potentials of M1, M2, M5 and M6 are grounded to VSS, and the body potentials of M3, M4, M7 and M8 are connected to the power supply voltage VDD; The dual-stage output network includes two auxiliary capacitors C LSP and C LSN And six switches S13 to S18, wherein one end of S13 is connected to one end of S17 and connected to the inverting output end of the common source common gate-common source double stage inverter, and the other end of S13 is connected to C LSN One end of the dynamic amplifier is connected to the inverting output terminal, C LSN The other end of S14 is connected to the other end of S17 and one end of S15. The other end of S15 is connected to the common mode voltage VCM. One end of S14 is connected to one end of S18 and connected to the positive phase output end of the common source and common gate-common source two-stage inverter. The other end of S14 is connected to C LSP One end of the dynamic amplifier is connected to the positive output terminal, C LSP The other end of is connected to the other end of S18 and one end of S16, and the other end of S16 is connected to the common mode voltage VCM.

2. The dual-stage amplification dynamic amplifier according to claim 1, characterized in that: In the reset phase, S1 and S3 are closed, S2 and S4 are open, and capacitor C RES During the amplification phase, S1 and S3 are disconnected, S2 and S4 are closed, and the capacitor C RES Power is supplied to the cascode-common-source two-stage inverter.

3. The dual-stage amplification dynamic amplifier according to claim 1, characterized in that: In the coarse quantization stage, S5-S8 are closed and S9-S12 are opened; in the level shift stage, S5-S8 are opened and S9-S12 are closed.

4. The dual-stage amplification dynamic amplifier according to claim 1, characterized in that: In the reset stage, S13~S18 are all closed, and the auxiliary capacitor C LSP and C LSN Both ends of the common-mode voltage VCM are connected to the common-mode voltage VCM at the same time, completing the zeroing of the amplification result of the common-source common-gate-common-source two-stage inverter; in the coarse quantization stage, S13~S16 are closed, S17 and S18 are disconnected, and the output signal of the common-source common-gate-common-source two-stage inverter has an auxiliary capacitor C LSP and C LSN On the top, we get the rough quantization result; In the level shift stage, S13~S16 are disconnected, S17 and S18 are closed, and the auxiliary capacitor C LSP and C LSN The drain voltage of M5-M8 is shifted to the common mode voltage to facilitate closed-loop charge transfer.

5. A fully differential switched capacitor closed-loop amplifier circuit, comprising a sampling switched capacitor circuit, an integrating switched capacitor circuit and a dynamic amplifier, wherein the sampling switched capacitor circuit is connected to the dynamic amplifier, and the integrating switched capacitor circuit is connected across the input and output ends of the dynamic amplifier, characterized in that: The dynamic amplifier is a dual-stage amplification dynamic amplifier as claimed in any one of claims 1 to 4.

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