Analog-to-digital converter and automatic analog-to-digital conversion rate adjusting method
By building a conversion rate automatic adjuster in an analog-to-digital converter, the clock frequency and sampling clock frequency number are automatically adjusted, and the accuracy of the analog-to-digital converter is solved, and high accuracy is achieved analog digital conversion.
Patent Information
- Application Number
- CN202311828457.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-17
- Filing Date
- 2023-12-27
- Publication Date
- 2025-01-17
AI Technical Summary
The accuracy of analog-to-digital converters may be affected by the weak input signals and the load effect of resistive voltage divider circuits, resulting in a decrease in accuracy, which is difficult for the existing technology to effectively solve this problem.
Design an analog-digital converter with automatic adjustment of analog-digital conversion rate. Through the built-in automatic adjustment of conversion rate, the clock frequency and sampling clock frequency are automatically adjusted to ensure accurate and accurate within the system bandwidth range. Distortion analog-to-digital conversion. The adjuster gradually adjusts the conversion rate parameters by testing the input signal until the evaluation error is no higher than the allowable error, achieving the optimal conversion rate.
Ensure the accuracy of the analog-to-digital converter, avoids manual trial and error and lengthy debugging processes, can automatically find the optimal conversion rate of unknown inputs, and adapt to input signals of various signal strengths.
Smart Images
Figure CN119324709A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an analog-to-digital converter (ADC). Background Art
[0002] The accuracy of the analog-to-digital converter may be affected by a weak input signal. In some cases, the load effect produced by the resistor divider circuit may also affect the accuracy of the analog-to-digital converter.
[0003] How to ensure the accuracy of analog-to-digital converters is a major issue in this technical field. Summary of the invention
[0004] The present invention discloses an analog-to-digital converter (ADC) with an automatic adjustment function for analog-to-digital conversion rate. The ADC automatically adjusts the analog-to-digital conversion rate according to input terminal characteristics, so that the analog-to-digital conversion is accurate and distortion-free while meeting the bandwidth requirements of the system.
[0005] An analog-to-digital converter implemented according to one embodiment of the present invention includes an analog-to-digital conversion hardware and a controller. The controller is coupled to the analog-to-digital conversion hardware and has a conversion rate automatic adjuster. The conversion rate automatic adjuster operates the analog-to-digital conversion hardware to convert a test input with a first conversion rate parameter, and collects a first evaluation value converted from the analog-to-digital conversion hardware. Compared with the first conversion rate parameter, the conversion rate automatic adjuster operates the analog-to-digital conversion hardware to convert the test input with a second conversion rate parameter at a higher speed, and collects a second evaluation value converted from the analog-to-digital conversion hardware, and the second evaluation value is an evaluation error away from the first evaluation value. In response to the evaluation error being higher than an allowable error, the conversion rate automatic adjuster automatically updates the second conversion rate parameter, operates the analog-to-digital conversion hardware at a reduced speed, and updates the second evaluation value until the evaluation error is not higher than the allowable error, and then the analog-to-digital conversion hardware is allowed to apply the latest version of the second conversion rate parameter.
[0006] In one embodiment, the conversion rate parameters adjusted by the conversion rate automatic adjuster include a clock frequency and a sampling clock frequency number. The first conversion rate parameter is set at a first clock frequency and a first sampling clock frequency number. In the second conversion rate parameter, the frequency of a second clock frequency that is changed by trial and error is always not lower than the first clock frequency. In the second conversion rate parameter, the frequency of a second sampling clock frequency that is changed by trial and error is always not more than the first sampling clock frequency number.
[0007] In one embodiment, the conversion rate automatic adjuster sets the first clock frequency to a minimum clock frequency, and sets the first sampling clock frequency number to a maximum sampling clock frequency number. In one embodiment, the conversion rate automatic adjuster sets the second clock frequency to start at a maximum clock frequency, and sets the second sampling clock frequency number to start at a minimum sampling clock frequency number.
[0008] In one embodiment, the conversion rate automatic adjuster automatically increases the second sampling clock frequency by an increment in response to the estimated error being higher than the allowable error. If the increment result exceeds the maximum sampling clock frequency, the conversion rate automatic adjuster decreases the frequency of the second clock frequency by a decrement and resets the second sampling clock frequency to the minimum sampling clock frequency.
[0009] In one implementation manner, the conversion rate parameter adjusted by the conversion rate automatic adjuster only includes the clock frequency but does not include the sampling clock frequency.
[0010] In one implementation manner, the conversion rate parameter adjusted by the conversion rate automatic adjuster only includes the sampling clock frequency number, but does not include the clock frequency.
[0011] A further implementation method is to realize the above concept as an automatic adjustment method for analog-to-digital conversion rate.
[0012] The present invention can ensure the accuracy of the analog-to-digital converter.
[0013] The following is a detailed description of the present invention with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 An analog-to-digital converter 104 on a chip 102 is illustrated according to one embodiment of the present invention;
[0015] Figure 2 is a flow chart, according to an embodiment of the present invention Figure 1 The conversion rate automatic adjustment process is executed by the conversion rate automatic adjuster 120 built into the controller 114 in the analog-to-digital converter 104; and
[0016] Figure 3 Explanation based on record 300 Figure 2 process.
[0017] Figure Number:
[0018] 102: Chip
[0019] 104:Analog-to-digital converter
[0020] 106: sampling and saving circuit
[0021] 108:12-bit Digital to Analog Converter
[0022] 110:Analog control logic
[0023] 112: Successive approximation analog-to-digital conversion register
[0024] 114: Controller
[0025] 116: Digital Control Logic
[0026] 118: Clock frequency generator
[0027] 120: Automatic conversion rate adjuster
[0028] 300: Record
[0029] CH0…CH15, Vref: chip pin 102
[0030] Dout: Analog-to-digital conversion result
[0031] Mux: Multiplexer
[0032] S202…S214: Steps
[0033] Vtest: test input DETAILED DESCRIPTION
[0034] The following description lists various embodiments of the present invention to introduce the basic concept of the present invention and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the claims.
[0035] Analog-to-digital converters may be used in a variety of chips. The various input signals and unpredictable signal strengths may greatly affect the accuracy of analog-to-digital conversion. For example, some sensors do not use an amplification circuit, and the sensed signal strength is extremely weak, causing the analog-to-digital converter to be unable to convert it into a correct digital value.
[0036] The present invention provides an analog-to-digital converter with an automatic analog-to-digital conversion rate adjustment function, wherein a controller operating analog-to-digital conversion hardware has a built-in automatic conversion rate adjuster to adjust a suitable analog-to-digital conversion rate for various input signals. The adjusted conversion rate parameters include: clock frequency, and / or the number of clocks for sample and hold.
[0037] Figure 1According to one embodiment of the present invention, an analog-to-digital converter 104 on a chip 102 is illustrated. The analog-to-digital converter 104 can receive various inputs through a multiplexer Mux, and then capture them through a sampling and saving circuit (S / Hcircuit) 106, and convert them by analog-to-digital conversion hardware to obtain an analog-to-digital conversion result Dout. The figure shows that the analog-to-digital conversion hardware is implemented by a successive approximation analog-to-digital converter (successive approximation ADC, which obtains the reference voltage from the chip 102 pin Vref), wherein the detailed modules include: a 12-bit digital-to-analog converter (12-bit DAC) 108, an analog control logic 110, and a successive approximation analog-to-digital conversion register 112. Other analog-to-digital conversion technologies can also be applied to implement the analog-to-digital conversion hardware.
[0038] In particular, the analog-to-digital converter 104 includes a controller 114, which includes a digital control logic 116, a clock frequency generator (ADC clock generator) 118, and an auto conversion rate adjuster 120. The digital control logic 116 controls the sample-save circuit 106 to set a sampling clock frequency. The clock frequency generator 118 generates a clock frequency, and further includes a function for controlling the analog control logic 110. The auto conversion rate adjuster 120 is used to control the digital control logic 116 to adjust the sampling clock frequency, or / and to control the clock frequency generator 118 to adjust the frequency of the generated clock frequency to meet the conversion rate of the system bandwidth and obtain an ideal analog-to-digital conversion result Dout. The sampling clock frequency and the clock frequency are both conversion rate parameters of the analog-to-digital converter 104. The present invention uses the auto conversion rate adjuster 120 to complete the automatic adjustment of these conversion rate parameters.
[0039] As shown in the figure, the multiplexer Mux is coupled to the inputs of the pins CH0-CH15 of the chip 102 and the inputs of other modules on the chip 102, and is further coupled to a test input Vtest to realize automatic adjustment of the conversion rate parameters.
[0040] One implementation method is to use a successive approximation method to find a conversion rate that meets the system bandwidth. The clock frequency is used as a coarse adjustment factor, and the sampling clock frequency is used as a fine adjustment factor.
[0041] Figure 2 is a flow chart, according to an embodiment of the present invention Figure 1 The conversion rate automatic adjustment procedure is executed by the conversion rate automatic adjuster 120 built into the controller 114 in the analog-to-digital converter 104 . Figure 1The analog-to-digital conversion hardware has a 12-bit analog-to-digital conversion capability. The process is to test half of the 12-bit conversion capability and automatically find the best conversion rate of the analog-to-digital converter 104 step by step. In the following evaluations, the simulated test input Vtest is 1 / 2VDD (half of the maximum input VDD), and the ideal analog-to-digital conversion result Dout is 2048. Other implementations can set the test input Vtest to other values.
[0042] Step S202 is executed at the initial time (t=0), the conversion rate automatic tuner 120 operates the analog-to-digital conversion hardware to convert the test input Vtest (=VDD / 2) with a first conversion rate parameter, and collects its analog-to-digital conversion result Dout as a first evaluation value Rold, and operates the analog-to-digital conversion hardware to convert the test input Vtest (=VDD / 2) with a second conversion rate parameter, and collects its analog-to-digital conversion result Dout as a second evaluation value Rnew. The first conversion rate parameter is slower than the second conversion rate parameter, and can convert the test input Vtest (=VDD / 2) into a more accurate analog-to-digital conversion result Dout (approximately 2048). One implementation method allows the first conversion rate parameter to use the lowest clock frequency Vmin and the maximum sampling clock frequency S&H_max, and the generated first evaluation value Rold must have the highest accuracy and can be used as a control group. The second conversion rate parameter is used for the experimental group. During the initial execution (t=0), the clock frequency Vtemp used by the second conversion rate parameter adopts the highest frequency clock frequency Vmax, and the sampling clock frequency S&H_temp adopts the minimum sampling clock frequency S&H_min, which is the highest speed setting. In other implementations, the first conversion rate parameter may also have other designs, not limited to the slowest setting. The initial second conversion rate parameter may also have other designs, not limited to the fastest setting.
[0043] In step S204, the conversion rate automatic tuner 120 determines whether the second evaluation value (Rnew) is close to the first evaluation value (Rold), and whether the evaluation error (Rold-Rnew) between the two satisfies a tolerance error; for example, if the condition Rold-Rnew<=2LSB is satisfied, the difference between the two analog-to-digital conversion results Rnew and Rold does not exceed 2. If the condition (Rold-Rnew<=2LSB) is not satisfied in step S204, the conversion rate automatic tuner 120 proceeds to step S206 to continue to search for the best conversion rate. Otherwise, the conversion rate automatic tuner 120 determines that the best conversion rate has been found, and the process proceeds to step S208 to set the analog-to-digital conversion hardware to adopt the best conversion rate found (i.e., the latest version of the clock frequency Vtemp, and the sampling clock frequency S&H_temp).
[0044] When the optimal conversion rate has not been found, the conversion rate automatic adjuster 120 performs fine adjustment of the conversion rate by adjusting the sampling clock frequency S&H_temp in a step-by-step manner in step S206. In one embodiment, the sampling clock frequency fine adjustment includes: S&H_temp=S&H_temp+S&H_step, and t++. The increment of the sampling clock frequency S&H_temp is S&H_step, and the test count t is incremented. The conversion rate automatic adjuster 120 performs step S210 to check whether the sampling clock frequency S&H_temp exceeds the maximum sampling clock frequency S&H_max (S&H_temp>S&H_max??). If not, the conversion rate automatic adjuster 120 performs step S212 to update the second evaluation value Rnew using the clock frequency Vtemp and the sampling clock frequency S&H_temp. Otherwise, the conversion rate automatic adjuster 120 performs step S214 to change the clock frequency Vtemp to roughly adjust the conversion rate.
[0045] In step S214, the conversion rate automatic adjuster 120 adjusts the clock frequency Vtemp in a step-down manner (frequency Vtemp = Vtemp - Vstep, Vstep is the frequency decrease amount of the clock frequency Vtemp), trying to significantly reduce the speed to ensure the accuracy of analog-to-digital conversion. In one embodiment, while the clock frequency Vtemp is decreasing, the sampling clock frequency number S&H_temp is reset to the minimum sampling clock frequency number, S&H_temp = S&H_min. Then, the conversion rate automatic adjuster 120 performs step S212, sampling the clock frequency Vtemp and the sampling clock frequency number S&H_temp to update the second evaluation value Rnew.
[0046] After the second evaluation value Rnew is updated in step S212, the process returns to step S204 to compare the experimental group (Rnew) and the control group (Rold) again to determine whether the clock frequency Vtemp and the sampling clock frequency S&H_temp are the optimal conversion rate settings.
[0047] During the automatic trial and error process, the frequency of the clock frequency Vtemp of the trial and error is always not lower than the lowest clock frequency Vmin, and the sampling clock frequency number S&H_temp of the trial and error is always not higher than the maximum sampling clock frequency number S&H max.
[0048] Figure 3 Explanation based on record 300 Figure 2In addition to the content of record 300, at the initial execution (t=0), the first evaluation value Rold for comparison generated by the slowest first conversion rate parameter (the lowest clock frequency Vmin (1MHz) and the maximum sampling clock frequency S&H_max (240)) is 2048. Record 300 shows the experimental group data (Vtemp, S&H_temp, Rnew) and the evaluation error (Rold-Rnew).
[0049] When the count t is 0, the second evaluation value Rnew generated by the highest clock frequency Vmax (90 MHz) and the minimum sampling clock frequency S&H_min (4) is 800, which differs from the first evaluation value Rold by 1248 (=2048-800), which is much larger than 2. The conversion rate automatic tuner 120 starts stepping trial and error (extending S&H_temp).
[0050] When the count t is 1 to 4, the conversion rate automatic tuner 120 maintains the highest frequency clock frequency Vmax (90MHz), but gradually increases the sampling clock frequency S&H_temp (60→120→180→240). However, t=4 shows that the evaluation error (Rold-Rnew) is 1133, which is still large. The conversion rate automatic tuner 120 slows down the clock frequency Vtemp (when the count t is 5 to 9, the clock frequency Vtemp drops to 86MHz) and conducts more bold trial and error.
[0051] When the count t is 10, the clock frequency Vtemp drops to 82MHz, and the evaluation error (Rold-Rnew) converges significantly. When the count t is 11, the clock frequency Vtemp remains at 82MHz, the sampling clock frequency S&H_temp is extended to 60, and the evaluation error (Rold-Rnew) is only 2. The conversion rate automatic adjuster 120 determines that the best conversion rate is found, fills the control register of the analog-to-digital converter 104, sets the digital control logic 116 to control the sample and hold circuit 106 with the best sampling clock frequency of 60, and sets the clock frequency generator 118 to generate a clock frequency of 82MHz.
[0052] When facing unknown sensor signals, engineers have to check the sensor electrical specifications and then go through lengthy trial and error to make the analog-to-digital conversion hardware operate at a better conversion rate. In contrast, the conversion rate automatic adjuster 120 of the present invention can automatically find the best conversion rate for unknown inputs when it is activated.
[0053] In some implementations, the slew rate stepping can be performed only on the clock frequency Vtemp.
[0054] In some implementations, the conversion rate stepping adjustment may be performed only on the sampling clock frequency S&H_temp.
[0055] In summary, one embodiment of the present invention discloses an analog-to-digital converter 104 including an analog-to-digital conversion hardware (108-112) and a controller 114. The controller 114 is coupled to the analog-to-digital conversion hardware and has a conversion rate automatic tuner 120. The conversion rate automatic tuner 120 operates the analog-to-digital conversion hardware to convert a test input Vtest with a first conversion rate parameter, and collects a first evaluation value Rold converted from the analog-to-digital conversion hardware. Compared with the first conversion rate parameter, the conversion rate automatic tuner 120 operates the analog-to-digital conversion hardware to convert the test input Vtest with a second conversion rate parameter at a higher speed, and collects a second evaluation value Rnew converted from the analog-to-digital conversion hardware, and the second evaluation value Rnew is an evaluation error (Rold-Rnew) from the first evaluation value Rold. In response to the evaluation error being higher than an allowable error (e.g., 2LSB), the conversion rate automatic tuner 120 automatically updates the second conversion rate parameter and slows down the analog-to-digital conversion hardware to update the second evaluation value Rnew until the evaluation error (Rold-Rnew) is no higher than the allowable error (2LSB), and then the analog-to-digital conversion hardware applies the latest version of the second conversion rate parameter.
[0056] The above concept can be further used to implement an automatic calibration method for analog-to-digital conversion rate. Any automatic calibration procedure of the conversion rate automatic calibrator 120 built into the analog-to-digital converter belongs to the scope of the present invention.
[0057] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the attached claims.
Claims
1. An analog-to-digital converter, characterized in that: include: - Analog-to-digital conversion hardware; as well as A controller coupled to the analog-to-digital conversion hardware and having a conversion rate automatic adjuster; in: The conversion rate automatic tuner operates the analog-to-digital conversion hardware to convert a test input with a first conversion rate parameter, and collects a first evaluation value converted from the analog-to-digital conversion hardware; The conversion rate automatic tuner operates the analog-to-digital conversion hardware to convert the test input at a second conversion rate parameter at a higher speed than the first conversion rate parameter, and collects a second evaluation value converted from the analog-to-digital conversion hardware, wherein the second evaluation value is an evaluation error from the first evaluation value; In response to the evaluation error being higher than an allowable error, the conversion rate automatic adjuster automatically updates the second conversion rate parameter and reduces the speed of the analog-to-digital conversion hardware to update the second evaluation value until the evaluation error is no higher than the allowable error, and then the analog-to-digital conversion hardware is caused to apply the latest version of the second conversion rate parameter.
2. The analog-to-digital converter according to claim 1, wherein: The conversion rate parameters adjusted by the conversion rate automatic adjuster include a clock frequency and a sampling clock frequency number; The first conversion rate parameter is set at a first clock frequency and a first sampling clock frequency; In the second conversion rate parameter, a frequency of a second clock frequency that is varied by trial and error is always not lower than the first clock frequency; and In the second conversion rate parameter, a second sampling clock frequency value varied by trial and error is always no greater than the first sampling clock frequency value.
3. The analog-to-digital converter according to claim 2, wherein: The conversion rate automatic adjuster sets the first clock frequency as a minimum clock frequency, and sets the first sampling clock frequency as a maximum sampling clock frequency.
4. The analog-to-digital converter according to claim 3, wherein: The conversion rate automatic adjuster sets the second clock frequency to start from a highest frequency clock frequency, and sets the second sampling clock frequency to start from a lowest sampling clock frequency.
5. The analog-to-digital converter according to claim 4, wherein: In response to the estimated error being higher than the allowable error, the conversion rate automatic tuner automatically increases the second sampling clock frequency by an increment; and If the increment result exceeds the maximum sampling clock frequency, the conversion rate automatic adjuster decreases the frequency of the second clock frequency by a decrement amount and resets the second sampling clock frequency to the minimum sampling clock frequency.
6. The analog-to-digital converter according to claim 1, wherein: The conversion rate parameter adjusted by the conversion rate automatic adjuster includes a clock frequency; The first conversion rate parameter is set at a first clock frequency; and In the second conversion rate parameter, a second clock frequency that is varied by trial and error has a frequency that is not always lower than the first clock frequency.
7. The analog-to-digital converter according to claim 6, wherein: The conversion rate automatic adjuster sets the first clock frequency to a lowest frequency clock frequency, and sets the second clock frequency to start from a highest frequency clock frequency; and In response to the estimated error being higher than the allowable error, the conversion rate auto-tuner automatically adjusts the conversion rate to A decrement decreases the frequency of the second clock frequency.
8. The analog-to-digital converter according to claim 1, wherein: The conversion rate parameter adjusted by the conversion rate automatic adjuster includes a sampling clock frequency; The first conversion rate parameter is set at a first sampling clock frequency; and In the second conversion rate parameter, a second sampling clock frequency value varied by trial and error is always no greater than the first sampling clock frequency value.
9. The analog-to-digital converter according to claim 8, wherein: The conversion rate automatic adjuster sets the first sampling clock frequency to a maximum sampling clock frequency; The conversion rate automatic adjuster sets the second sampling clock frequency to start from a minimum sampling clock frequency; and In response to the estimated error being higher than the allowable error, the conversion rate auto-tuner automatically increases the second sampling clock frequency by an increment.
10. A method for automatically adjusting analog-to-digital conversion rate, characterized in that: The conversion rate parameters used to adjust an analog-to-digital conversion hardware include: A conversion rate automatic tuner is provided, which operates the analog-to-digital conversion hardware to convert a test input with a first conversion rate parameter, and collects a first evaluation value converted from the analog-to-digital conversion hardware, and operates the analog-to-digital conversion hardware to convert the test input with a second conversion rate parameter at a higher speed than the first conversion rate parameter, and collects a second evaluation value converted from the analog-to-digital conversion hardware, wherein the second evaluation value is an evaluation error from the first evaluation value; In which, corresponding to the evaluation error being higher than an allowable error, the conversion rate automatic adjuster automatically updates the second conversion rate parameter and slows down the analog-to-digital conversion hardware to update the second evaluation value until the evaluation error is no higher than the allowable error, and then the analog-to-digital conversion hardware is allowed to apply the latest version of the second conversion rate parameter.
11. The method for automatically adjusting analog-to-digital conversion rate according to claim 10, wherein: The conversion rate parameters adjusted by the conversion rate automatic adjuster include a clock frequency and a sampling clock frequency number; The first conversion rate parameter is set at a first clock frequency and a first sampling clock frequency; In the second conversion rate parameter, a frequency of a second clock frequency that is varied by trial and error is always not lower than the first clock frequency; and In the second conversion rate parameter, a second sampling clock frequency value varied by trial and error is always no greater than the first sampling clock frequency value.
12. The method for automatically adjusting analog-to-digital conversion rate according to claim 11, wherein: The conversion rate automatic adjuster sets the first clock frequency as a minimum clock frequency, and sets the first sampling clock frequency as a maximum sampling clock frequency.
13. The method for automatically adjusting analog-to-digital conversion rate according to claim 12, wherein: The conversion rate automatic adjuster sets the second clock frequency to start from a highest frequency clock frequency, and sets the second sampling clock frequency to start from a lowest sampling clock frequency.
14. The method for automatically adjusting analog-to-digital conversion rate according to claim 13, wherein: In response to the estimated error being higher than the allowable error, the conversion rate automatic tuner automatically increases the second sampling clock frequency by an increment; and If the increment result exceeds the maximum sampling clock frequency, the conversion rate automatic adjuster decreases the frequency of the second clock frequency by a decrement amount and resets the second sampling clock frequency to the minimum sampling clock frequency.
15. The method for automatically adjusting analog-to-digital conversion rate according to claim 10, wherein: The conversion rate parameter adjusted by the conversion rate automatic adjuster includes a clock frequency; The first conversion rate parameter is set at a first clock frequency; and In the second conversion rate parameter, a second clock frequency that is varied by trial and error has a frequency that is not always lower than the first clock frequency.
16. The method for automatically adjusting analog-to-digital conversion rate according to claim 15, wherein: The conversion rate automatic adjuster sets the first clock frequency to a lowest frequency clock frequency, and sets the second clock frequency to start from a highest frequency clock frequency; and In response to the estimated error being higher than the allowable error, the conversion rate auto-tuner automatically adjusts the conversion rate to A decrement decreases the frequency of the second clock frequency.
17. The method for automatically adjusting analog-to-digital conversion rate according to claim 10, wherein: The conversion rate parameter adjusted by the conversion rate automatic adjuster includes a sampling clock frequency; The first conversion rate parameter is set at a first sampling clock frequency; and In the second conversion rate parameter, a second sampling clock frequency value varied by trial and error is always no greater than the first sampling clock frequency value.
18. The method for automatically adjusting analog-to-digital conversion rate according to claim 17, wherein: The conversion rate automatic adjuster sets the first sampling clock frequency to a maximum sampling clock frequency; The conversion rate automatic adjuster sets the second sampling clock frequency to start from a minimum sampling clock frequency; and In response to the estimated error being higher than the allowable error, the conversion rate auto-tuner automatically increases the second sampling clock frequency by an increment.