Self-aligned shield gate double-epitaxial super-junction MOSFET and manufacturing method thereof

Abstract

The invention discloses a self-aligned shield gate double-epitaxial super-junction MOSFET and a manufacturing method, and the MOSFET comprises a semiconductor layer which is disposed on a substrate, and the semiconductor layer is internally provided with a source region and a body region which are distributed from the surface to the substrate; a plurality of pairs of side walls arranged on the surface of the semiconductor layer; the gate trench is arranged below the surface of the semiconductor layer between each pair of side walls; a shielding gate and a grid electrode are arranged in the gate trench from bottom to top; the super junction trench is arranged below the surface of the semiconductor layer between two adjacent pairs of side walls, a first epitaxial layer of a first conductive type is arranged on the inner wall of the super junction trench, a second epitaxial layer of a second conductive type is arranged in the first epitaxial layer, and the first epitaxial layer and the second epitaxial layer are connected with the body region through the top. According to the invention, the area of the device can be reduced while the number of photomasks is reduced and self-alignment is realized, and the drift region can be directly changed into the intrinsic semiconductor layer, so that the on-resistance can be reduced while the withstand voltage is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a self-aligned shielded gate dual epitaxial super junction MOSFET and a manufacturing method thereof. Background Art

[0002] Compared with planar MOSFET, super junction (SJ) MOSFET has the characteristics of low on-resistance, fast switching speed, small chip size and low heat generation. Super junction has smaller junction capacitance. For super junction MOSFET, the reduction of resistance will bring obvious benefits, such as lower conduction loss or smaller die at the same on-resistance (Ron). In addition, the reduction of chip area will lead to lower junction capacitance and gate and output charge, which can reduce dynamic loss.

[0003] However, as the device area continues to shrink, the number of processing steps and the number of masks in the manufacturing process also increase, which undoubtedly increases the manufacturing cost. In addition, due to the existence of overlay error, the short-circuit resistance also increases.

[0004] At the same time, how to improve charge balance, further increase voltage resistance, reduce on-resistance, avoid avalanche breakdown and reduce parasitic capacitance have also become important topics for continuous improvement. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and to provide a self-aligned shielded gate dual epitaxial super junction MOSFET and a manufacturing method thereof.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] The present invention provides a self-aligned shielded gate dual epitaxial super junction MOSFET, comprising:

[0008] A semiconductor layer disposed on a substrate, wherein the semiconductor layer is provided with a source region and a body region sequentially distributed from a surface of the semiconductor layer toward the substrate;

[0009] A plurality of pairs of side walls are arranged in parallel on the surface of the semiconductor layer;

[0010] A gate trench is provided below the surface of the semiconductor layer between each pair of the sidewalls, wherein a shielding gate and a gate are provided in the gate trench from bottom to top;

[0011] A super junction trench is provided below the surface of the semiconductor layer between two adjacent pairs of the side walls, a first epitaxial layer of a first conductivity type is provided on the inner wall of the super junction trench, a second epitaxial layer of a second conductivity type is provided in the super junction trench within the first epitaxial layer, and the first epitaxial layer and the second epitaxial layer are connected to the body region through the top facing the surface of the semiconductor layer.

[0012] Further, a drift region of the first conductivity type is provided in the semiconductor layer, and the body region of the second conductivity type, the source region of the first conductivity type, the first epitaxial layer and the second epitaxial layer are located in the drift region; or, the semiconductor layer is an intrinsic semiconductor layer.

[0013] Further, bottoms of the super junction trench and the gate trench pass through the source region and the body region and are located in the semiconductor layer, and a depth of the super junction trench is greater than a depth of the gate trench.

[0014] Further, the first epitaxial layer and the second epitaxial layer are connected to the body region through a first transition connection region of the second conductivity type provided on the top facing the surface of the semiconductor layer; and / or, a second transition connection region of the first conductivity type surrounding the super junction trench and connecting the first epitaxial layer and the body region is also provided in the semiconductor layer below the body region; and / or, the second epitaxial layer has a gradient doping concentration inward along the inner wall of the super junction trench.

[0015] Furthermore, it also includes: a metal layer arranged on the surface of the semiconductor layer, and an interlayer dielectric layer arranged on the surface of the metal layer; the metal layer includes a gate metal separated between each pair of the side walls and connected to the gate, and a source region contact metal separated between two adjacent pairs of the side walls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, and the interlayer dielectric layer is located on the top of the gate metal, the top of the source region contact metal and the top of the side walls.

[0016] The present invention also provides a method for manufacturing a self-aligned shielded gate dual epitaxial super junction MOSFET, comprising:

[0017] providing a substrate, and forming a semiconductor layer on a surface of the substrate;

[0018] Forming a source region of a first conductivity type and a body region of a second conductivity type in the semiconductor layer, which are distributed in sequence from the surface of the semiconductor layer toward the substrate;

[0019] Forming a plurality of first hard mask layer patterns, second hard mask layer patterns contacting both sides of the first hard mask layer patterns, and a third hard mask layer pattern contacting between two of the second hard mask layer patterns on adjacent sides on the surface of the semiconductor layer;

[0020] The second hard mask layer pattern is removed, and then, sidewalls are formed on both sides of the first hard mask layer pattern and both sides of the third hard mask layer pattern, respectively, so as to form a pair of sidewalls formed by two sidewalls on adjacent sides between two adjacent first hard mask layer patterns and the third hard mask layer patterns;

[0021] Forming a gate trench passing through the source region and the body region below the surface of the semiconductor layer between each pair of the sidewalls, and forming a shielding gate and a gate from bottom to top in the gate trench;

[0022] forming a fourth hard mask layer pattern between each pair of the spacers, and then removing the first hard mask layer pattern and the third hard mask layer pattern;

[0023] A super junction trench passing through the source region and the body region is formed below the surface of the semiconductor layer between two adjacent pairs of the sidewalls, a first epitaxial layer of a first conductivity type is formed on the inner wall of the super junction trench, a second epitaxial layer of a second conductivity type is filled in the super junction trench within the first epitaxial layer, and then, by back etching, the tops of the first epitaxial layer and the second epitaxial layer are made lower than the surface of the semiconductor layer;

[0024] A first transition connection region of a second conductivity type connected to the body region is formed on top of the first epitaxial layer and the second epitaxial layer, and then the fourth hard mask layer pattern is removed.

[0025] Further, forming a plurality of first hard mask layer patterns on the surface of the semiconductor layer, contacting second hard mask layer patterns located on both sides of the first hard mask layer patterns, and contacting a third hard mask layer pattern between two of the second hard mask layer patterns located on adjacent sides, specifically includes:

[0026] Using a patterning process to form a plurality of first hard mask layer patterns on the surface of the semiconductor layer;

[0027] Forming a second hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern, and performing back etching to form a second hard mask layer pattern that contacts the first hard mask layer pattern on both sides, and exposing the top of the first hard mask layer pattern and the surface of the semiconductor layer between two second hard mask layer patterns on adjacent sides;

[0028] A third hard mask layer is formed on the surface of the semiconductor layer to cover the first hard mask layer pattern and the second hard mask layer pattern, and is back-etched to form a third hard mask layer pattern that contacts two of the second hard mask layer patterns located on adjacent sides and exposes the tops of the first hard mask layer pattern and the second hard mask layer pattern.

[0029] Furthermore, by sequentially forming a plurality of second sub-epitaxial layers of the second conductivity type having a gradient doping concentration in the super junction trench within the first epitaxial layer, the second epitaxial layer formed by the plurality of second sub-epitaxial layers has a gradient doping concentration inwardly along the inner wall of the super junction trench; and / or, by forming an implantation window between two adjacent pairs of the side walls and by ion implantation, the first transition connection region is formed on top of the first epitaxial layer and the second epitaxial layer; and / or, by forming an implantation window between two adjacent pairs of the side walls and by pocket ion implantation, a second transition connection region of the first conductivity type surrounding the super junction trench is formed in the semiconductor layer below the body region.

[0030] Further, a semiconductor layer of the first conductivity type is formed on the surface of the substrate to form a drift region of the first conductivity type in the semiconductor layer, and the body region, the source region, the first epitaxial layer and the second epitaxial layer are formed in the drift region; or, an intrinsic semiconductor layer is formed on the surface of the substrate.

[0031] Furthermore, after removing the fourth hard mask layer pattern, it also includes: filling metal layer material in the gaps between each of the side walls, and removing excess metal layer material located on the top surface of the side walls, forming a gate metal separated between each pair of the side walls and connected to the gate, and a source region contact metal separated between two adjacent pairs of the side walls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, thereby forming a metal layer; and forming an interlayer dielectric layer on the top of the metal layer and the top of the side walls.

[0032] It can be seen from the above technical scheme that the present invention can reduce the photomask while reducing the pitch by adopting multiple self-aligned patterning and sidewall processes (including forming the first hard mask layer pattern to the third hard mask layer pattern and the sidewall), so that the MOSFET device has a smaller tube core area, further reducing the resistance per square area, increasing the current density, and significantly reducing the cost; at the same time, since there is no overlay error, the short-circuit resistance can be effectively reduced; in this way, by removing the second hard mask layer pattern and the first hard mask layer pattern and the third hard mask layer pattern in steps, and using the formed sidewall structure, the super junction trench can be accurately self-aligned between adjacent gate trenches to effectively reduce the resistance and increase the switching speed. In addition, by adding the first epitaxial layer of the first conductivity type in the super junction trench, the doping concentration and thickness of the second epitaxial layer of the second conductivity type and the first epitaxial layer can be easily controlled to achieve a perfect charge balance. In this way, the drift region of the first conductivity type that is originally required to be formed by forming a semiconductor layer of the first conductivity type can be omitted by increasing the doping concentration of the first epitaxial layer, and thus the semiconductor layer of the first conductivity type can be directly changed to an intrinsic semiconductor layer, thereby improving the withstand voltage while reducing the on-resistance. At the same time, the shielded gate trench (SGT) structure formed also plays a role in avoiding avalanche breakdown and reducing parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic structural diagram of a self-aligned shielded gate dual epitaxial superjunction MOSFET according to a preferred embodiment of the present invention;

[0034] Figure 2-Figure 8 The present invention is a process flow chart of a method for manufacturing a self-aligned shielded gate dual epitaxial super junction MOSFET according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0036] Unless otherwise specified below, the various parts of the MOSFET device can be made of materials known to those skilled in the art. Semiconductor materials may include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si, Ge, etc. The gate conductor may be formed of various materials that can conduct electricity, such as metal, doped polysilicon layer, or a stacked gate conductor including a metal and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of the above-mentioned various conductive materials. The gate dielectric (gate oxide layer) may be made of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Furthermore, the gate dielectric may be formed not only of materials known to those skilled in the art, but also of materials to be developed in the future for use as gate dielectrics.

[0037] The first conductivity type may be one of N-type and P-type, and the second conductivity type may be the other of N-type and P-type. N-type may be formed by implanting N-type dopants (e.g., P, As, etc.) into a semiconductor material. P-type may be formed by implanting P-type dopants (e.g., B, etc.) into a semiconductor material. The above may be understood with reference to known techniques.

[0038] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0039] refer to Figure 1 A self-aligned shielded gate dual epitaxial super junction MOSFET of the present invention includes a substrate 10 and a semiconductor layer 22 disposed on the surface of the substrate 10 .

[0040] The semiconductor layer 22 is provided with a source region 13 of a first conductivity type and a body region 12 of a second conductivity type which are sequentially distributed from the surface of the semiconductor layer 22 toward the substrate 10 .

[0041] A plurality of pairs of sidewalls 15 are arranged in parallel on the surface of the semiconductor layer 22, and each pair of sidewalls 15 is provided with two sidewalls 151. Each pair of sidewalls 15 can be vertically arranged on the surface of the semiconductor layer 22, and the two sidewalls 151 in each pair of sidewalls 15 are spaced apart by a certain first distance L, and any two adjacent pairs of sidewalls 15 (i.e., the two sidewalls 151 located on adjacent (close) sides of the two adjacent pairs of sidewalls 15) are also spaced apart by a certain second distance H. The first distance L and the second distance H can be adjusted according to the process design.

[0042] A gate trench 19 is disposed between the two sidewalls 151 in each pair of sidewalls 15, extending from the surface of the semiconductor layer 22 downward into the semiconductor layer 22. In addition, the bottom of the gate trench 19 may sequentially pass through the source region 13 and the body region 12 and be located in the semiconductor layer 22. The width of the gate trench 19 is determined by the first distance L between the pair of sidewalls 15.

[0043] A shielding gate 29 , an isolation layer 28 and a gate 21 are arranged in the gate trench 19 from bottom to top. A gate oxide layer 20 is formed between the shielding gate 29 and the inner wall of the gate trench 19 , and between the gate 21 and the inner wall of the gate trench 19 and the isolation layer 28 .

[0044] At the same time, a super junction trench 24 extending from the surface of the semiconductor layer 22 downward into the semiconductor layer 22 is respectively provided between any two adjacent pairs of sidewalls 15. In addition, the bottom of the super junction trench 24 can sequentially pass through the source region 13 and the body region 12 and be located in the semiconductor layer 22. The width of the super junction trench 24 is determined by the second distance H between the two adjacent pairs of sidewalls 15.

[0045] refer to Figure 1 A first epitaxial layer 26 of the first conductivity type is provided on the inner wall of the super junction trench 24; a second epitaxial layer 25 of the second conductivity type is filled in the super junction trench 24 within the first epitaxial layer 26. The first epitaxial layer 26 and the second epitaxial layer 25 are used to form a double epitaxial super junction. The first epitaxial layer 26 and the second epitaxial layer 25 are connected to the body region 12 through the top 231 facing the surface of the semiconductor layer 22.

[0046] The super junction trench 24 is formed between every two adjacent gate trenches 19 in a self-aligned manner through the openings (having a second distance H) between every two adjacent pairs of spacers 15 .

[0047] The following description is made by taking the case where the first conductivity type is N type and the second conductivity type is P type as an example.

[0048] refer to Figure 1 In some embodiments, the substrate 10 may be a heavily doped N+ type silicon substrate 10 (N+ substrate) of the first conductivity type.

[0049] In some embodiments, the semiconductor layer 22 may be an epitaxial N-type silicon semiconductor layer 22 of the first conductivity type disposed on the surface of the substrate 10, and an epitaxial N-type drift region 11 (N driftEPI) of the first conductivity type is formed in the semiconductor layer 22. The body region 12, the source region 13, the first epitaxial layer 26, and the second epitaxial layer 25 are formed in the drift region 11.

[0050] In some embodiments, the depth of the super junction trench 24 below the surface of the semiconductor layer 22 is greater than the depth of the gate trench 19 below the surface of the semiconductor layer 22. For example, the bottom of the super junction trench 24 may be located at the interface between the semiconductor layer 22 and the substrate 10 (i.e., located on the surface of the substrate 10), and the bottom of the gate trench 19 may be located in the semiconductor layer 22 above the bottom of the super junction trench 24 and may maintain a certain distance from the substrate 10.

[0051] The body region 12 may be a lightly doped P-type body region 12 (P-body) of the second conductivity type.

[0052] The source region 13 may be a heavily doped N+ type source region 13 of the first conductivity type.

[0053] The first epitaxial layer 26 may be a first conductivity type medium-doped N-type silicon first epitaxial layer 26 (N EPI).

[0054] The second epitaxial layer 25 may be a P-type silicon second epitaxial layer 25 (PEPI) doped with a second conductivity type.

[0055] In some embodiments, the second epitaxial layer 25 has a gradient doping concentration along the inner wall of the super junction trench 24 toward the inside of the super junction trench 24 .

[0056] In some embodiments, the second epitaxial layer 25 is composed of multiple second sub-epitaxial layers formed sequentially in the super junction trench 24 within the first epitaxial layer 26, and the doping concentration of each second sub-epitaxial layer is different, thereby forming a second epitaxial layer 25 with a gradient doping concentration along the inner wall of the super junction trench 24 toward the inside of the super junction trench 24.

[0057] In some embodiments, since an N-type first epitaxial layer 26 is added between the N-type drift region 11 and the P-type second epitaxial layer 25 in the super junction trench 24, the doping concentration and thickness of the P-type second epitaxial layer 25 and the N-type first epitaxial layer 26 can be easily controlled to achieve a perfect charge balance, so that the N-type semiconductor layer 22 with the N-type drift region 11 can be directly changed to the intrinsic semiconductor layer 22 by increasing the doping concentration of the first epitaxial layer 26, thereby eliminating the need to set the drift region 11 in the intrinsic semiconductor layer 22. In this way, the on-resistance can be reduced while the withstand voltage is increased.

[0058] In some embodiments, the top 231 of the first epitaxial layer 26 and the second epitaxial layer 25 facing the surface of the semiconductor layer 22 is lower than the surface of the semiconductor layer 22 by a certain distance, and the first epitaxial layer 26 and the second epitaxial layer 25 are connected to the body region 12 exposed at the sidewall of the super junction trench 24 through the first transition connection region 23 of the second conductivity type provided on the top 231 facing the surface of the semiconductor layer 22. The first transition connection region 23 can be a heavily doped P+ type first transition connection region 23 of the second conductivity type to increase the P-type doping concentration in the top region of the second epitaxial layer 25 and improve the dynamic reliability of the formed device.

[0059] In some embodiments, a second transition connection region 27 of the first conductivity type surrounding the super junction trench 24 is further provided in the semiconductor layer 22 below the body region 12. In addition, the second transition connection region 27 is connected to the side surface of the first epitaxial layer 26 in the super junction trench 24 and the bottom of the body region 12. The second transition connection region 27 can be a medium-doped N-type second transition connection region 27 of the first conductivity type to reduce the resistance of the region.

[0060] In some embodiments, the bottom of the gate 21 away from the surface of the semiconductor layer 22 is located below the bottom of the body region 12 .

[0061] In some embodiments, the gate oxide layer 20 may include a first gate oxide layer 201 disposed between the shielding gate 29 and the inner wall of the gate trench 19 , and a second gate oxide layer 202 disposed between the gate 21 and the inner wall of the gate trench 19 and the isolation layer 28 .

[0062] In some embodiments, the shield gate 29 may be a heavily doped N+ type polysilicon shield gate 29 (poly 1) of a first conductivity type.

[0063] The gate 21 may be a heavily doped N+ type polysilicon gate 21 (Gate poly2) of the first conductivity type.

[0064] The gate oxide layer 20 (Gate OX) may be made of silicon dioxide.

[0065] The material of the isolation layer 28 may be tetraethyl orthosilicate oxide (ie, CVD oxide using tetraethyl orthosilicate TEOS precursor, referred to as TEOS OX), but is not limited thereto.

[0066] In some embodiments, the gate 21 and the top of the gate oxide layer 20 may protrude above the surface of the semiconductor layer 22 and be located between the pair of spacers 15 .

[0067] In some embodiments, a metal layer 18 is further provided on the surface of the semiconductor layer 22 between each sidewall 151. The metal layer 18 includes a gate metal 16 that fills and separates between each pair of sidewalls 15 and connects to the gate 21, and a source contact metal 17 that is separated between two adjacent pairs of sidewalls 15 and connects to the source region 13, the body region 12, the first epitaxial layer 26, and the second epitaxial layer 25 (connected through the first transition connection region 23). That is, the gate metal 16 and the source contact metal 17 in the metal layer 18 are isolated by the sidewall 151.

[0068] In some embodiments, an interlayer dielectric layer 14 is further disposed on the surface of the metal layer 18 . The interlayer dielectric layer 14 is located on the top of the gate metal 16 , the top of the source region contact metal 17 , and the top of each spacer 151 .

[0069] In some embodiments, the sidewall spacer 151 may be formed of a dielectric material.

[0070] In some embodiments, the gate metal 16 and the source contact metal 17 materials (metal layer 18 materials) include at least one of Au, Ag, Pt, Al, and W.

[0071] Adhesion layers (not shown) may be provided respectively between the gate metal 16 and the sidewall 151 and the top of the gate 21 (including the gate oxide layer 20), and between the source contact metal 17 and the sidewall 151, the exposed sidewall of the super junction trench 24 and the top of the first transition connection region 23. The adhesion layer material includes at least one of Ti, TiN and TaN.

[0072] A method for manufacturing a self-aligned shield gate 29 dual epitaxial super junction MOSFET of the present invention is described in detail below through specific implementation methods and in conjunction with the accompanying drawings.

[0073] refer to Figure 2-Figure 8 The present invention provides a method for manufacturing a self-aligned shielded gate 29 dual epitaxial super junction MOSFET, which can be used to manufacture the above-mentioned Figure 1 A self-aligned shielded gate 29 dual epitaxial super junction MOSFET of the present invention may include the following steps:

[0074] Step S1 : providing a substrate 10 , and forming a semiconductor layer 22 on a surface of the substrate 10 .

[0075] like Figure 2 As shown, a heavily doped N+ silicon substrate 10 (N+ substrate) may be used, and an N-type epitaxial silicon semiconductor layer 22 is formed on the silicon substrate 10 , and an epitaxial N-type drift region 11 (N drift EPI) is also formed.

[0076] Step S2 : forming a source region 13 of the first conductivity type and a body region 12 of the second conductivity type in the semiconductor layer 22 , which are sequentially distributed from the surface of the semiconductor layer 22 toward the substrate 10 .

[0077] like Figure 2 As shown, an ion implantation process may be used to implant P-type light doping into the semiconductor layer 22 from the surface of the semiconductor layer 22 to form a P-type body region 12 of the second conductivity type.

[0078] Next, an ion implantation process may be used to implant N+ type heavy doping into the semiconductor layer 22 from the surface of the semiconductor layer 22 , so as to form an N+ type source region 13 of the first conductivity type below the surface of the semiconductor layer 22 above the body region 12 .

[0079] Step S3: forming a plurality of first hard mask layer patterns 30, second hard mask layer patterns 31 contacting both sides of the first hard mask layer patterns 27, and third hard mask layer patterns 32 contacting between two second hard mask layer patterns 28 on adjacent sides on the surface of the semiconductor layer 22.

[0080] like Figure 2 As shown, a first hard mask layer material may be deposited on the surface of the semiconductor layer 22. Then, a photoresist layer is formed on the first hard mask layer. Next, a plurality of first hard mask layer patterns 30 (HM1) are formed on the surface of the semiconductor layer 22 through photolithography and etching patterning processes. Figure 2 FIG. 2 exemplarily shows that two first hard mask layer patterns 30 are formed, but the present invention is not limited thereto. Afterwards, the photoresist remaining on the first hard mask layer patterns 30 is removed.

[0081] The first hard mask layer material may be a conventional hard mask layer material, for example, the first hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.

[0082] like Figure 3 As shown, a conformal CVD process can be used to form a second hard mask layer on the surface of the semiconductor layer 22 to cover the first hard mask layer pattern 30. Then, the second hard mask layer is etched back to form a second hard mask layer pattern 31 (HM2) on both sides of each first hard mask layer pattern 30, which is in contact with the side surface of the first hard mask layer pattern 30, and exposes the top of the first hard mask layer pattern 30 and the two second hard mask layer patterns 31 located on the adjacent sides (i.e., located at Figure 3 The surface of the semiconductor layer 22 is shown between two second hard mask layer patterns 31 inside two adjacent first hard mask layer patterns 30.

[0083] When the second hard mask layer is deposited, the thickness during deposition can be controlled to reserve a width for subsequent deposition of the third hard mask layer.

[0084] The second hard mask layer material may be a conventional hard mask layer material, for example, one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0085] like Figure 3 As shown, a deposition process can be used to form a third hard mask layer on the surface of the semiconductor layer 22, covering the first hard mask layer pattern 30 and the second hard mask layer pattern 31, and completely filling the gap between the two second hard mask layer patterns 31 on the adjacent sides. Then, the third hard mask layer material can be etched back to form a third hard mask layer pattern 32 (HM3) in contact with the side surface of the second hard mask layer pattern 31 between the two second hard mask layer patterns 31 on the adjacent sides, and expose the tops of the first hard mask layer pattern 30 and the second hard mask layer pattern 31.

[0086] By conformally forming a second hard mask layer on the first hard mask layer pattern 30 and back-etching to form a second hard mask layer pattern 31 on both sides of the first hard mask layer pattern 30, a third hard mask layer pattern 32 can be self-aligned between the second hard mask layer patterns 31, thereby saving one photomask and achieving a reduction in pitch.

[0087] The third hard mask layer material may be a conventional hard mask layer material, for example, the third hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.

[0088] Step S4: remove the second hard mask layer pattern 31, and then form sidewalls 151 on both sides of the first hard mask layer pattern 30 and on both sides of the third hard mask layer pattern 32, respectively, to form a pair of sidewalls 15 formed by two sidewalls 151 on adjacent sides between two adjacent first hard mask layer patterns 30 and third hard mask layer patterns 32.

[0089] like Figure 4 As shown, the second hard mask layer pattern 31 can then be removed using different etching selectivity ratios between the second hard mask layer material and the first hard mask layer material and the third hard mask layer material to expose the surface of the semiconductor layer 22 located between the first hard mask layer pattern 30 and the third hard mask layer pattern 32.

[0090] like Figure 4As shown, next, a spacer 151 material is deposited on the surface of the semiconductor layer 22 exposed between the first hard mask layer pattern 30 and the third hard mask layer pattern 32, and the first hard mask layer pattern 30 and the third hard mask layer pattern 32 are covered. Then, a spacer process is adopted and back-etching is performed to form a spacer 151 (Spacer) structure on both sides of each first hard mask layer pattern 30 and each third hard mask layer pattern 32. Among them, a pair of spacers 15 is formed by the spacers 151 on two adjacent sides between the adjacent first hard mask layer pattern 30 and the third hard mask layer pattern 32.

[0091] The material of the spacer 151 may be a conventional spacer material having different etching selectivities with the material of the first hard mask layer and the material of the third hard mask layer.

[0092] Step S5: forming a gate trench 19 passing through the source region 13 and the body region 12 below the surface of the semiconductor layer 22 between each pair of spacers 15 , and forming a shielding gate 29 and a gate 21 from bottom to top in the gate trench 19 .

[0093] like Figure 4 As shown, then, using the combined pattern of the first hard mask layer pattern 30 and the side walls 151 on both sides, and the combined pattern of the third hard mask layer pattern 32 and the side walls 151 on both sides as a common mask, etching is performed downward on the surface of the semiconductor layer 22 exposed between each pair of side walls 15 to form a plurality of parallel deep trenches serving as gate trenches 19 in the semiconductor layer 22, and the bottom end of the gate trench 19 passes through the source region 13 and the body region 12 in sequence and is located in the semiconductor layer 22 (i.e., the area where the drift region 11 is located).

[0094] Then, a first gate oxide layer 201 material is deposited on the inner wall surface of the gate trench 19, and a shielding gate 29 material is further filled in the gate trench 19 within the first gate oxide layer 201 material, until the gap between each pair of side walls 15 is filled, so that the shielding gate 29 material covers the first gate oxide layer 201 material.

[0095] Next, the shielding gate 29 material may be etched back to form a first gate oxide layer 201 on the inner wall of the gate trench 19 , and the shielding gate 29 may be formed in the lower portion of the gate trench 19 within the first gate oxide layer 201 .

[0096] When etching back the material of the shielding gate 29 , the etching back time can be controlled so that the top of the shielding gate 29 is located in the semiconductor layer 22 below the body region 12 .

[0097] Then, the isolation layer 28 material is continuously filled in the gate trench 19 , and is etched back to form the isolation layer 28 on the top surface of the shielding gate 29 .

[0098] When etching back the isolation layer 28 material, the etching back time can be controlled so that the top of the isolation layer 28 is located in the semiconductor layer 22 below the body region 12 .

[0099] like Figure 5 As shown, next, a second gate oxide layer 202 material is deposited on the inner wall of the gate trench 19 above the isolation layer 28, and then the gate 21 material is continued to be filled in the remaining upper portion of the gate trench 19 within the second gate oxide layer 202, and back-etching is performed to form a second gate oxide layer 202 on the side wall of the gate trench 19 above the isolation layer 28, and a gate 21 is formed in the remaining upper portion of the gate trench 19 on the isolation layer 28.

[0100] When etching back the gate 21 material, the etching back time can be controlled so that the top of the gate 21 and the second gate oxide layer 202 protrude above the surface of the semiconductor layer 22 and are located between a pair of side walls 15, even if the top of the gate 21 and the second gate oxide layer 202 are located below the top of the pair of side walls 15.

[0101] Meanwhile, the bottom of the gate 21 can be formed to be located in the semiconductor layer 22 below the body region 12 by controlling the deposition thickness of the isolation layer 28 material.

[0102] The first gate oxide layer 201 and the second gate oxide layer 202 in the gate trench 19 form a gate oxide layer 20 .

[0103] The shield gate 29 and the gate 21 can be made of heavily doped N+ type polysilicon.

[0104] It can be seen that when forming the side wall 151, the horizontal width of the side wall 151 formed by back etching can be adjusted by controlling the deposition thickness of the side wall 151 material, so as to adjust the spacing between a pair of side walls 15 located between two adjacent first hard mask layer patterns 30 and third hard mask layer patterns 32, thereby achieving the adjustment of the horizontal width of the gate trench 19 formed by subsequent etching.

[0105] Step S6: forming a fourth hard mask layer pattern 33 between each pair of sidewalls 15, and then removing the first hard mask layer pattern 30 and the third hard mask layer pattern 32;

[0106] like Figure 5 As shown, then, a fourth hard mask layer material can be filled between each pair of sidewall spacers 15 through a deposition process to cover the sidewall spacers 151, the first hard mask layer pattern 30, and the third hard mask layer pattern 32. Then, the fourth hard mask layer is etched back to remove the excess fourth hard mask layer material on the top surfaces of the sidewall spacers 151, the first hard mask layer pattern 30, and the third hard mask layer pattern 32, thereby forming a fourth hard mask layer pattern 33 (HM4) located between a pair of sidewall spacers 15 and covering the gate 21 and the gate oxide layer 20.

[0107] The fourth hard mask layer material includes tetraethyl orthosilicate oxide (ie, CVD oxide using tetraethyl orthosilicate TEOS precursor, TEOS OX for short), but is not limited thereto.

[0108] like Figure 6 As shown, then, the third hard mask layer pattern 32 and the first hard mask layer pattern 30 are removed by etching back.

[0109] Step S7: A super junction trench 24 is formed below the surface of the semiconductor layer 22 between two adjacent pairs of side walls 15, passing through the source region 13 and the body region 12; a first epitaxial layer 26 of a first conductivity type is formed on the inner wall of the super junction trench 24; a second epitaxial layer 25 of a second conductivity type is filled in the super junction trench 24 within the first epitaxial layer 26; and then, by back etching, the tops 231 of the first epitaxial layer 26 and the second epitaxial layer 25 are made lower than the surface of the semiconductor layer 22.

[0110] like Figure 6 As shown, next, the fourth hard mask layer pattern 33 and the combined pattern of the sidewalls 151 on both sides thereof are used as a common mask to perform etching downward on the surface of the semiconductor layer 22 between two adjacent pairs of sidewalls 15, so as to form a super junction trench 24 passing through the source region 13 and the body region 12 in the semiconductor layer 22. The bottom of the super junction trench 24 can be located on the surface of the substrate 10 by etching.

[0111] Next, an N-type silicon first epitaxial layer 26 is first formed on the inner wall of the super junction trench 24 by using a doping epitaxial process. Then, the epitaxial process is continued to be used to fill the super junction trench 24 within the formed first epitaxial layer 26 to form a P-type silicon second epitaxial layer 25, and the super junction trench 24 is filled. When the second epitaxial layer 25 is formed by epitaxy, a plurality of P-type silicon second sub-epitaxial layers can be sequentially formed in the super junction trench 24 within the first epitaxial layer 26, and a gradient doping concentration can be provided between each second sub-epitaxial layer, so that the second epitaxial layer 25 formed by the plurality of second sub-epitaxial layers has a gradient doping concentration inwardly along the inner wall of the super junction trench 24, thereby forming a second epitaxial layer 25 with a doping concentration gradient.

[0112] In other embodiments, an undoped epitaxial process may be used to first form an undoped silicon second epitaxial layer 25, and then, through multiple steps of ion implantation with different doping doses, a P-type silicon second epitaxial layer 25 having a doping concentration gradient inwardly along the inner wall of the super junction trench 24 is formed.

[0113] Next, the first epitaxial layer 26 and the second epitaxial layer 25 can be etched back so that the top 231 of the first epitaxial layer 26 and the second epitaxial layer 25 is lower than the surface of the semiconductor layer 22 (that is, lower than the top surface of the super junction trench 24) to form a super junction. By controlling the etching back time, the top 231 of the first epitaxial layer 26 and the second epitaxial layer 25 can be located at a height position below the bottom of the source region 13, so that the source region 13 is exposed on the side wall of the super junction trench 24.

[0114] Step S8: forming a first transition connection region 23 of a second conductivity type connected to the body region 12 on the top 231 of the first epitaxial layer 26 and the second epitaxial layer 25, and then removing the fourth hard mask layer pattern 33.

[0115] like Figure 7 As shown, by utilizing the implantation window formed between two adjacent pairs of sidewalls 15 and adopting a pocket implant process, an N-type ion implantation region surrounding the super junction trench 24 is formed in the semiconductor layer 22 below the body region 12 to form a second transition connection region 27 .

[0116] Then, the implantation window formed between two adjacent pairs of side walls 15 is utilized again, and an ion implantation process is adopted to form a heavily doped P+ type ion implantation region on the top 231 of the first epitaxial layer 26 and the second epitaxial layer 25 exposed in the super junction trench 24, as the first transition connection region 23, and the first transition connection region 23 is connected to the body region 12 exposed on the side wall of the super junction trench 24.

[0117] Then, the fourth hard mask layer pattern 33 is removed by etching back, leaving a deposition space for the metal layer 18 between the sidewalls 151 .

[0118] In other embodiments, since the doping concentration and thickness of the P-type second epitaxial layer 25 and the N-type first epitaxial layer 26 can be easily controlled and a perfect charge balance can be achieved by adding an N-type first epitaxial layer 26, the N-type semiconductor layer 22 having the N-type drift region 11 can be directly changed into an intrinsic semiconductor layer 22 by increasing the doping concentration of the first epitaxial layer 26, thereby eliminating the need to set the drift region 11 in the intrinsic semiconductor layer 22 (i.e., forming the intrinsic semiconductor layer 22 on the surface of the substrate 10, and no longer forming the N-type drift region 11).

[0119] Afterwards, a metal layer 18 may be further formed between the spacers 151 , and an interlayer dielectric layer 14 may be formed on the metal layer 18 .

[0120] like Figure 8As shown, an adhesion layer (not shown) can be formed on the exposed surface of each sidewall 151, on the exposed sidewall of the super junction trench 24, on the top 231 of the first epitaxial layer 26 and the second epitaxial layer 25, and on the top of the gate 21 and the gate oxide layer 20 through a deposition process, and the metal layer 18 material is filled in the gaps between the sidewalls 151 on the adhesion layer to fill the gaps between the sidewalls 151. Then, by etching back or chemical mechanical polishing (CMP) the metal layer 18 material and the adhesion layer, the excess metal layer 18 material on the top surface of each sidewall 151 is removed to form a gate metal 16 separated between each pair of sidewalls 15 and connected to the gate 21, and a source region contact metal 17 separated between two adjacent pairs of sidewalls 15 and connected to the source region 13, the body region 12, the first epitaxial layer 26 and the second epitaxial layer 25 (connected through the first transition connection region 23), thereby forming a metal layer 18. That is, the gate metal 16 and the source contact metal 17 in the metal layer 18 are isolated by the spacer 151 .

[0121] Afterwards, an interlayer dielectric layer 14 (ILD) may be formed on the top surfaces of the spacers 151, the gate metal 16 and the source contact metal 17 (i.e., the top surface of the metal layer 18) through a deposition process. A metal interconnect layer may be further formed on the interlayer dielectric layer 14.

[0122] In summary, the present invention can reduce the number of masks and reduce the pitch at the same time by adopting multiple self-aligned patterning and sidewall processes (including forming the first hard mask layer pattern 30 to the fourth hard mask layer pattern 33 and the sidewall 151), so that the MOSFET device has a smaller die area, further reduces the resistance per square area, increases the current density, and significantly reduces the cost; at the same time, since there is no overlay error, the short-circuit resistance can be effectively reduced; in this way, by removing the second hard mask layer pattern 31 and the first hard mask layer pattern 30 and the third hard mask layer pattern 32 step by step, and using the formed sidewall 151 structure, the super junction trench 24 can be accurately self-aligned between adjacent gate trenches 19, which can effectively reduce the resistance and increase the switching speed. In addition, by adding the first epitaxial layer 26 of the first conductivity type in the super junction trench 24, the doping concentration and thickness of the second epitaxial layer 25 of the second conductivity type and the first epitaxial layer 26 can be easily controlled to achieve a perfect charge balance. In this way, the drift region 11 (drift) of the first conductivity type that originally needs to be formed by forming the semiconductor layer 22 of the first conductivity type can be omitted by increasing the doping concentration of the first epitaxial layer 26, and thus the semiconductor layer 22 of the first conductivity type can be directly changed to the intrinsic semiconductor layer 22, so that the on-resistance can be reduced while the withstand voltage is improved. At the same time, the shielding gate 29 trench (SGT) structure formed also advantageously plays a role in avoiding avalanche breakdown and reducing parasitic capacitance. All of these lay the foundation for further optimization of device performance.

[0123] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A self-aligned shielded gate dual epitaxial superjunction MOSFET, characterized in that: include: A semiconductor layer disposed on a substrate, wherein the semiconductor layer is provided with a source region and a body region sequentially distributed from a surface of the semiconductor layer toward the substrate; A plurality of pairs of side walls are arranged in parallel on the surface of the semiconductor layer; A gate trench is provided below the surface of the semiconductor layer between each pair of the sidewalls, wherein a shielding gate and a gate are provided in the gate trench from bottom to top; A super junction trench is provided below the surface of the semiconductor layer between two adjacent pairs of the side walls, a first epitaxial layer of a first conductivity type is provided on the inner wall of the super junction trench, a second epitaxial layer of a second conductivity type is provided in the super junction trench within the first epitaxial layer, and the first epitaxial layer and the second epitaxial layer are connected to the body region through the top facing the surface of the semiconductor layer.

2. The self-aligned shielded gate dual epitaxial superjunction MOSFET according to claim 1, characterized in that: A drift region of the first conductivity type is provided in the semiconductor layer, and the body region of the second conductivity type, the source region of the first conductivity type, the first epitaxial layer and the second epitaxial layer are located in the drift region; or, the semiconductor layer is an intrinsic semiconductor layer.

3. The self-aligned shielded gate dual epitaxial superjunction MOSFET according to claim 1, characterized in that: Bottom portions of the super junction trench and the gate trench pass through the source region and the body region and are located in the semiconductor layer, and a depth of the super junction trench is greater than a depth of the gate trench.

4. The self-aligned shielded gate dual epitaxial superjunction MOSFET according to claim 1, characterized in that: The first epitaxial layer and the second epitaxial layer are connected to the body region through a first transition connection region of the second conductivity type provided on the top facing the surface of the semiconductor layer; and / or, a second transition connection region of the first conductivity type surrounding the super junction trench and connecting the first epitaxial layer and the body region is also provided in the semiconductor layer below the body region; and / or, the second epitaxial layer has a gradient doping concentration inward along the inner wall of the super junction trench.

5. The self-aligned shielded gate dual epitaxial superjunction MOSFET according to claim 1, characterized in that: Also includes: A metal layer is arranged on the surface of the semiconductor layer, and an interlayer dielectric layer is arranged on the surface of the metal layer; the metal layer includes a gate metal separated between each pair of the side walls and connected to the gate, and a source contact metal separated between two adjacent pairs of the side walls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, and the interlayer dielectric layer is located on the top of the gate metal, the top of the source contact metal and the top of the side walls.

6. A method for manufacturing a self-aligned shielded gate dual epitaxial superjunction MOSFET, characterized in that: include: providing a substrate, and forming a semiconductor layer on a surface of the substrate; Forming a source region of a first conductivity type and a body region of a second conductivity type in the semiconductor layer, which are distributed in sequence from the surface of the semiconductor layer toward the substrate; Forming a plurality of first hard mask layer patterns, second hard mask layer patterns contacting both sides of the first hard mask layer patterns, and a third hard mask layer pattern contacting between two of the second hard mask layer patterns on adjacent sides on the surface of the semiconductor layer; The second hard mask layer pattern is removed, and then, sidewalls are formed on both sides of the first hard mask layer pattern and both sides of the third hard mask layer pattern, respectively, so as to form a pair of sidewalls formed by two sidewalls on adjacent sides between two adjacent first hard mask layer patterns and the third hard mask layer patterns; Forming a gate trench passing through the source region and the body region below the surface of the semiconductor layer between each pair of the sidewalls, and forming a shielding gate and a gate from bottom to top in the gate trench; forming a fourth hard mask layer pattern between each pair of the spacers, and then removing the first hard mask layer pattern and the third hard mask layer pattern; A super junction trench passing through the source region and the body region is formed below the surface of the semiconductor layer between two adjacent pairs of the sidewalls, a first epitaxial layer of a first conductivity type is formed on the inner wall of the super junction trench, a second epitaxial layer of a second conductivity type is filled in the super junction trench within the first epitaxial layer, and then, by back etching, the tops of the first epitaxial layer and the second epitaxial layer are made lower than the surface of the semiconductor layer; A first transition connection region of a second conductivity type connected to the body region is formed on top of the first epitaxial layer and the second epitaxial layer, and then the fourth hard mask layer pattern is removed.

7. The method for manufacturing a self-aligned shielded gate dual epitaxial super junction MOSFET according to claim 6, characterized in that: The forming of a plurality of first hard mask layer patterns on the surface of the semiconductor layer, contacting second hard mask layer patterns located on both sides of the first hard mask layer patterns, and contacting a third hard mask layer pattern between two of the second hard mask layer patterns located on adjacent sides specifically includes: Using a patterning process to form a plurality of first hard mask layer patterns on the surface of the semiconductor layer; Forming a second hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern, and performing back etching to form a second hard mask layer pattern that contacts the first hard mask layer pattern on both sides, and exposing the top of the first hard mask layer pattern and the surface of the semiconductor layer between two second hard mask layer patterns on adjacent sides; A third hard mask layer is formed on the surface of the semiconductor layer to cover the first hard mask layer pattern and the second hard mask layer pattern, and is back-etched to form a third hard mask layer pattern that contacts two of the second hard mask layer patterns located on adjacent sides and exposes the tops of the first hard mask layer pattern and the second hard mask layer pattern.

8. The method for manufacturing a self-aligned shielded gate dual epitaxial super junction MOSFET according to claim 6, characterized in that: By sequentially forming a plurality of second sub-epitaxial layers of the second conductivity type having a gradient doping concentration in the super junction trench within the first epitaxial layer, the second epitaxial layer formed by the plurality of second sub-epitaxial layers has a gradient doping concentration inwardly along the inner wall of the super junction trench; and / or, by forming an implantation window between two adjacent pairs of the side walls and by ion implantation, the first transition connection region is formed on top of the first epitaxial layer and the second epitaxial layer; and / or, by forming an implantation window between two adjacent pairs of the side walls and by pocket ion implantation, a second transition connection region of the first conductivity type surrounding the super junction trench is formed in the semiconductor layer below the body region.

9. The method for manufacturing a self-aligned shielded gate dual epitaxial super junction MOSFET according to claim 6, characterized in that: A semiconductor layer of the first conductivity type is formed on the surface of the substrate to form a drift region of the first conductivity type in the semiconductor layer, and the body region, the source region, the first epitaxial layer and the second epitaxial layer are formed in the drift region; or, an intrinsic semiconductor layer is formed on the surface of the substrate.

10. The method for manufacturing a self-aligned shielded gate dual epitaxial super junction MOSFET according to claim 6, characterized in that: After removing the fourth hard mask layer pattern, it also includes: filling the metal layer material in the gap between each of the side walls, and removing the excess metal layer material located on the top surface of the side wall, forming a gate metal separated between each pair of the side walls and connected to the gate, and a source region contact metal separated between two adjacent pairs of the side walls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, thereby forming a metal layer; and forming an interlayer dielectric layer on the top of the metal layer and the top of the side wall.

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