Epitaxial structure in semiconductor device

Abstract

The invention relates to an epitaxial structure in a semiconductor device. A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a substrate, a first nanostructure channel region and a second nanostructure channel region disposed on the substrate, a gate structure surrounding the first nanostructure channel region and the second nanostructure channel region, an inner gate spacer disposed along sidewalls of the gate structure and between the first nanostructure channel region and the second nanostructure channel region, and a source / drain (S / D) region. The S / D region includes an epitaxial liner disposed along the first and second nanostructure channel regions and sidewalls of the internal gate spacer, and a germanium-based epitaxial region disposed on the epitaxial liner. The semiconductor device also includes an isolation structure disposed between the germanium-based epitaxial region and the substrate.

Description

Technical Field

[0001] The present disclosure relates to epitaxial structures in semiconductor devices. Background Art

[0002] As semiconductor technology advances, there is an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). This shrinking increases the complexity of semiconductor manufacturing processes. Summary of the invention

[0003] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate; a first nanostructure channel region and a second nanostructure channel region, which are arranged on the substrate; a gate structure, which surrounds the first nanostructure channel region and the second nanostructure channel region; an internal gate spacer, which is arranged along the sidewalls of the gate structure and between the first nanostructure channel region and the second nanostructure channel region; a source / drain S / D region, comprising: an epitaxial liner, which is arranged along the sidewalls of the first nanostructure channel region and the second nanostructure channel region and the internal gate spacer; and a germanium-based epitaxial region, which is arranged on the epitaxial liner; and an isolation structure, which is arranged between the germanium-based epitaxial region and the substrate.

[0004] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate; a first nanosheet layer and a second nanosheet layer, which are arranged on the substrate; a first gate structure and a second gate structure, which surround the first nanosheet layer and the second nanosheet layer, respectively; a first gate spacer and a second gate spacer, which are arranged along the side walls of the first gate structure and the second gate structure, respectively; and a source / drain S / D region, comprising: a first epitaxial liner, which is arranged as a continuous layer along the side walls of the first nanosheet layer and the first gate spacer; a second epitaxial liner, which is arranged as a continuous layer along the side walls of the second nanosheet layer and the second gate spacer; and an epitaxial region, which is arranged between the first epitaxial liner and the second epitaxial liner.

[0005] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a nanosheet stack including a nanostructure layer and a sacrificial layer on a substrate; forming a polysilicon structure on the nanosheet stack; etching the nanostructure layer and the sacrificial layer to form source / drain S / D openings and isolation trenches in the nanosheet stack; forming an internal spacer on the sidewall of the sacrificial layer; forming an undoped semiconductor layer in the isolation trench; forming an epitaxial liner as a continuous layer on the sidewalls of the nanostructure layer and the internal spacer; and epitaxially growing a germanium-based layer on the epitaxial liner and the undoped semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1A and 1G Different isometric views of a semiconductor device having an epitaxial liner in source / drain (S / D) regions are shown in accordance with some embodiments.

[0008] Figures 1B to 1E as well as Figure 1H to Figure 1O Different cross-sectional views of a semiconductor device having an epitaxial liner in the S / D regions are shown in accordance with some embodiments.

[0009] Figure 1F A top view of a semiconductor device having an epitaxial liner is shown in accordance with some embodiments.

[0010] Figure 2 is a flow chart of a method for fabricating a semiconductor device having an epitaxial liner in the S / D regions according to some embodiments.

[0011] Figures 3 to 9 Cross-sectional views of a semiconductor device having an epitaxial liner in the S / D regions at various stages of its fabrication process are shown in accordance with some embodiments.

[0012] FIG. 10A to FIG. 13B Cross-sectional views of a semiconductor device having n-type and p-type FETs at various stages of its fabrication process are shown in accordance with some embodiments.

[0013] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a process for forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used herein, forming a first feature on a second feature means that the first feature and the second feature are formed in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. The repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Spatially relative terms (e.g., "below," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0016] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0017] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of the specification is interpreted by those skilled in the relevant art(s) based on the teachings herein.

[0018] In some embodiments, the terms "about" and "substantially" may indicate that the value of a given amount varies within 5% to 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10% to ±15%, ±15% to ±20% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one or more persons skilled in the relevant art(s) in accordance with the teachings herein.

[0019] The gate-all-around (GAA) transistor structure can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning processes or multi-patterning processes) can be used to pattern these structures. The double patterning process or the multi-patterning process can combine the photolithography process and the self-alignment process, thereby allowing the generation of patterns with, for example, a spacing smaller than the spacing obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0020] The GAA FET may include a fin substrate (also referred to as a "sheet substrate") disposed on a substrate, a stack of nanostructure channel regions disposed on the fin substrate, a gate structure surrounding each nanostructure channel region, and an internal spacer on the sidewall of the gate structure. The GAA FET may also include an S / D region, each of which may be disposed between a pair of nanostructure channel regions and located on a fin portion between the pair of nanostructure channel regions. Each S / D region may be formed by merging an epitaxial portion grown on the fin portion with an epitaxial portion grown on the sidewall of the pair of nanostructure channel regions. It may be challenging to control the direction and / or position of the merging of the epitaxial portions, which may result in the formation of voids in the S / D regions. In addition, because the epitaxial portions grow on different surfaces, any lattice mismatch between the epitaxial portions may cause crystal defects, such as dislocations in the S / D regions. The presence of such voids and / or crystal defects in the S / D regions may degrade the performance of the GAAFET. Furthermore, the merged portion of the p-type S / D regions (having a high concentration of germanium (Ge) atoms) may contact the internal spacers, which may lead to high parasitic resistance and capacitance, and high load-induced barrier lowering (DIBL) effect in GAA FETs, thereby degrading device performance.

[0021] In order to solve the above challenges of forming epitaxial S / D regions in GAA FETs, the present disclosure provides an example method for forming an epitaxial p-type S / D region on a nanostructure channel region to improve the epitaxial growth quality of the p-type S / D region and reduce parasitic resistance and capacitance, and DIBL effects in GAA FETs. In some embodiments, the p-type S / D region may include an epitaxial region based on Ge and an epitaxial liner along the sidewalls of the epitaxial region based on Ge. The epitaxial liner may be formed as a continuous layer on the sidewalls of the epitaxial region based on Ge facing the p-type S / D region of the nanostructure channel region and the internal spacer. In addition, a Ge-based epitaxial region may be epitaxially grown on the epitaxial liner. Epitaxially growing a Ge-based epitaxial region on a continuous layer of the epitaxial liner can improve the epitaxial growth quality of the Ge-based epitaxial region by preventing or minimizing defects from forming in the Ge-based epitaxial region, thereby improving S / D performance. The epitaxial liner may also prevent the Ge-based epitaxial region from contacting the internal spacer, thereby reducing parasitic resistance and capacitance, and DIBL effects in the GAA FET.

[0022] In some embodiments, the Ge-based epitaxial region may include a silicon germanium (SiGe) region having a Ge concentration of about 15 atomic % to about 50 atomic %. In some embodiments, the epitaxial liner may include an undoped silicon (Si) layer or a doped Si layer. In some embodiments, the doped Si layer may include boron and / or gallium dopants. In some embodiments, the concentration of the boron and / or gallium dopants may be about 1×10 20 Atom / cm 3 About 5×10 21 Atom / cm 3 . In some embodiments, the epitaxial liner can be Ge-free or can have a low concentration of Ge atoms (e.g., about 1 atomic % to about 20 atomic %, or about 6 atomic % to about 12 atomic %). In some embodiments, the portion of the epitaxial liner on the sidewalls of the nanostructure channel region can be thicker than the portion of the epitaxial liner on the sidewalls of the internal spacer. In some embodiments, the epitaxial liner can have a thickness of about 1 nm to about 12 nm to appropriately form a continuous layer on the sidewalls of the nanostructure channel region and the internal spacer facing the Ge-based epitaxial region.

[0023] Figure 1A An isometric view of a semiconductor device 100 having a PFET 102P and an NFET 102N (also referred to as “GAA PFET 102P and GAA NFET 102N”) is shown in accordance with some embodiments. Figure 1B The PFET 102P with additional structures according to some embodiments is shown along Figure 1A The cross-sectional view of line AA is shown in Figure 1 for simplicity. Figure 1AThese additional structures are not shown in FIG. Figure 1C An additional structure according to some embodiments is shown. Figure 1B An enlarged cross-sectional view of region 102P1 is shown for simplicity in Figure 1B These additional structures are not shown in FIG. Figure 1D and Figure 1E An additional structure according to some embodiments is shown. Figure 1C Different enlarged cross-sectional views of region 102P2 are shown for simplicity in FIG. Figure 1C These additional structures are not shown in FIG. Figure 1F According to some embodiments Figure 1C A top view of region 102P2. Figure 1G According to some embodiments Figure 1C An isometric view of area 102P2. Figure 1H , Figure 1J , Figure 1L and Figure 1N According to some embodiments, Figure 1A and Figure 1G Different cross-sectional views of line BB. Fig. 1I , Figure 1K and Figure 1M According to some embodiments, Figure 1G Different cross-sectional views of line CC. Fig.1O NFET 102N with additional structures according to some embodiments is shown along Figure 1A The cross-sectional view of the line DD is shown in Figure 1A These additional structures are not shown in FIG. Unless otherwise specified, FIG. 1A to FIG. 1O Discussion of elements with the same reference numerals in the drawings applies to each other.

[0024] The semiconductor device 100 may be formed on a substrate 104, wherein the PFET 102P and the NFET 102N are formed on different regions of the substrate 104. Other FETs and / or structures (e.g., isolation structures) may be formed between the PFET 102P and the NFET 102N on the substrate 104. In some embodiments, the substrate 104 may be a semiconductor material, such as Si, Ge, SiGe, a silicon-on-insulator (SOI) structure, and combinations thereof. In addition, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). The semiconductor device 100 may also include a shallow trench isolation (STI) region 105 disposed on the substrate 104. The STI region 105 may include an insulating material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), silicon germanium oxide (SiGeO2), or a plurality of other insulating materials. x ).

[0025] refer to Figure 1A and Figure 1B In some embodiments, the PFET 102P may include: (i) a fin substrate 106 (also referred to as a "sheet substrate 106") disposed on the substrate 104; (ii) an S / D region 108 disposed on the fin substrate 106; (iii) a nanostructure channel region 110 disposed adjacent to the S / D region 108; (iv) a gate structure 112 surrounding the nanostructure channel region 110; (v) a conductive cap layer 114; (vi) an insulating cap layer 116; (vii) an external gate spacer 118 disposed along a sidewall of the gate structure 112; (viii) an internal gate spacer 120 disposed along a sidewall of the S / D region 108; (ix) an ESL 122 disposed directly above the S / D region 108; (x) an ILD layer 124 disposed directly above the ESL 122; and (xi) an isolation structure 126. The S / D regions 108 may be referred to individually or collectively as a source or a drain, depending on the context.

[0026] In some embodiments, the fin base 106 may include a material similar to the substrate 104. The fin base 106 may have an elongated side extending along the X-axis. In some embodiments, the nanostructure channel region 110 may be in the form of a nanosheet, a nanowire, a nanorod, a nanotube, or other suitable nanostructure shape. As used herein, the term "nanostructure" defines a structure, layer, and / or region as having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) of less than about 100 nm (e.g., about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm). The nanostructure channel region 110 may include a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructure channel region 110 may include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon phosphide carbon (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), III-V semiconductor compounds, or other suitable semiconductor materials. In some embodiments, each of the nanostructure channel regions 110 may have a thickness of about 3 nm to about 15 nm along the Z axis. Although the nanostructure channel regions 110 are shown as rectangular cross-sections, the nanostructure channel regions may have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal).

[0027] Each gate structure 112 may be a multi-layer structure and may surround the nanostructure channel region 110, for which the gate structure 112 may be referred to as a "GAA structure" and the PFET 102P may be referred to as a GAA FET 102P. In some embodiments, the gate spacing S1 may be about 15 nm to about 25 nm. The gate spacing S1 is defined as the distance along the X-axis between adjacent gate structures 112. In some embodiments, each gate structure 112 may include (i) an interface oxide (IL) layer; (ii) a high-k (HK) gate dielectric layer disposed on the IL layer; (iii) a work function metal (WFM) layer disposed on the HK gate dielectric layer; and (iv) a gate metal fill layer disposed on the WFM layer. For simplicity, the different layers of the gate structure 112 are not shown.

[0028] In some embodiments, the IL layer may include SiO2, silicon germanium oxide (SiGeO x ) or germanium oxide (GeO xIn some embodiments, the HK gate dielectric layer may include a HK dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium aluminum oxide (ZrAlO), zirconium silicate (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium zinc oxide (HfZnO), and yttrium oxide (Y2O3). In some embodiments, the WFM layer may include a titanium (Ti)-based or tantalum (Ta)-based nitride or alloy that is substantially free of Al (e.g., without Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu). In some embodiments, the gate metal fill layer may include a suitable conductive material, for example, tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys and combinations thereof.

[0029] The conductive capping layer 114 may provide a conductive interface between the gate structure 112 and a gate contact structure (not shown) to electrically connect the gate structure 112 to the gate contact structure without forming the gate contact structure directly above or within the gate structure 112. The gate contact structure is not formed directly above or within the gate structure 112 to prevent the gate structure 112 from being contaminated by any processing material used to form the gate contact structure. In some embodiments, the conductive capping layer 114 may include a metal material, such as W, Ru, Mo, Co, other suitable metal materials, and combinations thereof.

[0030] The insulating capping layer 116 may be disposed directly above the conductive capping layer 114 and may protect the underlying conductive capping layer 114 from structural and / or compositional degradation during subsequent processing of the semiconductor device 100. In some embodiments, the insulating capping layer 116 may include a dielectric nitride or carbide material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbide (SiC), silicon oxycarbonitride (SiCON), and other suitable dielectric nitride or carbide materials.

[0031] In some embodiments, the gate structure 112 can be electrically isolated from the adjacent S / D region 108 by an external gate spacer 118. In some embodiments, the external gate spacer 118 can include an insulating material, such as SiO2, SiN, SiCN, SiOCN, and combinations thereof. In some embodiments, the portion of the gate structure 112 surrounding the nanostructure channel region 110 can be electrically isolated from the adjacent S / D region 108 by an internal gate spacer 120. The internal gate spacer 120 can include an insulating material, such as SiO2, SiN, SiCN, SiOCN, and combinations thereof. x , SiN, SiCN, SiOCN and combinations thereof.

[0032] In some embodiments, the ESL 122 may have a dielectric constant of about 4 to about 7. In some embodiments, the ESL 122 may include a dielectric material such as lanthanum oxide (LaO), aluminum oxide (Al2O3), yttrium oxide (Y2O3), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), SiOCN, SiOC, SiCN, zirconium nitride (ZrN), aluminum zirconium oxide (ZrAlO), TiO2, Ta2O3, ZrO2, HfO2, SiN, hafnium silicide (HfSi), aluminum oxynitride (AlON), SiO2, SiC, SiN, and zinc oxide (ZnO). In some embodiments, the ILD layer 124 may be disposed directly above the ESL 122. In some embodiments, the ILD layer 124 may include an insulating material such as SiO2, SiN, SiON, SiCN, and SiOCN. In some embodiments, the top surfaces of the ILD layer 124, the ESL 122, and the insulating cap layer 116 may be substantially coplanar with each other.

[0033] In some embodiments, an isolation structure 126 may be disposed below the S / D region 108 and in a recessed region of the fin substrate 106. As described in detail below, the recessed region in the fin substrate 106 may be formed during the formation of the S / D region 108. The isolation structure 126 may prevent the S / D region 108 from being epitaxially grown on the fin substrate 106 and prevent dopants from diffusing from the S / D region 108 to the fin substrate 106, thereby preventing current leakage between the S / D regions 108 and short channel effects in the PFET 102P. In some embodiments, each isolation structure 126 may include an undoped Si layer.

[0034] In some embodiments, a top surface 126t of the isolation structure 126 may be higher than a top surface 106t of the fin substrate 106. In some embodiments, the isolation structure 126 may extend into the fin substrate 106 by a distance D1 of about 10 nm to about 20 nm. In some embodiments, if the distance D1 is less than about 10 nm, the isolation structure 126 may not be sufficient to prevent dopants from diffusing from the S / D region 108 to the fin substrate 106. On the other hand, if the distance D1 is greater than about 20 nm, the processing time (e.g., etching time, deposition time) to form the isolation structure 126 increases, and thus the manufacturing cost of the PFET 102P increases.

[0035] refer to Figures 1A to 1C In some embodiments, each S / D region 108 may be disposed above the fin substrate 106 and may be electrically isolated from the fin substrate 106 by an isolation structure 126. In some embodiments, each S / D region 108 may include (i) a pair of epitaxial liners 108A facing each other and (ii) a Ge-based epitaxial region 108B. Each epitaxial liner 108A may form a continuous layer on the sidewalls of the nanostructure channel region 110 and the internal gate spacer 120 facing the S / D region 108 and along the YZ plane. The continuous layer of the epitaxial liner 108A may serve as a seed layer for epitaxially growing the Ge-based epitaxial region 108B. Epitaxially growing the Ge-based epitaxial region 108B on the continuous layer of the epitaxial liner 108A may improve the epitaxial growth quality of the Ge-based epitaxial region 108B by preventing or minimizing the formation of defects in the Ge-based epitaxial region 108B, thereby improving the performance of the PEFT 102B. The epitaxial liner 108A can also prevent the Ge-based epitaxial region 108B from contacting the internal gate spacer 120, thereby reducing parasitic resistance and capacitance in the PFET 102P, and the DIBL effect. In addition, as described in detail below, the epitaxial liner 108A can act as an ESL and protect the Ge-based epitaxial region from being etched during the formation of the gate structure 112.

[0036] A first portion 108A1 of the epitaxial liner 108A may be disposed and epitaxially grown directly over the sidewall of the nanostructure channel region 110 facing the S / D region 108 and along the YZ plane. A second portion 108A2 of the epitaxial liner 108A may be disposed directly over the sidewall of the internal gate spacer 120 facing the S / D region 108 and along the YZ plane. The second portion 108A2 of the epitaxial liner 108A may be formed by merging adjacent first portions 108A1 of the epitaxial liner 108A. In some embodiments, the sidewall of the epitaxial liner 108A in contact with the sidewalls of the nanostructure channel region 110 and the internal gate spacer 120 may have a curved cross-sectional profile. In some embodiments, the sidewall of the first portion 108A1 in contact with the Ge-based epitaxial region 108B may have a faceted cross-sectional profile, while the sidewall of the second portion 108A2 in contact with the Ge-based epitaxial region 108B may have a curved cross-sectional profile. In some embodiments, the facet cross-sectional profile may have a facet angle A of about 60 degrees to about 180 degrees. In some embodiments, a crystal direction of the facet sidewalls of the first portion 108A1 along the X-axis may be the same as a crystal direction of the substrate 104 .

[0037] In some embodiments, the epitaxial liner 108A may be an undoped Si layer or a doped Si layer. In some embodiments, the epitaxial liner 108A may include a boron dopant concentration of about 1×10 20 Atom / cm 3 To about 5×10 21 Atom / cm 3 , or about 6×10 20 Atom / cm 3 To about 8×10 20 Atom / cm 3 In some embodiments, the epitaxial liner 108A may include a gallium dopant concentration of about 1×10 20 Atom / cm 3 About 5×10 21 Atom / cm 3 In some embodiments, the epitaxial liner 108A may be Ge-free, or may include a low Ge concentration of about 1 atomic % to about 20 atomic %, or about 6 atomic % to about 12 atomic %.

[0038] In some embodiments, the epitaxial liner 108A may include a two-layer stack—an outer liner 130A and an inner liner 130B, such as Figure 1DAs shown. The outer liner 130A may form a continuous layer on the sidewalls of the nanostructure channel region 110 and the inner gate spacer 120 facing the S / D region 108 and along the YZ plane. The inner liner 130B may be disposed on the outer liner 130A and may form a continuous layer on the outer liner 130A. In some embodiments, the outer liner 130A may include an undoped Si layer, and the inner liner 130B may include a boron dopant concentration of about 1×10 20 Atom / cm 3 To about 5×10 21 Atom / cm 3 or about 6×10 20 Atom / cm 3 To about 8×10 20 Atom / cm 3 , or a gallium dopant concentration of about 1×10 20 Atom / cm 3 About 5×10 21 Atom / cm 3 In some embodiments, the outer liner 130A and the inner liner 130B may be Ge-free, or may include a low Ge concentration of about 1 atomic % to about 20 atomic %, or about 6 atomic % to about 12 atomic %. In some embodiments, the inner liner 130B may be thicker along the X-axis than the outer liner 130A.

[0039] In some embodiments, the epitaxial liner 108A may include a three-layer stack - an outer liner 132A, an intermediate liner 132B, and an inner liner 132C. Figure 1E As shown. The outer liner 132A may form a continuous layer on the sidewalls of the nanostructure channel region 110 and the inner gate spacer 120 facing the S / D region 108 and along the YZ plane. The intermediate liner 132B may be disposed on the outer liner 132A and may form a continuous layer on the outer liner 132A. The inner liner 132C may be disposed on the intermediate liner 132B and may form a continuous layer on the intermediate liner 132B. In some embodiments, the intermediate liner 132B may include an undoped Si layer, while the outer liner 132A and the inner liner 132C may include a doped Si layer. In some embodiments, the dopant concentration of the outer liner 132A may be lower than the dopant concentration of the inner liner 132C. In some embodiments, the outer liner 132A may have a dopant concentration of about 1×10 20 Atom / cm 3 To about 3×10 20 Atom / cm 3 The boron or gallium dopant concentration of the inner liner 132C may have a concentration of about 8×10 20 Atom / cm 3 To about 1×1021 Atom / cm 3 In some embodiments, the outer liner 132A, the intermediate liner 132B, and the inner liner 132C may be Ge-free or may include a low Ge concentration of about 1 atomic % to about 20 atomic %, or about 6 atomic % to about 12 atomic %. In some embodiments, the inner liner 132C may be thicker along the X-axis than the intermediate liner 132B and the outer liner 132A.

[0040] refer to Figure 1C In some embodiments, the first portion 108A1 of the epitaxial liner 108A may have a thickness T1 of about 1 nm to about 12 nm, or about 1.3 nm to about 2.3 nm. In some embodiments, the second portion 108A2 of the epitaxial liner 108A may have a thickness T2 of about 1 nm to about 12 nm, or about 0.5 nm to about 1.5 nm. In some embodiments, the thickness T1 may be greater than the thickness T2. In some embodiments, the first portion 108A1 of the epitaxial liner 108A with boron and germanium dopants may have a smaller aspect ratio (ratio between thickness T1 and height H1) than the first portion 108A1 of the epitaxial liner 108A with boron dopants and without germanium. In some embodiments, the first portion 108A1 with boron dopants and about 6 atomic % Ge may have an aspect ratio (T1:H1) of about 1:3 to about 1:4, while the first portion 108A1 with boron dopants and without germanium may have an aspect ratio (T1:H1) of about 1:2. In some embodiments, when the first portion 108A1 of the epitaxial liner 108A is formed on a stack of two to five nanostructure channel regions 110, it may have an aspect ratio (T1:H1) of about 1:4 to about 1:6. In some embodiments, when the epitaxial liner 108A is formed on a stack of more than five nanostructure channel regions 110, the aspect ratio of the first portion 108A1 formed on the topmost nanostructure channel region 110 may be greater than the aspect ratio of the first portion 108A1 formed on the bottommost nanostructure channel region 110.

[0041] In some embodiments, the first portion 108A1 of the epitaxial liner 108A may extend below the external gate spacer 118 to within a distance D2 of about 1 nm to about 2 nm from the adjacent gate structure 112. Within the range of the distance D2, the epitaxial liner 108A may reduce or minimize the channel resistance in the nanostructure channel region 110. The epitaxial liner 108A having the above concentration and / or size may be appropriately used as an ESL and reduce or minimize parasitic resistance and capacitance, and DIBL effect in the PFET 102P.

[0042] Figure 1F and Figure 1G They are shown respectively Figure 1C A top view and an isometric view of region 102P2, and Figure 1H Shown along Figure 1G For simplicity, Figure 1H The gate structure 112 surrounding the nanostructure channel region 110 and the internal gate spacer 120 is not shown. In some embodiments, the epitaxial liner 108A can be wider than the nanostructure channel region 110 along the Y axis, such as Figure 1F , Figure 1G and Figure 1H As shown. Figure 1F and Figure 1H As shown, epitaxial liner 108A may extend laterally by thicknesses T3 and T4 on either side of nanostructure channel region 110. In some embodiments, thicknesses T3 and T4 may be about 1 nm to about 12 nm.

[0043] In some embodiments, the thickness of the epitaxial liner 108A along the X-axis and the width of the epitaxial liner 108A along the Y-axis may vary with the width of the nanostructure channel region 110 and the fin substrate 106 , as shown in FIG. Figures 1I to 1N shown. Fig. 1I , Figure 1K and Figure 1M The graphs along the nanostructure channel region 110 and the fin base 106 are shown for different widths. Figure 1G Different cross-sectional views of line CC. Figure 1J , Figure 1L and Figure 1N The graphs along the nanostructure channel region 110 and the fin base 106 are shown for different widths. Figure 1G In some embodiments, when the width of the nanostructure channel region 110 and the fin base 106 is increased from the width W1 ( Figure 1J ) increases to width W2( Figure 1L ), and increases to width W3( Figure 1N ), the thickness of the epitaxial liner 108A along the X-axis can be increased from the thickness T5 ( Fig. 1I ) increases to thickness T8( Figure 1K ), and increases to a thickness of T11( Figure 1M ). In some embodiments, when the width W1 is about 11 nm, the thickness T5 may be about 1 nm to about 10 nm, when the width W2 is about 20 nm, the thickness T8 may be about 1.5 nm to about 15 nm, and when the width W3 is about 100 nm, the thickness T11 may be about 2 nm to about 20 nm.

[0044] Similarly, in some embodiments, when the width of the nanostructure channel region 110 and the fin base 106 is increased from the width W1 ( Figure 1J ) increases to width W2( Figure 1L ), and increases to width W3( Figure 1N ), the width of the epitaxial liner 108A and the Ge-based epitaxial region 108B along the Y axis can increase. As a result, the thickness of the extended portion of the epitaxial liner 108A extending over the side of the nanostructure channel region 110 increases along the Y axis, such as Figure 1J , Figure 1L and Figure 1N In some embodiments, when the width W1 is about 11 nm, the extended portion of the epitaxial liner 108A may have a thickness T6 and T7 of about 1 nm to about 3 nm. Figure 1J In some embodiments, when the width W2 is about 20 nm, the extended portion of the epitaxial liner 108A may have a thickness T9 and T10 of about 1.5 nm to about 5 nm. Figure 1L In some embodiments, when the width W3 is about 100 nm, the extended portion of the epitaxial liner 108A may have thicknesses T12 and T13 of about 2 nm to about 10 nm, as shown in FIG. Figure 1N shown.

[0045] refer to Figure 1C , the Ge-based epitaxial region 108B may be disposed on and in contact with the epitaxial liner 108A and the isolation structure 126. In some embodiments, the Ge-based epitaxial region 108B may include: (i) an epitaxial sub-region 108B1 epitaxially grown on the epitaxial liner 108A and the isolation structure 126; (ii) an epitaxial sub-region 108B2 epitaxially grown on the epitaxial sub-region 108B1; (iii) an epitaxial sub-region 108B3 epitaxially grown on the epitaxial sub-region 108B2; and (iv) an epitaxial sub-region 108B4 epitaxially grown on the epitaxial sub-regions 108B1, 108B2, and 108B3. In some embodiments, epitaxial sub-region 108B4 may act as a capping layer to prevent dopants from out-diffusion from epitaxial sub-regions 108B1 , 108B2 , and 108B3 and protect S / D region 108 during subsequent processing of PFET 102P.

[0046] In some embodiments, epitaxial sub-regions 108B1, 108B2, 108B3, and 108B4 may include epitaxially grown SiGe layers and may differ from one another based on the relative concentration of Ge atoms relative to Si atoms. In some embodiments, epitaxial sub-region 108B1 may include a Ge atomic concentration of about 15 atomic % to about 20 atomic % (any remaining atomic % being Si atoms) and may have a thickness of about 3 nm to about 4 nm. In some embodiments, each of epitaxial sub-regions 108B2, 108B3, and 108B4 may include a Ge atomic concentration of about 45 atomic % to about 55 atomic %, and any remaining atomic % being Si atoms.

[0047] In some embodiments, the epitaxial sub-regions 108B1, 108B2, 108B3, and 108B4 may be different from each other based on the concentration of p-type dopants (eg, boron atoms or gallium atoms). In some embodiments, the epitaxial sub-region 108B1 may include approximately 7×10 20 Atom / cm 3 To about 8×10 20 Atom / cm 3 In some embodiments, the epitaxial sub-region 108B2 may include about 8×10 20 Atom / cm 3 To about 1×10 21 Atom / cm 3 In some embodiments, each of the epitaxial sub-regions 108B3 and 108B4 may include approximately 1×10 21 Atom / cm 3 To about 2×10 21 Atom / cm 3 The boron dopant concentration is

[0048] refer to Figure 1A and Fig.1OIn some embodiments, the NFET 102N may include: (i) a fin substrate 107 (also referred to as a "sheet substrate 107") disposed on the substrate 104; (ii) an S / D region 109 disposed on the fin substrate 107; (iii) a nanostructure channel region 110 disposed adjacent to the S / D region 109; (iv) a gate structure 112 surrounding the nanostructure channel region 110; (v) a conductive cap layer 114; (vi) an insulating cap layer 116; (vii) an external gate spacer 118 disposed along a sidewall of the gate structure 112; (viii) an internal gate spacer 120 disposed along a sidewall of the S / D region 109; (ix) an ESL 122 disposed directly above the S / D region 109; (x) an ILD layer 124 disposed directly above the ESL 122; and (xi) an isolation structure 126 disposed below the S / D region 109. The S / D regions 109 may be referred to individually or collectively as a source or a drain, depending on the context. FIG. 1A to FIG. 1O Discussion of elements with the same reference numerals in the drawings applies to each other.

[0049] In some embodiments, the fin substrate 107 may include an n-type dopant (e.g., phosphorus or arsenic). In some embodiments, for the NFET 102N, the WFM layer of the gate structure 112 may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable aluminum-based materials.

[0050] In some embodiments, each S / D region 109 may include: (i) an S / D sub-region 109A epitaxially grown on the sidewall of the nanostructure channel region 110; (ii) an S / D sub-region 109B epitaxially grown on the S / D sub-region 109A; (iii) an S / D sub-region 109C epitaxially grown on the S / D sub-region 109B; (iv) an S / D sub-region 109D epitaxially grown on the S / D sub-region 109C; and (v) an S / D sub-region 109E epitaxially grown on the S / D sub-region 109D. The S / D sub-region 109A may be disposed directly above the nanostructure channel region 110 and may be in contact with the nanostructure channel region 110. In some embodiments, the number of S / D sub-regions 109A in each S / D region 109 may be equal to the number of nanostructure channel regions 110 facing each S / D region 109. For example, as Fig.1O As shown, the S / D region 109 includes eight S / D sub-regions 109A, which are equal to eight nanostructure channel regions 110 facing the S / D region 109 .

[0051] In some embodiments, the S / D sub-regions 109A, 109B, 109C, 109D, and 109E may include an epitaxially grown Si layer without any Ge atoms and may differ from each other based on the concentration of n-type dopants (e.g., phosphorus or arsenic atoms). In some embodiments, the S / D sub-region 109A may be undoped. In some embodiments, the S / D sub-region 109B may include approximately 1×10 20 Atom / cm 3 To about 1×10 21 Atom / cm 3 In some embodiments, the S / D sub-region 109C may include about 1×10 21 Atom / cm 3 To about 4×10 21 Atom / cm 3 In some embodiments, each of the S / D sub-regions 109D and 109E may include about 1×10 21 Atom / cm 3 To about 2×10 21 Atom / cm 3 The phosphorus dopant concentration is

[0052] Figure 2 According to some embodiments, the invention is used to manufacture the above reference Figures 1A to 1H 102P. For purposes of illustration, reference will be made to an exemplary method 200 for manufacturing a PFET 102P. Figures 3 to 9 An example manufacturing process of the PFET 102P is shown to describe Figure 2 The operation shown. Figures 3 to 9 According to some embodiments, PFET 102P is manufactured at various stages along the Figure 1A AA cross-sectional view of the method 200. The operations may be performed in a different order or not performed, depending on the particular application. It should be noted that the method 200 may not produce a complete PFET 102P. Therefore, it should be understood that additional processes may be provided before, during, and after the method 200, and only some of the other processes are briefly described herein. Unless otherwise specified, the Figures 1A to 1H as well as Figures 3 to 9 Discussion of elements with the same reference numerals in the drawings applies to each other.

[0053] refer to Figure 2 In operation 205, a superlattice structure is formed on the fin substrate, and a polysilicon structure is formed on the superlattice structure. Figure 3As described, a superlattice structure 311 (also referred to as a "nanosheet stack 311") is formed on the fin substrate 106, and a polysilicon structure 312 is formed on the superlattice structure 311. In some embodiments, a hard mask layer 342 and a hard mask layer 344 may be formed during the formation of the polysilicon structure 312. The superlattice structure 311 may include a nanostructure layer 110 and a nanostructure layer 310 arranged in an alternating configuration. In some embodiments, the nanostructure layer 110 may include Si, and the nanostructure layer 310 may include SiGe. In some embodiments, each of the nanostructure layer 110 and the nanostructure layer 310 may have a thickness of about 3 nm to about 15 nm along the Z axis. The nanostructure layer 310 is also referred to as a "sacrificial layer 310". During subsequent processing, the polysilicon structure 312 and the sacrificial layer 310 may be replaced with the gate structure 112 in a gate replacement process.

[0054] refer to Figure 2 In operation 210, S / D openings and spacer openings are formed in the superlattice structure, and isolation trenches are formed in the fin substrate. Figure 4 As described above, S / D openings 408 and spacer openings 420 are formed in the superlattice structure 311, and isolation trenches 426 are formed in the fin substrate 106. The S / D openings 408 may be formed by etching a portion of the superlattice structure 311 that is not covered by the polysilicon structure 312. After the S / D openings 408 are formed, isolation trenches 426 are formed, and the isolation trenches 426 extend into the fin substrate 106 by a distance D1. In some embodiments, the isolation trenches 426 may be formed by performing an etching process on a portion of the fin substrate 106 that is exposed in the S / D openings 408.

[0055] In some embodiments, etching of the superlattice structure 311 and the fin substrate 106 may include a plasma-based dry etching process using an etching gas such as carbon tetrafluoride (CF4), sulfur dioxide (SO2), hexafluoroethane (C2F6), chlorine (Cl2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and hydrogen bromide (HBr) and a mixed gas such as hydrogen (H2), oxygen (O2), nitrogen (N2), and argon (Ar). The etching may be performed at a temperature in a range of about 25°C to about 200°C and a pressure of about 5mTorr to about 50mTorr. The flow rate of the etching gas may be in a range of from about 5 standard cubic centimeters per minute (sccm) to about 100sccm. The plasma power may be in a range of from about 50W to about 200W, and the bias voltage may be about 30V to about 200V.

[0056] After forming the isolation trench 426, the spacer opening 420 can be formed by performing an etching process on the sidewall of the sacrificial layer 310 facing the S / D opening 408. The etching process can laterally etch the sacrificial layer 310 to laterally recess the sidewall of the sacrificial layer 310 relative to the sidewall of the nanostructure layer 110 facing the S / D opening 408. The etching process may include a dry etching process that has a higher etching selectivity for SiGe of the sacrificial layer 310 than for Si of the nanostructure layer 110. For example, a halogen-based chemical may exhibit a higher etching selectivity for Ge than for Si. Therefore, the halogen gas may etch SiGe faster than Si. In some embodiments, the halogen-based chemical may include a fluorine-based and / or chlorine-based gas. Alternatively, the etching of the sacrificial layer 310 may include a wet etching process that has a higher selectivity for SiGe than for Si. For example, the wet etching process may include using a mixture of sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ), and / or a mixture of ammonium hydroxide (NH 4 OH) with H 2 O 2 and deionized (DI) water.

[0057] refer to Figure 2 In operation 215, an internal gate spacer is formed in the spacer opening. For example, as shown in FIG. Figure 5 As described above, the internal gate spacer 120 is formed in the spacer opening 420. The formation of the internal gate spacer 120 may include the following sequential operations: (i) Figure 4 depositing a dielectric material layer (not shown) on the structure; and (ii) etching the dielectric material layer to form Figure 5 In some embodiments, the etching of the dielectric material layer may be an anisotropic dry etching process and may have a higher etching rate along the Z axis rather than along the X axis or the Y axis. As a result, the portion of the dielectric material layer in the S / D opening 408 and the isolation trench 426 may be etched, while the portion of the dielectric material layer in the spacer opening 420 may not be etched.

[0058] refer to Figure 2 In operation 220, an isolation structure is formed in the isolation trench. Figure 6 As described above, the isolation structure 126 is formed in the isolation trench 426 . In some embodiments, forming the isolation structure 126 may include: epitaxially growing an undoped silicon layer on the exposed surface of the fin substrate 106 in the isolation trench 426 .

[0059] refer to Figure 2 In operation 225, S / D regions are formed in the S / D openings. For example, as shown in FIG. Figure 7 and Figure 8As described above, the S / D region 108 is formed in the S / D opening 408. The formation of the S / D region 108 may include the following sequential operations: (i) epitaxially growing an epitaxial liner 108A on the sidewall of the nanostructure layer 110 facing the S / D opening 408, such as Figure 7 (ii) epitaxially growing an epitaxial sub-region 108B1 on the epitaxial liner 108A, as shown Figure 8 (iii) epitaxially growing an epitaxial sub-region 108B2 on the epitaxial sub-region 108B1, as shown in FIG. Figure 8 (iv) epitaxially growing an epitaxial sub-region 108B3 on the epitaxial sub-region 108B2; and (v) epitaxially growing an epitaxial sub-region 108B4 on the epitaxial sub-regions 108B1, 108B2 and 108B3, as shown Figure 8 In some embodiments, epitaxial growth of epitaxial liner 108A may be initiated by growing an epitaxial layer just above the sidewalls of nanostructure layer 110. Epitaxial growth of epitaxial liner 108A may continue until the epitaxial layers extend vertically to merge with each other and form a continuous layer on the sidewalls of nanostructure layer 110 and internal gate spacer 120, as shown. Figure 7 shown.

[0060] In some embodiments, epitaxially growing the epitaxial liner 108A may include exposing the S / D openings 408 to a Si precursor gas (e.g., dichlorosilane (DCS) gas or silane (SiH4) gas) and a boron precursor gas (e.g., diboron (B2H6) gas) at a temperature of about 500° C. to about 700° C. and a pressure of about 20 Torr to about 80 Torr. In some embodiments, the epitaxial liner 108A may be formed in a dual temperature epitaxial process, the epitaxial liner 108A having the structure described above with reference to FIG. Figure 1D The two-layer stack - the outer liner 130A and the inner liner 130B. In some embodiments, the outer liner 130A can be formed at a lower temperature than the inner liner 130B. In some embodiments, the S / D opening 408 can be exposed to a Si precursor gas at a temperature of about 400° C. to about 500° C. and a pressure of about 20 Torr to about 30 Torr to grow the undoped Si layer of the outer liner 130A. After growing the outer liner 130A, the S / D opening 408 and the outer liner 130A can be exposed to a Si precursor gas and a boron precursor gas at a temperature of about 500° C. to about 700° C. and a pressure of about 20 Torr to about 80 Torr to grow the doped Si layer of the inner liner 130B.

[0061] In some embodiments, during the epitaxial growth of the epitaxial liner 108A, the S / D opening 408 may also be exposed to an etching gas (e.g., a hydrogen chloride (HCl) gas having a gas flow rate of about 1 sccm to about 200 sccm) to control the thickness of the epitaxial liner 108A. In some embodiments, when the S / D opening 408 is exposed to the boron precursor gas having a gas flow rate of about 100 sccm, the S / D opening 408 may be exposed to an etching gas having a gas flow rate of about 50 sccm.

[0062] Within the above-noted ranges of temperature, pressure, and gas flow rates, the epitaxial liner 108A may be epitaxially grown with sufficient thickness and dopant concentration to function as an ESL and to reduce or minimize parasitic resistance and capacitance, and DIBL effects in the PFET 102P.

[0063] In some embodiments, after forming the S / D regions 108, the ESL 122 and the ILD layer 124 may be formed. Fig. 9 shown.

[0064] refer to Figure 2 In operation 230, the polysilicon structure and the sacrificial layer of the superlattice structure are replaced with the gate structure. Fig. 9 As described above, the polysilicon structure 312 and the sacrificial layer 310 are replaced with the gate structure 112. The gate structure 112 may include: Figure 8 The hard mask layer 342 and the hard mask layer 344, the polysilicon structure 312 and the sacrificial layer 310 are removed from the structure to form a gate opening (not shown), and a gate structure 112 is formed in the gate opening, such as Fig. 9 In some embodiments, after forming the gate structure 112, a conductive capping layer 114 and an insulating capping layer 116 may be formed. Fig. 9 shown.

[0065] In some embodiments, Figure 2 The method 200 may be used to form a PFET 102P and an NFET 102N substantially parallel to each other on the same substrate 104. In some embodiments, elements of the PFET 102P and NFET 102N may be formed simultaneously, except for their S / D regions, which may be formed sequentially. FIG. 10A to FIG. 13A and FIG. 10B to FIG. 13B The sequential formation of the S / D region 108 of the PFET 102P and the S / D region 109 of the NFET 102N is shown. FIG. 10A to FIG. 13A PFET 102P is shown at various stages of its fabrication along the Figure 1A The cross-sectional view of line AA, FIG. 10B to FIG. 13Bshows NFET 102N at various stages of its fabrication along the Figure 1A Unless otherwise stated, Figure 1A To Figure 10, FIG. 10A to FIG. 13A and FIG. 10B to FIG. 13B Discussion of elements with the same reference numerals in the drawings applies to each other.

[0066] Before forming the S / D regions 108 and 109, the substrate 104 may be subjected to Figure 2 Operations 205, 210, 215 and 220 are used to form Fig. 10A and Fig. 10B The fin substrate 106 and the fin substrate 107 may be substantially parallel to each other. In some embodiments, the S / D region 109 may be formed after the S / D region 108 is formed. The formation of the S / D region 108 may include the following sequential operations: (i) Fig. 10B A bottom anti-reflective coating (BARC) layer 1146 is deposited on the structure of the NFET 102N in the Fig. 11B (ii) depositing a hard mask layer 1148 (eg, aluminum oxide (AlO)) on the BARC layer 1146; x ) layer); (iii) Fig. 10A The structure of the PFET 102P is implemented Figure 2 Operation 225 is performed to form the S / D region 108, such as Fig.11A as shown; and (iv) from Fig. 11B The hard mask layer 1148 and the BARC layer 1146 are removed from the structure of FIG. The BARC layer 1146 and the hard mask layer 1148 can prevent the S / D region 108 from being formed in the S / D opening 408 of the NFET 102N.

[0067] Similar to forming the S / D region 108, forming the S / D region 109 may include the following sequential operations: (i) Fig.11A The BARC layer 1246 is deposited on the PFET 102P structure to form Fig. 12A (ii) depositing a hard mask layer 1248 (eg, AlO) on the BARC layer 1246; x (iii) performing a step of removing the hard mask layer 1148 and the BARC layer 1146 on the structure of the NFET 102N; Figure 2 Operation 225 is performed to form the S / D region 109, such as Fig. 12B as shown; and (iv) from Fig. 12A The hard mask layer 1248 and the BARC layer 1246 are removed from the structure. The BARC layer 1246 and the hard mask layer 1248 can prevent the S / D region 109 from being formed on the S / D region 108.

[0068] In some embodiments, after forming the S / D regions 108 and the S / D regions 109, the ESL 122 and the ILD layer 124 may be formed. Fig.13A and Fig. 13B In some embodiments, Fig.13A and Fig. 13B Operation 230 is performed to form gate structures 112 in PFET 102P and NFET 102N.

[0069] The present disclosure provides an example method of forming an epitaxial p-type S / D region (e.g., S / D region 108) on a nanostructure channel region (e.g., nanostructure channel region 110) to improve the epitaxial growth quality of the p-type S / D region and reduce parasitic resistance and capacitance, and DIBL effect in GAAFET. In some embodiments, the p-type S / D region may include a Ge-based epitaxial region (e.g., Ge-based epitaxial region 108B) and an epitaxial liner (e.g., epitaxial liner 108A) along the sidewalls of the Ge-based epitaxial region. The epitaxial liner may be formed as a continuous layer on the sidewalls of the Ge-based epitaxial region facing the p-type S / D region of the nanostructure channel region and the internal spacer (e.g., internal spacer 120). In addition, a Ge-based epitaxial region may be epitaxially grown on the epitaxial liner. Epitaxially growing a Ge-based epitaxial region on a continuous layer of the epitaxial liner may improve the epitaxial growth quality of the Ge-based epitaxial region by preventing or minimizing the formation of defects in the Ge-based epitaxial region, thereby improving S / D performance. The epitaxial liner can also prevent the Ge-based epitaxial region from contacting the internal spacer, thereby reducing parasitic resistance and capacitance in the GAA FET, as well as the DIBL effect.

[0070] In some embodiments, the Ge-based epitaxial region may include a silicon germanium (SiGe) region having a Ge concentration of about 15 atomic % to about 50 atomic %. In some embodiments, the epitaxial liner may include an undoped silicon (Si) layer or a doped Si layer. In some embodiments, the doped Si layer may include boron and / or gallium dopants. In some embodiments, the concentration of the boron and / or gallium dopants may be about 1×10 20 Atom / cm 3 About 5×10 21 Atom / cm 3. In some embodiments, the epitaxial liner can be Ge-free or can have a low concentration of Ge atoms (e.g., about 1 atomic % to about 20 atomic %, or about 6 atomic % to about 12 atomic %). In some embodiments, the portion of the epitaxial liner on the sidewalls of the nanostructure channel region (e.g., portion 108A1) can be thicker than the portion of the epitaxial liner on the sidewalls of the internal spacer (e.g., portion 108A2). In some embodiments, the epitaxial liner can have a thickness of about 1 nm to about 12 nm to appropriately form a continuous layer on the sidewalls of the nanostructure channel region and the internal spacer facing the Ge-based epitaxial region.

[0071] In some embodiments, a semiconductor device includes: a substrate, a first nanostructure channel region and a second nanostructure channel region disposed on the substrate, a gate structure surrounding the first nanostructure channel region and the second nanostructure channel region, an internal gate spacer disposed along a sidewall of the gate structure and between the first nanostructure channel region and the second nanostructure channel region, and an S / D region. The S / D region includes: an epitaxial liner disposed along the sidewalls of the first nanostructure channel region and the second nanostructure channel region and the internal gate spacer, and a germanium-based epitaxial region disposed on the epitaxial liner. The semiconductor device also includes an isolation structure disposed between the germanium-based epitaxial region and the substrate.

[0072] In some embodiments, a semiconductor device includes: a substrate, a first nanosheet layer and a second nanosheet layer disposed on the substrate, a first gate structure and a second gate structure surrounding the first nanosheet layer and the second nanosheet layer, respectively, a first gate spacer and a second gate spacer disposed along sidewalls of the first gate structure and the second gate structure, respectively, and an S / D region. The S / D region includes: a first germanium-free epitaxial liner disposed as a continuous layer along the sidewalls of the first nanosheet layer and the first gate spacer, a second germanium-free epitaxial liner disposed as a continuous layer along the sidewalls of the second nanosheet layer and the second gate spacer, and a germanium-based epitaxial region disposed between the first germanium-free epitaxial liner and the second germanium-free epitaxial liner.

[0073] In some embodiments, a method includes: forming a nanosheet stack having a nanostructure layer and a sacrificial layer on a substrate; forming a polysilicon structure on the nanosheet stack; etching the nanostructure layer and the sacrificial layer to form S / D openings and isolation trenches in the nanosheet stack; forming an internal spacer on the sidewall of the sacrificial layer; forming an undoped semiconductor layer in the isolation trench; forming a germanium-free epitaxial liner as a continuous layer on the sidewalls of the nanostructure layer and the internal spacer; and epitaxially growing a germanium-based layer on the germanium-free epitaxial liner and the undoped semiconductor layer.

[0074] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0075] Example 1. A semiconductor device, comprising: a substrate; a first nanostructure channel region and a second nanostructure channel region, which are arranged on the substrate; a gate structure, surrounding the first nanostructure channel region and the second nanostructure channel region; an internal gate spacer, arranged along the sidewalls of the gate structure and between the first nanostructure channel region and the second nanostructure channel region; a source / drain S / D region, comprising: an epitaxial liner, arranged along the sidewalls of the first nanostructure channel region and the second nanostructure channel region and the internal gate spacer; and a germanium-based epitaxial region, arranged on the epitaxial liner; and an isolation structure, arranged between the germanium-based epitaxial region and the substrate.

[0076] Example 2. A semiconductor device according to Example 1, wherein the epitaxial liner includes: a first portion having a first thickness, disposed on side walls of the first nanostructure channel region and the second nanostructure channel region; and a second portion having a second thickness, disposed on side walls of the internal gate spacer, wherein the first thickness is greater than the second thickness.

[0077] Example 3. A semiconductor device according to Example 1, wherein the epitaxial liner includes: a first portion having a small plane sidewall profile, which is arranged on the sidewalls of the first nanostructure channel region and the second nanostructure channel region; and a second portion having a curved sidewall profile, which is arranged on the sidewalls of the internal gate spacer.

[0078] Example 4. The semiconductor device of Example 1, wherein the epitaxial liner comprises an undoped silicon layer.

[0079] Example 5. The semiconductor device of Example 1, wherein the epitaxial liner comprises a germanium-free silicon layer including a boron or gallium dopant.

[0080] Example 6. The semiconductor device of Example 1, wherein the epitaxial liner comprises a silicon layer comprising germanium atoms at a concentration of 6 atomic % to 12 atomic %.

[0081] Example 7. The semiconductor device according to Example 1, wherein the epitaxial liner includes a silicon layer, the silicon layer includes a concentration of 1×10 20 Atom / cm 3 to 5×10 21 Atom / cm 3 of boron or gallium atoms.

[0082] Example 8. A semiconductor device according to Example 1, wherein the epitaxial liner includes: an undoped silicon layer disposed on the first nanostructure channel region and the second nanostructure channel region and the sidewalls of the internal gate spacer; and a doped silicon layer disposed on the undoped silicon layer.

[0083] Example 9. A semiconductor device according to Example 1, wherein the epitaxial liner includes: a first doped silicon layer having a first concentration of a dopant, disposed on the first nanostructure channel region and the second nanostructure channel region and the sidewalls of the internal gate spacer; an undoped silicon layer, disposed on the first doped silicon layer; and a second doped silicon layer having a second concentration of a dopant, disposed on the undoped silicon layer, wherein the second concentration is greater than the first concentration.

[0084] Example 10. The semiconductor device of Example 1, wherein the isolation structure comprises an undoped semiconductor layer.

[0085] Example 11. A semiconductor device, comprising: a substrate; a first nanosheet layer and a second nanosheet layer, arranged on the substrate; a first gate structure and a second gate structure, surrounding the first nanosheet layer and the second nanosheet layer, respectively; a first gate spacer and a second gate spacer, arranged along the side walls of the first gate structure and the second gate structure, respectively; and a source / drain S / D region, comprising: a first epitaxial lining, arranged as a continuous layer along the side walls of the first nanosheet layer and the first gate spacer; a second epitaxial lining, arranged as a continuous layer along the side walls of the second nanosheet layer and the second gate spacer; and an epitaxial region, arranged between the first epitaxial lining and the second epitaxial lining.

[0086] Example 12. The semiconductor device of Example 11, wherein the first epitaxial liner and the second epitaxial liner include a first germanium-free epitaxial liner and a second germanium-free epitaxial liner, respectively.

[0087] Example 13. The semiconductor device according to Example 11 further includes an undoped semiconductor layer disposed on the substrate and between the first nanosheet layer and the second nanosheet layer, wherein the first epitaxial liner, the second epitaxial liner and the epitaxial region are disposed on the undoped semiconductor layer and in contact with the undoped semiconductor layer.

[0088] Example 14. The semiconductor device of Example 11, wherein the first epitaxial liner and the second epitaxial liner include undoped silicon layers.

[0089] Example 15. The semiconductor device of Example 11, wherein the first epitaxial liner and the second epitaxial liner include a boron-doped or gallium-doped silicon layer.

[0090] Example 16. The semiconductor device of Example 11, wherein a width of the first epitaxial liner is greater than a width of the first nanosheet layer.

[0091] Example 17. A method for manufacturing a semiconductor device, comprising: forming a nanosheet stack including a nanostructure layer and a sacrificial layer on a substrate; forming a polysilicon structure on the nanosheet stack; etching the nanostructure layer and the sacrificial layer to form source / drain S / D openings and isolation trenches in the nanosheet stack; forming an internal spacer on the sidewall of the sacrificial layer; forming an undoped semiconductor layer in the isolation trench; forming an epitaxial liner as a continuous layer on the sidewalls of the nanostructure layer and the internal spacer; and epitaxially growing a germanium-based layer on the epitaxial liner and the undoped semiconductor layer.

[0092] Example 18. The method of Example 17, wherein forming the epitaxial liner comprises epitaxially growing a germanium-free and undoped silicon layer on the sidewalls of the nanostructure layer.

[0093] Example 19. The method of Example 17, wherein forming the epitaxial liner comprises: epitaxially growing a boron-doped or gallium-doped silicon layer on a sidewall of the nanostructure layer.

[0094] Example 20. A method according to Example 17, wherein forming the epitaxial liner includes: forming a first portion having a first thickness on the sidewall of the nanostructure layer; and forming a second portion having a second thickness on the sidewall of the internal spacer, wherein the first thickness is greater than the second thickness.

Claims

1. A semiconductor device, comprising: substrate; A first nanostructure channel region and a second nanostructure channel region are disposed on the substrate; a gate structure surrounding the first nanostructure channel region and the second nanostructure channel region; an internal gate spacer disposed along a sidewall of the gate structure and between the first nanostructure channel region and the second nanostructure channel region; Source / drain S / D regions, including: an epitaxial liner disposed along sidewalls of the first nanostructure channel region and the second nanostructure channel region and the inner gate spacer; and a germanium-based epitaxial region disposed on the epitaxial liner; and An isolation structure is disposed between the germanium-based epitaxial region and the substrate.

2. The semiconductor device according to claim 1, wherein The epitaxial lining comprises: a first portion having a first thickness disposed on sidewalls of the first nanostructure channel region and the second nanostructure channel region; and A second portion having a second thickness is disposed on a sidewall of the inner gate spacer, wherein the first thickness is greater than the second thickness.

3. The semiconductor device according to claim 1, wherein The epitaxial lining comprises: a first portion having a faceted sidewall profile disposed on sidewalls of the first nanostructured channel region and the second nanostructured channel region; and A second portion having a curved sidewall profile is disposed on a sidewall of the inner gate spacer.

4. The semiconductor device according to claim 1, wherein: The epitaxial liner includes an undoped silicon layer.

5. The semiconductor device according to claim 1, wherein The epitaxial liner includes a germanium-free silicon layer including a boron or gallium dopant.

6. The semiconductor device according to claim 1, wherein The epitaxial liner includes a silicon layer including germanium atoms at a concentration of 6 atomic % to 12 atomic %.

7. The semiconductor device according to claim 1, wherein The epitaxial liner includes a silicon layer, wherein the silicon layer includes a concentration of 1×10 20 Atom / cm 3 to 5×10 21 Atom / cm 3 of boron or gallium atoms.

8. The semiconductor device according to claim 1, wherein The epitaxial lining comprises: an undoped silicon layer disposed on the first nanostructure channel region, the second nanostructure channel region and the sidewalls of the internal gate spacer; and The doped silicon layer is disposed on the undoped silicon layer.

9. A semiconductor device comprising: substrate; A first nanosheet layer and a second nanosheet layer are disposed on the substrate; A first gate structure and a second gate structure surround the first nanosheet layer and the second nanosheet layer, respectively; A first gate spacer and a second gate spacer are disposed along side walls of the first gate structure and the second gate structure, respectively; as well as Source / drain S / D regions, including: a first epitaxial liner disposed as a continuous layer along sidewalls of the first nanosheet layer and the first gate spacer; a second epitaxial liner disposed as a continuous layer along sidewalls of the second nanosheet layer and the second gate spacer; and The epitaxial region is disposed between the first epitaxial liner and the second epitaxial liner.

10. A method for manufacturing a semiconductor device, comprising: forming a nanosheet stack including a nanostructure layer and a sacrificial layer on a substrate; forming a polysilicon structure on the nanosheet stack; etching the nanostructure layer and the sacrificial layer to form source / drain S / D openings and isolation trenches in the nanosheet stack; forming inner spacers on sidewalls of the sacrificial layer; forming an undoped semiconductor layer in the isolation trench; forming an epitaxial liner as a continuous layer on the sidewalls of the nanostructure layer and the internal spacers; as well as A germanium-based layer is epitaxially grown on the epitaxial liner and the undoped semiconductor layer.

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