A power mosfet device structure with improved short circuit tolerance

Abstract

Disclosed is a power MOSFET device structure with improved short circuit tolerance, in which a first-conductivity-type epitaxial drift region is located above a first-conductivity-type substrate, a first base region of a second-conductivity-type is located in the first-conductivity-type epitaxial drift region, a second base region of the second-conductivity-type is located in the first-conductivity-type epitaxial drift region, the first base region and the second base region are in contact with each other, a heavily doped base region of the second-conductivity-type is located in the first base region or in the first base region and extends into the second base region, a source region of the first-conductivity-type is heavily doped and is located in the first base region and in contact with the heavily doped base region, a current spreading region of the first-conductivity-type is in contact with the first base region and the second base region and extends into the first-conductivity-type epitaxial drift region beyond the second base region, a gate oxide region is located above the first base region, part of the current spreading region and part of the source region in contact, and a polysilicon region is located above the gate oxide region.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of silicon carbide (SiC) power devices, and in particular to a power MOSFET device structure for improving short-circuit resistance. BACKGROUND

[0002] Wide bandgap semiconductor materials have gradually been widely researched and applied, especially in replacing traditional Si-based devices in high power density applications, and have excellent performance, thanks to the more superior performance of the materials, which are more suitable for application in high-voltage, high-temperature, high-frequency, and other scenarios. SiC MOSFET, as an excellent substitute for Si IGBT, has better breakdown performance, faster switching speed, and smaller on-resistance, and has gradually been widely applied in electric vehicle inverters and photovoltaic inverters and other application scenarios, and has outstanding advantages in improving system power density and miniaturizing the system.

[0003] For SiC power MOSFET, thanks to the higher saturation electron drift speed and the thinner drift region thickness, a lower characteristic on-resistance can be achieved, and at the same time, a higher current density can be achieved. In comparison with Si IGBT, IGBT can generally withstand 10 μs of short-circuit stress when a short-circuit event occurs, and the main heat is mainly concentrated in the drift region, rather than below the channel. At the same time, since the Si IGBT has a thicker drift region thickness at the same voltage level, it can accommodate more heat diffusion. The heat of the SiC MOSFET is mainly concentrated in the current spreading region, and the thinner drift region thickness makes the heat of the gate oxide part concentrate faster, resulting in melting at the top of the device. The general SiC MOSFET can only achieve about 3 μs of short-circuit stress.

[0004] In order to enhance the short-circuit resistance, various schemes are proposed to regulate the resistance on the conduction path to improve the short-circuit performance, such as adding a lightly doped N-drift region in the source region and limiting the P region, improving the resistance on the path, and at the same time, having a certain pinch-off performance under high voltage. However, at the same time, such a structure greatly limits the over-current capacity of the device at room temperature.

[0005] The information disclosed in the background section merely serves to enhance the understanding of the background of the present application, and therefore can contain information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] Aiming at the deficiencies or defects of the prior art, a power MOSFET device structure with improved short-circuit resistance is provided, which improves the first-conductivity-type doping concentration and distribution of the current spreading region and the doping concentration and distribution shape of the second-conductivity-type base region, increases the field plate structure of the source to enhance the charge regulation effect, reduces the overcurrent capacity of the SiC MOSFET at high temperature in the short-circuit condition, thereby reducing the heat generation in the short-circuit process, while little affecting the overcurrent capacity in the conduction process, and the short-circuit performance of the device is improved.

[0007] The object of the present application is achieved by the following technical solutions.

[0008] A power MOSFET device structure with improved short-circuit resistance comprises,

[0009] a first-conductivity-type substrate,

[0010] a first-conductivity-type epitaxial drift region above the first-conductivity-type substrate,

[0011] a first base region of a second conductivity type in the first-conductivity-type epitaxial drift region,

[0012] a second base region of the second conductivity type in the first-conductivity-type epitaxial drift region, the first base region and the second base region being in contact with each other,

[0013] a heavily doped base region of the second conductivity type in the first base region or in the first base region and extending into the second base region,

[0014] a source region of the first conductivity type, which is heavily doped, the source region being in the first base region and in contact with the heavily doped base region,

[0015] a current spreading region of the first conductivity type, which is in contact with the first base region and the second base region and extends into the first-conductivity-type epitaxial drift region beyond the second base region,

[0016] a gate oxide region above the first base region, part of the current spreading region and part of the source region,

[0017] a polysilicon region above the gate oxide region.

[0018] The power MOSFET device structure with improved short-circuit resistance further comprises,

[0019] a source field plate region above the current spreading region and spaced between the gate oxide regions,

[0020] a source contact region below the heavily doped base region, the source field plate region and part of the source region.

[0021] The power MOSFET device structure with improved short-circuit tolerance further comprises an oxide isolation region between the source contact region and the polysilicon region to separate the source contact region and the polysilicon region.

[0022] The power MOSFET device structure with improved short-circuit tolerance has a width of the source field plate region less than a width of the current spreading region.

[0023] The power MOSFET device structure with improved short-circuit tolerance has a first conductivity type of N type and a second conductivity type of P type.

[0024] The power MOSFET device structure with improved short-circuit tolerance has a first conductivity type of P type and a second conductivity type of N type.

[0025] The power MOSFET device structure with improved short-circuit tolerance has a first conductivity type of P type and a second conductivity type of N type. 16 cm -3 ~ 5×10 17 cm -3 .

[0026] The power MOSFET device structure with improved short-circuit tolerance has a first conductivity type of P type and a second conductivity type of N type.

[0027] The power MOSFET device structure with improved short-circuit tolerance further comprises a drain metal electrode region below the first conductivity type substrate.

[0028] The power MOSFET device structure with improved short-circuit tolerance has a first conductivity type of P type and a second conductivity type of N type.

[0029] Compared with the prior art, the power MOSFET device structure with improved short-circuit tolerance has the following beneficial effects:

[0030] The present application benefits from a current spreading region of the first conductivity type that can be more highly doped, which is shielded by a first base region of the second conductivity type to adjust the resistance profile without reducing the overcurrent capability of the device when it is operated in the forward direction. The first base region of the second conductivity type and the second base region together with the source field plate adjust the charge when the device is operated in the reverse direction, protecting the gate oxide while achieving higher reverse performance, i.e., a certain degree of improvement in the figure of merit of the device. Due to the additional design of the second base region of the device and the structure capacitance conversion characteristics of the split gate, the device has lower gate charge and can achieve faster switching. The first base region and the second base region of the second doping type and the source field plate regulate the charge inside the device, the current spreading in the JFET is suppressed, the current at high temperature is limited, and thus the saturation current of the device at high temperature is reduced. When a short circuit occurs, the high power area is limited by the second base region in the structure of the device together with the source field plate, the temperature rise of the device is controlled, and the short circuit resistance for a longer time is achieved.

[0031] The above description is only a summary of the technical solutions of the present application. In order to make the technical solutions of the present application clearer, more detailed and understandable, and to enable the person skilled in the art to implement the content of the description, and to make the above and other purposes, features and advantages of the present application more obvious and understandable, the specific embodiments of the present application are described below. BRIEF DESCRIPTION OF DRAWINGS

[0032] Various other advantages and benefits of the present application will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a better understanding of the preferred embodiments, and are not to be considered as limiting of the present application. It should be readily understood that the drawings are merely illustrative of the present application and that they, therefore, do not limit the present application to the principles of the present application illustrated and discussed in connection with any one of the overall drawings. The same reference numerals in different drawings represent the same or similar elements.

[0033] In the drawings:

[0034] Figure 1 is a structural schematic diagram of the present application;

[0035] Figure 2 is a comparison diagram of the transfer characteristics of the present application and the prior art;

[0036] Figure 3 is a comparison diagram of the breakdown characteristics of the present application and the prior art;

[0037] Figure 4 is a comparison diagram of the short circuit current and junction temperature curves of the present application and the prior art;

[0038] Figure 5 The preparation flowchart of the present application is shown in the following.

[0039] The present application will be further explained in connection with the accompanying drawings and examples. DETAILED DESCRIPTION

[0040] The specific embodiments of the present application will be described in greater detail below with reference to the accompanying drawings. While the present application is described in terms of specific embodiments, it is to be understood that the application is not limited to these embodiments. Rather, they are provided to illustrate the present application to the accomplishment of which the application is intended to be fully

[0041] It should be noted that certain terms have been used throughout the specification and claims which have either been used as synonyms for, or to be understood via use in this patent to describe certain components. As would be understood by those skilled in the art, the components can be referred to by different names in different contexts. The specification and claims should not be construed as limited to the aforementioned terms. The description of the preferred embodiments is intended to be illustrative, and not to limit the scope of the application. What is desired to be protected by letters patent is set forth in the following claims.

[0042] In order to make the present application more clearly understood, the following further describes the embodiments of the present application with reference to the accompanying drawings and in conjunction with specific examples. The accompanying drawings do not limit the embodiments of the present application.

[0043] For better understanding, Figures 1 to 5 as shown, a power MOSFET device structure with improved short circuit withstand capability includes,

[0044] a first conductivity type substrate 212,

[0045] a first conductivity type epitaxial drift region 211 above the first conductivity type substrate 212,

[0046] a first base region 208 of a second conductivity type in the first conductivity type epitaxial drift region 211,

[0047] a second base region 209 of the second conductivity type in the first conductivity type epitaxial drift region 211, the first base region 208 and the second base region 209 being in contact with each other,

[0048] a heavily doped base region 207 of a second conductivity type disposed in the first base region 208 or in the first base region 208 and extending deeper than the second base region 209,

[0049] a source region 206 of a first conductivity type, heavily doped, disposed in the first base region 208 and in contact with the heavily doped base region 207,

[0050] a current spreading region 210 of a first conductivity type in contact with the first base region 208 and the second base region 209 and extending deeper than the second base region 209 into an epitaxial drift region 211 of the first conductivity type,

[0051] a gate oxide region 204 disposed in contact over the first base region 208, a portion of the current spreading region 210 and a portion of the source region 206,

[0052] a polysilicon region 203 disposed over the gate oxide region 204.

[0053] The preferred embodiment of the short circuit tolerant power MOSFET device structure further comprises,

[0054] a source field plate region 205 disposed over the current spreading region 210 and spaced apart from the gate oxide region 204,

[0055] a source contact region 201 disposed in close contact under the heavily doped base region 207, the source field plate region 205 and a portion of the source region 206.

[0056] The preferred embodiment of the short circuit tolerant power MOSFET device structure further comprises an oxide isolation region 202 disposed between the source contact region 201 and the polysilicon region 203 to separate the source contact region 201 and the polysilicon region 203.

[0057] The preferred embodiment of the short circuit tolerant power MOSFET device structure further comprises that the width of the source field plate region 205 is less than the width of the current spreading region 210.

[0058] The preferred embodiment of the short circuit tolerant power MOSFET device structure further comprises that the first conductivity type is N-type and the second conductivity type is P-type.

[0059] The preferred embodiment of the short circuit tolerant power MOSFET device structure further comprises that the first conductivity type is P-type and the second conductivity type is N-type.

[0060] The preferred embodiment of the short circuit tolerant power MOSFET device structure further comprises that the current spreading region 210 of the first conductivity type has a doping concentration of 1 x 1018 cm-3. 16 cm -35 x 10 17 cm -3 .

[0061] In a preferred embodiment of the power MOSFET device structure with improved short-circuit withstand capability, the depth of the current spreading region 210 of the first conductivity type exceeds the depth of the second base region 209 of the second conductivity type.

[0062] In a preferred embodiment of the power MOSFET device structure with improved short-circuit withstand capability, the power MOSFET device structure further comprises a drain metal electrode region 213 located below the first conductivity type substrate 212.

[0063] In a preferred embodiment of the power MOSFET device structure with improved short-circuit withstand capability, the polysilicon region 203 comprises a first doped type of polysilicon, the first base region 208 and the second base region 209 are of a second doped type different from the first doped type, the second base region exceeds the width of the first base region w1 by 0.3 μm to 1 μm in the width w2 extending towards the current spreading region, and the narrowest part of the current spreading region is 0.3 μm to 1 μm.

[0064] In one embodiment, a power MOSFET device structure with improved short-circuit withstand capability comprises,

[0065] a first conductivity type substrate 212,

[0066] a first conductivity type epitaxial drift region 211 located above the first conductivity type substrate 212,

[0067] a drain metal electrode region 213 located below the first conductivity type substrate 212,

[0068] a first base region 208 of a second conductivity type provided in the first conductivity type epitaxial drift region 211,

[0069] a second base region 209 of the second conductivity type provided in the first conductivity type epitaxial drift region 211, the first base region 208 and the second base region 209 being in contact with each other,

[0070] a heavily doped base region 207 of the second conductivity type provided in the first base region 208 or provided in the first base region 208 and extending into the second base region 209,

[0071] a source region 206 of the first conductivity type heavily doped, the source region 206 being provided in the first base region 208 and in contact with the heavily doped base region 207,

[0072] a current spreading region 210 of the first conductivity type in contact with the first base region 208 and the second base region 209 and extending deeper into the first conductivity type epitaxial drift region 211 than the second base region 209,

[0073] a gate oxide region 204 in contact with the first base region 208, the current spreading region 210 and the source region 206,

[0074] a polysilicon region 203 disposed on the gate oxide region 204, the polysilicon region 203 comprising polysilicon of the first doping type,

[0075] a source field plate region 205 disposed on the current spreading region 210 and spaced between the gate oxide regions 204,

[0076] a source contact region 201 in close contact with the heavily doped base region 207, the source field plate region 205 and the source region 206,

[0077] an oxide isolation region 202 disposed between the source contact region 201 and the polysilicon region 203 to separate the source contact region 201 and the polysilicon region 203.

[0078] In one embodiment, the first conductivity type substrate 212 is a silicon carbide substrate.

[0079] In one embodiment, the power MOSFET device structure for improving short-circuit withstand capability includes a silicon carbide substrate of a first conductivity type and an epitaxial drift region 211 of the first conductivity type located above the silicon carbide substrate. Below the substrate is a drain metal electrode region 213. The epitaxial drift region 211 contains a current extension region 210 and a source region 206 of the first conductivity type, a first base region 208, a second base region 209 of the second conductivity type, and a heavily doped base region 207 of the second conductivity type. The current extension region 210 is located at the center and is interlocked with the first base region 208 and the second base region 209. The first base region 208 and the second base region 209 are in contact with each other. The source region 206 is enclosed inside the first base region 208. The lateral width of the second base region 209 is greater than that of the first base region 208 and extends into the interior of the current extension region 210. The heavily doped base region 207 extends into the interior of the first base region 208 and the second base region 209 and is in contact with the source region 206, exhibiting an axisymmetric structure. Above the first conductivity type epitaxial drift region 211 are a gate oxide region 204 and a first doped polysilicon region 203. The polysilicon region 203 is stacked above the gate oxide region 204 and forms the gate region. The gate oxide region 204 is located above the first base region 208, part of the current extension region 210, and part of the source region 206. The source contact region 201 is located above the heavily doped base region 207 and part of the source region 206. The polysilicon region 203 and the source contact region 201 are separated by an oxide layer isolation region 202. Directly above the current extension region 210, at a distance from the polysilicon region 203, is an oxide layer of different thickness than the gate oxide region, forming the source field plate region 205. Above it is the source contact region 201, which is a metallic structure.

[0080] As a further technical solution, the doping concentration of the current extension region 210 of the first conductivity type is 1×10⁻⁶. 16 cm -3 ~ 5×10 17 cm -3 The width of the current extension region 210 depends on the width of the first base region 208 and the second base region 209 of the second conductivity type.

[0081] As a further technical solution, the depth of the current extension region 210 of the first conductivity type exceeds the depth of the second base region 209 of the second conductivity type.

[0082] As a further technical solution, the depth of the current extension region 210 of the first conductivity type is located within the depth range of the second base region 209 of the second conductivity type.

[0083] As a further technical solution, the depth of the current extension region 210 of the first conductivity type is shallower than the depth of the second base region 209 of the second conductivity type.

[0084] As a further technical solution, the doping concentration of the current spreading region 210 of the first conductivity type is of a gradual type, the doping concentration above the second base region 209 is different from the doping concentration of the rest, and according to different designs, it can present positive doping and reverse doping or trapezoidal doping distribution.

[0085] As a further technical solution, the doping concentration of the second base region 209 of the second conductivity type is 1×10 17 cm -3 ~ 1×10 19 cm -3 , and generally decays from the top position downward, and the doping concentration at the center position is higher, and can present uniform doping distribution.

[0086] As a further technical solution, the second base region 209 of the second conductivity type can be realized by epitaxy, and the second base region 209 of the second conductivity type is grown after the drift region of the first conductivity type is grown, and then a layer of the first conductivity type is epitaxially grown for other structures. In order to realize the corresponding structure, the width control needs to be realized by ion implantation of the first conductivity type.

[0087] As a further technical solution, the width of the second base region 209 of the second conductivity type beyond the first base region 208 is 0.3μm~1μm, and the width between the second base regions 209, that is, the narrowest part of the current spreading region 210 is 0.3μm~1μm.

[0088] As a further technical solution, the depth and doping concentration of the second base region 209 of the second conductivity type are determined according to the depth and doping concentration of the current spreading region 210 of the first conductivity type above the second base region 209.

[0089] As a further technical solution, the thickness of the source field plate region 205 is 10nm~1μm, and the dielectric type can vary from silicon dioxide to High-K dielectric.

[0090] As a further technical solution, the width of the source field plate region 205 determines the charge regulation ability of this part, and the vicinity of the contact between the source field plate region 205 and the first base region 208, the second base region 209 and the current spreading region 210 also has charge regulation ability. Adjust the relationship between the parts to achieve the desired charge regulation ability.

[0091] As a further technical solution, the source field plate region 205 structure is cancelled while the structure part of the split gate is retained to realize different charge regulation abilities. The split gate includes the gate oxide region 204 and the polysilicon region 203.

[0092] As a further technical solution, the structure part of the source field plate and the split gate are cancelled at the same time to realize different charge regulation capabilities.

[0093] In the above technical solution, for the N-type SiC power MOS device, the first conductivity type refers to N-type, and the second conductivity type refers to P-type; and for the P-type SiC power MOS device, the first conductivity type refers to P-type, and the second conductivity type refers to N-type.

[0094] In one embodiment, the SiC power MOSFET device structure for improving short-circuit resistance capability includes a first conductivity type substrate 212, a first conductivity type epitaxial drift region 211 located above the first conductivity type substrate 212, a drain metal electrode region 213 below the first conductivity type substrate 212, a first base region 208 and a second base region 209 of a second conductivity type inside the first conductivity type substrate 212, the first base region 208 and the second base region 209 contacting each other, a heavily doped base region 207 of the second conductivity type inside the first base region 208 and the second base region 209, the heavily doped base region 207 can be only inside the first base region 208 or can extend into the second base region 209, a source region 206 of the first conductivity type which is heavily doped and inside the first base region 208, the source region 206 contacting the heavily doped base region 207. The current spreading region of the first conductivity type contacts the first base region 208 and the second base region 209, and extends into the first conductivity type epitaxial drift region 211 beyond the second base region 209. Above the first conductivity type epitaxial drift region 211 are a gate oxide region 204, a polysilicon region 203, a source contact region 201 and a source field plate region 205, an oxide isolation region 202 between the source contact region and the polysilicon region, the source contact region 201 closely contacting the heavily doped base region 207 and part of the source region 206 below, the gate oxide region 204 closely contacting part of the source region 206, the first base region 208 and part of the current spreading region 210 below, the whole being an axisymmetric structure, the source field plate region 205 being located between the two parts of the split gate, the source field plate region 205 closely contacting the source contact region 201 and being located between the two parts of the oxide isolation region 202, the current spreading region 210 below the source field plate region 205 and having a width smaller than that of the current spreading region 210.

[0095] In one embodiment, the region can be a layer, such as the current spreading region can be a current spreading region layer. The layer can be stacked.

[0096] Figure 2 The transfer characteristic curve representing the newly proposed device structure is shown, which represents the normal temperature overcurrent capability of the device when the drain voltage is 20V. The simulation is obtained by using the simulation software Sentaurus TCAD.

[0097] Figure 3The breakdown characteristic curve representing the newly proposed device structure shows the ability of the device to withstand the drain voltage when the gate voltage is 0, that is, the reverse withstand voltage level of the device. The simulation is obtained by using the simulation software Sentaurus TCAD.

[0098] Figure 4 The trend of the drain current and the average junction temperature of the device over time under the short circuit condition, that is, when the gate voltage is 20V and the drain voltage is 400V, is shown. The longer the device can withstand, the stronger the ability is, and it also shows that the proposed structure can achieve better high-temperature current limiting capability and reduce the temperature rise of the device. The simulation is obtained by using the simulation software Sentaurus TCAD.

[0099] Figure 5 A process flow chart for implementing the device structure is given, which can be realized by combining the actual process.

[0100] The above describes the basic principles of the present application in combination with specific embodiments, but it should be pointed out that the advantages, advantages, effects and the like mentioned in the present application are only examples and not limitations, and these advantages, advantages, effects and the like cannot be considered as the must-have of each embodiment of the present application. In addition, the above specific details are only for the purpose of example and for the purpose of understanding, and are not limited to the above specific details to realize the present application.

[0101] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain modifications, alterations, changes, additions and sub-combinations thereof.

Claims

1. A power MOSFET device structure with improved short circuit withstand capability, characterized by, It comprises, a first conductivity type substrate, a first conductivity type epitaxial drift region over the first conductivity type substrate, a first base region of a second conductivity type in the first conductivity type epitaxial drift region, a second base region of the second conductivity type in the first conductivity type epitaxial drift region, the first and second base regions contacting each other, a heavily doped base region of the second conductivity type in the first base region or in the first base region and extending into the second base region, a source region of the first conductivity type, heavily doped, in the first base region and contacting the heavily doped base region, a current spreading region of the first conductivity type contacting the first and second base regions and extending into the first conductivity type epitaxial drift region beyond the second base region, a gate oxide region contacting the first base region, a portion of the current spreading region and a portion of the source region, a polysilicon region over the gate oxide region.

2. The short- withstand capability enhanced power MOSFET device structure of claim 1, wherein, Preferably, further comprising, a source field plate region over the current spreading region and spaced between the gate oxide regions, a source contact region contacting the heavily doped base region, the source field plate region and a portion of the source region.

3. The short resistance tolerant power MOSFET device structure of claim 2, wherein, Further comprising an oxide spacer region between the source contact region and the polysilicon region to separate the source contact region and the polysilicon region.

4. The short resistance tolerant power MOSFET device structure of Claim 2, wherein the gate oxide layer is formed of a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and silicon carbide. The source field plate region has a width less than a width of the current spreading region.

5. The short resistance tolerant power MOSFET device structure of Claim 1, wherein, The first conductivity type is N-type and the second conductivity type is P-type.

6. The short resistance tolerant power MOSFET device structure of Claim 1, wherein, The first conductivity type is P-type and the second conductivity type is N-type.

7. The short resistance tolerant power MOSFET device structure of Claim 1, wherein, The doping concentration of the current spreading region of the first conductivity type is 1 x 1015cm-3 16 cm -3 ~ 5 x 1015cm-3 17 cm -3 .

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