Shield gate groove type power MOSFET structure and preparation method thereof

Abstract

The invention relates to a shield gate groove type power MOSFET structure and a preparation method thereof, and belongs to the technical field of power semiconductors. The structure comprises a drain region, an N-type substrate and an N-type drift region from bottom to top. The trench extends downwards from the upper surface to the drift region, the upper part in the trench is provided with a control gate, and the side wall is provided with a gate oxide layer; and a shielding grid connected with the source electrode is arranged at the lower part. And a three-layer composite layer structure is arranged between the shield grid and the side wall and the bottom of the groove. A P-type floating ring is formed in the drift region at the bottom of the groove, a P-type body region is arranged above the drift region, and an N + source region is arranged in the body region. The surface of the device is covered with a dielectric layer, and the contact hole exposes part of the source region and the body region and is filled with a metal layer to form a source electrode. The three-layer composite shield gate oxide layer structure adopted by the invention can accelerate drift region depletion under the same drain-source voltage, so that the switching loss is reduced; meanwhile, the equivalent capacitance is improved, and the voltage endurance capability of the device is enhanced.

Description

Technical Field

[0001] This application belongs to the field of power semiconductor technology, specifically relating to a shielded gate trench power MOSFET structure and its fabrication method. Background Technology

[0002] In the design of power semiconductor devices, charge coupling effect is a critical factor. Traditional power semiconductor devices typically employ a shielded gate trench structure, using a shielded gate connected to the source to assist in depleting the drift region, thereby improving the electric field distribution, reducing gate-drain capacitance, and optimizing dynamic performance. However, as power electronic systems evolve towards higher voltage and higher frequency, this traditional structure has gradually revealed its limitations. First, the structure with a P-ring at the bottom of the individual trench requires additional process steps and photolithography, which not only increases production complexity but also significantly raises manufacturing costs. Second, the traditional silicon dioxide dielectric layer, due to its low dielectric constant, results in a slow device response speed, a problem particularly prominent in high-frequency applications, severely limiting device performance. This application addresses these shortcomings by proposing a novel power semiconductor device structure. By innovatively combining an optimized shielded gate design and a novel high-dielectric-constant dielectric material, it not only simplifies the manufacturing process and reduces costs but also significantly improves the device's response speed and overall performance in high-frequency applications. Summary of the Invention

[0003] To solve the above problems, the technical solution adopted in this application is: A shielded gate trench power MOSFET structure includes: The drain region is located at the bottom of the structure; An N-type substrate is located above the drain region; N - Type-2 drift region, located above the N-type substrate; The trench extends downward from the upper surface of the device, passes through the P-type body region, and enters the N-type region. - Inside the drift zone; A control gate is located in the upper part of the trench; A gate oxide layer is located on the sidewall of the control gate; A shielding grid, located in the lower part of the trench, is electrically connected to the source electrode; A composite layer is located between the sidewalls and bottom of the shielding grid and the sidewalls and bottom of the trench; P-type floating ring, formed at the bottom of the groove, N - In the drift region; The P-type body region is located in the N-type region. - Above the drift zone; N + The source region is formed on the P-type body region and located on both sides of the control gate; A dielectric layer that covers the upper surface of the device; Contact holes penetrate the dielectric layer and expose a portion of the N. + The source region and the P-type body region; A metal layer is filled in the contact hole and covers part of the surface of the dielectric layer to form a source metal.

[0004] Furthermore, the composite layer is a three-layer composite dielectric layer, consisting of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer from the inside out. The second silicon oxide layer is grown on N-type silicon oxide. - The silicon nitride layer provides a good interface with the silicon substrate in the drift region; the silicon nitride layer is the core functional layer with a dielectric constant greater than that of the silicon dioxide layer, which is used to improve the equivalent capacitance of the composite layer; the first silicon oxide layer provides a good interface for forming a stable contact with the shielding gate and provides protection for the silicon nitride layer.

[0005] Furthermore, the total thickness of the composite layer is 500 nm, wherein the second silicon oxide layer is grown by a thermal oxidation process, and the thickness of the second silicon oxide layer accounts for 1% to 4% of the total thickness; the thickness of the silicon nitride layer accounts for 9% to 26% of the total thickness, and the remaining thickness is the thickness of the first silicon oxide layer.

[0006] Furthermore, the thickness of the N-type substrate is 10 μm to 200 μm.

[0007] Furthermore, the drain region uses a high-doping concentration of N. + Type of material.

[0008] Furthermore, the depth of the trench is 1 μm to 8 μm.

[0009] Furthermore, the control gate material is polycrystalline silicon with a thickness of 100nm to 200nm, the gate oxide layer has a thickness of 10nm to 90nm, and the shielding gate has a thickness of 0.5μm to 1μm.

[0010] Furthermore, the knot depth of the P-type floating ring is 0.15 to 0.25 times the groove depth.

[0011] This application also provides a method for fabricating a shielded gate trench power MOSFET structure, including the following steps: Step S1: Epitaxial layer growth. An N-type epitaxial layer is grown on an N-type substrate. The crystal orientation of the N-type epitaxial layer is 100, the epitaxial thickness is 8-10 μm, and the resistivity is 0.1-0.3 Ω·cm. Step S2, trench etching: Trenches are formed on the N-type epitaxial layer through photolithography and etching processes. Specific steps include: Step S21: Dry etching, using anisotropic plasma etching, with an etching angle of 88°~89° and a depth of 1μm~8μm, to form a deep trench with steep sidewalls; Step S22: Wet etching, followed by isotropic wet etching, using an acidic solution to etch silicon, forming smooth, sharp corners at the bottom of the trenches to improve the electric field distribution; the etching rate is the same in all directions, with lateral and longitudinal etching reaching 1.0 μm to 1.1 μm; Step S3 involves implantation of the P-type body region and P-type ring. The implantation region is defined by photolithography. First, a 0.01 μm to 0.03 μm SiO2 layer is grown by thermal oxidation as the screen oxide layer, followed by boron ion implantation. The implantation energy is 90–210 keV, and the dose is 5 × 10⁻⁶ keV. 12 ~1×10 13 cm -2 Then, annealing is carried out in a high-temperature, inert gas environment to activate impurities and form P-type body regions and P-type floating rings. Step S4: Composite layer growth. A composite layer serving as the shielding barrier medium is grown within the trench. This specifically includes the following steps: Step S41: Grow a second silicon oxide layer with a thickness of 5nm to 20nm by thermal oxidation process at a temperature of 900℃ to 1100℃; Step S42: Grow a silicon nitride layer with a thickness of 45nm to 130nm by LPCVD (chemical vapor deposition); Step S43: Deposit a first silicon oxide layer with a thickness of 350 nm to 450 nm using PECVD (plasma-enhanced chemical vapor deposition) with a TEOS source at 350 °C to 500 °C. Step S5: Shielding gate growth. A phosphorus-doped polycrystalline silicon shielding gate is deposited by LPCVD. The thickness of the shielding gate is 0.5μm to 1μm, the temperature is 500℃ to 600℃, and it is wet-etched to the corresponding position. Then, the composite layer is wet-etched to the corresponding position. Step S6: Dielectric layer deposition, using HDPCVD method to deposit a dielectric layer for isolating the control gate and the shielding gate; Step S7, formation of the gate oxide layer and the control gate: First, a sacrificial oxide layer with a thickness of 0.01μm to 0.03μm is grown to remove surface impurities, clean the silicon surface, and repair damage; then, the final gate oxide layer is grown through a thermal oxidation process at an oxidation temperature of 900℃ to 1100℃, with a gate oxide layer thickness of 0.01μm to 0.09μm, the appropriate gate oxide layer thickness being selected according to different threshold voltages; phosphorus-doped polysilicon is deposited and etched by LPCVD, simultaneously etching away SiO2 and polysilicon on the silicon wafer surface, forming the control gate on the upper part of the trench; Steps S8 and N +Source region implantation: The source region is defined by photolithography, and arsenic ion implantation is performed at an energy of 40–50 keV and a dose of 0.8 × 10⁻⁶. 15 ~1.2×10 15 cm -2 Then anneal at 900℃~1000℃ for 25~35 minutes to form N + Source region; Step S9: Contact hole etching. SiO2 is deposited via PECVD as the interlayer dielectric layer. Contact holes are etched using photolithography and dry etching processes. The width of the contact holes is 0.3 μm to 0.5 μm, and the depth extends into the P-type body region. BF2 ion implantation is performed through the contact holes to form P-type bodies in the P-type body region. + In the contact area, reduce contact resistance and suppress the turn-on of parasitic NPN transistors; annealing temperature is 700℃~900℃, time is 40 seconds~60 seconds; Step 10: Metallization. An Al metal layer with a thickness of 3 μm to 8 μm is deposited by sputtering, and source and gate metal electrodes are formed by photolithography and etching.

[0012] Compared with the prior art, the beneficial effects of this application are as follows: 1. This application provides a shielded gate trench power MOSFET structure. This application adopts a three-layer composite shielded gate oxide layer structure, which can make the drift region deplete faster under the same drain-source voltage and reduce switching losses. The three-layer composite layer structure in this application improves the equivalent capacitance of the composite layer and enhances the voltage withstand capability of the device.

[0013] 2. This application provides a shielded gate trench power MOSFET structure. By forming a P-type floating ring at the bottom of the trench, this application effectively improves the electric field distribution, reduces electric field concentration, thereby reducing the breakdown voltage of the device and improving the reliability of the device. The smooth rounded corner design at the bottom of the trench, achieved through a wet etching process, further optimizes the electric field distribution, reduces local high electric field regions, and improves the withstand voltage performance of the device.

[0014] 3. This application provides a method for fabricating a shielded gate trench power MOSFET structure. Each step in the fabrication method of this application adopts a mature semiconductor manufacturing process, which has good process compatibility and is easy to realize large-scale production. Attached Figure Description

[0015] Figure 1 This is a structural diagram of the present application; Figure 2 This is a flowchart of the epitaxial layer growth process of the preparation method in this application; Figure 3 This is a flow chart of the trench etching process for the preparation method of this application; Figure 4 This is a process flow diagram of the P-type body region fabrication method of the present application; Figure 5 This is a flowchart of the composite layer etching process for the preparation method of this application; Figure 6 This is a flowchart of the shielding gate growth process of the preparation method in this application; Figure 7 This is a flowchart of the gate oxide layer growth process of the preparation method in this application; Figure 8 This is a flowchart of the metal layer photolithography process for the preparation method of this application; Figure 9 This is a diagram showing the electric field distribution E curve of the structure in this application; Figure 10 This is a plot of the gate charge Qg curve for the structure of this application; Figure 11 This is a structural simulation diagram of this application.

[0016] In the diagram: 1. Drain region, 2. N-type substrate, 3. N - 4. P-type drift region, 5. Control gate, 6. Gate oxide layer, 7. Shielding gate, 8. First silicon oxide layer, 9. Silicon nitride layer, 10. Second silicon oxide layer, 11. P-type floating ring, 12. Trench, 13. N-type floating ring. + 13. Source region, 14. P-type body region, 15. Contact hole, 16. Metal layer, 17. Dielectric layer. Detailed Implementation

[0017] The present application will be further described in detail below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present application.

[0018] like Figures 1 to 11 As shown, this application provides a shielded gate trench power MOSFET structure, including, from bottom to top, a drain region 1, an N-type substrate 2, and an N-type gate trench. - Type drift region 3. The drain region 1 is a highly doped N-type region. + For the N-type material, the typical thickness of the N-type substrate 2 is 10 μm to 200 μm; In the active region of the device, the N - A P-type body region 13 is formed above the drift region 3. A trench 11 extends downwards from the upper surface of the device, successively passing through the P-type body region 13 and penetrating into the N-type drift region. - Within the drift region 3, the depth of the trench 11 can be any value ranging from 1 μm to 8 μm, with an optimal etching depth of 5.8 μm. The N-type depth at the bottom of the trench 11 is...- In the drift region 3, a P-type floating ring 10 is formed by ion implantation and annealing. The junction depth of the P-type floating ring 10 is any value in the range of 0.15μm to 2μm, and the optimal junction depth is 1.16μm. This structure helps to optimize the electric field distribution and improve the breakdown voltage of the device.

[0019] The trench 11 is divided into upper and lower parts. The lower part of the trench 11 is filled with a shielding gate 6, which is made of phosphorus-doped or boron-doped polycrystalline silicon with a thickness ranging from 0.5 μm to 1 μm, with an optimal thickness of 0.8 μm. A composite dielectric layer is provided between the sidewalls and bottom of the shielding gate 6 and the silicon surface of the trench 11. This composite layer has a three-layer structure, consisting of, from the inside out: a first silicon oxide layer 7, a silicon nitride layer 8, and a second silicon oxide layer 9. The second silicon oxide layer 9 is grown on N-type silicon oxide. - On the drift region 3, a good interface with the silicon substrate is provided; the silicon nitride layer 8 is the core functional layer, with a dielectric constant greater than that of the silicon dioxide layer, used to improve the equivalent capacitance of the composite layer; the first silicon oxide layer 7 provides a good interface for stable contact with the shielding gate 6 and provides protection for the silicon nitride layer 8. In this application, P-type implantation is performed at the bottom of the trench 11, and the P-type body region 13 is generated simultaneously, without the need for additional processes, saving costs. Figure 9 The figure shows the longitudinal electric field distribution E curves of the two simulated structures. Figure 9 It can be seen that the optimized structure's electric field distribution is more approximately rectangular, the peak electric field at the bottom of trench 11 is reduced by 21.05%, and the breakdown voltage is increased by 10%. In this application, a three-layer composite dielectric layer (SiO2 / Si3N4 / SiO2) is used instead of the SiO2 used in the ordinary structure, and the dielectric layer thickness is reduced by 13% compared to the original thickness. Figure 9 The image shows two simulated structures. C gd The curve shows that the gate-drain capacitance C gd The Miller platform was reduced in size by 33.3%, optimizing dynamic characteristics. For example... Figure 11 The image shown is a simulated two-dimensional planar structure of the structure described in this application. Figure 11 In the diagram, the X-axis represents the vertical distance from the silicon surface to the substrate; the Y-axis represents the horizontal distance, and the structure is symmetrical along the Y-axis. The colored areas represent the doping concentration of that region.

[0020] The total thickness of the composite layer is 500 nm, wherein the second silicon oxide layer 9 is grown by a thermal oxidation process, and the thickness of the second silicon oxide layer 9 accounts for 1% to 4% of the total thickness; the thickness of the silicon nitride layer 8 accounts for 9% to 26% of the total thickness, and the remaining thickness is the thickness of the first silicon oxide layer 7. In this embodiment, the optimal thickness of the second silicon oxide layer 9 is 7 nm, the optimal thickness of the silicon nitride layer 8 is 100 nm, and the optimal thickness of the first silicon oxide layer is 393 nm.

[0021] The upper part of trench 11 is the control gate 4, which is made of phosphorus-doped polycrystalline silicon with a thickness of 100nm to 200nm. The sidewalls of the control gate 4 are connected to the silicon body (P-type body region 13 and N-type body region 14). - The gate oxide layer 5 isolates the drift regions 3 from each other. The gate oxide layer 5 is generally very thin, with a thickness of 10 nm to 90 nm. The optimal thickness of the gate oxide layer 5 is 50 nm. The control gate 4 and the shielding gate 6 below are electrically isolated by the subsequently filled dielectric layer 16.

[0022] N-type structures are formed on both sides of the upper part of the P-type body region 13. + Source region 12. The upper surface of the device is covered by dielectric layer 16, and contact hole 14 penetrates dielectric layer 16, exposing part of N. + Source region 12 and the underlying P-type body region 13. Metal layer 15 fills contact hole 14 and partially covers the surface of dielectric layer 16. The upper metal layer 15 forms the source metal for connecting the source potential. The source penetrates into the N-type region through contact hole 14. + Source region 12 is connected to shielding gate 6 to achieve connection with N + Ohmic contact between source region 12 and P-type body region 13.

[0023] The thickness of the N-type substrate 2 is 10μm to 200μm, wherein the optimal thickness of the N-type substrate 2 is 150μm.

[0024] The drain region 1 uses a high-doped N2O3 concentration. + Type of material.

[0025] This application also provides a method for fabricating a shielded gate trench power MOSFET structure, including the following steps: Step S1: Epitaxial layer growth. An N-type epitaxial layer is grown on an N-type substrate 2. The N-type epitaxial layer has a crystal orientation of 100, an epitaxial thickness of 8–10 μm, and a resistivity of 0.1–0.3 Ω·cm. In this application, the crystal orientation of 100 for the N-type epitaxial layer refers to a crystal orientation index of 100, which describes a specific direction of atomic arrangement in silicon crystals. This orientation determines the surface properties of the epitaxial layer and the substrate, directly affecting the quality of subsequent key process steps such as oxidation and etching, and the electrical performance of the final device. For modern MOS devices, a 100 crystal orientation is the preferred choice for manufacturing high-quality gate oxide.

[0026] Step S2, trench etching: Trench 11 is formed on the N-type epitaxial layer by photolithography and etching processes. Specific steps include: Step S21: Dry etching, using anisotropic plasma etching, with an etching angle of 88° to 89° and a depth of 1 μm to 8 μm, to form a deep trench with steep sidewalls; in this embodiment, the optimal etching depth of the trench 11 is 5.8 μm.

[0027] Step S22: Wet etching, followed by isotropic wet etching, using an acidic solution to etch silicon to form smooth, sharp corners at the bottom of trench 11, improving the electric field distribution; the etching rate is the same in all directions, with lateral and longitudinal co-etching of 1.0 μm to 1.1 μm, and the optimal lateral and longitudinal co-etching width is 1.02 μm; Step S3 involves implantation of the P-type body region and P-type ring. The implantation area is defined by photolithography. First, a 0.01 μm to 0.03 μm SiO2 layer is grown by thermal oxidation as the screen oxide layer. The optimal thickness of the screen oxide layer is 0.02 μm. Then, boron ion implantation is performed. The implantation energy is 90–210 keV, and the dose is 5 × 10⁻⁶ keV. 12 ~1×10 13 cm -2 Then, annealing is carried out in a high-temperature, inert gas environment to activate impurities and form P-type body region 13 and P-type floating ring 10. Step S4: Composite layer growth. A composite layer serving as the shielding gate medium is grown within trench 11, specifically including the following steps: Step S41: Grow a second silicon oxide layer 9 by thermal oxidation process, with a thickness of 5nm to 20nm and a temperature of 900℃ to 1100℃; the optimal thickness of the second silicon oxide layer 9 is 7nm. Step S42: A silicon nitride layer 8 is grown by LPCVD (chemical vapor deposition) with a thickness of 45 nm to 130 nm; the optimal thickness of the silicon nitride layer 8 is 100 nm. Step S43: Deposit the first silicon oxide layer 7 with a thickness of 350 nm to 450 nm using PECVD (plasma-enhanced chemical vapor deposition) with a TEOS source at 350 °C to 500 °C; the optimal thickness of the first silicon oxide layer is 393 nm.

[0028] Step S5: Shielding gate growth. A phosphorus-doped or boron-doped polycrystalline silicon shielding gate 6 is deposited by LPCVD. The thickness of the shielding gate 6 is 0.5 μm to 1 μm, the temperature is 500℃ to 600℃, and it is wet-etched to the corresponding position. Then, the composite layer is wet-etched to the corresponding position. The optimal thickness of the shielding gate 6 is 0.8 μm. Step S6: Dielectric layer deposition. The dielectric layer 16 is deposited using the HDPCVD method to fill and isolate the control gate 4 and shielding gate 6 that are subsequently formed. Step S7, formation of the gate oxide layer and control gate: First, a sacrificial oxide layer with a thickness of 0.01 μm to 0.03 μm is grown to remove surface impurities, clean the silicon surface, and repair damage. Then, the final gate oxide layer 5 is grown through a thermal oxidation process at an oxidation temperature of 900℃ to 1100℃. The thickness of the gate oxide layer 5 is 0.01 μm to 0.09 μm, and the appropriate gate oxide layer thickness is selected according to different threshold voltages; the optimal thickness of the gate oxide layer 5 is 50 nm. Phosphorus-doped polysilicon is deposited by LPCVD and etched, simultaneously etching away SiO2 and polysilicon on the silicon wafer surface to form the control gate 4 in the upper part of the trench. Steps S8 and N + Source region implantation: The source region is defined by photolithography, and arsenic ion implantation is performed at an energy of 40–50 keV and a dose of 0.8 × 10⁻⁶. 15 ~1.2×10 15 cm -2 Then anneal at 900℃~1000℃ for 25~35 minutes to form N + Source region 12; Step S9: Contact hole etching. SiO2 is deposited by PECVD as the interlayer dielectric layer. Contact holes 14 are etched using photolithography and dry etching processes. The width of contact holes 14 is 0.3 μm to 0.5 μm, and the depth extends into the P-type body region 13. BF2 ion implantation is performed through contact holes 14 to form P-type bodies in the P-type body region 13. + The contact area reduces contact resistance and suppresses the turn-on of parasitic NPN transistors; the annealing temperature is 700℃~900℃, the time is 40 seconds~60 seconds, the optimal annealing time is 48 seconds, and the optimal hole width of contact hole 14 is 0.4μm. Step 10: Metallization. An Al metal layer 15 is formed by sputtering, with a thickness of 3 μm to 8 μm, and the optimal thickness of the metal layer 15 is 5 μm. The source and gate metal electrodes are then formed by photolithography and etching.

[0029] The shielded gate trench power MOSFET provided in this application achieves the following beneficial effects by introducing a three-layer composite dielectric layer (SiO2 / Si3N4 / SiO2) as the insulating layer of the shielded gate and optimizing the design of the P-type floating ring: Optimized electric field distribution: The P-type floating ring and the smooth trench bottom work together to make the electric field distribution more uniform when the device is reverse biased, which significantly improves the breakdown voltage.

[0030] Reduced gate-drain capacitance: The shielded gate structure effectively reduces the overlap area between the control gate and the drain, thereby reducing Miller capacitance (Cgd), improving the switching speed of the device, and reducing switching losses.

[0031] Improved interface properties: The composite dielectric layer combines the good interface properties of thermally oxidized SiO2 with the high dielectric constant of Si3N4. While ensuring insulation reliability, it enhances the depletion effect of the shielding field plate on the drift region, which helps to reduce the on-resistance.

[0032] High process compatibility: All process steps adopted are conventional technologies in the semiconductor manufacturing field, which are easy to integrate and implement, and have good industrialization prospects.

[0033] Of course, the above embodiments are not intended to limit this application, and this application is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of this application should also fall within the protection scope of this application.

Claims

1. A shielded gate trench power MOSFET structure, characterized in that: include: Drain region (1) is located at the bottom of the structure; The N-type substrate (2) is located above the drain region (1); N - Type drift region (3) is located above N-type substrate (2); The trench (11) extends downward from the upper surface of the device, passes through the P-type body region (13), and enters the N-type body region. - Inside the drift zone (3); The control gate (4) is located in the upper part of the trench (11); A gate oxide layer (5) is located on the sidewall of the control gate (4); The shielding grid (6) is located in the lower part of the trench (11); A composite layer is located between the sidewalls and bottom of the shielding grid (6) and the sidewalls and bottom of the trench (11); P-type floating ring (10), formed at the bottom of the groove (11) N - In the drift region (3); The P-type body region (13) is located in the N-type body region (13). - Above the drift zone (3); N + The source region (12) is formed on the P-type body region (13) and located on both sides of the control gate (4); A dielectric layer (16) covers the upper surface of the device; Contact hole (14), penetrating the dielectric layer (16) and exposing part of the N + Source region (12) and the P-type body region (13); A metal layer (15) is filled in the contact hole (14) and covers part of the surface of the dielectric layer (16) to form a source metal.

2. The shielded gate trench power MOSFET structure according to claim 1, characterized in that: The composite layer is a three-layer composite dielectric layer, consisting of a first silicon oxide layer (7), a silicon nitride layer (8), and a second silicon oxide layer (9) from the inside out. The second silicon oxide layer (9) is grown on N-type silicon oxide. - On the drift region (3), a good interface with the silicon substrate is provided; the silicon nitride layer (8) is the core functional layer with a dielectric constant greater than that of the silicon dioxide layer, which is used to improve the equivalent capacitance of the composite layer; the first silicon oxide layer (7) provides a good interface for forming a stable contact with the shielding gate (6) and provides protection for the silicon nitride layer (8).

3. The shielded gate trench power MOSFET structure according to claim 2, characterized in that: The total thickness of the composite layer is 500 nm, wherein the second silicon oxide layer (9) is grown by thermal oxidation process, and the thickness of the second silicon oxide layer (9) accounts for 1% to 4% of the total thickness; the thickness of the silicon nitride layer (8) accounts for 9% to 26% of the total thickness, and the remaining thickness is the thickness of the first silicon oxide layer (7).

4. The shielded gate trench power MOSFET structure according to claim 2, characterized in that: The thickness of the N-type substrate (2) is 10 μm to 200 μm.

5. The shielded gate trench power MOSFET structure according to claim 3, characterized in that: The drain region (1) uses a high concentration of N-doped material. + Type of material.

6. The shielded gate trench power MOSFET structure according to claim 1, characterized in that: The depth of the groove (11) is 1μm to 8μm.

7. The shielded gate trench power MOSFET structure according to claim 1, characterized in that: The control gate (4) is made of polycrystalline silicon and has a thickness of 100nm to 200nm. The gate oxide layer (5) has a thickness of 10nm to 90nm and the shielding gate (6) has a thickness of 0.5μm to 1μm.

8. The shielded gate trench power MOSFET structure according to claim 1, characterized in that: The knot depth of the P-type floating ring (10) is 0.15 to 0.25 times the depth of the groove (11).

9. A method for fabricating a shielded gate trench power MOSFET structure, characterized in that: Includes the following steps: Step S1: Epitaxial layer growth. An N-type epitaxial layer is grown on an N-type substrate (2). The crystal orientation of the N-type epitaxial layer is 100, the thickness of the epitaxial layer is 8-10 μm, and the resistivity is 0.1-0.3 Ω·cm. Step S2, trench etching: trenches (11) are formed on the N-type epitaxial layer by photolithography and etching processes. The specific steps include: Step S21: Dry etching, using anisotropic plasma etching, with an etching angle of 88°~89° and a depth of 1μm~8μm, to form a deep trench with steep sidewalls; Step S22: Wet etching, followed by isotropic wet etching, using an acidic solution to etch silicon to form a trench (11) with a smooth, sharp bottom corner to improve the electric field distribution; the etching rate is the same in all directions, and the lateral and longitudinal directions are etched together for 1.0 μm to 1.1 μm; Step S3 involves implantation of the P-type body region and P-type ring. The implantation region is defined by photolithography. First, a 0.01 μm to 0.03 μm SiO2 layer is grown by thermal oxidation as the screen oxide layer, followed by boron ion implantation. The implantation energy is 90–210 keV, and the dose is 5 × 10⁻⁶ keV. 12 ~1×10 13 cm -2 Then, annealing is carried out in a high-temperature, inert gas environment to activate impurities and form P-type body regions (13) and P-type floating rings (10). Step S4, composite layer growth: A composite layer serving as the shielding gate medium is grown within the trench (11), specifically including the following steps: Step S41: A second silicon oxide layer (9) is grown by thermal oxidation process, with a thickness of 5nm to 20nm and a temperature of 900℃ to 1100℃; Step S42: A silicon nitride layer (8) with a thickness of 45 nm to 130 nm is grown by LPCVD (chemical vapor deposition); Step S43: Deposit the first silicon oxide layer (7) with a thickness of 350 nm to 450 nm using PECVD (plasma-enhanced chemical vapor deposition) with a TEOS source at a temperature of 350 °C to 500 °C. Step S5: Shielding gate growth. A phosphorus-doped (or boron-doped) polycrystalline silicon shielding gate (6) is deposited by LPCVD. The thickness of the shielding gate (6) is 0.5μm to 1μm, the temperature is 500℃ to 600℃, and it is wet-etched to the corresponding position. Then, the composite layer is wet-etched to the corresponding position. Step S6: Dielectric layer deposition. A dielectric layer (16) is formed by deposition using the HDPCVD method to isolate the control gate (4) and the shielding gate (6). Step S7, formation of gate oxide layer and control gate: First, a sacrificial oxide layer with a thickness of 0.01μm to 0.03μm is grown to remove surface impurities, clean the silicon surface and repair damage; then, the final gate oxide layer (5) is grown by thermal oxidation process at an oxidation temperature of 900℃ to 1100℃. The thickness of the gate oxide layer (5) is 0.01μm to 0.09μm, and the appropriate gate oxide layer thickness is selected according to different threshold voltages; phosphorus-doped polysilicon is deposited by LPCVD and etched, while simultaneously etching away SiO2 and polysilicon on the silicon wafer surface, forming the control gate (4) on the upper part of the trench. Steps S8 and N + Source region implantation: The source region is defined by photolithography, and arsenic ion implantation is performed at an energy of 40–50 keV and a dose of 0.8 × 10⁻⁶. 15 ~1.2×10 15 cm -2 Then anneal at 900℃~1000℃ for 25~35 minutes to form N + Source region (12); Step S9: Contact hole etching. SiO2 is deposited by PECVD as the interlayer dielectric layer. The contact holes (14) are etched by photolithography and dry etching processes. The width of the contact holes (14) is 0.3μm to 0.5μm, and the depth extends into the P-type body region (13). BF2 ion implantation is performed through the contact holes (14) to form P-type bodies in the P-type body region (13). + In the contact area, reduce contact resistance and suppress the turn-on of parasitic NPN transistors; annealing temperature is 700℃~900℃, time is 40 seconds~60 seconds; Step 10: Metallization. An Al metal layer (15) is formed by sputtering, with a thickness of 3 μm to 8 μm. Source and gate metal electrodes are formed by photolithography and etching.

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