A display panel and a manufacturing method thereof

Abstract

The present application discloses a display panel and a manufacturing method thereof, which relates to the display field. The display panel comprises: a first array chip, a second array chip and a third array chip arranged in a direction perpendicular to the plane where the display panel is located; the first array chip comprises a plurality of first light-emitting units; the third array chip is located on the light-emitting side of the first array chip, the third array chip comprises a plurality of second light-emitting units, and the side of the third array chip away from the first array chip is the light-emitting side of the display panel; the second array chip is located between the first array chip and the third array chip, and is used to provide display driving signals for the first light-emitting unit and the second light-emitting unit; a light processing layer is provided between the layer where the first light-emitting unit is located and the layer where the second light-emitting unit is located, and the light processing layer is used to form a third color of light emission based on the light emitted by part of the first light-emitting unit. The display panel can achieve higher integration, higher performance, higher reliability and lower power consumption.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof. Background Art

[0002] As people's demand for the performance of display devices increases, various display technologies are emerging. Specifically, compared with traditional liquid crystal display (LCD) technology and organic light-emitting diode display technology, Micro-LED display technology has broad application prospects in virtual reality (VR), augmented reality (AR), car display, television, mobile phone, tablet, notebook computer and other fields due to its advantages of high brightness, high resolution, high response speed, low power consumption and long life. However, due to the difference between red light Micro-LED epitaxial materials and blue light Micro-LED and green light Micro-LED epitaxial materials, it is impossible to directly grow and prepare full-color Micro-LED display panels from the same epitaxial material, which makes the current Micro-LED full-color display device have the problems of high cost, low yield and poor reliability. Summary of the invention

[0003] In view of the above problems, the present application provides a display panel and a method for manufacturing the same to solve the problems of high cost, low yield and poor reliability of current Micro-LED full-color display devices.

[0004] The specific plan is as follows:

[0005] A display panel comprises: a first array chip, a second array chip and a third array chip arranged in a direction perpendicular to a plane where the display panel is located; wherein:

[0006] The first array chip includes a plurality of first light emitting units, and the first light emitting units emit light of a first color;

[0007] The third array chip is located at the light-emitting side of the first array chip, the third array chip comprises a plurality of second light-emitting units, the second light-emitting units emit light of a second color, and a side of the third array chip away from the first array chip is the light-emitting side of the display panel;

[0008] The second array chip is located between the first array chip and the third array chip, and is used to provide display driving signals for the first light-emitting unit and the second light-emitting unit;

[0009] A light processing layer is provided between the layer where the first light emitting unit is located and the layer where the second light emitting unit is located, and the light processing layer is used to form light emission of a third color based on part of the light emitted by the first light emitting unit.

[0010] A method for manufacturing a display panel, comprising:

[0011] A first array chip, a second array chip and a third array chip are prepared respectively, wherein the first array chip comprises a plurality of first light-emitting units, which emit light of a first color; the third array chip comprises a plurality of second light-emitting units, which emit light of a second color; and the second array chip is used to provide display driving signals for the first light-emitting units and the second light-emitting units;

[0012] A second array chip is bonded to the light-emitting side of the first array chip, and a third array chip is bonded to the side of the second array chip away from the first array chip, wherein the side of the third array chip away from the first array chip is the light-emitting side of the display panel;

[0013] A light processing layer is provided between the layer where the first light emitting unit is located and the layer where the second light emitting unit is located, and the light processing layer is used to form light emission of a third color based on part of the light emitted by the first light emitting unit.

[0014] In the display panel and the manufacturing method thereof provided by the embodiment of the present application, the first array chip, the second array chip and the third array chip are arranged in a direction perpendicular to the plane where the display panel is located, that is, the display panel is manufactured by adopting the three-dimensional stacking technology. First, the three-dimensional stacking technology manufacturing equipment is simple, and it also allows the integration of more functions, so that the manufacturing method of the display panel provided by the embodiment of the present application can be mass-produced at a low cost; secondly, the three-dimensional stacking technology does not require the chip to be divided into LED units, but is bonded and connected in the form of a whole piece, which is simpler and has a higher yield; thirdly, the three-dimensional stacking chip can be mass-produced according to different functional chips, distributed execution, and it is easy to improve the production efficiency of the display panel provided by the embodiment of the present application; moreover, when the three-dimensional stacking technology realizes full-color display, only the failed chip needs to be replaced as a whole during the chip repair process, so that the display panel manufactured by the manufacturing method of the display panel provided by the embodiment of the present application has a lower cost and process complexity during subsequent repair; finally, the three-dimensional stacking technology realizes full-color display without cutting and transferring the connection of a single LED unit. Compared with mass transfer, in the manufacturing method of the display panel provided by the embodiment of the present application, the display unit has fewer defects due to the process and higher reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0016] Figure 1 A flowchart of a method for manufacturing a display panel provided in one embodiment of the present application;

[0017] Figure 2-Figure 13 A schematic diagram of some local structures involved in the manufacturing process of a display panel provided in one embodiment of the present application;

[0018] Figure 14-Figure 27 A schematic diagram of some local structures involved in a manufacturing process of a display panel provided in yet another embodiment of the present application.

[0019] The accompanying drawings are marked as follows:

[0020] 101-first sapphire substrate; 102-first light emitting layer; 103-first p-electrode; 104-first n-electrode; 105-A passivation layer; 106-A wiring layer; 107-A bonding layer;

[0021] 201- SiC substrate layer; 202- SiC drift layer; 203- SiC CMOS region; 204-C passivation layer (i.e., first passivation layer); 205-B wiring layer (i.e., first wiring layer); 206-B bonding layer (i.e., first bonding layer);

[0022] 301 - second sapphire substrate; 302 - second light-emitting layer; 303 - second p-electrode; 304 - second n-electrode; 305 - E passivation layer; 306 - C wiring layer; 307 - C bonding layer;

[0023] 401-light conversion unit; 402-light filter layer;

[0024] 501-G passivation layer (i.e., the third passivation layer); 502- through-hole metal; 503- D bonding layer (i.e., the second bonding layer). DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0026] It is obvious to those skilled in the art that various modifications and changes can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and changes of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0027] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0028] As described in the background technology section, current Micro-LED full-color display devices have problems such as high cost, low yield, and poor reliability.

[0029] The existing Micro-LED full-color display device is mainly produced through Micro-LED mass transfer to form a variety of color light-emitting units in the Micro-LED full-color display device. Specifically, Micro-LED mass transfer requires the precise transfer of millions of micron-level RGB three-color LED chips from their growth substrate to the target substrate. The current mainstream stamp transfer technology, laser transfer technology, electrostatic force pickup technology, electromagnetic pickup technology, fluid assembly technology and other mass transfer methods have no way to truly solve the problems of high manufacturing cost, low yield, low production efficiency, difficult repair, and poor reliability.

[0030] This is because mass transfer technology requires additional advanced equipment, which is costly. Moreover, mass transfer technology has high requirements for alignment equipment and is easily affected by mechanical stress, thermal stress or chemical environment changes during the transfer process, which can cause damage to the material structure and device function, thereby affecting the yield. In addition, mass transfer technology is affected by the transfer equipment, and the equipment precision requirements are extremely high, resulting in low equipment utilization. Moreover, due to its complex process limitations, it will directly affect the overall production efficiency in all aspects. In addition, mass transfer technology requires failure monitoring and repair of individual LED units. Due to the small size, it will cause technical implementation difficulties, and it requires expensive, high-precision equipment to execute, which is very difficult and costly. Moreover, the mass transfer process requires cutting and transfer connection of individual LED units. Due to the increase in defects caused by the process, the reliability is poor.

[0031] In addition, in the field of full-color display, the role of active driver chips in Micro-LED display panels is crucial. They are responsible for controlling the switching and brightness of each Micro-LED pixel. By independently controlling the Micro-LED pixels of each color, various colors are mixed to achieve full-color display and multi-level grayscale adjustment to enhance the fineness and layering of the image. The current mainstream Micro-LED display drivers are thin-film transistor (TFT) drivers and silicon-based CMOS drivers. Among them, the TFT drive circuit needs to be maintained in the on state, which will inevitably lead to high and uneven power consumption and heat generation, and its response speed is slower than that of CMOS drivers, which will affect the performance of high dynamic range display. However, silicon-based CMOS drivers are not very suitable for transparent display application scenarios because the epitaxial structure cannot transmit light from the front. Therefore, the current mainstream Micro-LED display drivers largely limit the application of full-color Micro-LED displays, especially in application scenarios such as VR / AR.

[0032] In view of this, the embodiment of the present application provides a display panel and a method for making the same, which adopts a three-dimensional stacking technology, and the three-dimensional stacking technology is an advanced integrated circuit manufacturing technology, which uses micro-machining technologies such as wafer bonding technology, interlayer connection technology, and advanced packaging technology to stack multiple chips together in a vertical direction to form a multi-layer three-dimensional structure; in a traditional two-dimensional integrated circuit chip, the functional units on the chip are arranged in a plane, while in a three-dimensional stacked chip, multiple chip layers can be stacked together vertically to achieve interlayer connection and interconnection of different functional units, thereby achieving higher integration, smaller size, higher performance and lower power consumption, so that the display panel provided by the embodiment of the present application has the advantages of low manufacturing cost, high yield, high production efficiency, low repair difficulty, and high reliability. In addition, the display panel and the method for making the same provided by the embodiment of the present application place the driver chip in the middle of the light-emitting chip, which helps to reduce the number of external connections of the driver chip, and can make the driver chip's driving energy closer to the light-emitting chip, reducing energy loss during transmission.

[0033] Specifically, Figure 1 As shown, the manufacturing method of the display panel provided in the embodiment of the present application includes:

[0034] S1: preparing a first array chip, a second array chip and a third array chip respectively, wherein the first array chip comprises a plurality of first light-emitting units, which emit light of a first color; the third array chip comprises a plurality of second light-emitting units, which emit light of a second color; and the second array chip is used to provide display driving signals for the first light-emitting units and the second light-emitting units;

[0035] S2: bonding a second array chip to the light emitting side of the first array chip, and bonding a third array chip to the side of the second array chip away from the first array chip, wherein the side of the third array chip away from the first array chip is the light emitting side of the display panel;

[0036] A light processing layer is provided between the layer where the first light emitting unit is located and the layer where the second light emitting unit is located, and the light processing layer is used to form light emission of a third color based on part of the light emitted by the first light emitting unit.

[0037] It should be noted that the embodiment of the present application does not limit the preparation order of the first array chip, the second array chip and the third array chip, that is, the embodiment of the present application can prepare the first array chip, the second array chip and the third array chip in sequence, or can prepare the first array chip, the third array chip and the second array chip in sequence, or can prepare the third array chip, the second array chip and the first array chip in sequence, or adopt other preparation orders, as long as the first array chip, the second array chip and the third array chip are obtained respectively.

[0038] In the manufacturing method of the display panel provided in the embodiment of the present application, the first array chip, the second array chip and the third array chip are arranged in a direction perpendicular to the plane where the display panel is located, that is, the display panel is manufactured by adopting the three-dimensional stacking technology. First, the three-dimensional stacking technology manufacturing equipment is simple, and it also allows the integration of more functions, so that the manufacturing method of the display panel provided in the embodiment of the present application can be mass-produced at a low cost; secondly, the three-dimensional stacking technology does not require the chip to be divided into LED units, but is bonded and connected in the form of a whole piece, which is simpler and has a higher yield; thirdly, the three-dimensional stacking chip can be mass-produced according to different functional chips, distributed execution, and it is easy to improve the production efficiency of the display panel provided in the embodiment of the present application; moreover, when the three-dimensional stacking technology realizes full-color display, only the failed chip needs to be replaced as a whole during the chip repair process, so that the display panel manufactured by the manufacturing method of the display panel provided in the embodiment of the present application has a lower cost and process complexity during subsequent repair; finally, the three-dimensional stacking technology realizes full-color display without cutting and transferring the connection of a single LED unit. Compared with mass transfer, in the manufacturing method of the display panel provided in the embodiment of the present application, the display unit has fewer defects due to the process and higher reliability.

[0039] Moreover, the display panel and the manufacturing method thereof provided in the embodiment of the present application place the second array chip between the first array chip and the third array chip, that is, place the driving chip in the middle of the light-emitting chip, which helps to reduce the number of external connections of the driving chip and enables the driving energy of the driving chip to be closer to the light-emitting chip, thereby reducing energy loss during transmission.

[0040] The following describes the manufacturing method provided in the embodiment of the present application by taking the embodiment of the present application that the first array chip, the second array chip and the third array chip can be prepared in sequence as an example.

[0041] Optionally, the method for manufacturing a display panel provided in the embodiment of the present application includes:

[0042] S10: preparing a first array chip, wherein the first array chip comprises a plurality of first light-emitting units, and the first light-emitting units emit light of a first color.

[0043] Optionally, in one embodiment of the present application, Figure 2 As shown, preparing the first array chip includes:

[0044] The epitaxial wafer of the first light-emitting unit is prepared on the first sapphire substrate 101. Specifically, the epitaxial wafer of the first light-emitting unit is prepared on the first sapphire substrate 101, comprising: sequentially growing a u-GaN layer, an n-GaN layer, a first light-emitting MQW layer, an electron blocking layer, and a p-GaN layer on the first sapphire substrate 101 to obtain the epitaxial wafer of the first light-emitting unit;

[0045] Etching the region where the first light-emitting unit is to be formed on the epitaxial wafer of the first light-emitting unit, such as inductively coupled plasma etching, until the u-GaN layer is exposed, thereby obtaining a plurality of first light-emitting layers 102 arranged in an array, wherein the first light-emitting layer 102 is used to emit light of a first color;

[0046] A first p-electrode 103 and a first n-electrode 104 are formed on the first light-emitting layer 102, wherein the first p-electrode 103 is electrically connected to the p-GaN layer in the first light-emitting layer 102, and the first n-electrode 104 is electrically connected to the n-GaN layer in the first light-emitting layer 102;

[0047] Depositing an A passivation layer 105 covering the first light-emitting layer, and etching the A passivation layer 105 to form an A opening region, wherein the A opening region includes an A opening and a B opening, wherein the A opening exposes a portion of the first p-electrode 103, and the B opening exposes a portion of the first n-electrode 104;

[0048] forming an A wiring layer 106, wherein the A wiring layer 106 includes an A electrical connection line electrically connected to the first p-electrode 103 through an A opening, and a B electrical connection line electrically connected to the first n-electrode 104 through a B opening;

[0049] Forming a B passivation layer covering the A passivation layer 105 and the A wiring layer 106, and etching the B passivation layer to form a B opening area, wherein the B opening area includes a C opening and a D opening, wherein the C opening exposes a partial area of ​​the A electrical connection line, and the D opening exposes a partial area of ​​the B electrical connection line;

[0050] An A bonding layer 107 is formed, wherein the A bonding layer includes an A metal portion electrically connected to the A electrical connection line through a C opening, a B metal portion electrically connected to the B electrical connection line through a D opening, and a C metal portion located on a surface of the B passivation layer away from the A passivation layer, wherein the C metal portion is used for subsequent electrical connection to a second light-emitting unit, and the A bonding layer is also used for subsequent bonding to a second array chip.

[0051] S20: preparing a second array chip, where the second array chip is used to provide display driving signals for the first light-emitting unit and the second light-emitting unit.

[0052] Optionally, in one embodiment of the present application, specifically, in one embodiment of the present application, as Figure 3 As shown, preparing the drive array chip includes:

[0053] Providing an n-type doped SiC epitaxial wafer, optionally, the n-type doped SiC epitaxial wafer is a transparent epitaxial wafer of a first light-emitting unit, and the SiC epitaxial wafer includes a SiC substrate layer 201 and a SiC drift layer 202;

[0054] forming a SiC CMOS region 203 in the SiC drift layer 202;

[0055] Depositing a C passivation layer (i.e., a first passivation layer) 204 on the surface of the SiC CMOS region 203, and forming a C opening region (i.e., a first opening region) on the C passivation layer (i.e., the first passivation layer) 204, wherein the C opening region includes an E opening (i.e., a first opening), an F opening (i.e., a second opening), and a G opening (i.e., a third opening) corresponding to the positions of the gate electrode, the source electrode, and the drain electrode in the SiC CMOS region 203;

[0056] Prepare a B wiring layer (i.e., a first wiring layer) 205, wherein the B wiring layer (i.e., the first wiring layer) 205 includes a C electrical connection line (i.e., a first electrical connection line) electrically connected to the gate electrode through an E opening, a D electrical connection line (i.e., a second electrical connection line) electrically connected to the source electrode through an F opening, and an E electrical connection line (i.e., a third electrical connection line) electrically connected to the drain electrode through a G opening;

[0057] Depositing a D passivation layer (i.e., a second passivation layer) covering the C passivation layer and the B wiring layer, and etching the D passivation layer to form a D opening region (i.e., a second opening region), wherein the D opening region includes an H opening (i.e., a fourth opening), an I opening (i.e., a fifth opening), and a J opening (i.e., a sixth opening);

[0058] A B bonding layer (i.e., the first bonding layer) 206 is formed, wherein the B bonding layer includes a D metal portion (the first metal portion) electrically connected to the C electrical connection line through an H opening, an E metal portion (i.e., the second metal portion) electrically connected to the D electrical connection line through an I opening, an F metal portion (i.e., the third metal portion) electrically connected to the E electrical connection line through a J opening, and a G metal portion (i.e., the fourth metal portion) located on the surface of the D passivation layer away from the C passivation layer. Thus, a second array chip is obtained, and the B bonding layer is also used for subsequent bonding with the first array chip.

[0059] Specifically, in one embodiment of the present application, forming a SiC CMOS region in a SiC drift layer includes:

[0060] Multiple ion implantation is performed in the SiC drift layer to obtain a p-type lightly doped region as a channel region and an n-type heavily doped region as a substrate bias region;

[0061] Multiple ion implantation is performed in the channel region to obtain a p-type heavily doped region as a body bias region and an n-type heavily doped region as a source region and a drain region;

[0062] A dielectric is deposited in the upper region between the source region and the drain region as a gate dielectric layer, and metals are prepared above the gate dielectric layer, above the source region, and above the drain region to obtain a gate electrode, a source electrode, and a drain electrode, thereby obtaining a SiC CMOS region.

[0063] Optionally, in one embodiment of the present application, while preparing the B wiring layer, depositing the C passivation layer and preparing the B bonding layer, a flat capacitor (not shown) can be prepared in the reserved capacitor area to provide capacitor charging and discharging for active addressing drive display.

[0064] On the basis of the above embodiments, in one embodiment of the present application, the second array chip includes a through-hole metal connection area. In this embodiment, the B bonding layer also includes an H metal portion (i.e., a fifth metal portion) located in the through-hole metal connection area, and the H metal portion is used to be electrically connected to the second light-emitting unit later. While preparing the B bonding layer, the H metal portion is pre-prepared on the surface of the second array chip corresponding to the through-hole metal connection area to provide an electrical connection between the through-hole metal connection area and the B wiring layer.

[0065] S30: preparing a third array chip, wherein the third array chip comprises a plurality of second light emitting units, and the second light emitting units emit light of a second color.

[0066] Optionally, in one embodiment of the present application, Figure 4 As shown, preparing the third array chip includes:

[0067] Growing an epitaxial wafer of a second light-emitting unit on a second sapphire substrate 301, specifically comprising sequentially growing a u-GaN layer, an n-GaN layer, a second light-emitting MQW layer, an electron blocking layer, and a p-GaN layer on the second sapphire substrate to obtain the epitaxial wafer of the second light-emitting unit;

[0068] Etching the region where the second light-emitting unit is to be formed on the epitaxial wafer of the second light-emitting unit, such as inductively coupled plasma etching, until the u-GaN layer is exposed, thereby obtaining a plurality of second light-emitting layers 302 arranged in an array, wherein the second light-emitting layer 302 is used to emit light of a second color;

[0069] A second p-electrode 303 and a second n-electrode 304 are formed on the second light-emitting layer 302, wherein the second p-electrode 303 is electrically connected to the p-GaN layer in the second light-emitting layer 302, and the second n-electrode 304 is electrically connected to the n-GaN layer in the second light-emitting layer 302;

[0070] Depositing an E passivation layer 305 covering the second light-emitting layer 302, and etching the E passivation layer 305 to form an E opening region, wherein the E opening region includes a K opening exposing a portion of the second p-electrode 303, and an L opening exposing a portion of the second n-electrode 304;

[0071] Forming a C wiring layer 306, wherein the C wiring layer 306 includes an F electrical connection line electrically connected to the second p-electrode 303 through a K opening, and a G electrical connection line electrically connected to the second n-electrode 304 through an L opening;

[0072] Forming an F passivation layer covering the E passivation layer 305 and the C wiring layer 306, and etching the F passivation layer to form an F opening area, wherein the F opening area includes an M opening and an N opening, wherein the M opening exposes a partial area of ​​the E electrical connection line, and the N opening exposes a partial area of ​​the F electrical connection line;

[0073] A C bonding layer 307 is formed, and the C bonding layer 307 includes an I metal portion electrically connected to the E electrical connection line through an M opening, a J metal portion electrically connected to the F electrical connection line through an N opening, and a K metal portion located on the surface of the F passivation layer away from the E passivation layer. The C bonding layer 307 is also used for subsequent bonding with the second array chip, thereby obtaining a third array chip.

[0074] S40: preparing a light processing layer, wherein the light processing layer is located between the layer where the first light emitting unit is located and the layer where the second light emitting unit is located, and the light processing layer is used to form light emission of a third color based on part of the light emitted by the first light emitting unit.

[0075] It should be noted that, in this embodiment, the display panel includes a first light emitting area, a second light emitting area and a third light emitting area, wherein the first light emitting area is used to emit light of a first color, the second light emitting area is used to emit light of a second color, and the third light emitting area is used to emit light of a third color, so that the display panel can achieve full-color display.

[0076] Specifically, in one embodiment of the present application, the light processing layer includes a light conversion layer and a filter layer, wherein the light conversion layer is used to form light emission of a third color based on the light emitted by part of the first light-emitting unit (i.e., the first light-emitting unit corresponding to the position of the third light-emitting area), and the filter layer is used to filter out other light in the light conversion layer except the light of the third color, but the present application is not limited to this. In other embodiments of the present application, the light processing layer can also be other structures, depending on the specific circumstances.

[0077] Optionally, based on the above embodiments, in one embodiment of the present application, the light conversion layer is located on the first array chip, includes a plurality of light conversion units, and is correspondingly located above the first light-emitting unit that provides a light source for converting light of a third color, and the filter layer is located on the second array chip, and is correspondingly located above the light conversion unit; in another embodiment of the present application, the light conversion layer is located on the second array chip, includes a plurality of light conversion units, and is correspondingly located above the first light-emitting unit that provides a light source for converting light of a third color, and the filter layer is located on the third array chip, and is correspondingly located above the light conversion unit. The present application does not limit this, and it depends on the specific circumstances. Below, taking the light conversion layer being located on the first array chip and the filter layer being located on the second array chip as an example, the manufacturing aspects provided in the embodiments of the present application will continue to be described.

[0078] Specifically, in one embodiment of the present application, Figure 5 As shown, preparing the light processing layer includes:

[0079] Coating photoresist on the first array chip, etching the photoresist on the upper side of the first light-emitting unit located in the area where the light of the third color is to be emitted, forming an etched array, preparing a third color quantum dot material on the etched array, and obtaining a light conversion layer, wherein the light conversion layer includes a plurality of light conversion units 401;

[0080] Photoresist is coated on the second driving array chip, and the photoresist is etched at a position directly above the corresponding light conversion unit 401 to form an etched array, and a filter material is prepared on the etched array to obtain a filter layer 402 .

[0081] S50: bonding a second array chip to the light emitting side of the first array chip, and bonding a third array chip to a side of the second array chip away from the first array chip, wherein the side of the third array chip away from the first array chip is the light emitting side of the display panel.

[0082] Specifically, in one embodiment of the present application, bonding the second array chip on the light-emitting side of the first array chip includes: aligning and connecting the bonding metal layer (i.e., bonding layer A) on the first array chip with the bonding metal layer (i.e., bonding layer B) on the corresponding second array chip, and performing hot pressing welding for 10 min to 60 min under the conditions of a temperature in the range of 250 ° C. to 400 ° C. and a pressure in the range of 10 kPa to 100 kPa, so that the first array chip and the second array chip are completely bonded and connected, such as Figure 6 shown.

[0083] Optionally, in one embodiment of the present application, after bonding the second array chip to the light emitting side of the first array chip and before bonding the third array chip to the side of the second array chip away from the first array chip, the method further comprises:

[0084] like Figure 6 and Figure 7 As shown, the SiC substrate layer 201 in the second array chip is removed, and the SiC drift layer 202 in the second array chip is thinned;

[0085] like Figure 8 As shown, the SiC drift layer 202 is etched to form a first through hole penetrating the SiC drift layer, wherein the first through hole exposes at least a portion of the H metal portion (ie, the fifth metal portion);

[0086] like Fig. 9 As shown, a G passivation layer (i.e., a third passivation layer) 501 is formed on the side of the SiC drift layer 202 away from the first array chip and on the surface of the first through hole, and the G passivation layer is etched to form a second through hole, wherein the second through hole exposes at least a portion of the bottom of the first through hole to expose at least a portion of the H metal portion;

[0087] like Fig.10 As shown, a through-hole metal 502 is formed in the second through-hole;

[0088] like Fig.11As shown, a D bonding layer (i.e., a second bonding layer) 503 is formed on the surface of the G passivation layer (i.e., the third passivation layer) 501 away from the first array chip and on the surface of the through-hole metal 502 away from the first array chip. The D bonding layer is used for subsequent bonding with the third array chip, thereby obtaining a through-hole metal connection area.

[0089] Specifically, in one embodiment of the present application, after bonding the second array chip to the light-emitting side of the first array chip and before bonding the third array chip to the side of the second array chip away from the first array chip, the method further includes:

[0090] After the first array chip and the second array chip are bonded, the substrate layer of the second array chip is removed by wire cutting or laser cutting, and the second array chip is thinned to 5 um by a thinning and polishing process;

[0091] Performing inductively coupled plasma etching from a position of the second array chip away from the first array chip on a side corresponding to the through-hole metal connection area to form a first through-hole in the driving array chip, wherein the first through-hole exposes a partial area of ​​the bonding layer between the second array chip and the first array chip;

[0092] Depositing a G passivation layer on the side wall of the first through hole and on the surface of the second array chip away from the first array chip, and etching the G passivation layer to form a second through hole, wherein the second through hole exposes a partial area of ​​the bonding layer between the second dynamic array chip and the first array chip;

[0093] Preparing a through-hole metal in the second through-hole, wherein the through-hole metal completely fills the second through-hole and is electrically connected to a portion of the bonding layer between the third array chip and the first array chip exposed by the second through-hole;

[0094] A D bonding layer is formed on the side of the second array chip away from the first array chip and on the side of the through-hole metal away from the first array chip. The D bonding layer is used for subsequent bonding with the third array chip to obtain a through-hole metal connection area.

[0095] Specifically, in one embodiment of the present application, bonding the third array chip on the side of the second array chip away from the first array chip includes: aligning and connecting the C bonding layer on the third array chip with the D bonding layer on the corresponding second array chip, and performing hot pressing welding for 10 min to 60 min under the conditions of a temperature range of 250 ° C to 400 ° C and a pressure range of 10 kPa to 100 kPa, so that the third array chip is completely bonded to the second array chip, such as Fig.12 shown.

[0096] Based on any of the above embodiments, in one embodiment of the present application, the manufacturing method further includes: Fig.13 As shown, the second sapphire substrate 301 of the third array chip is peeled off. Optionally, in one embodiment of the present application, peeling off the third array chip substrate includes:

[0097] Laser lift-off technology is used to penetrate the second sapphire substrate of the third array chip using a high-energy pulsed laser beam, the laser photon energy of the high-energy pulsed laser beam is between the sapphire band gap and the GaN band gap of the third array chip, and the interface of the second sapphire substrate of the third array chip and the GaN material epitaxially grown on the surface of the second sapphire substrate is uniformly scanned, and the second sapphire substrate of the bonded third array chip is removed to form a three-dimensional stacked full-color active drive display panel with light emitting from the top surface, that is, a three-dimensional stacked full-color active drive display panel with light emitting from the side of the third array chip away from the second array chip.

[0098] It should be noted that, in the above embodiment, the formation of the through-hole metal is located after the second array chip and the third array chip are bonded. In other embodiments of the present application, the formation of the through-hole metal can also be located before the bonding of the second array chip and the third array chip, such as Figure 14-Figure 27 shown.

[0099] Optionally, in one embodiment of the present application, the formation of the through-hole metal may also be before the bonding of the first array chip and the second array chip. In this embodiment, preparing the driving array chip includes:

[0100] like Fig.15 As shown, an n-type doped SiC epitaxial wafer is provided, wherein the SiC epitaxial wafer includes a SiC substrate layer 201 and a SiC drift layer 202;

[0101] forming a SiC CMOS region 203 in the SiC drift layer;

[0102] like Fig.16 As shown, etching is performed in the SiC drift layer 202 at a position corresponding to the through-hole metal connection region, such as inductively coupled plasma etching of a deep trench, to form a first through-hole;

[0103] like Fig.17 As shown, a C passivation layer (i.e., a first passivation layer) 204 is deposited on the surface of the SiC CMOS region 203 and the surface of the first through hole, and a C opening region is formed on the C passivation layer, wherein the C opening region includes an E opening (i.e., a first opening), an F opening (i.e., a second opening), and a G opening (i.e., a third opening) etched at positions corresponding to the gate electrode, the source electrode, and the drain electrode in the SiC CMOS region 203. Optionally, the C opening region also exposes the bottom of the first through hole;

[0104] Prepare a B wiring layer (i.e., a first wiring layer) 205, wherein the B wiring layer includes a C electrical connection line (i.e., a first electrical connection line) electrically connected to the gate electrode through an E opening, a D electrical connection line (i.e., a second electrical connection line) electrically connected to the source electrode through an F opening, and an E electrical connection line (i.e., a third electrical connection line) electrically connected to the drain electrode through a G opening;

[0105] Depositing a D passivation layer covering the C passivation layer (i.e., the first passivation layer) 204 and the B wiring layer (i.e., the first wiring layer) 205, and etching the D passivation layer to form a D opening region, wherein the D opening region includes an H opening (i.e., the fourth opening), an I opening (i.e., the fifth opening), and a J opening (i.e., the sixth opening), and the D opening region also exposes the bottom of the first through hole;

[0106] like Fig.18 As shown, a through-hole metal 502 is formed in the first through-hole, and the through-hole metal 502 fills the first through-hole;

[0107] like Fig.19 As shown, a B bonding layer (i.e., a first bonding layer) 206 is formed, and the B bonding layer (i.e., the first bonding layer) 206 includes a D metal portion (a first metal portion) electrically connected to the C electrical connection line (a first electrical connection line) through an H opening, an E metal portion (i.e., a second metal portion) electrically connected to the D electrical connection line through an I opening, and an F metal portion (i.e., a third metal portion) electrically connected to the E electrical connection line through a J opening, and an H metal portion (i.e., a fifth metal portion) electrically connected to the through-hole metal 502. Thus, a driving array chip is obtained, and the B bonding layer (i.e., the first bonding layer) 206 is also used for subsequent bonding with a blue light LED array chip.

[0108] On the basis of the above embodiment, in one embodiment of the present application, after bonding the second array chip to the light emitting side of the first array chip and before bonding the third array chip to the side of the second array chip away from the first array chip, the method further includes:

[0109] like Fig.23 As shown, the SiC substrate layer 201 in the second array chip is removed, and the SiC drift layer 202 in the second array chip is thinned until the end surface of the through-hole metal 502 away from the first array chip is exposed;

[0110] like Fig.24 As shown, a G passivation layer (i.e., a third passivation layer) 501 is formed on the side of the SiC drift layer 202 away from the first array chip and on the surface of the through-hole metal 502, and the G passivation layer is etched to form a second through hole, wherein the second through hole exposes at least a portion of the through-hole metal;

[0111] like Fig.25 As shown, a D bonding layer (i.e., a second bonding layer) 503 is formed on the surface of the G passivation layer (i.e., the third passivation layer) 501 away from the first array chip and on the surface of the through-hole metal 502 away from the first array chip. The D bonding layer (i.e., the second bonding layer) 503 is used for subsequent bonding with the third array chip, thereby obtaining a through-hole metal connection area.

[0112] From the above, it can be seen that the manufacturing method of the display panel provided in the present application prepares the first array chip, the second array chip, the light processing layer and the third array chip together by three-dimensional stacking. Through the advanced packaging technology and color conversion scheme of three-dimensional stacking, the problems of high cost, low yield and poor reliability brought about by mass transfer to achieve full-color display are effectively avoided.

[0113] Moreover, the manufacturing method of the display panel provided in the present application integrates a transparent SiCCMOS active driver chip into a full-color Micro-LED panel by applying three-dimensional stacking technology, and utilizes the advantages of good transparency and high integration of the SiC CMOS active driver chip to reduce the integration of the full-color active driver display. It also has the advantages of full-color luminescence and transparency on the light-emitting surface, and has significant advantages and broad application prospects in the field of VR / AR display. It can effectively solve the difficulties in transferring full-color display chips and the many technical problems of driver chips affecting full-color Micro-LED displays.

[0114] In addition, the manufacturing method of the display panel provided in the embodiment of the present application places the second array chip between the first array chip and the third array chip, that is, places the driving chip in the middle of the light-emitting chip, which helps to reduce the number of external connections of the driving chip and enables the driving energy of the driving chip to be closer to the light-emitting chip, thereby reducing energy loss during transmission.

[0115] The following takes the case where the first array chip is a blue LED array chip and the third array chip is a green LED array chip as an example, and describes the method for manufacturing the display panel provided in the embodiment of the present application in combination with specific embodiments:

[0116] Specifically, in one embodiment of the present application, the method for manufacturing the display panel includes:

[0117] S11: preparing a blue light LED array chip.

[0118] Specifically, Figure 2 As shown, in one embodiment of the present application, preparing a blue light LED array chip includes:

[0119] A u-GaN layer, an n-GaN layer, a blue light emitting MQW layer, an electron blocking layer, and a p-GaN layer are sequentially grown on a first sapphire substrate 101 to obtain a blue light LED epitaxial wafer;

[0120] Performing inductively coupled plasma etching on the blue LED epitaxial wafer in the area corresponding to the blue LED unit (such as a blue micro light emitting diode) until the u-GaN layer is exposed, thereby obtaining a plurality of blue light emitting layers arranged in an array;

[0121] A first p-electrode 103 and a first n-electrode 104 are formed on the blue light emitting layer, wherein the first p-electrode 103 is electrically connected to the p-GaN layer, and the first n-electrode 104 is electrically connected to the n-GaN layer;

[0122] Depositing an A passivation layer 105 covering the blue light emitting layer, and etching the A passivation layer 105 to form an A opening region, wherein the A opening region includes an A opening and a B opening, wherein the A opening exposes a portion of the first p-electrode 103, and the B opening exposes a portion of the first n-electrode 104;

[0123] forming an A wiring layer 106, wherein the A wiring layer 106 includes an A electrical connection line electrically connected to the first p-electrode 103 through an A opening, and a B electrical connection line electrically connected to the first n-electrode 104 through a B opening;

[0124] Forming a B passivation layer covering the A passivation layer and the A wiring layer, and etching the B passivation layer to form a B opening area, wherein the B opening area includes a C opening and a D opening, wherein the C opening exposes a partial area of ​​the A electrical connection line, and the D opening exposes a partial area of ​​the B electrical connection line;

[0125] An A bonding layer 107 is formed, wherein the A bonding layer 107 includes an A metal portion electrically connected to the A electrical connection line through a C opening, a B metal portion electrically connected to the B electrical connection line through a D opening, and a C metal portion located on a surface of the B passivation layer away from the A passivation layer, wherein the C metal portion is used for subsequent electrical connection to a second light-emitting unit, and the A bonding layer is also used for subsequent bonding to a second array chip.

[0126] S21: preparing a drive array chip.

[0127] Specifically, in one embodiment of the present application, Figure 3 As shown, preparing the drive array chip includes:

[0128] Providing an n-type doped SiC epitaxial wafer, wherein the SiC epitaxial wafer comprises a SiC substrate layer 201 and a SiC drift layer 202;

[0129] Multiple ion implantation is performed in the SiC drift layer 202 to obtain a p-type lightly doped region as a channel region and an n-type heavily doped region as a substrate bias region;

[0130] Multiple ion implantation is performed in the channel region to obtain a p-type heavily doped region as a body bias region and an n-type heavily doped region as a source region and a drain region;

[0131] A dielectric is deposited in the region above the source region and the drain region as a gate dielectric layer, and metals are respectively prepared above the gate dielectric layer, above the source region, and above the drain region to obtain a gate electrode, a source electrode, and a drain electrode, thereby obtaining a SiC CMOS region 203;

[0132] Depositing a C passivation layer (i.e., a first passivation layer) 204 on the surface of the SiC CMOS region 203, and forming a C opening region on the C passivation layer (i.e., the first passivation layer) 204, wherein the C opening region includes an E opening, an F opening, and a G opening corresponding to the positions of the gate electrode, the source electrode, and the drain electrode, respectively;

[0133] Prepare a B wiring layer (i.e., a first wiring layer) 205, wherein the B wiring layer includes a C electrical connection line electrically connected to the gate electrode through an E opening, a D electrical connection line electrically connected to the source electrode through an F opening, and an E electrical connection line electrically connected to the drain electrode through a G opening;

[0134] Depositing a D passivation layer covering the C passivation layer (i.e., the first passivation layer) 204 and the B wiring layer (i.e., the first wiring layer) 205, and etching the D passivation layer to form a D opening region, wherein the D opening region includes an H opening, an I opening, and a J opening;

[0135] A B bonding layer (i.e., the first bonding layer) 206 is formed, and the B bonding layer (i.e., the first bonding layer) 206 includes a D metal portion electrically connected to the C electrical connection line through an H opening, an E metal portion electrically connected to the D electrical connection line through an I opening, an F metal portion electrically connected to the E electrical connection line through a J opening, and a G metal portion located on the surface of the D passivation layer away from the C passivation layer. Thus, a driving array chip is obtained, and the B bonding layer (i.e., the first bonding layer) 206 is also used for subsequent bonding with a blue light LED array chip.

[0136] On the basis of the above-mentioned embodiment, in one embodiment of the present application, the second array chip includes a through-hole metal connection area. In this embodiment, the B bonding layer also includes an H metal portion located in the through-hole metal connection area, and the H metal portion is used to be electrically connected to the second light-emitting unit later. While preparing the B bonding layer (i.e., the first bonding layer) 206, an H metal portion is prepared on the surface of the second array chip corresponding to the through-hole metal connection area to provide an electrical connection between the through-hole metal connection area and the B wiring layer (i.e., the first wiring layer) 205.

[0137] Optionally, in one embodiment of the present application, while preparing the B wiring layer (i.e., the first wiring layer) 205, depositing the C passivation layer (i.e., the first passivation layer) 204, and preparing the B bonding layer (i.e., the first bonding layer) 206, a flat capacitor (not shown) can be prepared in the reserved capacitor area to provide capacitor charging and discharging for the active addressing drive display.

[0138] S31: preparing a green LED array chip.

[0139] Specifically, in one embodiment of the present application, Figure 4 As shown, preparing a green light LED array chip includes:

[0140] On the second sapphire substrate 301, a u-GaN layer, an n-GaN layer, a green light emitting MQW layer, an electron blocking layer, and a p-GaN layer are sequentially grown to obtain a green light LED epitaxial wafer;

[0141] Performing inductively coupled plasma etching on the green LED epitaxial wafer in the area corresponding to the green LED unit (i.e., green micro light emitting diode) until the u-GaN layer is exposed, thereby obtaining a plurality of green light emitting layers arranged in an array;

[0142] A second p-electrode 303 and a second n-electrode 304 are formed on the green light emitting layer, wherein the second p-electrode 303 is electrically connected to the p-GaN layer, and the second n-electrode 304 is electrically connected to the n-GaN layer;

[0143] Depositing an E passivation layer 305 covering the green light emitting layer, and etching the E passivation layer 305 to form an E opening region, wherein the E opening region includes a K opening exposing a portion of the second p-electrode 303 and an L opening exposing a portion of the second n-electrode 304;

[0144] Forming a C wiring layer 306, wherein the C wiring layer 306 includes an F electrical connection line electrically connected to the second p-electrode 303 through a K opening, and a G electrical connection line electrically connected to the second n-electrode 304 through an L opening;

[0145] Forming an F passivation layer covering the E passivation layer and the C wiring layer, and etching the F passivation layer to form an F opening area, wherein the F opening area includes an M opening and an N opening, wherein the M opening exposes a partial area of ​​the E electrical connection line, and the N opening exposes a partial area of ​​the F electrical connection line;

[0146] A C bonding layer 307 is formed, and the C bonding layer 307 includes an I metal portion electrically connected to the E electrical connection line through an M opening, a J metal portion electrically connected to the F electrical connection line through an N opening, and a K metal portion located on the surface of the F passivation layer away from the E passivation layer. The C bonding layer is also used for subsequent bonding with a second array chip, thereby obtaining a green light LED array chip.

[0147] S41: preparing a light processing layer.

[0148] Specifically, in one embodiment of the present application, Figure 5 As shown, preparing the light processing layer includes:

[0149] Coating a photoresist on a blue LED array chip, etching the photoresist on the upper side of the blue LED unit located in the area where red emission light is to be formed to form an etched array, preparing a red quantum dot material on the etched array to obtain a red conversion layer, wherein the red conversion layer includes a plurality of red conversion units;

[0150] A photoresist is coated on the driving array chip, and the photoresist is etched at a position directly above the corresponding red conversion unit to form an etched array. A filter material is prepared on the etched array to obtain a filter layer 402 .

[0151] S51: Figure 6 As shown, the blue LED array chip and the driver array chip are bonded, specifically including: aligning and connecting the bonding metal layer (i.e., bonding layer A) on the blue LED array chip with the bonding metal layer (i.e., bonding layer B) on the corresponding driver array chip, and performing hot pressing welding for 10 min to 60 min under the conditions of a temperature in the range of 250 ° C to 400 ° C and a pressure in the range of 10 kPa to 100 kPa, so that the blue LED array chip and the driver array chip are completely bonded.

[0152] S61: preparing a through-hole metal connection area in the driving array chip,

[0153] Specifically, in one embodiment of the present application, preparing a through-hole metal connection area in the driving array chip includes:

[0154] like Figure 7 As shown, after the blue LED array chip and the driving array chip are bonded, the SiC substrate layer 201 of the driving array chip is removed by wire cutting or laser cutting, and the drift layer in the driving array chip is thinned to 5 um by a thinning and polishing process;

[0155] like Figure 8As shown, inductively coupled plasma etching is performed from a position corresponding to a through-hole metal connection area on a side of the thinned driving array chip away from the blue LED array chip to form a first through-hole in the driving array chip, wherein the first through-hole exposes a partial area of ​​the bonding layer between the driving array chip and the blue LED array chip;

[0156] like Fig. 9 As shown, a G passivation layer (i.e., a third passivation layer) 501 is deposited on the sidewall of the first through hole and the surface of the thinned driving array chip away from the blue LED array chip, and the G passivation layer (i.e., the third passivation layer) 501 is etched to form a second through hole, wherein the second through hole exposes a partial area of ​​the bonding layer between the driving array chip and the blue LED array chip;

[0157] like Fig.10 As shown, a through-hole metal 502 is prepared in the second through-hole, and the through-hole metal 502 completely fills the second through-hole and is electrically connected to a partial area of ​​the bonding layer between the driving array chip and the blue LED array chip exposed by the second through-hole;

[0158] like Fig.11 As shown, a D bonding layer (i.e., a second bonding layer) 503 is formed on the side of the driving array chip away from the blue LED array chip and on the surface of the through-hole metal 502 away from the blue LED array chip. The D bonding layer (i.e., the second bonding layer) 503 is used for the subsequent bonding step with the green LED array chip, thereby obtaining a through-hole metal connection area.

[0159] S71: Bonding the driver array chip and the green LED array chip.

[0160] Specifically, in one embodiment of the present application, Fig.12 As shown, the bonding drive array chip and the green light LED array chip include:

[0161] The C bonding layer 307 on the green LED array chip is aligned and connected with the D bonding layer (i.e., the second bonding layer) 503 on the corresponding driving array chip, and hot pressing welding is performed for 10 min to 60 min under the conditions of a temperature range of 250°C to 400°C and a pressure range of 10 kPa to 100 kPa, so that the green LED array chip and the driving array chip are completely bonded.

[0162] S81: Fig.13 As shown, the green LED array chip substrate is peeled off.

[0163] Optionally, in one embodiment of the present application, stripping the green LED array chip substrate includes:

[0164] Laser lift-off technology is used to penetrate the second sapphire substrate 301 with a high-energy pulsed laser beam, the laser photon energy of which is between the sapphire band gap and the GaN band gap, to uniformly scan the second sapphire substrate 301 and the interface of the GaN material epitaxially grown on the surface of the second sapphire substrate 301, and remove the second sapphire substrate 301 of the bonded green LED array chip to form a three-dimensional stacked full-color active drive display panel with light emitting from the top surface, that is, a three-dimensional stacked full-color active drive display panel with light emitting from the green LED array chip on the side away from the drive array chip.

[0165] In another embodiment of the present application, the method for manufacturing the display panel includes:

[0166] S12: Fig.14 As shown, a blue LED array chip is prepared. Since the process of preparing the blue LED array chip is the same as that in step S11, this application will not repeat it any more.

[0167] S22: preparing a driving array chip.

[0168] Specifically, in one embodiment of the present application, preparing a drive array chip includes:

[0169] like Fig.15 As shown, an n-type doped SiC epitaxial wafer is provided, wherein the SiC epitaxial wafer includes a SiC substrate layer 201 and a SiC drift layer 202;

[0170] Multiple ion implantation is performed in the SiC drift layer 202 to obtain a p-type lightly doped region as a channel region and an n-type heavily doped region as a substrate bias region;

[0171] Multiple ion implantation is performed in the channel region to obtain a p-type heavily doped region as a body bias region and an n-type heavily doped region as a source region and a drain region;

[0172] A dielectric is deposited in the region above the source region and the drain region as a gate dielectric layer, and metals are respectively prepared above the gate dielectric layer, above the source region, and above the drain region to obtain a gate electrode, a source electrode, and a drain electrode, thereby obtaining a SiC CMOS region 203;

[0173] like Fig.16 As shown, a deep trench is etched by inductively coupled plasma at a position corresponding to a through-hole metal connection region in the SiC drift layer 202 to form a first through-hole;

[0174] like Fig.17As shown, a C passivation layer (i.e., the first passivation layer) 204 is deposited on the surface of the SiC CMOS region 203 and the surface of the first through hole, and a C opening region is formed on the C passivation layer (i.e., the first passivation layer) 204, wherein the C opening region includes an E opening, an F opening, and a G opening etched at positions corresponding to the gate electrode, the source electrode, and the drain electrode. Optionally, the C opening region also exposes the bottom of the first through hole;

[0175] Prepare a B wiring layer (i.e., a first wiring layer) 205, wherein the B wiring layer includes a C electrical connection line electrically connected to the gate electrode through an E opening, a D electrical connection line electrically connected to the source electrode through an F opening, and an E electrical connection line electrically connected to the drain electrode through a G opening;

[0176] Depositing a D passivation layer covering the C passivation layer (i.e., the first passivation layer) 204 and the B wiring layer (i.e., the first wiring layer) 205, and etching the D passivation layer to form a D opening region, wherein the D opening region includes an H opening, an I opening, and a J opening, and the D opening region also exposes the bottom of the first through hole;

[0177] like Fig.18 As shown, a through-hole metal 502 is formed in the first through-hole, and the through-hole metal 502 fills the first through-hole;

[0178] like Fig.19 As shown, a B bonding layer (i.e., a first bonding layer) 206 is formed, and the B bonding layer (i.e., the first bonding layer) 206 includes a D metal portion electrically connected to the C electrical connection line through an H opening, an E metal portion electrically connected to the D electrical connection line through an I opening, an F metal portion electrically connected to the E electrical connection line through a J opening, and an H metal portion electrically connected to the through-hole metal 502. Thus, a driving array chip is obtained, and the B bonding layer (i.e., the first bonding layer) 206 is also used for subsequent bonding with a blue light LED array chip.

[0179] On the basis of the above embodiments, optionally, in one embodiment of the present application, while preparing the B wiring layer (i.e., the first wiring layer) 205, depositing the C passivation layer (i.e., the first passivation layer) 204, and preparing the B bonding layer (i.e., the first bonding layer) 206, a flat capacitor (not shown) can be prepared in the reserved capacitor area to provide capacitor charging and discharging for active addressing drive display.

[0180] S32: Fig. 20 As shown, a green LED array chip is prepared. Since the process of preparing the green LED array chip is the same as step S31 in the previous embodiment, this application will not repeat it any more.

[0181] S42: Fig.21As shown, a light processing layer is prepared. Since the process of preparing the light processing layer is the same as step S41 in the previous embodiment, this application will not repeat it any more.

[0182] S52: Fig. 22 As shown, the blue LED array chip and the driving array chip are bonded. Since the process of bonding the blue LED array chip and the driving array chip is the same as step S51 in the previous embodiment, this application will not repeat it here.

[0183] S62: preparing a through-hole metal connection area in the driving array chip,

[0184] Specifically, in one embodiment of the present application, preparing a through-hole metal connection area in the driving array chip includes:

[0185] like Fig.23 As shown, after the blue LED array chip and the driving array chip are bonded, the SiC substrate layer 201 of the driving array chip is removed by wire cutting or laser cutting, and the driving array chip is thinned by a thinning and polishing process until the end face of the through-hole metal 502 away from the blue LED array chip is exposed;

[0186] like Fig.24 As shown, a G passivation layer (i.e., a third passivation layer) 501 is deposited from the side of the thinned driving array chip away from the blue LED array chip, and the G passivation layer (i.e., the third passivation layer) 501 is etched to form a second through hole, wherein the second through hole exposes the end surface of the through hole metal 502 away from the blue LED array chip;

[0187] like Fig.25 As shown, a D bonding layer (i.e., a second bonding layer) 503 is formed on the side of the driving array chip away from the blue LED array chip and on the surface of the through-hole metal 502 away from the blue LED array chip. The D bonding layer (i.e., the second bonding layer) 503 is used for the subsequent bonding step with the green LED array chip, thereby obtaining a through-hole metal connection area.

[0188] S72: Fig.26 As shown, the driving array chip and the green LED array chip are bonded. Since the process of bonding the driving array chip and the green LED array chip is the same as step S71 in the previous embodiment, this application will not repeat it here.

[0189] S82: Fig. 27 As shown, the green LED array chip substrate is peeled off. Since the process of peeling off the green LED array chip substrate is the same as step S81 in the previous embodiment, this application will not repeat it here.

[0190] In addition, an embodiment of the present application further provides a display panel, and the display panel can be manufactured using the manufacturing method provided by any of the above embodiments.

[0191] Specifically, the display panel provided in the embodiment of the present application includes: a first array chip, a second array chip and a third array chip arranged in a direction perpendicular to the plane where the display panel is located; wherein,

[0192] The first array chip includes a plurality of first light emitting units, and the first light emitting units emit light of a first color;

[0193] The third array chip is located at the light-emitting side of the first array chip, the third array chip comprises a plurality of second light-emitting units, the second light-emitting units emit light of a second color, and a side of the third array chip away from the first array chip is the light-emitting side of the display panel;

[0194] The second array chip is located between the first array chip and the third array chip, and is used to provide display driving signals for the first light-emitting unit and the second light-emitting unit;

[0195] A light processing layer is provided between the layer where the first light emitting unit is located and the layer where the second light emitting unit is located, and the light processing layer is used to form light emission of a third color based on part of the light emitted by the first light emitting unit.

[0196] Optionally, in an embodiment of the present application, the first array chip and the second array chip are bonded to each other, and the second array chip and the third array chip are bonded to each other.

[0197] Based on the above embodiments, in one embodiment of the present application, the first light-emitting unit is a blue light-emitting unit, and the second light-emitting unit is a green light-emitting unit. The present application does not limit this. In other embodiments of the present application, the first light-emitting unit may be a green light-emitting unit, and the second light-emitting unit may be a blue light-emitting unit, depending on the specific circumstances.

[0198] The display panel provided in the embodiment of the present application is described below by taking the case where the first light-emitting unit is a blue light-emitting unit and the second light-emitting unit is a green light-emitting unit as an example.

[0199] Specifically, in one embodiment of the present application, the first array chip includes a plurality of blue LED units, such as blue micro light emitting diodes; and the third array chip includes a plurality of green LED units, such as green micro light emitting diodes.

[0200] Specifically, in one embodiment of the present application, continue as follows Fig. 27 As shown, the first array chip includes:

[0201] A first sapphire substrate 101;

[0202] A plurality of first light-emitting layers 102 located on the surface of the first sapphire substrate 101, wherein the first light-emitting layers 102 include a u-GaN layer, an n-GaN layer, a first light-emitting MQW layer, an electron blocking layer, and a p-GaN layer arranged in a direction perpendicular to the first sapphire substrate 101;

[0203] a first p-electrode 103 and a first n-electrode 104 electrically connected to the first light-emitting layer 102, wherein the first p-electrode 103 is electrically connected to the p-GaN layer, and the first n-electrode 104 is electrically connected to the n-GaN layer;

[0204] An A passivation layer 105 covering the first light-emitting layer 102, wherein the A passivation layer 105 has an A opening region, wherein the A opening region includes an A opening and a B opening, wherein the A opening exposes a portion of the first p-electrode 103, and the B opening exposes a portion of the first n-electrode 104;

[0205] An A wiring layer 106, wherein the A wiring layer 106 includes an A electrical connection line electrically connected to the first p-electrode 103 through an A opening, and a B electrical connection line electrically connected to the first n-electrode 104 through a B opening;

[0206] A B passivation layer covering the A passivation layer 105 and the A wiring layer 106, the B passivation layer having a B opening region, the B opening region including a C opening and a D opening, the C opening exposing a partial region of the A electrical connection line, and the D opening exposing a partial region of the B electrical connection line;

[0207] A bonding layer 107, the A bonding layer 107 includes an A metal portion electrically connected to the A electrical connection line through a C opening, a B metal portion electrically connected to the B electrical connection line through a D opening, and a C metal portion located on a surface of the B passivation layer away from the A passivation layer, the C metal portion is used for subsequent electrical connection to a second light-emitting unit, and the A bonding layer is also used for subsequent bonding to a second array chip.

[0208] Optionally, in one embodiment of the present application, the size of the first light-emitting unit is greater than 0 μm and less than 500 μm; however, the present application does not limit this and it depends on the specific circumstances.

[0209] It should be noted that, due to the high transparency, high thermal conductivity, high electron mobility, high breakdown voltage, and high radiation resistance of SiC epitaxy to prepare CMOS active driver chips, the performance and reliability of Micro-LED driver display can be improved, and it has great advantages and potential in the field of full-color transparent display. Therefore, in one embodiment of the present application, the second array chip is prepared on a SiC transparent epitaxial wafer, and includes a plurality of CMOS display driver units; specifically, the plurality of CMOS display driver units include a plurality of first display driver units and a plurality of second display driver units; wherein the first light-emitting unit in the first array chip is electrically connected to the first display driver unit, and the second light-emitting unit in the third array chip is electrically connected to the second display driver unit. It should also be noted that, in this embodiment, the plurality of first display driver units include a plurality of first sub-display driver units and a plurality of second sub-display driver units, wherein the first sub-display driver unit is used to provide a display drive signal to a first light-emitting unit that does not provide light to the light processing layer, and the second sub-display driver unit is used to provide a display drive signal to a first light-emitting unit that provides light to the light processing layer, so that the light of the first color and the light of the third color emitted by the display panel can be independently controlled.

[0210] Specifically, in one embodiment of the present application, continue as follows Fig. 27 As shown, the second array chip is a SiC transparent epitaxial lateral CMOS driver chip, comprising:

[0211] An n-type doped SiC transparent epitaxial wafer, wherein the SiC epitaxial wafer comprises a SiC drift layer 202, wherein a SiC CMOS region 203 is formed in the SiC drift layer;

[0212] A C passivation layer (i.e., a first passivation layer) 204 located on the surface of the SiC CMOS region 203, wherein the C passivation layer (i.e., the first passivation layer) 204 has a C opening region, wherein the C opening region includes an E opening, an F opening, and a G opening which correspond to the positions of the gate electrode, the source electrode, and the drain electrode in the SiC CMOS region 203 in sequence;

[0213] A B wiring layer (i.e., a first wiring layer) 205, wherein the B wiring layer (i.e., the first wiring layer) 205 includes a C electrical connection line electrically connected to the gate electrode through an E opening, a D electrical connection line electrically connected to the source electrode through an F opening, and an E electrical connection line electrically connected to the drain electrode through a G opening;

[0214] A D passivation layer covering the C passivation layer (ie, the first passivation layer) 204 and the B wiring layer (ie, the first wiring layer) 205, wherein the D passivation layer has a D opening region, and the D opening region includes an H opening, an I opening, and a J opening;

[0215] The B bonding layer (i.e., the first bonding layer) 206 includes a D metal portion electrically connected to the C electrical connection line through an H opening, an E metal portion electrically connected to the D electrical connection line through an I opening, an F metal portion electrically connected to the E electrical connection line through a J opening, and a G metal portion located on the surface of the D passivation layer away from the C passivation layer. Thus, a driving array chip is obtained, and the B bonding layer is also used for subsequent bonding with the first array chip.

[0216] Specifically, in one embodiment of the present application, the SiC CMOS region in the SiC drift layer includes:

[0217] The p-type lightly doped region in the drift layer is used as the channel region, the n-type heavily doped region in the drift layer is used as the substrate bias region, the p-type heavily doped region in the channel region is used as the body bias region, and the n-type heavily doped region in the channel region is used as the source region and the drain region;

[0218] The dielectric located in the upper region between the source region and the drain region serves as a gate dielectric layer, and the gate electrode, source electrode and drain electrode are located above the gate dielectric layer, the source region and the drain region.

[0219] Optionally, in one embodiment of the present application, the display panel further includes: a flat panel capacitor (not shown) to provide capacitor charging and discharging for active addressing driving display, wherein one electrode plate of the flat panel capacitor is formed simultaneously with the B wiring layer, and the other electrode plate is formed simultaneously with the B bonding layer, so as to simplify the process flow of the display panel.

[0220] On the basis of the above embodiments, in one embodiment of the present application, the second array chip includes a through-hole metal connection area, and the second light-emitting unit in the third array chip is electrically connected to the second array chip toward the first array chip through the through-hole metal connection area to be electrically connected to the second display driving unit.

[0221] Optionally, in one embodiment of the present application, the B bonding layer also includes an H metal portion located in the through-hole metal connection area, the second array chip includes a through-hole penetrating the SiC drift layer and a through-hole metal located in the through-hole, one end of the through-hole metal is electrically connected to the H metal portion, and the other end is electrically connected to the bonding layer located between the second array chip and the third array chip, so as to realize the electrical connection between the second display driving unit and the second light-emitting unit.

[0222] It should be noted that, in the above embodiment, the second array chip further includes a G passivation layer, which is located on the surface of the second array chip away from the first array chip and exposes an end of the through-hole metal away from the first array chip.

[0223] Specifically, in one embodiment of the present application, in a plane parallel to the display panel, the projection of the through-hole metal connection area is located around the projection of the second light-emitting unit, so as to achieve electrical connection between the second light-emitting unit and the second display driving unit without affecting the display of the second light-emitting unit.

[0224] Optionally, in one embodiment of the present application, the CMOS display driving unit adopts a Micro-LED active site selection driving method; the capacitor area provides capacitance for the active site selection driving; and the B wiring layer provides electrical connection between devices for the active site selection driving.

[0225] Specifically, in one embodiment of the present application, in a direction parallel to the plane where the display panel is located, the size of the CMOS display driving unit is greater than 0 μm and less than 50 μm, so as not to affect the Micro-LED array display while ensuring the normal driving operation of the CMOS display driving unit, but the present application does not limit this and it depends on the specific situation.

[0226] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Fig. 27 As shown, the third array chip includes:

[0227] A second sapphire substrate 301;

[0228] A plurality of second light-emitting layers 302 located on the surface of the second sapphire substrate 301, wherein the second light-emitting layers 302 include a u-GaN layer, an n-GaN layer, a second light-emitting MQW layer, an electron blocking layer, and a p-GaN layer arranged in a direction perpendicular to the second sapphire substrate 301;

[0229] a second p-electrode 303 and a second n-electrode 304 electrically connected to the second light-emitting layer 302, wherein the second p-electrode 303 is electrically connected to the p-GaN layer, and the second n-electrode 304 is electrically connected to the n-GaN layer;

[0230] An E passivation layer 305 covering the second light-emitting layer 302, wherein the E passivation layer 305 has an E opening region, wherein the E opening region includes: a K opening exposing a portion of the second p-electrode 303, and an L opening exposing a portion of the second n-electrode 304;

[0231] A C wiring layer 306, wherein the C wiring layer 306 includes an F electrical connection line electrically connected to the second p-electrode 303 through a K opening, and a G electrical connection line electrically connected to the second n-electrode 304 through an L opening;

[0232] An F passivation layer covering the E passivation layer 305 and the C wiring layer 306, wherein the F passivation layer has an F opening region, wherein the F opening region includes an M opening and an N opening, wherein the M opening exposes a partial region of the E electrical connection line, and the N opening exposes a partial region of the F electrical connection line;

[0233] The C bonding layer 307 includes an I metal portion electrically connected to the E electrical connection line through an M opening, a J metal portion electrically connected to the F electrical connection line through an N opening, and a K metal portion located on the surface of the F passivation layer away from the E passivation layer. The C bonding layer is also used for subsequent bonding with the second array chip to obtain a third array chip.

[0234] Optionally, in an embodiment of the present application, in a direction parallel to the plane where the display panel is located, the size of the third light-emitting unit is greater than 0 μm and less than 500 μm, but the present application does not limit this and it depends on the specific circumstances.

[0235] On the basis of any of the above embodiments, in one embodiment of the present application, the light processing layer includes a light conversion layer and a filter layer, wherein the light conversion layer is used to form a third color of light emission based on part of the light emitted by the first light-emitting unit, and the filter layer is used to filter out other light in the light conversion layer except the third color of light, but the present application is not limited to this. In other embodiments of the present application, the light processing layer can also be other structures, depending on the specific circumstances.

[0236] Optionally, based on the above embodiment, in one embodiment of the present application, the light conversion layer is located on the first array chip, includes a plurality of light conversion units, and is correspondingly located above the first light emitting unit that provides a light source for converting light of a third color, and the filter layer is located on the second array chip, and is correspondingly located above the light conversion unit; in another embodiment of the present application, the light conversion is located on the second array chip, includes a plurality of light conversion units, and is correspondingly located above the first light emitting unit that provides a light source for converting light of a third color, and the filter layer is located on the third array chip, and is correspondingly located above the light conversion unit. The present application does not limit this, and it depends on the specific circumstances.

[0237] It should be noted that, in the above embodiment, in a plane parallel to the display panel, the sizes of the light conversion unit and the filter layer are consistent with the size of the first light emitting unit providing a light source for converting the light of the third color.

[0238] It should also be noted that since blue Micro-LED is far superior to green Micro-LED in terms of manufacturing cost, stability, lifespan, color purity, luminous efficiency, and difficulty of epitaxial growth, in one embodiment of the present application, in order to achieve better full-color display performance, the first light-emitting unit is a blue light-emitting unit, the second light-emitting unit is a green light-emitting unit, and the light processing layer includes a plurality of regularly distributed red quantum dots. Optionally, in this embodiment, the filter layer has a filtering effect on the blue light band of 400nm to 500nm. However, this application does not limit this, and it depends on the specific circumstances.

[0239] In summary, the display panel provided in the embodiment of the present application forms a full-color display by vertically stacking three array chips, namely a first array chip, a second array chip, and a third array chip, in a three-dimensional stacking manner. Compared with existing quantum dot full-color displays, mass transfer full-color displays, etc., it can achieve higher integration, higher performance, higher reliability, and lower power consumption.

[0240] Moreover, in the display panel provided in the embodiment of the present application, the second array chip is located between the first array chip and the third array chip, that is, the driving chip is located in the middle of the light-emitting chip, which helps to reduce the number of external connections of the driving chip and enables the driving energy of the driving chip to be closer to the light-emitting chip, thereby reducing energy loss during transmission.

[0241] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0242] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same figure marks throughout the embodiments of the specification identify the same structure. It should also be noted that in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. For example, A passivation layer ~ G passivation layer is used to distinguish different passivation layers, A electrical connection line ~ F electrical connection line is used to distinguish different electrical connection lines, A opening ~ N opening is used to distinguish different openings, A metal part ~ H metal part is used to distinguish different metal parts, and so on.

[0243] Moreover, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of more restrictions, the elements defined by the phrase "comprising a ..." do not exclude the presence of additional identical elements in the article or device comprising the above elements.

[0244] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: The first array chip, the second array chip and the third array chip are arranged in a direction perpendicular to the plane where the display panel is located; wherein, The first array chip includes a plurality of first light emitting units, and the first light emitting units emit light of a first color; The third array chip is located at the light-emitting side of the first array chip, the third array chip comprises a plurality of second light-emitting units, the second light-emitting units emit light of a second color, and a side of the third array chip away from the first array chip is the light-emitting side of the display panel; The second array chip is located between the first array chip and the third array chip, and is used to provide display driving signals for the first light-emitting unit and the second light-emitting unit; A light processing layer is provided between the layer where the first light emitting unit is located and the layer where the second light emitting unit is located, and the light processing layer is used to form light emission of a third color based on part of the light emitted by the first light emitting unit.

2. The display panel according to claim 1, characterized in that: The light processing layer includes a light conversion layer and a filter layer, wherein the light processing layer is located on the first array chip and the filter layer is located on the second array chip, or the light processing layer is located on the second array chip and the filter layer is located on the third array chip.

3. The display panel according to claim 1, characterized in that: The first light emitting unit is a blue light emitting unit, the second light emitting unit is a green light emitting unit, and the light processing layer forms red light emission based on the light emitted by the blue light emitting unit.

4. The display panel according to claim 1, characterized in that: The second array chip includes multiple CMOS display driving units; the multiple CMOS display driving units include multiple first display driving units and multiple second display driving units; wherein the first light-emitting unit in the first array chip is electrically connected to the first display driving unit, and the second light-emitting unit in the third array chip is electrically connected to the second display driving unit.

5. The display panel according to claim 4, characterized in that: The second array chip has a through-hole metal connection area, and the second light-emitting unit in the third array chip is electrically connected to the second array chip toward the first array chip through the through-hole metal connection area, so as to be electrically connected to the second display driving unit.

6. The display panel according to claim 4, characterized in that: The driving mode of the CMOS display driving unit in the third array chip adopts the Micro-LED active site selection driving mode.

7. A method for manufacturing a display panel, characterized in that: include: A first array chip, a second array chip and a third array chip are prepared respectively, wherein the first array chip comprises a plurality of first light-emitting units, which emit light of a first color; the third array chip comprises a plurality of second light-emitting units, which emit light of a second color; and the second array chip is used to provide display driving signals for the first light-emitting units and the second light-emitting units; A second array chip is bonded to the light-emitting side of the first array chip, and a third array chip is bonded to the side of the second array chip away from the first array chip, wherein the side of the third array chip away from the first array chip is the light-emitting side of the display panel; A light processing layer is provided between the layer where the first light emitting unit is located and the layer where the second light emitting unit is located, and the light processing layer is used to form light emission of a third color based on part of the light emitted by the first light emitting unit.

8. The method according to claim 7, characterized in that: The steps of preparing the first array chip, the second array chip and the third array chip respectively include: Prepare a first array chip, wherein the first array chip includes a plurality of first light-emitting units, and the first light-emitting units emit light of a first color; preparing a second array chip, wherein the second array chip is used to provide a display driving signal for the first light-emitting unit and the second light-emitting unit; preparing a third array chip, the third array chip comprising a plurality of second light emitting units, the second light emitting units emitting light of a second color; A light processing layer is prepared, the light processing layer is located between the layer where the first light emitting unit is located and the layer where the second light emitting unit is located, and the light processing layer is used to form light emission of a third color based on part of the light emitted by the first light emitting unit.

9. The manufacturing method according to claim 8, characterized in that: The second array chip has a through-hole metal connection area, and the through-hole metal connection area has a through-hole metal that penetrates the drift layer in the second array chip. The second light-emitting unit in the third array chip is electrically connected to the second array chip toward the first array chip through the through-hole metal.

10. The manufacturing method according to claim 9, characterized in that: The formation of the through-hole metal is after the first array chip and the second array chip are bonded, and the preparation of the second array chip includes: Providing an n-type doped SiC epitaxial wafer, wherein the SiC epitaxial wafer comprises a SiC substrate layer and a SiC drift layer; forming a SiC CMOS region in the SiC drift layer; Depositing a first passivation layer on the surface of the SiC CMOS region, and forming a first opening region in the first passivation layer, wherein the first opening region includes a first opening, a second opening, and a third opening corresponding to positions of a gate electrode, a source electrode, and a drain electrode in the SiC CMOS region; Prepare a first wiring layer, the first wiring layer comprising a first electrical connection line electrically connected to the gate electrode through a first opening, a second electrical connection line electrically connected to the source electrode through a second opening, and a third electrical connection line electrically connected to the drain electrode through a third opening; Depositing a second passivation layer covering the first passivation layer and the first wiring layer, and etching the second passivation layer to form a second opening region, wherein the second opening region includes a fourth opening, a fifth opening, and a sixth opening; A first bonding layer is formed, the first bonding layer including a first metal portion electrically connected to the first electrical connection line through a fourth opening, a second metal portion electrically connected to the second connection line through a fifth opening, and a third metal portion electrically connected to the third electrical connection line through a sixth opening, a fourth metal portion located on a surface of the second passivation layer away from the first passivation layer, and a fifth metal portion located in the through-hole metal connection area.

11. The manufacturing method according to claim 10, characterized in that: After bonding the second array chip to the light-emitting side of the first array chip and before bonding the third array chip to the side of the second array chip away from the first array chip, the method further includes: removing the SiC substrate layer in the second array chip, and thinning the SiC drift layer in the second array chip; Etching the SiC drift layer to form a first through hole penetrating the SiC drift layer, wherein the first through hole exposes at least a portion of the fifth metal portion; forming a third passivation layer on a side of the SiC drift layer away from the first array chip and on a surface of the first through hole, and etching the third passivation layer to form a second through hole, wherein the second through hole exposes at least a portion of the bottom of the first through hole to expose at least a portion of the fifth metal portion; forming a via metal in the second via; A second bonding layer is formed on a surface of the third passivation layer away from the first array chip and a surface of the through-hole metal away from the first array chip, and the second bonding layer is used for subsequent bonding with the third array chip.

12. The manufacturing method according to claim 9, characterized in that: The formation of the through-hole metal is before the first array chip and the second array chip are bonded, and the preparation of the driving array chip includes: Providing an n-type doped SiC epitaxial wafer, wherein the SiC epitaxial wafer comprises a SiC substrate layer and a SiC drift layer; forming a SiC CMOS region in the SiC drift layer; Etching in the SiC drift layer at a position corresponding to a through-hole metal connection region to form a first through-hole; Depositing a first passivation layer on the surface of the SiC CMOS region and the surface of the first through hole, and forming a first opening region on the first passivation layer, wherein the first opening region includes a first opening, a second opening, and a third opening corresponding to the positions of the gate electrode, the source electrode, and the drain electrode in the SiC CMOS region, and the first opening region also exposes the bottom of the first through hole; Prepare a first wiring layer, the first wiring layer comprising a first electrical connection line electrically connected to the gate electrode through a first opening, a second electrical connection line electrically connected to the source electrode through a second opening, and a third electrical connection line electrically connected to the drain electrode through a third opening; Depositing a second passivation layer covering the first passivation layer and the first wiring layer, and etching the second passivation layer to form a second opening area, wherein the second opening area includes a fourth opening, a fifth opening, and a sixth opening, and the second opening area also exposes the bottom of the first through hole; forming a through-hole metal in the first through-hole, wherein the through-hole metal fills the first through-hole; A first bonding layer is formed, the first bonding layer including a first metal portion electrically connected to the first electrical connection line through a fourth opening, a second metal portion electrically connected to the second connection line through a fifth opening, a third metal portion electrically connected to the third electrical connection line through a sixth opening, and a fifth metal portion located in the through-hole metal connection area.

13. The manufacturing method according to claim 12, characterized in that: After bonding the second array chip to the light-emitting side of the first array chip and before bonding the third array chip to the side of the second array chip away from the first array chip, the method further includes: Removing the SiC substrate layer in the second array chip, and thinning the SiC drift layer in the second array chip until the end surface of the through-hole metal away from the first array chip is exposed; forming a third passivation layer on a side of the SiC drift layer away from the first array chip and on a surface of the through-hole metal, and etching the third passivation layer to form a second through-hole, wherein the second through-hole exposes at least a portion of the through-hole metal; A second bonding layer is formed on a surface of the third passivation layer away from the first array chip and a surface of the through-hole metal away from the first array chip.

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