System and method for optimizing metrology markers

Abstract

Systems, methods, and computer software for optimizing metrology markers are disclosed. A method includes simulating an etch process based on one or more of pattern density, in-mark changes caused by microload effects, or sensitivity of in-mark changes to etch chemicals. The method may predict an effect of an etch-induced process on the metrology mark based on a simulation of the etch process, and optimize the metrology mark based on the predicted effect of the etch-induced process.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to US application 63 / 390,459, filed on July 19, 2022, which is incorporated herein by reference in its entirety. Technical Field

[0003] The description herein generally relates to the design and optimization of etched metrology marks. More specifically, the present disclosure includes apparatus, methods, and computer programs for optimizing metrology marks using simulations that take into account physical and chemical influences on the etching process. Background Art

[0004] Lithographic projection apparatus may be used, for example, in the manufacture of integrated circuits (ICs). In this case, a patterning device (e.g., a mask) may contain or provide a pattern corresponding to a single layer (a "design layout") of the IC, and the pattern may be transferred to a target portion (e.g., including one or more dies) on a substrate (e.g., a silicon wafer) that has been coated with a layer of radiation-sensitive material ("resist"), such as by irradiating the target portion through the pattern on the patterning device. Typically, a single substrate contains multiple adjacent target portions, and the lithographic projection apparatus transfers the pattern to the target portions successively, one target portion at a time. In one type of lithographic projection apparatus, the pattern on the entire patterning device is transferred to one target portion at a time; such an apparatus may also be referred to as a stepper. In an alternative apparatus, a step-and-scan apparatus may cause the projection beam to be scanned over the patterning device in a given reference direction (the "scanning" direction) while the substrate is moved parallel or antiparallel to the reference direction. Different portions of the pattern on the patterning device are gradually transferred to one target portion. Typically, since the lithographic projection apparatus will have a speed reduction ratio M (eg 4), the speed F at which the substrate moves will be 1 / M times the speed at which the projection beam scans the patterning device. More information on lithographic apparatus can be found in, for example, US 6,046,792, which is incorporated herein by reference.

[0005] Before the pattern is transferred from the pattern forming device to the substrate, the substrate may undergo various processes such as priming, resist coating, and soft baking. After exposure, the substrate may undergo other processes ("post-exposure processes") such as post-exposure baking (PEB), development, hard baking, and measurement / inspection of the transferred pattern. This series of processes is used as the basis for preparing individual layers of a device such as an IC. The substrate may then undergo various processes such as etching, ion implantation (doping), metallization, oxidation, chemical mechanical polishing, etc., all of which are intended to complete the various layers of the device. If several layers are required in the device, the entire process or a variation thereof is repeated for each layer. Ultimately, the device will be present in each target portion on the substrate. These devices are then separated from each other by techniques such as cutting or sawing so that the individual devices can be assembled on a carrier, connected to pins, etc.

[0006] Therefore, manufacturing devices (such as semiconductor devices) typically involves processing a substrate (e.g., a semiconductor wafer) using multiple manufacturing processes to form various features and multiple layers of the device. Such layers and features are typically manufactured and processed using, for example, deposition, lithography, etching, chemical mechanical polishing, and ion implantation. Multiple devices can be manufactured on multiple chips on a substrate and then separated into individual devices. This device manufacturing process can be considered a patterning process. The patterning process involves patterning steps such as optical and / or nanoimprint lithography using a pattern forming device in a lithographic apparatus to transfer the pattern on the pattern forming device to the substrate, and typically but optionally involves one or more related pattern processing steps, such as resist development by a developing apparatus, baking the substrate using a baking tool, etching the pattern using an etching apparatus, etc.

[0007] It should be noted that photolithography is a central step in the manufacture of devices such as ICs, where patterns formed on a substrate define the functional elements of the device, such as microprocessors, memory chips, etc. Similar photolithography techniques are also used to form flat panel displays, micro-electromechanical systems (MEMS), and other devices.

[0008] As semiconductor manufacturing processes continue to advance, the size of functional elements continues to decrease, while at the same time, the number of functional elements (such as transistors) per device has been steadily increasing for decades, following a trend known as "Moore's Law." In the current state of the art, the layers of a device are manufactured using a lithography projection apparatus that projects a design layout onto a substrate using illumination from a deep ultraviolet illumination source, thereby producing individual functional elements having dimensions well below 100 nm (i.e., less than half the wavelength of the radiation from the illumination source (e.g., an illumination source of 193 nm)).

[0009] The process of printing features with dimensions smaller than the classical resolution limit of a lithographic projection apparatus may be referred to as low-k1 lithography, according to the resolution formula CD = k1×λ / NA, where λ is the wavelength of the radiation employed (e.g., 248 nm or 193 nm), NA is the numerical aperture of the projection optics in the lithographic projection apparatus, CD is the "critical dimension" (usually the smallest feature size printed) and k1 is an empirical resolution factor. In general, the smaller k1 is, the more difficult it becomes to reproduce on a substrate a pattern that resembles the shape and dimensions planned by the circuit designer in order to achieve specific electrical functions and performance. To overcome these difficulties, complex fine tuning steps may be applied to the lithographic projection apparatus, the design layout, or the patterning device. These steps include, for example, but are not limited to: optimization of NA and optical coherence settings, self-defining illumination schemes, use of phase-shifting patterning devices, optical proximity correction (OPC, sometimes also referred to as "optical and process correction") in the design layout, or other methods generally defined as "resolution enhancement techniques" (RET). The term "projection optics" as used herein should be broadly interpreted to cover various types of optical systems, including, for example, refractive optics, reflective optics, apertures, and refractive-reflective optics. The term "projection optics" may also include components that operate according to any of these design types for guiding, shaping, or controlling a projection radiation beam, either collectively or individually. The term "projection optics" may include any optical component in a lithographic projection apparatus, regardless of where the optical component is located on the optical path of the lithographic projection apparatus. Projection optics may include optical components for shaping, adjusting, and / or projecting radiation from a source before it passes through a patterning device, and / or optical components for shaping, adjusting, and / or projecting radiation after it passes through a patterning device. Projection optics typically do not include a source and a patterning device. Summary of the invention

[0010] Systems, methods, and computer software for optimizing metrology marks are disclosed. In one aspect, a method includes simulating an etching process based on one or more of pattern density, intra-mark variations caused by microloading effects, or sensitivity of intra-mark variations to etching chemistry. The method can predict the effects of etching-induced processes on the metrology marks based on the simulation of the etching process, and optimize the metrology marks based on the predicted effects of the etching-induced processes.

[0011] In some variations, the etch rate in the simulation may be based at least in part on a function of CD, wherein coefficients in the function depend on the etch chemistry. The function may be an exponential term with the coefficients, the function partially determining the etch load of the etch process.

[0012] In some variations, the intra-mark variation caused by the micro-loading effect may include the CD or sidewall angle or bottom side tilt of the measured mark being greater or less than the ideal measured mark. For example, the intra-mark variation caused by the micro-loading effect may be based on the pattern density. In addition, determining the sensitivity of the intra-mark variation to the etching chemistry may include determining the etching rate based on determining whether the etching mechanism is forward hysteresis or reverse hysteresis by the etching chemistry.

[0013] In some variations, optimizing the metrology marks may include optimizing metrology mark placement based on an intra-die overlap fingerprint generated by a simulation of the etching process at a first length scale. This may also include obtaining a metrology mark design and a metrology mark placement in a die, inputting the metrology mark design into the simulation at the first length scale, extracting a critical region in a die based on the intra-die overlap fingerprint determined by the simulation; and optimizing the metrology mark placement while avoiding the critical region to minimize the intra-die overlap fingerprint.

[0014] In some variations, the metrology mark design may be based on one or more of CD, pitch, segment, or surrounding fill structure. The simulation may also be based on inputting stackup information of the metrology mark design, the stackup information including layers in the die, the inputting the metrology mark design may include determining an etching mechanism, wherein the simulation may be based on whether the etching mechanism is forward hysteresis or reverse hysteresis.

[0015] In some variations, optimizing the metrology mark may include optimizing a metrology mark design based on an intra-die overlap fingerprint generated from a simulation of the etching process at a second length scale. This may include obtaining a metrology mark design and a metrology mark placement in a die, inputting the metrology mark design into the simulation at the second length scale, extracting the intra-mark overlap fingerprint from the simulation at the second length scale, and optimizing the metrology mark design to reduce the intra-mark overlap fingerprint.

[0016] In some variations, optimizing the metrology mark may include optimizing one or more of the CD, pitch, design, and segment of the metrology mark, and may further include optimizing the surrounding fill pattern to reduce intra-mark variation.

[0017] In some variations, a method may include inputting ideal metrology marks; determining a bottom side tilt map, a side wall angle map, a CD map, and an etch depth map based on predicting the effect of the etch-induced process for each of the ideal metrology marks, generating a three-dimensional representation of the post-etch mark geometry based on the bottom side tilt map, the side wall angle map, the CD map, and the etch depth map; and determining a combination of the ideal metrology marks, the combination improving the performance of a die using the combination, the performance being determined based at least on the three-dimensional representation.

[0018] In some variations, improving the performance includes reducing alignment position deviation, and the performance may be determined using a finite-difference time-domain optical solver. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this application document, illustrate certain aspects of the subject matter disclosed herein and, together with the description, help explain some principles associated with the disclosed embodiments. In the accompanying drawings,

[0020] Figure 1 A block diagram showing various subsystems of a lithographic projection apparatus according to an embodiment of the present disclosure is shown.

[0021] Figure 2 An exemplary flow chart for simulating lithography in a lithographic projection apparatus according to an embodiment of the present disclosure is illustrated.

[0022] Figure 3 Illustrated are metrology marks on a die with varying pattern density according to an embodiment of the present disclosure.

[0023] Figure 4 A simplified etching process according to an embodiment of the present disclosure is illustrated.

[0024] Figure 5 The effect of feature size on etch rate according to an embodiment of the present disclosure is illustrated.

[0025] Figure 6 The effect of adjacent pattern density on the etching performance of a metrology mark according to an embodiment of the present disclosure is illustrated.

[0026] Figure 7 A process of optimizing metrology marks according to an embodiment of the present disclosure is illustrated.

[0027] Figure 8 A process for optimizing metrology mark placement according to an embodiment of the present disclosure is illustrated.

[0028] Fig. 9 A process of optimizing metrology mark design according to an embodiment of the present disclosure is illustrated.

[0029] Fig.10 is a schematic diagram illustrating metrology marks with variations in CD, bottom side slope, and sidewall angle according to an embodiment of the present disclosure.

[0030] Fig.11 is a schematic diagram illustrating a process for optimizing metrology mark design according to an embodiment of the present disclosure.

[0031] Fig.12 is a block diagram of an exemplary computer system according to an embodiment of the present disclosure.

[0032] Fig.13 is a schematic diagram of a lithography projection apparatus according to an embodiment of the present disclosure.

[0033] Fig.14 is a schematic diagram of another lithography projection apparatus according to an embodiment of the present disclosure.

[0034] Fig.15 is a detailed view of a lithographic projection apparatus according to an embodiment of the present disclosure.

[0035] Fig.16 is a detailed view of a source collector module of a lithographic projection apparatus according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Although specific reference may be made herein to the manufacture of ICs, it should be clearly understood that the description herein has many other possible applications. For example, other possible applications may be used to manufacture integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid crystal display panels, thin film magnetic heads, etc. It will be understood by those skilled in the art that any use of the terms "reticle", "wafer" or "die" herein in the context of such alternative applications should be considered interchangeable with the more general terms "mask", "substrate" and "target portion", respectively.

[0037] In this document, the terms "radiation" and "beam" are used to cover all types of electromagnetic radiation, including ultraviolet radiation (e.g. having a wavelength of 365nm, 248nm, 193nm, 157nm or 126nm) and EUV (extreme ultraviolet radiation, e.g. having a wavelength in the range of about 5-100nm).

[0038] The pattern forming device may include or may form one or more design layouts. The design layout may be generated using a CAD (computer-aided design) program, a process commonly referred to as EDA (electronic design automation). Most CAD programs follow a predetermined set of design rules in order to create a functional design layout / pattern forming device. These rules are set by processing and design constraints. For example, the design rules define the spatial tolerances between devices (such as gates, capacitors, etc.) or interconnects to ensure that the devices or lines do not interact with each other in an undesirable manner. One or more of the design rule constraints may be referred to as "critical dimensions" (CD). The critical dimension of a device may be defined as the minimum width of a line or hole, or the minimum spacing between two lines or two holes. Therefore, CD determines the overall size and density of the designed device. Of course, one of the goals in device manufacturing is to faithfully reproduce the original design intent on the substrate (via the pattern forming device).

[0039] The terms "mask" or "patterning device" as used herein may be broadly interpreted as referring to a general patterning device that can be used to impart a patterned cross-section to an incident radiation beam, the patterned cross-section corresponding to the pattern to be produced in a target portion of the substrate; the term "light valve" may also be used in this context. In addition to classical masks (transmissive or reflective; binary, phase-shift, hybrid, etc.), other examples of these patterning devices include programmable mirror arrays and programmable LCD arrays.

[0040] An example of a programmable mirror array may be a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such a device is that (for example) addressed areas of the reflective surface reflect incident radiation as diffracted radiation, while unaddressed areas reflect incident radiation as undiffracted radiation. By using suitable filters, the undiffracted radiation can be filtered out of the reflected beam, leaving only the diffracted radiation; in this way, the beam is patterned according to the addressing pattern of the matrix-addressable surface. The required matrix addressing can be performed using suitable electronic methods.

[0041] An example of a programmable LCD array is given in US Pat. No. 5,229,872, which is incorporated herein by reference.

[0042] Figure 1A block diagram of various subsystems of a lithographic projection apparatus 10A according to an embodiment of the present disclosure is illustrated. The main components are a radiation source 12A, which may be a deep ultraviolet excimer laser source or other types of sources including an extreme ultraviolet (EUV) source (as described above, the lithographic projection apparatus itself need not have a radiation source); illumination optics, which, for example, define partial coherence (expressed as sigma or σ) and may include optics 14A, 16Aa, and 16Ab that shape the radiation from source 12A; a patterning device 18A; and transmissive optics 16Ac that projects an image of the patterning device pattern onto a substrate plane 22A. An adjustable filter or hole 20A at the pupil plane of the projection optics can limit the angular range of the beam incident on the substrate plane 22A, where the maximum possible angle defines the numerical aperture NA=n sin(Θmax) of the projection optics, where n is the refractive index of the medium between the substrate and the last element of the projection optics, and Θmax is the maximum angle of the beam emerging from the projection optics that can still be incident on the substrate plane 22A.

[0043] In a lithographic projection apparatus, a source provides illumination (i.e., radiation) to a patterning device, and projection optics shapes the illumination light via the patterning device and directs the illumination onto a substrate. The projection optics may include at least some of components 14A, 16Aa, 16Ab, and 16Ac. An aerial image (AI) is a distribution of radiation intensity at the substrate level. A resist image may be calculated from an aerial image using a resist model, an example of which may be found in U.S. Patent Application Publication No. US2009-0157630, the disclosure of which is incorporated herein by reference in its entirety. The resist model is only related to the properties of the resist layer (e.g., the effects of chemical processes occurring during exposure, post-exposure baking (PEB), and development). The optical properties of the lithographic projection apparatus (e.g., the properties of the illumination, patterning device, and projection optics) determine the aerial image and may be defined in an optical model. Since the patterning device used in the lithographic projection apparatus may be changed, it is desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus, which includes at least the source and projection optics. Details of techniques and models for converting a design layout into various lithographic images (e.g., aerial images, resist images, etc.), applying OPC using these techniques and models, and evaluating performance (e.g., in terms of process window) are described in U.S. Patent Application Publication Nos. US2008-0301620, US2007-0050749, US2007-0031745, US2008-0309897, US2010-0162197, and US2010-0180251, the disclosures of each of which are incorporated herein by reference in their entirety.

[0044] One aspect of understanding the lithography process is understanding the interaction of radiation and patterning devices. The electromagnetic field of the radiation after it passes through the patterning device can be determined based on the electromagnetic field of the radiation before it reaches the patterning device and a function that characterizes the interaction. This function can be called the mask transmission function (the mask transmission function can be used to describe the interaction with a transmissive patterning device and / or a reflective patterning device).

[0045] The mask transmission function can have a variety of different forms. One form is binary. A binary mask transmission function has either of two values ​​(e.g., zero and a positive constant) at any given position on the pattern forming device. A mask transmission function in binary form can be referred to as a binary mask. Another form is continuous. That is, the modulus of the transmittance (or reflectance) of the pattern forming device is a continuous function of the position on the pattern forming device. The phase of the transmittance (or reflectance) can also be a continuous function of the position on the pattern forming device. A mask transmission function in continuous form can be referred to as a continuous tuning mask or a continuous transmission mask (CTM). For example, a CTM can be represented as a pixelated image, where each pixel can be assigned a value between 0 and 1 (e.g., 0.1, 0.2, 0.3, etc.), rather than a binary value of 0 or 1. In one embodiment, the CTM can be a pixelated grayscale image, where each pixel has a value (e.g., a value in the range [-255, 255], a normalized value in the range [0, 1] or [-1, 1] or other appropriate range).

[0046] The thin mask approximation, also known as the Kirchhoff boundary condition, is widely used to simplify the determination of the interaction of radiation and the patterning device. The thin mask approximation assumes that the thickness of the structure on the patterning device is very small compared to the wavelength, and the width of the structure on the mask is very large compared to the wavelength. Therefore, the thin mask approximation assumes that the electromagnetic field behind the patterning device is the product of the incident electromagnetic field and the mask transmission function. However, as the lithography process uses shorter and shorter wavelength radiation and the structures on the patterning device become smaller and smaller, the assumption of the thin mask approximation may break down. For example, due to the finite thickness of the structure ("mask 3D effect" or "M3D"), the interaction of radiation with the structure (e.g., the edge between the top surface and the sidewall) may become significant. Including this scattering in the mask transmission function can enable the mask transmission function to better capture the interaction of radiation with the patterning device. The mask transmission function under the thin mask approximation can be referred to as a thin mask transmission function. The mask transmission function including M3D can be referred to as an M3D mask transmission function.

[0047] According to an embodiment of the present disclosure, one or more images may be generated. These images include various types of signals that may be characterized by a pixel value or an intensity value of each pixel. Depending on the relative value of the pixels within the image, the signal may be referred to as a weak signal or a strong signal, for example, as understood by a person of ordinary skill in the art. The terms "strong" and "weak" are relative terms based on the intensity values ​​of the pixels within the image, and the scope of the present disclosure may not be limited to a specific intensity value. In one embodiment, strong signals and weak signals may be identified based on a selected threshold. In one embodiment, the threshold may be fixed (e.g., the midpoint of the highest intensity and the lowest intensity of the pixels in the image). In one embodiment, a strong signal may refer to a signal having a value greater than or equal to the average signal value of the entire image, and a weak signal may refer to a signal having a value less than the average signal value. In one embodiment, the relative intensity value may be based on a percentage. For example, a weak signal may be a signal having an intensity less than 50% of the highest intensity of the pixels within the image (e.g., the pixels corresponding to the target pattern may be considered as pixels with the highest intensity). In addition, each pixel within the image may be considered as a variable. According to the present embodiment, a derivative or partial derivative may be determined for each pixel within the image, and the value of each pixel may be determined or modified based on an estimate of a cost function and / or a gradient-based cost function calculation. For example, a CTM image may include pixels, each of which is a variable that may take any real number.

[0048] Figure 2 An exemplary flow chart for simulating lithography in a lithographic projection apparatus according to an embodiment of the present disclosure is illustrated. A source model 31 represents the optical properties of a source (including radiation intensity distribution and / or phase distribution). A projection optics model 32 represents the optical properties of the projection optics (including changes in radiation intensity distribution and / or phase distribution caused by the projection optics). A design layout model 35 represents the optical properties of a design layout (including changes in radiation intensity distribution and / or phase distribution caused by the design layout 33), which represents the arrangement of features on or formed by a pattern forming device. An aerial image 36 can be simulated based on the design layout model 35, the projection optics model 32, and the design layout model 35. A resist image 38 can be simulated based on the aerial image 36 using a resist model 37. For example, a simulation of lithography can predict the profile and / or CD in a resist image.

[0049] More specifically, it is noted that the source model 31 can represent the optical characteristics of the source, including but not limited to numerical aperture settings, illumination sigma (σ) settings, and any specific illumination shape (e.g., off-axis radiation sources such as toroidal, quadrupole, dipole, etc.). The projection optics model 32 can represent the optical characteristics of the projection optics, including aberrations, distortions, one or more refractive indices, one or more physical sizes, or one or more physical dimensions, etc. The design layout model 35 can represent one or more physical properties of a physical pattern forming device, such as described in U.S. Patent No. 7,587,704, which is incorporated herein by reference in its entirety. The purpose of the simulation is to accurately predict, for example, edge placement, spatial image intensity slope, and / or CD, which can then be compared to the expected design. The expected design is typically defined as a pre-OPC design layout, which can be provided in a standardized digital file format such as GDSII or OASIS or in other file formats.

[0050] From this design layout, one or more portions may be identified, which are referred to as "snippets". In an embodiment, a set of snippets is extracted, which represents complex patterns in the design layout (typically about 50 to 1000 snippets, but any number of snippets may be used). These patterns or snippets represent small portions of the design (e.g., circuits, cells, or patterns), and in particular, snippets typically represent small portions that require specific attention and / or verification. In other words, a snippet may be a portion of the design layout, or may be similar to a portion of the design layout or have similar behavior to a portion of the design layout, where one or more critical features are identified through experience (including snippets provided by customers), trial and error, or running full chip simulations. A snippet may contain one or more test patterns or gauge patterns.

[0051] The customer may a priori propose an initial larger set of segments based on one or more known critical feature areas in the design layout that require specific image optimization. Alternatively, in another embodiment, the initial larger set of segments may be extracted from the entire design layout by using some automated algorithm (such as machine vision) or a manual algorithm that identifies one or more critical feature areas.

[0052] In a lithographic projection apparatus, as an example, the cost function can be expressed as

[0053] (Equation 1)

[0054] Among them, (z1, z2, …, z N ) are N design variables or the values ​​of the N design variables. p (z1, z2,…,z N ) can be the design variables (z1, z2,…, zN ), such as the design variables (z1, z2,…, z N ) is the difference between the actual value and the expected value of a characteristic of a set of values ​​of w p is with f p (z1, z2,…, z N ) is associated with a weight constant. For example, a feature may be the position of an edge of a pattern measured at a given point on the edge. Different f p (z1, z2,…, z N ) can have different weights w p For example, if a particular edge has a narrow range of allowed positions, then f, which represents the difference between the actual position of the edge and the expected position, p (z1, z2,…, z N ) weight w p can be given a higher value. p (z1, z2,…, z N ) can also be a function of the interlayer characteristics, which are in turn the design variables (z1, z2,…, z N ). Of course, CF(z1,z2,…, z N ) is not limited to the form of equation 1. CF(z1, z2,…, z N ) may be in any other suitable form.

[0055] The cost function may represent any one or more suitable characteristics of the lithographic projection apparatus, the lithographic process, or the substrate, such as focus, CD, image shift, image distortion, image rotation, random variation, yield, local CD variation, process window, inter-layer characteristics, or a combination thereof. In one embodiment, the design variables (z1, z2, ..., z N ) includes one or more selected from dose, global bias of the patterning device, and / or illumination shape. Since the embodiment is a resist image that is generally indicative of a pattern on a substrate, the cost function may include a function representing one or more characteristics of the resist image. For example, f p (z1, z2,…,z N ) can simply be the distance between a point in the resist image and the expected position of that point (i.e., the edge placement error EPE P (z1, z2,…, z N )). Design variables may include any adjustable parameters, such as adjustable parameters of the source, patterning device, projection optics, dose, focus, etc.

[0056] The lithographic apparatus may include components collectively referred to as "wavefront manipulators", which may be used to adjust the shape of the wavefront and the intensity distribution and / or phase shift of the radiation beam. In one embodiment, the lithographic apparatus may adjust the wavefront and intensity distribution at any position along the optical path of the lithographic projection apparatus, such as adjusting the wavefront and intensity distribution at a position in front of the pattern forming device, near the pupil plane, near the image plane, and / or near the focal plane. The wavefront manipulator may be used to correct or compensate for specific distortions of the wavefront and intensity distribution and / or phase shift caused by, for example, temperature changes in the source, pattern forming device, lithographic projection apparatus, thermal expansion of components of the lithographic projection apparatus, etc. Adjusting the wavefront and intensity distribution and / or phase shift may change the value of the characteristic represented by the cost function. This change may be simulated according to a model or may be actually measured. The design variables may include parameters of the wavefront manipulator.

[0057] The design variables can have constraints, which can be expressed as (z1, z2, …, z N )∈Z, where Z is the set of possible values ​​of the design variables. One possible constraint on the design variables may be imposed by the desired output of the lithographic projection apparatus. Without such a constraint imposed by the desired output, the optimization may produce an unrealistic set of design variable values. For example, if dose is the design variable, in the absence of such a constraint, the optimization may produce dose values ​​that make the output economically unachievable. However, the validity of the constraint should not be interpreted as a requirement. For example, the output may be affected by the pupil filling ratio. For some illumination designs, a low pupil filling ratio may discard radiation, resulting in lower output. The output may also be affected by the resist chemistry. Slower resists (e.g., resists that require a higher amount of radiation to be properly exposed) will result in lower output.

[0058] As used herein, the term "patterning process" refers to a process that produces an etched substrate by applying light having a specific pattern as part of a photolithography process.

[0059] As used herein, the term "target pattern" refers to an idealized pattern to be etched on a substrate.

[0060] As used herein, the term "printed pattern" refers to a physical pattern formed on a substrate based on a design layout. For example, the printed pattern may include vias, contact holes, grooves, channels, recesses, edges, or other two-dimensional and three-dimensional features produced by a photolithography process.

[0061] As used herein, the term "process model" refers to a model that includes one or more models that simulate a patterning process. For example, a process model may include any combination of an optics model (e.g., the optics model models a lens system / projection system used to deliver light during a lithography process and may include modeling a final optical image of light reaching the photoresist), a mask model, a resist model (e.g., the resist model models physical effects (such as chemical effects) on the resist caused by light), an OPC model (e.g., the OPC model may be used to make a design layout and may include sub-resolution resist features (SRAF), etc.), an imaging device model (e.g., the imaging device model models what the imaging device may image based on the printed pattern).

[0062] As used herein, the term "imaging device" refers to any number or combination of devices and associated computer hardware and software that can be configured to generate an image of a target, such as a printed pattern or a portion of the printed pattern. Non-limiting examples of imaging devices may include: scanning electron microscopes (SEMs), x-ray machines, etc.

[0063] Figure 3 Metrology marks on a die having varying pattern densities according to an embodiment of the present disclosure are shown. Metrology marks can be physical features etched into a substrate of a die printed using the photolithography methods described herein. Metrology marks can be used to provide reference points that can be detected and measured by a metrology system (e.g., a scanning electron microscope, an optical device, etc.). Metrology marks can be used to determine variations from die to die that may indicate manufacturing errors or other process effects that may need to be corrected. Metrology marks can also be implemented on different layers of a die and thus can be used to determine overlap or other level-related features.

[0064] exist Figure 3 In the example shown, die 310 is depicted as having a complex printed pattern. The enlarged view shows region 320, and depicts different regions of die 310 having different pattern densities (e.g., there may be more or fewer etched features in a given region), such as high density region 330 and low density region 340. In this particular example, the high density region has less open area than the low density region. However, in the example Figure 4 In the different examples shown, the reverse is also true, where the high density regions 330 are also high open area regions. Also shown are metrology marks 350 that may span the boundaries between the various high density regions 330 and low density regions 340. In other embodiments, the metrology marks may be entirely within the region with consistent pattern density, or in other approaches, may be provided anywhere and at any layer within the die.

[0065] An enlarged view 360 of a single metrology mark 350 illustrates one example of a metrology mark design, where the metrology mark may include multiple features, such as lines that may be etched into a die. Although metrology mark 350 is an example design, different embodiments may utilize different designs (e.g., see Fig.10 350 ). While the etching process used to form the metrology marks may require nominally identical features (e.g., each line may be expected to be identical), the lines may be near areas of the die 350 that may have different pattern densities, which may result in variations in the etch rate when the metrology marks are formed. Such variations may then interfere with the use of the metrology marks as accurate reference points. Various embodiments of the present disclosure provide methods for optimizing metrology marks to reduce such variations. Because these variations may be caused by variations in the etch rate caused by local pattern features and may only occur over a limited spatial range, these variations may appear as asymmetry in an otherwise symmetrical mark. Therefore, as used herein, the term "asymmetry" is generally synonymous with the term "variation."

[0066] Figure 4 A simplified etching process according to an embodiment of the present disclosure is illustrated. Figure 4 , plasma etching is depicted by showing an exemplary plasma source 410 that produces charged species (ions) 412, and uncharged species 414 (neutral and radicals) from a supply of etching gas 416 (e.g., a reactive gas diluted with an inert gas). The ions 412 and uncharged species 414 together form an etchant that reacts with the surface of the substrate 420 (where not protected by the resist layer) and removes material from the substrate 420 in the form of emissions or radiation 418. Features 430 are then etched from the substrate 420 by removing the emissions 418. The emissions 418 can be volatile byproducts or non-volatile products that are redeposited elsewhere. As shown, these features can have properties similar to Figure 3 High density regions 330 and low density regions 340 are depicted.

[0067] Figure 4 Also depicted is an etchant concentration 440 and an emission concentration 450. The etchant concentration 440 may be lower in high open area regions 330, and the emission concentration 450 may be lower in low open area regions 340. This may be because the consumption of the etchant may be higher in high open area regions. Thus, the etching rate may be a function of the local open area, and therefore indirectly depends on the pattern density.

[0068] Figure 5The effect of feature size on etch rate is illustrated in accordance with an embodiment of the present invention. Another process that may affect the etch rate may be the etch chemistry itself. Graph 510 depicts the variation of etch rate with feature size (e.g., critical dimension or CD). "Positive hysteresis" 512 is depicted by the lower dashed curve and shows that with lean chemistry (e.g., plasma rich in fluorine radicals), the etch rate increases with CD because the etchant is more readily available and the etch byproducts are more readily removed when the CD is larger. However, there may be other process gases (e.g., CF-rich plasmas) that have the opposite behavior. x Base polymer) - the etch rate decreases with CD. This is likely due to the fluorocarbon etchant passivating the feature and causing the etch rate to decrease with increasing CD. This "reverse hysteresis" 514 behavior is depicted by the upper solid curve.

[0069] Figure 520 depicts passivation and how combinations of these chemical processes work to increase or decrease CD 530. When the etchant consists of more fluorine radicals (F x ) this will cause a CD expansion of 522. However, passivating substances (such as CF x ) and / or emitting material (SiF x The contribution of the etch rate (combination of silicon substrate material and fluorine gas) may cause CD shrinkage 524. Spatial variations in CD due to positive or negative hysteresis effects may be due to microloading. Therefore, there may be different degrees of passivation as a function of feature depth, and thus may cause the etch rate to be higher near the top of the feature. Among other effects, this may cause the sidewall angle 540 of the feature to be different from the ideal angle of 90 degrees.

[0070] Figure 6 The effect of adjacent pattern density on the etch performance of a metrology mark according to an embodiment of the present disclosure is illustrated.The physical etching process described above may contribute to varying the etch performance, such as CD or overlay (OVL), of features present in any particular metrology mark. Figure 6 Reproduced in Figure 3 An enlarged view 360 of the measurement mark 350 depicted in FIG.

[0071] Also shown are graphs 610 and 630, which depict examples of CD variation 620 and OVL variation 640 due to such etch-induced process effects. In this example, the CD and OVL variations depict that the CD (e.g., the width of the line features in the metrology mark 350) and OVL are fairly constant across the lines, except for the outer two lines which have substantial variation. As described above, this variation may be due to differences in etch rates.

[0072] Figure 7A process of optimizing metrology marks according to an embodiment of the present disclosure is illustrated. Figure 7 The depicted method can reduce variations due to the physical etching process described herein. At 710, the method can include simulating the etching process based on one or more of pattern density, intra-mark variations due to microloading effects, or sensitivity of intra-mark variations to etching chemistry. Pattern density is as described above, and again refers to local feature density (e.g., density of features) that may affect the etching rate (such as due to localized consumption of etchant). Figure 3 and Figure 4 “Intra-mark variation due to microload effects” refers to the variation across measured marks due to microloads (e.g. Figure 4 In various embodiments, the intra-mark variation caused by micro-loading effects may include the CD or sidewall angle or floor tilt of the metrology mark being larger or smaller than the ideal metrology mark. Figure 5 An example of such variation is depicted in FIG. 5 by showing the sidewall angle 540. The intra-mark variation due to microloading effects can be based at least on pattern density. This can be understood based on measuring features of the mark having different proximity to areas of lower / higher pattern density, which have been explained herein to affect the etch rate due to, for example, differential depletion of the etchant. "Sensitivity of intra-mark variation to etching chemistry" refers to the variation in etch rate based on the chemical composition and / or relative concentration of the etchant, which may dominate the etch rate as a function of CD (e.g., Figure 5 ), and is further described below with respect to simulations of the effects of improved micro-loading.

[0073] At 720, the method can include predicting the effects of etch-induced processes on metrology marks based on a simulation of the etch process. As described herein, the predictions can be generated by computationally simulating physical and chemical processes that affect etch rates.

[0074] At 730, the method may include optimizing the metrology mark based on the predicted etch-induced process impact. Optimizing the metrology mark may include multiple iterative processes, where different designs and / or locations of the metrology mark may be simulated for a given etch process. The performance of the metrology mark may be evaluated when varying the metrology mark, etch chemistry, etch process, or any other aspect of the lithography process to select / place the optimal metrology mark.

[0075] In some embodiments, the etch rate in the simulation can be based at least in part on a function of CD, where the coefficients in the function depend on the etching chemistry. For example, a model for simulating the effects of microloading can be written as:

[0076] Equation 2

[0077] in, J q is the flux of the etchant species q that can be calculated using multi-scale gradient convolution, G is the Gaussian kernel, λ is the mean free path, and L is the etching load and depends on the perimeter map r and the CD-related etching rate E. The function E can be expressed as an exponential term with coefficients, where the function partially determines the etching load of the etching process. In particular, E can be expressed as:

[0078] Equation 3

[0079] Where E0 is the target etch rate, and coefficients a and b may depend on the etch chemistry and may be determined empirically, for example, by measuring variations in CD and / or etch rate given various metrology marks, local conditions, etch chemistry, etc. Determining the sensitivity of intra-mark variations to etch chemistry may include determining the etch rate based on determining whether the etch mechanism is forward hysteresis or reverse hysteresis by the etch chemistry (which may be reflected in Equation 3 above).

[0080] Figure 8 The process of optimizing measurement mark placement according to an embodiment of the present disclosure is illustrated. Some embodiments for optimizing measurement marks may include optimizing measurement mark placement based on an intra-die overlap fingerprint (identification feature) generated by a simulation of an etching process at a first length scale. The intra-die overlap fingerprint refers to the characteristic variation between the determined overlaps within the die. For example, in an ideal case, the overlap between different levels of the printed die will be zero. However, in practice there may be some overlaps, and these overlaps can be determined based on measuring the measurement marks. In the case where the measurement marks change due to the etching process, this may affect the accurate determination of the overlap. Examples of the first length scale that can be used include length scales between 0.1um and 10um, such as 1um, 2um, or 5um. Using such a relatively large length scale can facilitate rapid simulation when determining measurement marks to prevent and determine the final overlap.

[0081] exist Figure 8In the illustrated embodiment, an example process may include, 810, obtaining a metrology mark design and metrology mark placement in a die. Such an initial design and placement may be based on a library of preset positions of different metrology mark designs and metrology mark placements. 820, the process may include inputting the metrology mark design into a simulation at a first length scale. 830, the process may include extracting critical regions in the die based on an intra-die overlap fingerprint determined by the simulation. For example, locations in the die that are suboptimal or prohibited for placing metrology marks based on the intra-die overlap fingerprint. These locations may be "critical locations" and may be excluded by the optimization process when optimizing the metrology mark design and / or placement. 840, the process may include optimizing the metrology mark placement while avoiding critical regions to minimize the intra-die overlap fingerprint. For example, the intra-die overlap fingerprint may be parameterized by a deviation from an optimal cumulative overlap. Then, simulations of the resulting metrology marks of different designs and / or placements may cover a parameter space, where an optimal metrology mark placement may be considered to minimize such a deviation (or fingerprint).

[0082] Fig. 9 The process of optimizing the metrology mark design according to an embodiment of the present disclosure is illustrated. Some embodiments for optimizing the metrology mark design are based on overlapping fingerprints within the mark generated by simulating the etching process at a second length scale. Examples of second length scales that can be used include length scales between 0.1nm and 10nm, such as 1nm, 2nm, or 5nm. Using such relatively small length scales can facilitate accurate simulations while taking into account local pattern density, which can be nanometer or even sub-nanometer length scales. Fig. 9 A process that can be used to perform this optimization on the metrology marker design is described. Fig. 9 The detailed procedures shown do not necessarily need to be Figure 8 Thus, various embodiments of the present disclosure may generally include optimizing measurement mark placement at a first length scale, and optimizing measurement mark design at a second length scale, wherein optionally, either optimization may be performed by Figure 8 and Fig. 9 The detailed process is enhanced.

[0083] For example, Fig. 9 The detailed process depicted in the may include, 910, obtaining a metrology mark design and a metrology mark placement in a die. 920, the process may include inputting the metrology mark design into a simulation at a second length scale. 930, the process may include extracting an intra-mark overlap fingerprint from the simulation at the second length scale. 940, the process may include optimizing the metrology mark design to reduce the intra-mark overlap fingerprint.

[0084] In some embodiments, multiscale convolution is performed based on different physics at various scales. In some embodiments, a superposition of different physics at multiple length scales is used, where each length scale corresponds to a different physical effect or physical aspect. The different physical effects in the multiscale convolution can include pattern-perimeter-density-induced (1) micro-loading effects due to etchant flux variations, which lead to process asymmetry; (2) electrical effects due to surface charging and thus plasma sheath variations, which lead to etching non-uniformity caused by ion tilt; (3) stress effects, which may lead to mark deformation, etching non-uniformity, overlap problems; and / or (4) other physical effects, which may lead to undesirable effects, such as etching non-uniformity, poor overlap.

[0085] Various aspects of metrology mark design and placement can be included in the simulation. For example, in some embodiments, the metrology mark design can be based on one or more of CD, pitch, segment, or surrounding fill structure. The simulation can also be based on stackup information for inputting the metrology mark design, which stackup information includes the layers in the die. The inputting the metrology mark design can also include determining the etching mechanism, where the simulation can be based on whether the etching mechanism is forward hysteresis or reverse hysteresis.

[0086] Similarly, optimizing the metrology mark placement may include optimizing one or more of the CD, pitch, design, and segment of the metrology mark. In addition, optimizing the metrology mark placement may also include optimizing the surrounding fill pattern to reduce the variation within the mark. Optimizing the surrounding fill pattern combines the etching simulation with the simulation of the lithography process itself (e.g., mask / resist simulation, aerial image simulation, etc.).

[0087] Fig.10 is a schematic diagram illustrating metrology marks with variations in CD, bottom side slope, and sidewall angle according to an embodiment of the present disclosure. Fig.10 An example of a metrology mark 1010 is depicted with adjacent high density regions 1020 and low density regions 1030. The simulations described herein incorporate physical effects, such as due to etching chemistry, that may cause the geometry of the metrology mark (e.g., bottom side tilt, sidewall angle, etc.) to deviate from ideal. Fig.10An example of a metrology mark 1010 having an area where such asymmetry may occur is depicted. An asymmetric bottom side tilt region 1040 may be an area of ​​the metrology mark 1010 that has a variation in bottom side tilt (i.e., a deviation from an etched feature having a flat bottom surface that may be ideal or expected by the etching process). Variations in bottom side tilt can affect metrology measurements, and optical wafer alignment metrology can be used for overlay control. This can include accurately measuring the geometric center or point of interest (POI) of a grating structure. However, when the alignment mark based on the grating structure has a bottom side tilt, post-etch, the measurement of the geometric center may deviate from the POI. The bottom side tilt region 1040 can be represented by a bottom side tilt map, which can be a contour map (capturing height / depth in the mark), discrete data points for height / depth, surface normal vectors, etc.

[0088] Similarly, the metrology mark 1010 can have an asymmetric sidewall slope region 1050 where there may be variations in the sidewall angle that may affect the CD measurement. The sidewall angle can be parameterized as a sidewall angle vector. The sidewall angle vector can be implemented as a sidewall angle map showing vectors representing the normals of the various sidewalls. The features present in the metrology mark 1010 can be modeled with a 3D geometry engine to provide a complete representation of the metrology mark. Fig.10 An example of a feature is also shown in , where graph 1060 depicts a perspective view looking down at the feature and shows that there is a bottom side slope 1062, which causes the bottom side of the feature to have a peaking. Graph 1070 shows an inversion of the feature shown in graph 1060, depicting a feature having a sidewall angle 1072 and an example of a sidewall angle vector 1072.

[0089] Fig.11 is a diagram illustrating a process of optimizing a measurement mark design according to an embodiment of the present disclosure. Fig.10 As depicted, modeling of simulated metrology markers may be accomplished through various processes disclosed herein. Fig.11 An example process is depicted in and may include, 1110 inputting an ideal metrology mark. An ideal metrology mark may include a metrology mark that may be designed to have an accurate shape, vertical sidewalls, a flat bottom side, etc. Such an ideal metrology mark may be represented by a GDS data file and stored in a library or database of metrology marks, or other similar data storage methods. In another embodiment, the input may be a post-development geometry of the metrology mark.

[0090] At 1120, the process may include determining a bottom side slope map, a side wall angle map, a CD map, and an etch depth map based on the predicted etch-induced process effects for each ideal metrology mark. Determination of these maps may include simulations as described herein that take into account microloading effects, local pattern density, etc.

[0091] At 1130 , the process can include generating a three-dimensional representation of a post-etch mark geometry based on the bottom side tilt map, the side wall angle map, the CD map, and the etch depth map.

[0092] At 1140, the process may include determining a combination of ideal metrology marks that will improve performance of a die using the combination, the performance determined based at least on the three-dimensional representation. Such a combination may be robust to etch process variations and may therefore improve performance of the die.

[0093] Some embodiments of improving the performance of a die using this method may include reducing alignment position deviations. The performance may be determined using a finite difference time domain optical solver that can perform a three-dimensional representation and quantify changes in simulated etch features. By determining the performance of a metrology mark, the metrology mark may be optimized or selected to provide improvements in the ability of such metrology marks to facilitate analysis of printed dies.

[0094] Fig.12 is a block diagram of an exemplary computer system CS according to an embodiment of the present disclosure.

[0095] The computer system CS includes a bus BS or other communication mechanism for communicating information, and a processor PRO (or multiple processors) coupled to the bus BS for processing information. The computer system CS also includes a main memory MM coupled to the bus BS for storing instructions and information to be executed by the processor PRO, such as a random access memory (RAM) or other dynamic storage device. The main memory MM can also be used to store temporary variables or other intermediate information during the execution of the instructions to be executed by the processor PRO. The computer system CS also includes a read-only memory (ROM) ROM or other static storage device coupled to the bus BS for storing static information and instructions for the processor PRO. A storage device SD such as a magnetic disk or optical disk is provided and coupled to the bus BS for storing information and instructions.

[0096] The computer system CS can be coupled to a display DS for displaying information to a computer user via a bus BS, such as a cathode ray tube (CRT) or a flat panel display or a touch panel display. An input device ID including alphanumeric keys and other keys is coupled to the bus BS for communicating information and command selections to the processor PRO. Another type of user input device is a cursor control CC, such as a mouse, trackball or cursor direction keys, for communicating direction information and command selections to the processor PRO and for controlling cursor movement on the display DS. This input device typically has two degrees of freedom on two axes, namely a first axis (e.g., x) and a second axis (e.g., y), which allows the device to specify a position in a plane. A touch panel (screen) display can also be used as an input device.

[0097] According to one embodiment, the computer system CS can be executed in response to the processor PRO executing one or more sequences of one or more instructions contained in the main memory MM and the part of one or more methods as described in this article. These instructions can be read into the main memory MM from another computer-readable medium such as a storage device SD. The execution of the instruction sequence contained in the main memory MM causes the processor PRO to execute the process steps described herein. One or more processors in a multi-processing arrangement can also be adopted to execute the instruction sequence contained in the main memory MM. In an alternative embodiment, a hard-wired circuit system can be used instead of or in combination with software instructions. Therefore, the description herein is not limited to any specific combination of hardware circuits and software.

[0098] As used herein, the term "computer-readable medium" refers to any medium that participates in providing instructions to the processor PRO for execution. This medium can take many forms, including but not limited to non-volatile media, volatile media and transmission media. Non-volatile media include, for example, optical disks or disks, such as storage devices SD. Volatile media include dynamic memory, such as main memory MM. Transmission media include coaxial cables, copper wires and optical fibers, including wires containing bus BS. Transmission media can also take the form of sound waves or light waves, such as sound waves or light waves generated during radio frequency (RF) and infrared (IR) data communication. Computer-readable media can be non-temporary, such as floppy disks, floppy disks, hard disks, magnetic tapes, any other magnetic media, CD-ROMs, DVDs, any other optical media, punch cards, paper tapes, any other physical media with hole patterns, RAMs, PROMs and EPROMs, FLASH-EPROMs, any other memory chips or cassettes. Non-temporary computer-readable media can record instructions thereon. When instructions are executed by a computer, the instructions can implement any feature described herein. Transitory computer readable media may include carrier waves or other propagated electromagnetic signals.

[0099] Various forms of computer-readable media may be involved in carrying one or more sequences of one or more instructions to the processor PRO for execution. For example, the instructions may be initially carried on a disk of a remote computer. The remote computer may load the instructions into its dynamic memory and send the instructions via a telephone line using a modem. The modem local to the computer system CS may receive data on the telephone line and convert the data into an infrared signal using an infrared transmitter. An infrared detector coupled to the bus BS may receive the data carried in the infrared signal and place the data on the bus BS. The bus BS carries the data to the main memory MM, from which the processor PRO retrieves and executes the instructions. The instructions received by the main memory MM may optionally be stored on a storage device SD before or after being executed by the processor PRO.

[0100] The computer system CS may also include a communication interface CI coupled to the bus BS. The communication interface CI provides a bidirectional data communication coupling with a network link NDL connected to a local area network LAN. For example, the communication interface CI may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a telephone line of a corresponding type. As another example, the communication interface CI may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. A wireless link may also be implemented. In any such implementation, the communication interface CI sends and receives electrical, electromagnetic or optical signals carrying digital data streams representing various types of information.

[0101] The network link NDL typically provides data communication to other data devices through one or more networks. For example, the network link NDL can provide a connection to the host computer HC through a local area network LAN. This can include data communication services provided through the global packet data communication network (now generally referred to as the "Internet" INT). The local area network LAN (Internet) all use electrical signals, electromagnetic signals or optical signals that carry digital data streams. The signals passing through the various networks and the signals on the network data link NDL and passing through the communication interface CI (the signals carry digital data to and from the computer system CS) are example forms of carrier waves that transport information.

[0102] The computer system CS can send messages and receive data including process codes via the network, the network data link NDL and the communication interface CI. In the Internet example, the host computer HC can transmit the requested code for the application program via the Internet INT, the network data link NDL, the local area network LAN and the communication interface CI. For example, such a download application program can provide all or part of the method described herein. The received code can be executed by the processor PRO when received, and / or stored in the storage device SD, or other non-volatile storage device for later execution. In this way, the computer system CS can obtain the application code in the form of a carrier wave.

[0103] Fig.13 is a schematic diagram of a lithography projection apparatus according to an embodiment of the present disclosure.

[0104] The lithographic projection apparatus may include an illumination system IL, a first stage MT, a second stage WT and a projection system PS.

[0105] The illumination system IL may condition the radiation beam B. In this particular case, the illumination system also comprises a radiation source SO.

[0106] A first stage (eg patterning device table) MT may be provided with a patterning device holder to hold a patterning device MA (eg reticle) and connected to a first positioner to accurately position the patterning device relative to the item PS.

[0107] A second stage (eg substrate table) WT may be provided with a substrate holder to hold a substrate W (eg a resist coated silicon wafer) and connected to a second positioner to accurately position the substrate relative to item PS.

[0108] A projection system ("lens") PS (eg, a refractive, reflective, or catadioptric optical system) may image the illuminated portion of the patterning device MA onto a target portion C of the substrate W (eg, comprising one or more dies).

[0109] As described herein, the apparatus may be transmissive (i.e., having a transmissive patterning device). However, in general, it may also be reflective, for example (having a reflective patterning device). The apparatus may employ different kinds of patterning devices for typical masks; examples include programmable mirror arrays or LCD matrices.

[0110] A source SO (e.g. a mercury lamp or an excimer laser, an LPP (laser produced plasma) EUV source) generates a radiation beam. This beam is supplied to an illumination system (illuminator) IL, for example directly or after traversing a conditioning device (such as a beam expander Ex). The illuminator IL may comprise an adjustment device AD ​​for setting the outer and / or inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in the beam. In addition, the adjustment device AD ​​typically comprises various other components, such as an integrator IN and a condenser CO. In this way, the beam B impinging on the patterning device MA has a desired uniformity and intensity distribution in its cross section.

[0111] In some embodiments, the source SO may be within the housing of the lithography projection device (for example, this is usually the case when the source SO is a mercury lamp), but the source SO may also be remote from the lithography projection device and the radiation beam generated by the source SO may be guided into the device (for example, with the aid of suitable guide mirrors); the latter may be the case when the source SO is an excimer laser (for example, based on KrF, ArF or F2 lasers).

[0112] The beam PB may then impinge on the patterning device MA which is held on the patterning device table MT. Having traversed the patterning device MA, the beam B may pass through a lens PL which focuses the beam B onto a target portion C of the substrate W. With the aid of the second positioning device (and the interferometric measurement device IF), the substrate table WT may be accurately moved, for example so as to position a different target portion C in the path of the beam PB. Similarly, the first positioning device may be used to accurately position the patterning device MA relative to the path of the beam B, for example after mechanically acquiring the patterning device MA from a patterning device library, or during a scan. Typically, movement of the stage MT, WT may be achieved with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning). However, in the case of a stepper (as opposed to a step-and-scan tool), the patterning device table MT may be connected to the short-stroke actuator only, or may be fixed.

[0113] The depicted tool can be used in two different modes, a step mode and a scan mode. In the step mode, the patterning device table MT remains essentially stationary and the entire patterning device image is projected once (i.e. a single "flash") onto a target portion C. The substrate table WT can be moved in the x and / or y direction so that the beam PB can irradiate a different target portion C.

[0114] In scan mode, essentially the same scenario applies, except that a given target portion C is not exposed in a single "flash". Instead, the patterning device table MT can be moved in a given direction (the so-called "scanning direction", e.g. the y-direction) at a speed v, so that the projection beam B is scanned over the patterning device image; simultaneously, the substrate table WT is simultaneously moved in the same or opposite direction at a speed V=Mv, where M is the magnification of the lens PL (typically M=1 / 4 or 1 / 5). In this way, a relatively large target portion C can be exposed without having to sacrifice resolution.

[0115] Fig.14 is a schematic diagram of another lithographic projection apparatus (LPA) according to an embodiment of the present disclosure.

[0116] The LPA may comprise a source collector module SO, an illumination system (illuminator) IL configured to condition a radiation beam B (eg EUV radiation), a support structure MT, a substrate table WT and a projection system PS.

[0117] The support structure (e.g., patterning device table) MT may be configured to support a patterning device (e.g., mask or reticle) MA and connected to a first positioner PM configured to accurately position the patterning device;

[0118] The substrate table (eg, wafer stage) WT may be configured to hold a substrate (eg, a resist-coated wafer) W and connected to a second positioner PW configured to accurately position the substrate.

[0119] The projection system (eg, a reflective projection system) PS may be configured to project the pattern imparted to the radiation beam B by the patterning device MA onto a target portion C of the substrate W (eg, comprising one or more dies).

[0120] As described herein, the LPA can be reflective (e.g., using a reflective patterning device). It should be noted that because most materials are absorptive in the EUV wavelength range, the patterning device can have a multilayer reflector, which includes, for example, multi-stacked molybdenum and silicon. In one example, the multi-stacked reflector has 40 layers of molybdenum and silicon pairs, where the thickness of each layer is one quarter wavelength. Even smaller wavelengths can be produced using x-ray lithography. Since most materials are absorptive at EUV and x-ray wavelengths, the patterned thin block of absorbing material on the patterning device topography (e.g., a TaN absorber on top of a multilayer reflector) defines whether the feature will be printed (positive resist) or not (negative resist).

[0121] The illuminator IL may receive an extreme ultraviolet radiation beam from a source collector module SO. Methods of generating EUV radiation include, but are not necessarily limited to, converting a material into a plasma state having at least one element (e.g., xenon, lithium, or tin) using one or more emission lines in the EUV range. In one such method, commonly referred to as laser produced plasma ("LPP"), a plasma may be generated by irradiating a fuel (such as a droplet, stream, or cluster of a material having a line-emitting element) with a laser beam. The source collector module SO may be part of an EUV radiation system that includes a laser for providing a laser beam that excites the fuel. The resulting plasma emits output radiation (e.g., EUV radiation) that is collected using a radiation collector disposed in the source collector module. The laser and the source collector module may be separate entities, such as when a CO2 laser is used to provide a laser beam for fuel excitation.

[0122] In this case, the laser is not considered to form part of the lithographic apparatus, and the radiation beam may be delivered from the laser to the source collector module by means of a beam delivery system including, for example, suitable directing mirrors and / or a beam expander. In other cases, for example, when the source is a discharge produced plasma EUV generator (commonly referred to as a DPP source), the source may be an integral part of the source collector module.

[0123] The illuminator IL may include an adjuster for adjusting the angular intensity distribution of the radiation beam. Typically, at least the outer radial extent and / or the inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in a pupil plane of the illuminator may be adjusted. In addition, the illuminator IL may include various other components, such as a facet field and a pupil mirror arrangement. The illuminator may be used to adjust the radiation beam to have a desired uniformity and intensity distribution in its cross-section.

[0124] The radiation beam B may be incident on a patterning device (e.g., a mask) MA held on a support structure (e.g., a patterning device table) MT and patterned by the patterning device. After being reflected from the patterning device (e.g., a mask) MA, the radiation beam B passes through a projection system PS, which focuses the beam onto a target portion C of the substrate W. With the aid of a second positioner PW and a position sensor PS2 (e.g., an interferometric measurement device, a linear encoder, or a capacitive sensor), the substrate table WT may be accurately moved (e.g., so as to position a different target portion C in the path of the radiation beam B). Similarly, a first positioner PM and a further position sensor PS1 may be used to accurately position the patterning device (e.g., a mask) MA relative to the path of the radiation beam B. The patterning device (e.g., a mask) MA and the substrate W may be aligned using patterning device alignment marks M1, M2 and substrate alignment marks P1, P2.

[0125] The depicted device LPA can be used in at least one of the following modes: a stepping mode, a scanning mode and a stationary mode.

[0126] In step mode, the support structure (e.g. patterning device table) MT and the substrate table WT are kept substantially stationary (i.e. a single static exposure) while the entire pattern imparted to the radiation beam is projected at one time onto a target portion C. The substrate table WT is then shifted in the X-direction and / or Y-direction so that a different target portion C can be exposed.

[0127] In scan mode, the support structure (e.g. patterning device table) MT and substrate table WT are scanned synchronously (i.e. single dynamic exposure) as a pattern imparted to the radiation beam is projected onto a target portion C. The velocity and direction of the substrate table WT relative to the support structure (e.g. patterning device table) MT may be determined by the (de-)magnification and image reversal characteristics of the projection system PS.

[0128] In stationary mode, the support structure (e.g. patterning device table) MT is held substantially stationary, thereby holding the programmable patterning device, and the substrate table WT is moved or scanned, while a pattern imparted to the radiation beam is projected onto a target portion C. In this mode, a pulsed radiation source is typically employed, and the programmable patterning device is updated as required after each movement of the substrate table WT or between successive radiation pulses during a scan. This mode of operation may be readily applicable to maskless lithography using a programmable patterning device, such as a programmable mirror array.

[0129] Fig.15 is a detailed view of a lithographic projection apparatus according to an embodiment of the present disclosure.

[0130] As shown, the LPA may include a source collector model SO, an illumination system IL, and a projection system PS. The source collector model SO is constructed and arranged so that a vacuum environment can be maintained in the closed structure ES of the source collector model SO. A plasma source may be generated by a discharge to form a hot plasma HP emitting EUV radiation. EUV radiation may be generated by a gas or vapor (e.g., Xe gas, Li vapor, or Sn vapor), wherein a hot plasma HP is generated to emit radiation in the EUV range of the electromagnetic spectrum. The hot plasma HP may be generated, for example, by a discharge causing at least partially ionized plasma. For example, a partial pressure of 10Pa of Xe, Li, Sn vapor, or any other suitable gas or vapor may be required to effectively generate radiation. In some embodiments, an excited tin (Sn) plasma is provided to generate EUV radiation.

[0131] The radiation emitted by the hot plasma HP enters the collector chamber CC from the source chamber SC via an optional gas barrier or contaminant trap CT (also referred to as a contaminant barrier or fin trap in some cases), which is positioned in or behind the opening of the source chamber SC. The contaminant trap CT may include a channel structure. The contaminant trap CT may also include a gas barrier or a combination of a gas barrier and a channel structure. The contaminant trap or contaminant barrier CT is also indicated herein as including at least a channel structure as known in the art.

[0132] The collector chamber CC may include a radiation collector CO, which may be a so-called grazing incidence collector. The radiation collector CO has an upstream radiation collector side US and a downstream radiation collector side DS. Radiation passing through the radiation collector CO may be reflected by a grating spectral filter SF and thereby focused at a virtual source point IF along the optical axis indicated by the dash-dot line "O". The virtual source point IF may be referred to as an intermediate focus, and the source collector module may be arranged such that the intermediate focus IF is located at or near an opening OP in the enclosed structure ES. The virtual source point IF is an image of the radiation emitting plasma HP.

[0133] The radiation then passes through an illumination system IL which may include a faceted field mirror arrangement FM and a faceted pupil mirror arrangement PM which are arranged to provide a desired angular distribution of the radiation beam B at the patterning device MA and a desired uniformity of radiation amplitude at the patterning device MA. When the radiation beam B is reflected at the patterning device MA (held by the support structure MT), a patterned beam PB is formed and is imaged by the projection system PS via a reflective element RE onto a substrate W held by a substrate table WT.

[0134] In general, more elements than shown may be present in the illumination optics unit IL and the projection system PS. For example, a grating spectral filter SF may optionally be present depending on the type of lithographic apparatus. Furthermore, more mirrors may be present than shown in the figures, for example 1-6 additional reflective elements may be present in the projection system PS.

[0135] The collector optics CO may be a nested collector with a grazing incidence reflector GR, which is only an example of a collector (or collector reflector). The grazing incidence reflector GR is arranged axially symmetrical around the optical axis O, and this type of collector optics CO may be used in conjunction with a discharge produced plasma source (commonly referred to as a DPP source).

[0136] Fig.16 is a detailed view of a source collector module SO of a lithographic projection apparatus LPA according to an embodiment of the present disclosure.

[0137] The source collector module SO may be part of an LPA radiation system. The laser LA may be arranged to deposit laser energy into a fuel such as xenon (Xe), tin (Sn) or lithium (Li), thereby producing a highly ionized plasma HP with an electron temperature of several 10 eV. The high energy radiation produced during the deexcitation and recombination of these ions is emitted from the plasma, collected by the near normal incidence collector optics CO, and focused onto an opening OP in the enclosed structure ES.

[0138] The concepts disclosed herein can simulate or mathematically model any general imaging system for imaging sub-wavelength features, and may be particularly useful for emerging imaging technologies that can produce shorter and shorter wavelengths. Emerging technologies that have been used include EUV (extreme ultraviolet), DUV lithography that can produce 193nm wavelengths using ArF lasers, and even 157nm wavelengths using fluorine lasers. In addition, EUV lithography can produce wavelengths in the range of 20nm-50nm using synchrotrons or by bombarding materials (solid or plasma) with high-energy electrons to produce photons in this range.

[0139] The embodiments of the present disclosure can be further described by the following clauses.

[0140] 1. A method for optimizing measurement marking, the method comprising:

[0141] simulating an etching process based on one or more of pattern density, intra-mark variations due to microloading effects, or sensitivity of intra-mark variations to etching chemistry;

[0142] predicting the effect of an etch-induced process on the metrology mark based on a simulation of the etch process; and

[0143] The metrology signatures are optimized based on the predicted etch-induced process impacts.

[0144] 2. The method of clause 1, wherein the etch rate in the simulation is based at least in part on a function of CD, wherein coefficients in the function depend on the etch chemistry.

[0145] 3. The method of clause 2, wherein the function is an exponential term with the coefficients, the function partially determining an etch load of the etching process.

[0146] 4. The method of clause 1, wherein the intra-mark variation caused by the micro-loading effect comprises that the CD or the sidewall angle or the bottom side tilt of the measured mark is greater or less than that of the ideal measured mark.

[0147] 5. A method according to item 4, wherein the intra-mark variation caused by the micro-loading effect is based on the pattern density.

[0148] 6. The method of clause 1, wherein determining a sensitivity of the variation within the mark to an etch chemistry comprises determining an etch rate based on determining whether an etching mechanism is forward hysteresis or reverse hysteresis by the etch chemistry.

[0149] 7. The method of clause 1, wherein optimizing the metrology marks comprises optimizing metrology mark placement based on an in-die overlay fingerprint generated from a simulation of the etch process at a first length scale.

[0150] 8. The method of clause 7, further comprising:

[0151] Obtaining metrology mark design and metrology mark placement in the die;

[0152] inputting the metrology mark design into the simulation at the first length scale;

[0153] extracting critical regions in a die based on the intra-die overlapping fingerprints determined by the simulation; and

[0154] The metrology mark placement is optimized while avoiding the critical area to minimize overlapping fingerprints within the die.

[0155] 9. A method according to item 8, wherein the measurement mark design is based on one or more of CD, pitch, segment or surrounding filling structure.

[0156] 10. The method of clause 8, wherein the simulating is further based on inputting stackup information of the metrology mark design, the stackup information comprising layers in the die.

[0157] 11. The method of clause 8, wherein inputting the measurement mark design further comprises:

[0158] An etching mechanism is determined, wherein the simulation is based on whether the etching mechanism is forward hysteresis or reverse hysteresis.

[0159] 12. The method of clause 7, wherein optimizing the metrology mark comprises optimizing a metrology mark design based on an in-die overlay fingerprint generated from a simulation of the etch process at a second length scale.

[0160] 13. The method of clause 12, further comprising:

[0161] Obtaining metrology mark design and metrology mark placement in the die;

[0162] inputting the metrology mark design into the simulation at the second length scale;

[0163] extracting the intra-mark overlap fingerprint from the simulation at the second length scale; and

[0164] The metrology mark design is optimized to reduce overlapping fingerprints within the mark.

[0165] 14. The method of clause 13, wherein optimizing the metrology mark placement further comprises optimizing one or more of the CD, pitch, design, and segment of the metrology marks.

[0166] 15. The method of clause 13, wherein optimizing the measurement mark placement further comprises optimizing a surrounding fill pattern to reduce intra-mark variation.

[0167] 16. The method of clause 1, further comprising:

[0168] Enter the ideal measurement mark;

[0169] determining a bottom side tilt map, a side wall angle map, a CD map, and an etch depth map based on predicting the effect of the etch-induced process for each of the ideal metrology marks;

[0170] generating a three-dimensional representation of a post-etch mark geometry based on the bottom side slope map, the side wall angle map, the CD map, and the etch depth map; and

[0171] A combination of the ideal metrology marks is determined, the combination improving a performance of a die using the combination, the performance being determined based at least on the three-dimensional representation.

[0172] 17. A method according to item 16, wherein improving the performance includes reducing alignment position deviation.

[0173] 18. A method according to clause 16, wherein the performance is determined using a finite-difference time-domain optical solver.

[0174] 19. A method according to clause 1, wherein the simulation includes performing multi-scale convolution based on different physical effects at various length scales.

[0175] 20. A method according to item 19, wherein the multi-scale convolution comprises the superposition of physical effects at multiple length scales.

[0176] 21. A method according to item 20, wherein the different physical influences include (1) microloading effects due to etchant flux variations, which lead to process asymmetry; (2) electrical effects due to surface charging and thus plasma sheath variations, which lead to etching non-uniformity caused by ion tilt; and / or (3) stress effects, which can lead to mark deformation, etching non-uniformity, and overlap problems.

[0177] 22. A non-transitory computer-readable medium having recorded thereon instructions for optimizing measurement marks, the instructions, when executed by one or more processors, causing the one or more processors to perform the method according to any one of clauses 1-21.

[0178] 23. A system for optimizing measurement marking, the system comprising:

[0179] at least one programmable processor; and

[0180] A non-transitory computer-readable medium having recorded thereon instructions for optimizing measurement marks, the instructions, when executed by one or more processors, causing the one or more processors to perform a method according to any one of clauses 1-21.

[0181] Although the concepts disclosed herein may be used for imaging on substrates such as silicon wafers, it should be understood that the disclosed concepts may be used in any type of lithography imaging system (eg, a lithography imaging system for imaging on substrates other than silicon wafers).

[0182] The combination and sub-combination of the elements disclosed herein constitute separate embodiments and are provided as examples only. In addition, the above description is intended to be illustrative rather than restrictive. Therefore, it will be apparent to those skilled in the art that the invention described can be modified without departing from the scope of the claims set forth below.

Claims

1. A non-transitory computer-readable medium having instructions recorded thereon, which, when executed by one or more processors, cause the one or more processors to perform a method for optimizing a metrology signature, the method comprising: simulating an etching process based on one or more of pattern density, intra-mark variations due to microloading effects, or sensitivity of intra-mark variations to etching chemistry; predicting an effect of an etching-induced process on the metrology mark based on a simulation of the etching process; as well as The metrology signatures are optimized based on the predicted etch-induced process impacts.

2. The medium of claim 1, wherein the etch rate in the simulation is based at least in part on a function of CD, wherein coefficients in the function depend on the etch chemistry.

3. The medium of claim 1, wherein the intra-mark changes caused by the micro-loading effect include: The CD or side wall angle or bottom side inclination of the measurement mark is greater or less than the ideal measurement mark.

4. The medium of claim 1, wherein the intra-mark variation caused by the micro-loading effect is determined based on the pattern density.

5. The medium of claim 1 , wherein determining the sensitivity of the variation within the mark to an etching chemistry comprises: The etch rate is determined based on whether the etching mechanism is forward hysteresis or reverse hysteresis determined by the etch chemistry.

6. The medium of claim 1, wherein optimizing the metrology signature comprises: Metrology mark placement is optimized based on an in-die overlay fingerprint generated from a simulation of the etching process at a first length scale.

7. The medium of claim 6, further comprising: Obtaining metrology mark design and metrology mark placement in the die; inputting the metrology mark design into the simulation at the first length scale; extracting critical regions in a die based on the intra-die overlapping fingerprints determined by the simulation; and The metrology mark placement is optimized while avoiding the critical area to minimize overlapping fingerprints within the die.

8. The medium of claim 7, wherein the metrology mark design is based on one or more of CD, pitch, segment, or surrounding fill structure, and wherein the simulation is also based on stackup information input into the metrology mark design, the stackup information comprising layers in the die, and wherein inputting the metrology mark design further comprises determining an etching mechanism, wherein the simulation is based on whether the etching mechanism is forward hysteresis or reverse hysteresis.

9. The medium of claim 7, wherein optimizing the metrology signature comprises: The metrology mark design is optimized based on an in-die overlapping fingerprint generated from a simulation of the etching process at a second length scale.

10. The medium of claim 9, further comprising: Obtaining the metrology mark design and the metrology mark placement in the die; inputting the metrology mark design into the simulation at the second length scale; extracting the intra-mark overlap fingerprint from the simulation at the second length scale; and Optimizing the measurement mark design to reduce overlapping fingerprints within the mark, Optimizing the placement of the measurement marks also includes optimizing one or more of the CD, pitch, design, and segment of the measurement marks.

11. The medium of claim 1 , further comprising: Enter the ideal measurement mark; determining a bottom side tilt map, a side wall angle map, a CD map, and an etch depth map based on predicting the effect of the etch-induced process for each of the ideal metrology marks; generating a three-dimensional representation of a post-etch mark geometry based on the bottom side tilt map, the side wall angle map, the CD map, and the etch depth map; as well as A combination of the ideal metrology marks is determined, the combination improving a performance of a die using the combination, the performance being determined based at least on the three-dimensional representation.

12. The medium of claim 11, wherein improving the performance comprises reducing alignment position deviation, and wherein the performance is determined using a finite-difference time-domain optical solver.

13. The medium of claim 1, wherein the simulation comprises performing multi-scale convolution based on different physical effects at multiple length scales.

14. The medium of claim 13, wherein the multi-scale convolution comprises a superposition of physical effects at multiple length scales.

15. The medium of claim 14, wherein the different physical effects include (1) microloading effects due to etchant flux variations, which lead to process asymmetry; (2) electrical effects due to surface charging and thus plasma sheath variations, which lead to etching non-uniformities caused by ion tilt; and / or (3) stress effects, which can lead to mark deformation, etching non-uniformities, and overlap problems.

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