Pixel structure, array infrared detector and manufacturing method

Abstract

The invention provides a pixel structure, an array infrared detector and a manufacturing method, the pixel structure comprises a substrate, a cavity, a main release groove, a first auxiliary release groove, a second auxiliary release groove and a temperature difference thermopile, the cavity is embedded in the substrate, the part, suspended above the cavity, of the substrate forms a suspension layer, and the first auxiliary release groove and the second auxiliary release groove are embedded in the suspension layer. The suspension layer comprises a cantilever beam and an infrared absorption film, the main release groove is located on the two sides of the cantilever beam, the first auxiliary release groove is located in the cantilever beam, the second auxiliary release groove is located in the infrared absorption film, and the temperature difference thermopile is located on the substrate and comprises a plurality of thermocouple pairs extending from the supporting frame to the infrared absorption film through the cantilever beam. In the pixel structure, the first auxiliary release groove and the second auxiliary release groove can reduce heat loss and improve the response rate of a device. The array infrared detector adopting the pixel structure is compatible with a CMOS (complementary metal oxide semiconductor) process, can meet the multi-scene multifunctional intelligent application requirement, is favorable for reducing the device size, reduces the production cost, and realizes batch production.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology and relates to a pixel structure, an array infrared detector and a manufacturing method. Background Art

[0002] A sensor is a device that can convert physical or chemical quantities into electrical signals that are easy to use. Micro-Electro-Mechanical System (MEMS) technology is a bridge between the macroscopic world and the microscopic world. MEMS sensors are new sensors manufactured using microelectronics and micromachining technology. They are small in size, light in weight, low in cost, low in power consumption, and suitable for mass production. At present, the integration of MEMS sensors and signal processing circuits is the main technical trend in the development of sensor technology, making sensors more miniaturized and intelligent.

[0003] MEMS thermopiles are widely used in the field of infrared temperature measurement. Based on the Seebeck effect, when external radiation reaches the surface of the chip, the thermopile chip generates a temperature difference, thereby generating an electric potential difference to achieve the purpose of temperature measurement. Due to its advantages such as non-contact temperature measurement, wide temperature range, fast sensitivity, and small size, it is widely used in smart home appliances, automotive control, medical systems, industrial control, etc., such as precise temperature measurement and intelligent control of home appliances such as microwave ovens and refrigerators; product quality and status monitoring of automobile tires and internal temperature systems of automobiles; furnace temperature monitoring and system control, flame detection, electrical switch monitoring and busbar monitoring in industry; plant surface temperature measurement in automatic irrigation systems in agriculture and other application scenarios. Infrared sensors are also widely used in the military, for example, they play an important role in regional early warning, special gas detection, night vision observation, and soldier logistics support.

[0004] Thermopile detectors are no longer limited to single-point temperature measurement. Infrared thermopile arrays can achieve regional detection, and large-scale arrays can even achieve low-resolution imaging. The thermopile infrared market is moving towards small-scale arrays of thermopile pixels and compatibility with CMOS to achieve lower costs, more functions, smaller sizes, and more intelligence.

[0005] The voltage response of existing thermopile pixel structures generally cannot meet the needs of high-precision measurement. Existing MEMS infrared thermopiles have a single function and are generally only used for temperature measurement. However, the single temperature measurement function can no longer meet the needs of multi-scenario and multi-functional intelligent applications. In addition, existing thermopile detectors or array infrared detectors that are not compatible with CMOS processes are usually connected to application-specific integrated circuit (ASIC) chips through wire bonding, which has complicated processes, large sizes, and high overall costs. Existing thermopile sensors that are compatible with CMOS processes and integrated with CMOS circuits usually achieve thermal isolation by releasing the back cavity through deep back etching. Because deep back etching requires back alignment and the back etching depth is large, the overall cost is still high.

[0006] Therefore, how to optimize the layout design of the thermopile pixel structure to improve the response rate of the device and enable it to be prepared with a CMOS-MEMS integrated design, so as to meet the needs of multi-scenario and multi-functional intelligent applications, reduce device size, and reduce production costs, has become an important technical problem that technical personnel in this field need to solve urgently.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a pixel structure, an array infrared detector and a manufacturing method for solving the problems of low response rate, large device size and high manufacturing cost of the existing thermopile pixel structure.

[0009] To achieve the above-mentioned object and other related objects, the present invention provides a pixel structure, comprising:

[0010] substrate;

[0011] A cavity is embedded in the substrate, a portion of the substrate suspended above the cavity constitutes a suspension layer, a portion of the substrate located around the cavity constitutes a support frame, the suspension layer comprises a cantilever beam and an infrared absorbing film, one end of the cantilever beam is connected to the support frame, and the other end of the cantilever beam is connected to the edge of the infrared absorbing film;

[0012] Main release grooves, located on both sides of the cantilever beam and vertically penetrating the suspension layer to communicate with the cavity;

[0013] A first auxiliary release groove is located in the cantilever beam and vertically penetrates the cantilever beam to communicate with the cavity;

[0014] A second auxiliary release groove is located in the infrared absorbing film and vertically penetrates the infrared absorbing film and communicates with the cavity;

[0015] A temperature differential thermal stack is located on the substrate, and the temperature differential thermal stack includes a plurality of thermocouple pairs, the thermocouple pairs extend from the supporting frame via the cantilever beam to the infrared absorbing film, the hot ends of the thermocouple pairs are located above the infrared absorbing film, and the cold ends of the thermocouple pairs are located on the supporting frame.

[0016] Optionally, in the plane where the cantilever beam is located and perpendicular to the extension direction of the cantilever beam, the cantilever beam is divided into a first edge arm area, a middle arm area and a second edge arm area by two separately arranged first auxiliary release grooves, at least one group of the thermocouple pairs passes through the first edge arm area, at least one group of the thermocouple pairs passes through the middle arm area, and at least one group of the thermocouple pairs passes through the second edge arm area.

[0017] Optionally, the infrared absorption film has a first hot zone and a plurality of second hot zones arranged at intervals, and the distance between the second hot zone and the center of the infrared absorption film is greater than the distance between the first hot zone and the center of the infrared absorption film, wherein the hot end of the thermocouple pair passing through the first edge arm zone is located in one of the second hot zones, the hot end of the thermocouple pair passing through the middle arm zone is located in the first hot zone, and the hot end of the thermocouple pair passing through the second edge arm zone is located in another of the second hot zones.

[0018] Optionally, there are two groups of thermocouple pairs passing through the middle arm area, one group of thermocouple pairs passing through the cantilever beam and then bypassing from one side of the second auxiliary release groove to the first hot zone, and the other group of thermocouple pairs passing through the cantilever beam and then bypassing from the other side of the second auxiliary release groove to the first hot zone.

[0019] Optionally, the pixel structure includes a plurality of the cantilever beams, and two adjacent cantilever beams are spaced apart by the main release groove.

[0020] Optionally, the extension direction of the first auxiliary release groove is parallel to the extension direction of the cantilever beam, and the second auxiliary release groove includes a heat blocking groove, and the extension direction of the heat blocking groove forms an intersection angle of 80°-100° with the extension direction of the first auxiliary release groove.

[0021] Optionally, the second auxiliary release groove further includes an enhanced release groove, and an extension direction of the enhanced release groove is parallel to an extension direction of the cantilever beam.

[0022] Optionally, the pixel structure further includes a heating resistor, the heating resistor is located on the infrared absorption film, and the distance between the hot end of the thermocouple pair and the center of the infrared absorption film is greater than the distance between the heating resistor and the center of the infrared absorption film.

[0023] Optionally, the pixel structure further includes a heat capacity enhancement body, which is located on the infrared absorption film, and the distance between the hot end of the thermocouple pair and the center of the infrared absorption film is greater than the distance between the heat capacity enhancement body and the center of the infrared absorption film.

[0024] Optionally, the first auxiliary release groove has at least one corner at one end facing the supporting frame, wherein any one of the corners is selected from one of an arc angle, an obtuse angle and a right angle.

[0025] Optionally, the cold end of the thermocouple pair is located outside the opening range of the cavity and is spaced a preset distance from the opening edge of the cavity, and one end of the main release groove toward the supporting frame and one end of the first auxiliary release groove toward the supporting frame are both located within the opening range of the cavity and are spaced a preset distance from the opening edge of the cavity.

[0026] Optionally, the thermocouple pair includes a first conductivity type polysilicon thermocouple bar and a second conductivity type polysilicon thermocouple bar, and multiple groups of the thermocouple pairs are connected in at least one of series and parallel, the first conductivity type is P type or N type, and the second conductivity type is opposite to the first conductivity type.

[0027] The present invention also provides an array infrared detector, comprising:

[0028] A MEMS array sensor, comprising a plurality of pixel structures as described above, wherein the plurality of pixel structures are arranged in an array and share the substrate;

[0029] A CMOS circuit is located in the substrate and at the periphery of the MEMS array sensor;

[0030] A conductive interconnection layer is located on the substrate, and the MEMS array sensor and the CMOS circuit are electrically connected via the conductive interconnection layer.

[0031] The present invention also provides a method for manufacturing an array infrared detector, the method for manufacturing the array infrared detector as described above comprises the following steps:

[0032] Providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region located outside the first region;

[0033] forming an isolation structure in the semiconductor substrate, the isolation structure starting from the top surface of the semiconductor substrate and extending downward but not penetrating the semiconductor substrate, the isolation structure comprising a first isolation body located in the first region and a second isolation body located in the second region;

[0034] Forming a first conductive type polysilicon layer on the semiconductor substrate and patterning it to obtain a first conductive type polysilicon thermocouple bar located on the first insulator and a first conductive type polysilicon gate located in the second region, forming a second conductive type polysilicon layer on the semiconductor substrate and patterning it to obtain a second conductive type polysilicon thermocouple bar located on the first insulator and a second conductive type polysilicon gate located in the second region;

[0035] Forming the conductive interconnect layer on the semiconductor substrate, wherein the conductive interconnect layer includes a dielectric layer and at least one metal wire layer embedded in the dielectric layer;

[0036] forming the main release groove, the first auxiliary release groove and the second auxiliary release groove, wherein the main release groove, the first auxiliary release groove and the second auxiliary release groove all vertically penetrate the dielectric layer and the first isolation body;

[0037] An etching solution is injected through the main release groove, the first auxiliary release groove and the second auxiliary release groove to corrode the portion of the semiconductor substrate located below the first isolation body to obtain the cavity.

[0038] As described above, the pixel structure of the present invention includes a substrate, a cavity, a main release groove, a first auxiliary release groove, a second auxiliary release groove and a temperature difference heat pile, wherein the cavity is buried in the substrate, and the portion of the substrate suspended above the cavity constitutes a suspension layer, the suspension layer includes a cantilever beam and an infrared absorption film, the main release groove is located on both sides of the cantilever beam, the first auxiliary release groove is located in the cantilever beam, the second auxiliary release groove is located in the infrared absorption film, and the temperature difference heat pile is located on the substrate and includes a plurality of groups of thermocouples extending from the support frame to the infrared absorption film via the cantilever beam. In the pixel structure of the present invention, the first auxiliary release groove can reduce the thermal conductivity of the cantilever beam, reduce heat loss, and improve the response rate of the device. The second auxiliary release groove is conducive to the formation of the cavity on the one hand, and can hinder the heat of the infrared absorption film from being transferred along the cantilever beam to the cold end on the other hand, further reducing heat loss and improving the response rate of the device. The array infrared detector using the pixel structure of the present invention is compatible with the CMOS process, can meet the requirements of multi-scenario multi-function intelligent applications, is conducive to reducing the size of the device, reducing production costs, and realizing mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1An exemplary plan layout diagram of the pixel structure of the present invention in the first embodiment is shown.

[0040] Figure 2 An exemplary plan layout diagram of the suspension layer, the supporting frame and the cavity of the pixel structure of the present invention in the first embodiment is shown.

[0041] Figure 3 Shown is a schematic diagram of the end of a relief groove without chamfering.

[0042] Figure 4 Shown is another schematic diagram of the end of the relief groove without chamfering.

[0043] Figure 5 A schematic diagram of a relief groove end portion that has been chamfered and has a rounded corner and an obtuse corner is shown.

[0044] Figure 6 A schematic diagram showing a relief groove end with chamfered corners.

[0045] Figure 7 A schematic diagram showing a relief groove end that has been chamfered and has one right angle and two obtuse corners.

[0046] Figure 8 A schematic diagram of a relief groove end portion that has been chamfered and has one obtuse angle and one right-angle corner is shown.

[0047] Fig. 9 The diagram shows the position correspondence between an exemplary plan layout diagram and a simplified cross-sectional view of the pixel structure of the present invention in the first embodiment.

[0048] Fig.10 An enlarged view of an example of the pixel structure of the present invention in the area where the heating resistor is located and its vicinity in the first embodiment is shown.

[0049] Fig.11 An exemplary plan layout diagram of the pixel structure of the present invention in the second embodiment is shown.

[0050] Fig.12 An exemplary plan layout diagram of the suspension layer, the supporting frame and the cavity of the pixel structure of the present invention in the second embodiment is shown.

[0051] Fig.13 Shown is a simplified cross-sectional view of an example of a pixel structure of the present invention in the second embodiment.

[0052] Fig.14 An enlarged view of an example of the pixel structure of the present invention in the area where the heating resistor is located and its vicinity in the second embodiment is shown.

[0053] Fig.15 Shown is an exemplary plan layout diagram of the array infrared detector of the present invention in the third embodiment.

[0054] Fig.16 Display as Fig.15 Simplified cross-sectional view of .

[0055] Fig.17 It shows the process flow chart of the method for manufacturing the array infrared detector of the present invention in the fourth embodiment.

[0056] Fig.18 It is a schematic diagram showing the structure of the array infrared detector manufacturing method of the present invention after forming an N-well and a P-well in a semiconductor substrate in the fourth embodiment.

[0057] Fig.19 It is a schematic diagram showing the structure of the array infrared detector manufacturing method of the present invention after forming an isolation structure in a semiconductor substrate in the fourth embodiment.

[0058] Fig. 20 It is a schematic diagram of the structure presented after forming polysilicon layers of different conductivity types on a semiconductor substrate and patterning them in the fourth embodiment of the manufacturing method of the array infrared detector of the present invention.

[0059] Fig.21 It is a schematic diagram showing the structure of the array infrared detector after the PMOS tube and the NMOS tube in the CMOS area are prepared in the fourth embodiment of the manufacturing method of the present invention.

[0060] Fig. 22 It is a schematic diagram of the structure presented after preparing the first dielectric layer, the first through-hole layer and the first metal layer in the fourth embodiment of the manufacturing method of the array infrared detector of the present invention.

[0061] Fig.23 It is a schematic diagram of the structure presented after preparing the second dielectric layer, the second through hole layer, the second metal layer, the third dielectric layer, the third through hole layer, the third metal layer, the fourth dielectric layer, the fourth through hole layer, the fourth metal layer and the passivation layer in the fourth embodiment of the manufacturing method of the array infrared detector of the present invention.

[0062] Fig.24 It is a schematic diagram showing the structure of the array infrared detector manufacturing method of the present invention after etching the passivation layer to expose the pad in the fourth embodiment.

[0063] Fig.25 It is a schematic diagram showing the structure of the array infrared detector manufacturing method of the present invention after the release grooves are formed in the fourth embodiment.

[0064] Fig.26It is a schematic diagram of the structure of the array infrared detector manufacturing method of the present invention after the cavity is formed in the fourth embodiment.

[0065] Component number description

[0066] 1 Base

[0067] 2 Cavity

[0068] 3 Main release groove

[0069] 4 First auxiliary release groove

[0070] 5 Second auxiliary release groove

[0071] 501 Heat Blocking Slot

[0072] 502 Enhanced Release Groove

[0073] 6 Thermocouple

[0074] 7 Suspension layer

[0075] 8 Support frame

[0076] 9 Cantilever beam

[0077] 901 First Edge Arm

[0078] 902 Middle Arm Area

[0079] 903 Second marginal arm area

[0080] 10 Infrared absorption film

[0081] A. The first hot zone

[0082] B. Second hot zone

[0083] 11 Thermocouple pairs

[0084] 11a First conductivity type polysilicon thermocouple strip

[0085] 11b Second conductivity type polysilicon thermocouple strip

[0086] 12 Hot End

[0087] 13 Cold Junction

[0088] 14 Hot end metal

[0089] 15a, 15b Cold end metal

[0090] 16 Heating resistor

[0091] 17 Connecting Metal

[0092] 18 Heat capacity enhancement

[0093] 18a Central enhancer

[0094] 18b Peripheral reinforcement

[0095] 19 MEMS array sensor

[0096] 20 CMOS Circuits

[0097] 21. Semiconductor substrate

[0098] M First Area

[0099] N Second Area

[0100] 22 N-well

[0101] 23 P-well

[0102] 24 First Isolation Body

[0103] 25 Second Isolation

[0104] 26 First conductivity type polysilicon gate

[0105] 27 Second conductivity type polysilicon gate

[0106] 28 Gate dielectric layer

[0107] 29 Conductive interconnect layer

[0108] 30 Dielectric layer

[0109] 31 Metal conductor layer

[0110] 32 Conductive plug

[0111] 33 Passivation layer

[0112] 34 Passivation layer

[0113] Steps S1 to S6 DETAILED DESCRIPTION

[0114] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0115] See also Figures 1 to 26It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0116] Embodiment 1

[0117] This embodiment provides a pixel structure, see Figure 1 , showing an example plan layout diagram of the pixel structure, including a substrate 1, a cavity 2 (the opening outline is represented by a dotted frame), a main release groove 3, a first auxiliary release groove 4, a second auxiliary release groove 5 and a temperature difference thermal pile 6, wherein the cavity 2 is buried in the substrate 1, the portion of the substrate 1 suspended above the cavity 2 constitutes a suspension layer 7, the portion of the substrate 1 located around the cavity 2 constitutes a support frame 8, the suspension layer 7 includes a cantilever beam 9 and an infrared absorption film 10, one end of the cantilever beam 9 is connected to the support frame 8, and the other end of the cantilever beam 9 is connected to the edge of the infrared absorption film 10; the main release groove 4 is located at the cantilever beam 9. 9 is located on both sides and vertically penetrates the suspension layer 7 to communicate with the cavity 2; the first auxiliary release groove 4 is located in the cantilever beam 9 and vertically penetrates the cantilever beam 9 to communicate with the cavity 2; the second auxiliary release groove 5 is located in the infrared absorption film 10 and vertically penetrates the infrared absorption film 10 to communicate with the cavity 2; the temperature difference thermal pile 6 is located on the substrate 1, and the temperature difference thermal pile 6 includes a plurality of groups of thermocouple pairs 11, and the thermocouple pairs 11 extend from the supporting frame 8 via the cantilever beam 9 to the infrared absorption film 10, the hot end 12 of the thermocouple pair 11 is located above the infrared absorption film, and the cold end 13 of the thermocouple pair 11 is located on the supporting frame 8.

[0118] Specifically, the area where the infrared absorption film 10 is located is used to absorb infrared rays, the cavity 2 is used for thermal insulation between the infrared absorption film 10 and the rest of the substrate 1, the cantilever beam 9 is connected between the infrared absorption film 10 and the supporting frame 8 to provide support for the infrared absorption film 10, the main release groove 3, the first auxiliary release groove 4 and the second auxiliary release groove 5 serve as injection channels for anisotropic wet etching liquid during device manufacturing so that the etching liquid can enter the interior of the substrate 1 through the release grooves to etch the cavity 2 under the infrared absorption film 10, and the temperature difference thermal pile 6 mainly measures external radiation to achieve the purpose of measuring temperature.

[0119] As an example, the base 1 may include a semiconductor substrate and required components such as an isolation structure and a transistor formed in the semiconductor substrate. The material of the semiconductor substrate may be silicon, germanium, germanium silicon, III-V compounds or other suitable semiconductor materials. The depth of the cavity 2 buried in the base 1 may be set to 100 microns or other suitable depths. The cavity 2 of sufficient depth can thermally insulate the infrared absorption film 10 from the substrate, thereby preventing the heat absorbed by the infrared absorption film 10 from being lost.

[0120] As an example, a plurality of groups of the thermocouple pairs are connected in series and in parallel in at least one manner, the first conductivity type is P type or N type, and the second conductivity type is opposite to the first conductivity type. In this embodiment, the thermocouple pair 11 includes a first conductivity type polysilicon thermocouple strip 11a and a second conductivity type polysilicon thermocouple strip 11b, the first conductivity type polysilicon thermocouple strip 11a and the second conductivity type polysilicon thermocouple strip 11b extend in parallel, one end of the first conductivity type polysilicon thermocouple strip 11a located on the infrared absorption film 10 is connected to the end of the second conductivity type polysilicon thermocouple strip 11b facing the infrared absorption film 10 through a hot end metal 14, and one end of the first conductivity type polysilicon thermocouple strip 11a located on the support frame 8 is connected to the second conductivity type polysilicon thermocouple strip of another thermocouple pair through a cold end metal 15a (for example, the subsequent Fig. 9 ) or through the cold end metal 15a as an output end of the temperature difference thermal pile 6 (for example Figure 1 ), one end of the second conductive type polysilicon thermocouple bar 11b located on the support frame 8 is connected to the first conductive type polysilicon thermocouple bar of another thermocouple pair through a cold end metal 15b. The hot end metal 14, the cold end metal 15a and the cold end metal 15b can be made of aluminum or other suitable materials.

[0121] For a clearer illustration of the layout of the relief grooves, see Figure 2 , which is an exemplary plan layout diagram of the suspension layer 7, the support frame 8 and the cavity 2. In this embodiment, the infrared absorption film 10 is a regular octagonal structure and is located at the center of the pixel structure. In other embodiments, the infrared absorption film 10 may also be circular, square or other suitable shapes, not limited to this embodiment.

[0122] As an example, the pixel structure includes a plurality of cantilever beams 9, and two adjacent cantilever beams 9 are spaced apart by the main release groove 3. Figure 2In the example presented, the pixel structure includes four cantilever beams 9, and each of the cantilever beams 9 extends from the four corners of the cavity 2 to the center at 45° and is connected to the four oblique angles of the infrared absorption film 10. The multiple cantilever beams 9 are evenly arranged on the infrared absorption film 10 so that the infrared absorption film 10 is evenly stressed and more stable. In other embodiments, the number of cantilever beams 9 can also be adjusted as needed, such as 2, 3, 6, etc., which is not limited to this embodiment.

[0123] Specifically, the first auxiliary release groove 4 located in the cantilever beam 9 serves as an injection channel for the etching liquid on the one hand, ensuring that the substrate material under the cantilever beam 9 can be fully corroded, and on the other hand, it can reduce the thermal conductivity of the cantilever beam 9, thereby further ensuring the performance of the temperature difference thermal stack 6. In this embodiment, the extension direction of the first auxiliary release groove 4 is parallel to the corresponding extension direction of the cantilever beam 9 (i.e., where the first auxiliary release groove 4 is located).

[0124] As an example, the first auxiliary release groove 4 has at least one corner at one end facing the support frame 8. In this embodiment, any of the corners is preferably selected from one of a circular arc angle, an obtuse angle and a right angle, which can be achieved by chamfering. Figure 3 and Figure 4 , showing two schematic diagrams of the ends of the relief groove without chamfering, both of which include sharp corners. Figures 5 to 8 , showing four schematic diagrams of the ends of the release grooves that have been chamfered. Figure 5 Shown are situations where the release groove ends have arc angles and obtuse angles. Figure 6 Shown is a case where the end of the release groove has a rounded angle. Figure 7 Shown is a case where the end of the release groove has one right angle and two obtuse angles. Figure 8 The embodiment shows a situation where the end of the release groove has an obtuse angle and a right angle. Compared with the solution without chamfering, the chamfering solution can reduce the stress concentrated at the connection between the cantilever beam 9 and the support frame 8, improve the mechanical stability of the structure, thereby improve the yield rate of the product, and avoid stress damage to the structure under external movement impact or thermal shock.

[0125] As an example, the arc angle may be an R chamfer of 4 μm, but is not limited to an R chamfer of 4 μm.

[0126] Specifically, the second auxiliary release groove 5 located in the infrared absorption film 10, on the one hand, serves as an injection channel for the etching solution, ensuring that the substrate material under the infrared absorption film 10 can be fully corroded to completely separate the infrared absorption film 10 from the substrate, thereby reducing the hill-like structure of the bottom surface of the cavity after wet etching; on the other hand, it can prevent the central temperature of the infrared absorption film 10 from being transferred to the surrounding area, further increasing the temperature difference and ensuring the performance of the temperature difference thermal stack 6.

[0127] As an example, the second auxiliary release groove 5 includes a heat blocking groove 501, and the extension direction of the heat blocking groove 501 is at an intersection angle of 80°-100° with the corresponding extension direction of the first auxiliary release groove (i.e., located in the same cantilever beam 9). In this embodiment, the extension direction of the heat blocking groove 501 is preferably at an intersection angle of 90° with the corresponding extension direction of the first auxiliary release groove, which can more directly and effectively block heat transfer.

[0128] As an example, see Fig. 9 , which is a position correspondence diagram of the plane layout diagram of the pixel structure and the simplified cross-sectional diagram, wherein the cold end 13 of the thermocouple pair 11 is located outside the opening range of the cavity 2 and is spaced apart from the opening edge of the cavity 2 by a preset distance, and the end of the main release groove 3 facing the support frame 8 and the end of the first auxiliary release groove 4 facing the support frame 8 are both located within the opening range of the cavity 2 and are spaced apart from the opening edge of the cavity 2 by a preset distance. For example, the distance between the end of the main release groove 3 facing the support frame 8 and the end of the first auxiliary release groove 4 facing the support frame 8 and the cold end of the thermocouple pair can be set to 15 microns or other suitable lengths, and the distance between the end of the main release groove 3 facing the support frame 8 and the end of the first auxiliary release groove 4 facing the support frame 8 and the edge of the cavity 2 can be set to 10 microns or other suitable lengths. Such a setting can prevent the lateral corrosion error during the corrosion of the anisotropic wet etching solution from causing the cold end to not completely contact the support frame 8, resulting in a low output signal.

[0129] As an example, see Figure 2 In this embodiment, in the plane where the cantilever beam 9 is located and perpendicular to the extension direction of the cantilever beam 9, the cantilever beam 9 is divided into a first edge arm area 901, a middle arm area 902 and a second edge arm area 903 by two separately arranged first auxiliary release grooves 4.

[0130] As an example, in the extension direction perpendicular to the cantilever beam 9, the width of the first auxiliary release groove 4 is set to 7 microns, the width of the middle arm region 902 is set to 40 microns, the width of the first edge arm region 901 and the second edge arm region 903 are both set to 20 microns, the width of the middle arm region 902 is the sum of the widths of the first edge arm region 901 and the second edge arm region 903, the first edge arm region 901 and the second edge arm region 903 have the same width and are symmetrical in shape. In other embodiments, the width of the first auxiliary release groove 4, the width of the first edge arm region 901, the width of the middle arm region 902, and the width of the second edge arm region 903 can also be adjusted as needed, and are not limited to this embodiment.

[0131] Please refer to Figure 1 and Figure 2 , at least one group of the thermocouple pairs passes through the first edge arm area 901, at least one group of the thermocouple pairs passes through the middle arm area 902, and at least one group of the thermocouple pairs passes through the second edge arm area 903. In this embodiment, the number of thermocouple pairs passing through the first edge arm area 901 is one group, the number of thermocouple pairs passing through the middle arm area 902 is two groups, and the number of thermocouple pairs passing through the second edge arm area 903 is one group. In other embodiments, the number of thermocouple pairs passing through each arm area can be adjusted as needed, and is not limited to this embodiment.

[0132] As an example, the infrared absorption film 10 has a first hot zone A and a plurality of spaced second hot zones B, wherein the distance between the second hot zone B and the center of the infrared absorption film 10 is greater than the distance between the first hot zone A and the center of the infrared absorption film 10, wherein the hot end of the thermocouple pair passing through the first edge arm zone 901 is located in one of the second hot zones B, the hot end of the thermocouple pair passing through the middle arm zone 902 is located in the first hot zone A, and the hot end of the thermocouple pair passing through the second edge arm zone 903 is located in another of the second hot zones B.

[0133] As an example, in this embodiment, among the two groups of thermocouple pairs passing through the intermediate arm area 902, one group of the thermocouple pairs passes through the cantilever beam 9 and then goes around from one side of the second auxiliary release groove 5 to the first hot zone A, and the other group of the thermocouple pairs passes through the cantilever beam 9 and then goes around from the other side of the second auxiliary release groove 5 to the first hot zone A.

[0134] Specifically, the hot ends of the thermocouple pairs passing through the middle arm 902 region are extended to the first hot zone A closer to the center of the infrared absorption film 10, so that a higher temperature in the central area can be obtained, and the temperature difference is larger, thereby increasing the voltage output; and the hot ends of the thermocouple pairs passing through the first edge arm area 901 and the second edge arm area 903 are extended to the second hot zone B located at the edge area of ​​the infrared absorption film 10. Compared with all the hot ends extending to the center, the resistance of the thermopile can be reduced, and its thermal noise is reduced, which is beneficial to improving the signal-to-noise ratio (S / N) of the device.

[0135] As an example, the pixel structure may further include a heating resistor 16, the heating resistor 16 is located on the infrared absorption film 10, and the distance between the hot end of the thermocouple pair 11 and the center of the infrared absorption film 10 is greater than the distance between the heating resistor 16 and the center of the infrared absorption film 10. The method of heating the temperature difference thermal stack 6 by the heating resistor 16 can actively generate a temperature difference between the hot end and the cold end of the thermocouple pair, thereby realizing the function of self-detection and calibration of whether the working state of the temperature difference thermal stack 6 is normal.

[0136] For details, please refer to Fig.10 , showing an example enlarged view of the area where the heating resistor 16 is located and its vicinity. In this embodiment, the heating resistor 16 is located in the central area of ​​the infrared absorption film 10, and is composed of four polysilicon resistor bars connected in series via a connecting metal 17. The distribution positions of the four polysilicon resistor bars correspond to the distribution positions of the hot ends of multiple groups of thermocouple pairs.

[0137] It should be pointed out that, in addition to achieving the purpose of self-detection calibration of the temperature difference thermal stack 6, the heating resistor 16 can also be combined with special packaging to measure the gas flow rate. The measurement principle is that when the heating resistor 16 generates heat, when gas flows through the heating resistor 16, the airflow will drive the heat distribution in the central area of ​​the infrared absorption film 10 to change, and the change in heat distribution further causes the potential difference of the thermocouple pair 11 to change. By measuring the resistance of the thermocouple strip, the gas flow rate can be measured.

[0138] As an example, the pixel structure further includes a heat capacity enhancement body 18, and the distance between the hot end of the thermocouple pair 11 and the center of the infrared absorption film 10 is greater than the distance between the heat capacity enhancement body 18 and the center of the infrared absorption film 10. The heat capacity enhancement body 18 does not participate in the electrical connection circuit of the heating resistor 16 or the thermopile 6, and does not affect the electrical properties of the thermopile and the heating resistor, but the heat capacity enhancement body 18 is located in the central area of ​​the infrared absorption film 10, which can increase the heat capacity of the hot end of the thermopile to a certain extent, accumulate more heat, increase the temperature difference between the hot and cold ends of the thermopile, and thus improve the voltage response of the thermopile.

[0139] As an example, the heat capacity enhancement body 18 is made of polycrystalline silicon blocks. In this embodiment, the heat capacity enhancement body 18 includes a central reinforcement body 18a located in the area surrounded by the heating resistor 16 and a plurality of peripheral reinforcement bodies 18b located outside the heating resistor 16. The central reinforcement body 18a is cross-shaped, and the peripheral reinforcement body 18b is square-shaped. In other embodiments, the layout and shape of the heat capacity enhancement body 18 can be adjusted as needed, which is not limited to this embodiment.

[0140] The pixel structure of this embodiment is provided with a first auxiliary release groove in the cantilever beam, and a second auxiliary release groove in the infrared absorption film, wherein the first auxiliary release groove can reduce the thermal conductivity of the cantilever beam, reduce heat loss, and improve the response rate of the device, and the second auxiliary release groove includes a heat blocking groove, which is beneficial to the formation of the cavity on the one hand, and can hinder the heat of the infrared absorption film from being transferred along the cantilever beam to the cold end on the other hand, thereby further reducing heat loss and improving the response rate of the device.

[0141] Embodiment 2

[0142] This embodiment and the first embodiment adopt basically the same technical solution, the difference being that in the first embodiment, the second auxiliary release groove 5 includes a heat blocking groove 501, and the extension direction of the heat blocking groove 501 forms an intersection angle of 80°-100° with the extension direction of the first auxiliary release groove 4, while in this embodiment, the second auxiliary release groove 5 not only includes the heat blocking groove 501, but also further includes an enhanced release groove.

[0143] For details, please refer to Fig.11 and Fig.12 ,in, Fig.11 Shown is an example plan layout diagram of the pixel structure in this embodiment. Fig.12 Shown is an example plan layout diagram of the suspension layer 7, the supporting frame 8 and the cavity 2 in the pixel structure of this embodiment. It can be seen that the second auxiliary release groove 5 located in the infrared absorption film 10 further includes an enhanced release groove 502, and the extension direction of the enhanced release groove 502 is parallel to the extension direction of the corresponding cantilever beam 9 (that is, the enhanced release groove 502 is located). When the extension direction of the heat blocking groove 501 and the extension direction of the first auxiliary release groove 4 are at an intersection angle of 90°, the second auxiliary release groove 5 composed of the heat blocking groove 501 and the enhanced release groove 502 is cross-shaped.

[0144] As an example, the length of the enhanced release groove 502 extending in a direction parallel to the extension direction of the cantilever beam 9 is greater than the length of the heat blocking groove 501, thereby ensuring that the substrate below the central area of ​​the infrared absorption film 10 is completely wet-etched, further reducing the hill-like structure on the bottom surface of the cavity after wet etching, or even completely eliminating the hill-like structure, thereby reducing heat loss. Fig.13 , which is a simplified cross-sectional view of an example of the pixel structure described in this embodiment, relative to Fig. 9 The situation shown, Fig.12 In the embodiment, the bottom surface of the cavity 2 is flat and has no hill-like structure.

[0145] See also Fig.14 , which is an enlarged view of the area where the heating resistor 16 is located and its vicinity in this embodiment, relative to Fig.10 The situation shown, Fig.13 In the illustrated case, since the enhanced release groove 502 additionally occupies a certain area, the heat capacity enhancement body 18 only includes the central enhancement body 18a located in the area surrounded by the heating resistor 16. Of course, in other embodiments, the heat capacity enhancement body 18 is not limited to being located only in the area surrounded by the heating resistor 16, and this is not excessively limited here.

[0146] The pixel structure of this embodiment is provided with a first auxiliary release groove in the cantilever beam, and a second auxiliary release groove in the infrared absorption film, wherein the first auxiliary release groove can reduce the thermal conductivity of the cantilever beam, reduce heat loss, and improve the response rate of the device, and the second auxiliary release groove includes a heat blocking groove and an enhanced release groove, which can, on the one hand, hinder the heat of the infrared absorption film from being transferred along the cantilever beam to the cold end, further reduce heat loss, and improve the response rate of the device, and on the other hand, facilitate the substrate below the central area of ​​the infrared absorption film 10 to be completely wet-etched, further reduce the hill-like structure on the bottom surface of the cavity after wet etching, or even completely eliminate the hill-like structure, thereby reducing heat loss.

[0147] Embodiment 3

[0148] This embodiment provides an array infrared detector, see Fig.15 and Fig.16 ,in, Fig.15 An example plan layout diagram of the array infrared detector is shown. Fig.16 Display as Fig.15A simplified cross-sectional view (showing the cavity 2), the array infrared detector includes a MEMS array sensor 19, a CMOS circuit 20 and a conductive interconnection layer (not shown), wherein the MEMS array sensor 19 includes a plurality of pixel structures as described in Example 1 or Example 2, the plurality of pixel structures are arranged in an array and share the substrate, the CMOS circuit 19 is located in the substrate and at the periphery of the MEMS array sensor 19, the conductive interconnection layer is located on the substrate, and the MEMS array sensor 19 and the CMOS circuit 20 are electrically connected via the conductive interconnection layer.

[0149] As an example, the MEMS array sensor 19 is located at the center of the chip, which is to ensure that each side of the array sensor maintains the same thermal capacitance and thermal conductivity, and avoid output errors of each pixel caused by different positions in the same chip.

[0150] As an example, the multiple pixel structures constituting the MEMS array sensor 19 are arranged in a rectangular array, for example, Fig.15 The arrangement shown is a 3×3 matrix, but in other embodiments, the number and specific arrangement of the pixel structures constituting the MEMS array sensor 19 can be adjusted as needed and is not limited to this embodiment.

[0151] As an example, the conductive interconnect layer includes a dielectric layer and at least one metal wire layer embedded in the dielectric layer, wherein the metal wire layer at the bottom layer is electrically connected to the MEMS array sensor 19 and the CMOS circuit 20 through a conductive plug to achieve electrical connection between the MEMS array sensor 19 and the CMOS circuit 20, so that data reading control can be performed. In this embodiment, the metal wire layer at the bottom layer of the conductive interconnect layer includes the hot end metal 14, the cold end metal 15a, the cold end metal 15b and the connecting metal 17.

[0152] As an example, when the conductive interconnect layer includes multiple metal wire layers, two adjacent metal wire layers are also electrically connected via a conductive plug.

[0153] The array infrared detector of this embodiment integrates the MEMS array sensor and the CMOS circuit into one chip, which can improve the response rate of the device, achieve a smaller device size, and meet the needs of multi-scenario and multi-functional intelligent applications. For example, it can not only be used for single-point or multi-point temperature measurement, but also realize imaging functions, and combine with heating resistors and subsequent packaging to realize gas flow measurement functions, etc.

[0154] Embodiment 4

[0155] This embodiment provides a method for manufacturing an array infrared detector. The method can be used to manufacture the array infrared detector described in Example 3. Fig.17 , which is a process flow chart of the method for manufacturing the array infrared detector, comprising the following steps:

[0156] S1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region located outside the first region;

[0157] S2: forming an isolation structure in the semiconductor substrate, wherein the isolation structure starts from the top surface of the semiconductor substrate and extends downward but does not penetrate the semiconductor substrate, and the isolation structure includes a first isolation body located in the first region and a second isolation body located in the second region;

[0158] S3: forming a first conductive type polysilicon layer on the semiconductor substrate and patterning it to obtain a first conductive type polysilicon thermocouple strip located on the first insulator and a first conductive type polysilicon gate located in the second region, forming a second conductive type polysilicon layer on the semiconductor substrate and patterning it to obtain a second conductive type polysilicon thermocouple strip located on the first insulator and a second conductive type polysilicon gate located in the second region;

[0159] S4: forming the conductive interconnect layer on the semiconductor substrate, wherein the conductive interconnect layer includes a dielectric layer and at least one metal wire layer embedded in the dielectric layer;

[0160] S5: forming the main release groove, the first auxiliary release groove and the second auxiliary release groove, wherein the main release groove, the first auxiliary release groove and the second auxiliary release groove all vertically penetrate the dielectric layer and the first isolation body;

[0161] S6: Injecting etching solution through the main release groove, the first auxiliary release groove and the second auxiliary release groove to corrode the portion of the semiconductor substrate located below the first isolation body to obtain the cavity.

[0162] First see Fig.18 , perform the step S1: provide a semiconductor substrate 21, the semiconductor substrate 21 includes a first region M and a second region N located outside the first region M.

[0163] As an example, the material of the semiconductor substrate 21 can be selected from silicon, germanium, germanium silicon, III-V compounds or other suitable semiconductor materials. In this embodiment, the semiconductor substrate 21 is selected from <100> The silicon wafer with a crystalline orientation is first cleaned and dried, and then an N well 22 and a P well 23 are sequentially formed in the semiconductor substrate 21 through conventional semiconductor processes such as epitaxial growth, photoresist patterning, ion implantation, and annealing. The N well 22 and the P well 23 are used for the subsequent manufacture of MOS transistors of the CMOS circuit 20.

[0164] Please see again Fig.19 , execute the step S2: form an isolation structure in the semiconductor substrate 21, the isolation structure starts from the top surface of the semiconductor substrate 21 and extends downward, but does not penetrate the semiconductor substrate 21, the isolation structure includes a first isolation body 24 located in the first area M and a second isolation body 25 located in the second area N.

[0165] As an example, the isolation structure uses a shallow trench isolation structure (STI), which can be specifically formed by forming an isolation oxide layer on the surface of the semiconductor substrate 21, depositing a silicon nitride hard mask layer, and obtaining an STI groove by photoresist patterning and etching, and then cleaning the inner wall of the trench in turn, thermally oxidizing the inner wall of the trench to form a silicon oxide seed layer, filling the trench with oxide by chemical vapor deposition (CVD) or other suitable methods, and then performing oxide flattening and removing the silicon nitride hard mask layer by chemical mechanical polishing (CMP) to obtain the isolation structure.

[0166] Specifically, the first insulator 24 serves as the first supporting layer and insulating layer of the thermopile 6 , and the second insulator 25 is used to isolate the N-well 22 and the P-well 23 .

[0167] Please see again Fig. 20 , perform the step S3: form a first conductive type polysilicon layer on the semiconductor substrate 21 and pattern it to obtain a first conductive type polysilicon thermocouple strip 11a located on the first isolation body 24 and a first conductive type polysilicon gate 26 located in the second region N, form a second conductive type polysilicon layer on the semiconductor substrate 21 and pattern it to obtain a second conductive type polysilicon thermocouple strip 11b located on the first isolation body 24 and a second conductive type polysilicon gate 27 located in the second region N.

[0168] As an example, a silicon dioxide layer is first grown on the surface of the semiconductor substrate 21 by thermal oxidation as a gate dielectric layer 28, and then polysilicon is deposited by low-pressure chemical vapor deposition (LPCVD), and then different types of doping are performed on different regions of the polysilicon in turn; and the polysilicon film layer is photolithographically and etched to simultaneously obtain the first conductive type polysilicon gate 26, the second conductive type polysilicon gate 27, the first conductive type polysilicon thermocouple bar 11a and the second conductive type polysilicon thermocouple bar 11b.

[0169] In this embodiment, the heating resistor 16 made of polysilicon is also obtained at the same time (not shown in FIG. Fig. 20 ) and the heat capacity enhancement body 18 (not shown in Fig. 20 (displayed in the figure).

[0170] In this embodiment, Fig.21 As shown, the PMOS tube and NMOS tube in the CMOS area are further prepared through standard integrated circuit processes such as lightly doped drain, sidewall preparation, source and drain injection, etc.

[0171] Please see again Figure 22 to Figure 24 , performing the step S4: forming a conductive interconnection layer 29 on the semiconductor substrate, wherein the conductive interconnection layer 29 includes a dielectric layer 30 and at least one metal wire layer 31 embedded in the dielectric layer 30 .

[0172] As an example, the conductive interconnection layer 29 includes multiple metal wire layers 31, and the metal wire layer 31 at the bottom layer is electrically connected to the MEMS array sensor 19 and the CMOS circuit 20 through a conductive plug 32 to achieve electrical connection between the MEMS array sensor 19 and the CMOS circuit 20, so that data reading control can be performed, and two adjacent metal wire layers 31 are also electrically connected through the conductive plug 32. In this embodiment, the metal wire layer 31 at the bottom layer of the conductive interconnection layer 29 includes the hot end metal 14, the cold end metal 15a, the cold end metal 15b and the connecting metal 17.

[0173] The formation process of the conductive interconnect layer 29 is described below by taking an example:

[0174] like Fig. 22 As shown, the first dielectric layer, the first through-hole layer and the first metal layer are prepared by standard 1P4M processes such as contact hole formation process and local interconnection process to realize electrical connection between metal interconnection and thermocouple strips, and at this time, the output of each pixel structure is connected to the CMOS circuit 20 through the first metal layer.

[0175] like Fig.23As shown, the second dielectric layer, the second through-hole layer, the second metal layer, the third dielectric layer, the third through-hole layer, the third metal layer, the fourth dielectric layer, the fourth through-hole layer, the fourth metal layer and the passivation layer 33 are prepared by the standard 1P4M process.

[0176] like Fig.24 As shown, the passivation layer 33 is etched through photolithography to expose the pad 34 .

[0177] Please see again Fig.25 , execute the step S5: form the main release groove 3, the first auxiliary release groove 4 and the second auxiliary release groove 5, and the main release groove 3, the first auxiliary release groove 4 and the second auxiliary release groove 5 all vertically penetrate the dielectric layer 30 and the first isolation body 24.

[0178] As an example, various release grooves are formed by photolithography and etching, and the etching depth is required to completely expose the semiconductor substrate 21. The deeper the etching depth, the better the subsequent wet etching effect and the faster the rate.

[0179] Please see again Fig.26 , execute the step S6: through the main release groove 3, the first auxiliary release groove 4 (not in Fig.25 ) and the second auxiliary release groove 5 (not shown in Fig.25 (shown in the figure) an etching solution is injected to corrode the portion of the semiconductor substrate 21 located below the first insulator 24 to obtain the cavity 2.

[0180] Specifically, the cavity 2 realizes thermal isolation between the surface structure and the semiconductor substrate 21. In this embodiment, an anisotropic etching solution (TMAH tetramethylammonium hydroxide, potassium hydroxide solution or other alkaline solution) is injected into each release groove, so that the semiconductor substrate 21 below the temperature difference thermal stack is corroded to form a cavity, and thermal isolation is achieved to obtain the pixel structure described in the first or second embodiment, and the array infrared detector has a two-dimensional array of the pixel structure.

[0181] As an example, during wet etching, the back side of the semiconductor substrate 21 needs a silicon oxide layer as back side protection to prevent the back side of the semiconductor substrate 21 from being damaged.

[0182] As an example, the obtained cavity 2 presents an inverted trapezoidal structure. For the shape of the second auxiliary release groove 5 in the first embodiment, the bottom center of the cavity 2 will appear as follows: Fig. 9 The tiny hill-like structure shown in FIG. 1 is smaller than that in FIG. 1 , while for the optimized shape of the second auxiliary release groove 5 in the second embodiment, the hill-like structure is reduced or even disappears.

[0183] At this point, an array infrared detector is manufactured. The manufacturing method of the array infrared detector of this embodiment uses the CMOS process to prepare a CMOS-MEMS fully integrated array infrared detector, which can improve the intelligent processing capability of the sensor, has a smaller size, lower cost, and can be mass-produced.

[0184] In summary, the pixel structure of the present invention includes a substrate, a cavity, a main release groove, a first auxiliary release groove, a second auxiliary release groove and a temperature difference heat pile, wherein the cavity is buried in the substrate, and the part of the substrate suspended above the cavity constitutes a suspension layer, the suspension layer includes a cantilever beam and an infrared absorption film, the main release groove is located on both sides of the cantilever beam, the first auxiliary release groove is located in the cantilever beam, the second auxiliary release groove is located in the infrared absorption film, and the temperature difference heat pile is located on the substrate and includes a plurality of groups of thermocouples extending from the support frame through the cantilever beam to the infrared absorption film. In the pixel structure of the present invention, the first auxiliary release groove can reduce the thermal conductivity of the cantilever beam, reduce heat loss, and improve the response rate of the device. The second auxiliary release groove is conducive to the formation of the cavity on the one hand, and can hinder the heat of the infrared absorption film from being transferred along the cantilever beam to the cold end on the other hand, further reducing heat loss and improving the response rate of the device. The array infrared detector using the pixel structure of the present invention is compatible with the CMOS process, can meet the requirements of multi-scenario multi-function intelligent applications, is conducive to reducing the size of the device, reducing production costs, and realizing mass production. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0185] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A pixel structure, characterized in that: include: substrate; A cavity is embedded in the substrate, a portion of the substrate suspended above the cavity constitutes a suspension layer, a portion of the substrate located around the cavity constitutes a support frame, the suspension layer comprises a cantilever beam and an infrared absorbing film, one end of the cantilever beam is connected to the support frame, and the other end of the cantilever beam is connected to the edge of the infrared absorbing film; Main release grooves, located on both sides of the cantilever beam and vertically penetrating the suspension layer to communicate with the cavity; A first auxiliary release groove is located in the cantilever beam and vertically penetrates the cantilever beam to communicate with the cavity; A second auxiliary release groove is located in the infrared absorbing film and vertically penetrates the infrared absorbing film and communicates with the cavity; A temperature differential thermal stack is located on the substrate, and the temperature differential thermal stack includes a plurality of thermocouple pairs, the thermocouple pairs extend from the supporting frame via the cantilever beam to the infrared absorbing film, the hot ends of the thermocouple pairs are located above the infrared absorbing film, and the cold ends of the thermocouple pairs are located on the supporting frame.

2. The pixel structure according to claim 1, characterized in that: In the plane where the cantilever beam is located and perpendicular to the extension direction of the cantilever beam, the cantilever beam is divided into a first edge arm area, a middle arm area and a second edge arm area by two separately arranged first auxiliary release grooves, at least one group of the thermocouple pairs passes through the first edge arm area, at least one group of the thermocouple pairs passes through the middle arm area, and at least one group of the thermocouple pairs passes through the second edge arm area.

3. The pixel structure according to claim 2, characterized in that: The infrared absorption film has a first hot zone and a plurality of second hot zones arranged at intervals, wherein the distance between the second hot zone and the center of the infrared absorption film is greater than the distance between the first hot zone and the center of the infrared absorption film, wherein the hot end of the thermocouple pair passing through the first edge arm zone is located in one of the second hot zones, the hot end of the thermocouple pair passing through the middle arm zone is located in the first hot zone, and the hot end of the thermocouple pair passing through the second edge arm zone is located in another of the second hot zones.

4. The pixel structure according to claim 3, characterized in that: There are two groups of thermocouple pairs passing through the middle arm area, one group of thermocouple pairs passing through the cantilever beam and then bypassing from one side of the second auxiliary release groove to the first hot zone, and the other group of thermocouple pairs passing through the cantilever beam and then bypassing from the other side of the second auxiliary release groove to the first hot zone.

5. The pixel structure according to any one of claims 1 to 4, characterized in that: The pixel structure includes a plurality of cantilever beams, and two adjacent cantilever beams are spaced apart by the main release groove.

6. The pixel structure according to any one of claims 1 to 4, characterized in that: The extension direction of the first auxiliary release groove is parallel to the extension direction of the cantilever beam, and the second auxiliary release groove includes a heat blocking groove, and the extension direction of the heat blocking groove forms an intersection angle of 80°-100° with the extension direction of the first auxiliary release groove.

7. The pixel structure according to claim 6, characterized in that: The second auxiliary release groove further includes an enhanced release groove, and an extending direction of the enhanced release groove is parallel to an extending direction of the cantilever beam.

8. The pixel structure according to any one of claims 1 to 4, characterized in that: The pixel structure further includes a heating resistor, which is located on the infrared absorption film. The distance between the hot end of the thermocouple pair and the center of the infrared absorption film is greater than the distance between the heating resistor and the center of the infrared absorption film.

9. The pixel structure according to any one of claims 1 to 4, characterized in that: The pixel structure also includes a heat capacity enhancement body, which is located on the infrared absorption film, and the distance between the hot end of the thermocouple pair and the center of the infrared absorption film is greater than the distance between the heat capacity enhancement body and the center of the infrared absorption film.

10. The pixel structure according to any one of claims 1 to 4, characterized in that: The first auxiliary release groove has at least one corner at one end facing the supporting frame, wherein any one of the corners is selected from one of an arc angle, an obtuse angle and a right angle.

11. The pixel structure according to any one of claims 1 to 4, characterized in that: The cold end of the thermocouple pair is located outside the opening range of the cavity and is spaced a preset distance from the opening edge of the cavity. One end of the main release groove toward the supporting frame and one end of the first auxiliary release groove toward the supporting frame are both located within the opening range of the cavity and are spaced a preset distance from the opening edge of the cavity.

12. The pixel structure according to any one of claims 1 to 4, characterized in that: The thermocouple pairs include a first conductivity type polysilicon thermocouple strip and a second conductivity type polysilicon thermocouple strip, and multiple groups of the thermocouple pairs are connected in at least one of series and parallel connection. The first conductivity type is P type or N type, and the second conductivity type is opposite to the first conductivity type.

13. An array infrared detector, characterized in that: include: A MEMS array sensor, comprising a plurality of pixel structures according to any one of claims 1 to 12, wherein the plurality of pixel structures are arranged in an array and share the substrate; A CMOS circuit is located in the substrate and at the periphery of the MEMS array sensor; A conductive interconnection layer is located on the substrate, and the MEMS array sensor and the CMOS circuit are electrically connected via the conductive interconnection layer.

14. A method for manufacturing an array infrared detector, characterized in that: The manufacturing method is used to manufacture the array infrared detector as claimed in claim 13, comprising the following steps: Providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region located outside the first region; forming an isolation structure in the semiconductor substrate, the isolation structure starting from the top surface of the semiconductor substrate and extending downward but not penetrating the semiconductor substrate, the isolation structure comprising a first isolation body located in the first region and a second isolation body located in the second region; Forming a first conductive type polysilicon layer on the semiconductor substrate and patterning it to obtain a first conductive type polysilicon thermocouple bar located on the first insulator and a first conductive type polysilicon gate located in the second region, forming a second conductive type polysilicon layer on the semiconductor substrate and patterning it to obtain a second conductive type polysilicon thermocouple bar located on the first insulator and a second conductive type polysilicon gate located in the second region; Forming the conductive interconnect layer on the semiconductor substrate, wherein the conductive interconnect layer includes a dielectric layer and at least one metal wire layer embedded in the dielectric layer; forming the main release groove, the first auxiliary release groove and the second auxiliary release groove, wherein the main release groove, the first auxiliary release groove and the second auxiliary release groove all vertically penetrate the dielectric layer and the first isolation body; An etching solution is injected through the main release groove, the first auxiliary release groove and the second auxiliary release groove to corrode the portion of the semiconductor substrate located below the first isolation body to obtain the cavity.

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