Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device. The array substrate comprises a plurality of data lines arranged in a first direction, a plurality of grid lines arranged in a second direction, and a plurality of sub-pixel groups formed by overlapping two adjacent grid lines in the plurality of grid lines with the data lines in an insulated manner; each sub-pixel group comprises two sub-pixels; the sub-pixel groups comprise a first sub-pixel group, a second sub-pixel group and a third sub-pixel group which are sequentially and alternately arranged along a first direction; wherein the sub-pixels in the second sub-pixel group are used for emitting first color light; the two sub-pixels in the first sub-pixel group are respectively used for emitting the second color light and the third color light, and the two sub-pixels in the third sub-pixel group are respectively used for emitting the second color light and the third color light. According to the embodiment of the invention, the two sub-pixels emitting the first color light are adjacently arranged to realize mixed fuzzy light emitting, so that defects such as vertical stripes of the array substrate with a double-gate design are avoided, and the light emitting uniformity of the array substrate is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of display devices, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] The related art proposes to use thin film transistors (TFT) integrated behind the liquid crystal pixels to drive the liquid crystal display (LCD), so as to achieve screen display with advantages such as high brightness and high contrast. In order to achieve patterned light emission, the pixels are generally arranged in an array. In order to drive and control the pixels arranged in the array, it is usually done by electrically connecting the pixels with staggered gate lines and data lines, thereby controlling the light emission colors of the red, green and blue (RGB) three primary color pixels in each pixel unit through the switch of the thin film transistor, and controlling the color of the light emitted by the pixel unit. With the year-on-year development and relative maturity of LCD display, the demands such as cost reduction and image quality improvement are also increasing day by day. In order to meet these demands, the related art proposes various innovative designs for the array substrate in LCD display, such as adjusting the number, arrangement and connection mode of the gate lines and data lines. However, these innovative designs often have unexpected disadvantages, which may have adverse effects on the realization of the functions of the array substrate, and even lead to a decrease in the display performance of the array substrate.

[0003] It should be noted that the information distinguishing the invention in the above background technology is only used to enhance the understanding of the background of the invention, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the invention

[0004] The embodiments of the present application provide an array substrate, a display panel and a display device, which are intended to realize the light emission of two pixel units of three primary color pixels by means of a first sub-pixel group, a second sub-pixel group and a third sub-pixel group that are alternately arranged in sequence, and wherein two sub-pixels emitting a first color light are adjacently arranged between two adjacent pixel units and can realize mixed fuzzy light emission, thereby coordinating the light emission of the sub-pixels in the first sub-pixel and the third sub-pixel group on both sides, each forming a pixel unit, and partially or completely solving the problem of vertical stripes in the display of the array substrate caused by uneven brightness of the sub-pixels emitting the first color light, thereby improving the display performance of the array substrate.

[0005] In one aspect, an embodiment of the present application provides an array substrate, including:

[0006] A plurality of data lines arranged along a first direction, a plurality of gate lines arranged along a second direction, and a plurality of sub-pixel groups surrounded by two adjacent gate lines of the plurality of gate lines being insulated and overlapped with the data lines; each sub-pixel group includes two sub-pixels;

[0007] The sub-pixel groups include: a first sub-pixel group, a second sub-pixel group and a third sub-pixel group which are alternately arranged in sequence along the first direction;

[0008] Among them, the sub-pixels in the second sub-pixel group are used to emit the first color light; the two sub-pixels in the first sub-pixel group are used to emit the second color light and the third color light respectively, and the two sub-pixels in the third sub-pixel group are used to emit the second color light and the third color light respectively.

[0009] Optionally, two sub-pixels in each of the sub-pixel groups are arranged along the first direction;

[0010] Along the first direction, two sub-pixels in the first sub-pixel group are used to emit the second color light and the third color light in sequence, and two sub-pixels in the third sub-pixel group are used to emit the third color light and the second color light in sequence.

[0011] Optionally, the first color light includes blue light, the second color light includes red light, and the third color light includes green light.

[0012] Optionally, in the sub-pixel groups between adjacent gate lines, sub-pixels in the first sub-pixel group and the third sub-pixel group for emitting light of the same color are electrically connected to the gate lines on the same side, respectively.

[0013] Optionally, the sub-pixels in each of the sub-pixel groups are electrically connected to the data lines on the same side of the sub-pixel group and the gate lines on both sides of the sub-pixel group;

[0014] The sub-pixel groups arranged along the second direction and located between the same group of gate lines are electrically connected to the data lines on both sides alternately, and the sub-pixel groups arranged along the first direction and located between the same group of data lines are electrically connected to the data lines on the same side respectively.

[0015] Optionally, the gate line has a set power-on timing;

[0016] In the first sub-pixel group or the third sub-pixel group, the sub-pixels adjacent to the second sub-pixel group are used to be electrically connected to a gate line with a relatively earlier power-on timing among the gate lines adjacent to both sides of the current sub-pixel group;

[0017] In the second sub-pixel group, the sub-pixels adjacent to the first sub-pixel group are used to be electrically connected to a gate line with a relatively later power-on timing among the gate lines adjacent to both sides of the current first sub-pixel group.

[0018] Optionally, the luminous intensity of the sub-pixels in the first sub-pixel group and / or the third sub-pixel group is higher than the luminous intensity of the sub-pixels in the second sub-pixel group.

[0019] Optionally, it also includes: an integrated gate drive circuit;

[0020] The integrated gate drive circuit is used to control the power-on timing and power-on duration of each gate line;

[0021] Among them, along the second direction, the power-on timing of each gate line is set by the integrated gate driving circuit to be successively increased, and the power-on time periods of two adjacent gate lines overlap with each other and the overlapping time period of two adjacent gate lines is equal to two-thirds of the power-on time length.

[0022] Through the above embodiments, the array substrate provided by the present application has the following advantages:

[0023] The array substrate provided in the embodiment of the present application can realize the light emission of two pixel units of three primary color pixel points by means of a first sub-pixel group, a second sub-pixel group and a third sub-pixel group which are arranged alternately in sequence, and the two sub-pixels emitting the first color light are adjacently arranged between two adjacent pixel units and can realize mixed fuzzy light emission, thereby coordinating the light emission of the sub-pixels in the first sub-pixel and the third sub-pixel group on both sides, each forming a pixel unit, partially or completely solving the problem of vertical stripes in the display of the array substrate caused by uneven brightness of the sub-pixels emitting the first color light, thereby improving the display performance of the array substrate.

[0024] On the other hand, an embodiment of the present application further provides a display panel, comprising the array substrate in the above embodiment.

[0025] Optionally, it also includes: a color filter layer;

[0026] The color filter layer includes a plurality of filter units arranged in an array, and the colors of the filter color resists of the plurality of filter units correspond one to one with the luminous colors of the sub-pixels.

[0027] The display panel provided in the embodiment of the present application includes the array substrate in the above embodiment and also has all the advantages of the above array substrate.

[0028] On the other hand, an embodiment of the present application further provides a display device, comprising the display panel in the above embodiment.

[0029] The display device provided in the embodiment of the present application includes the display panel in the above embodiment and also has all the advantages of the above display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are for reference and illustration only and are not intended to limit the scope of protection of this application. The technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0031] Figure 1 A schematic diagram showing the arrangement and connection of an array substrate in an embodiment provided by the present application is shown;

[0032] Figure 2 A schematic diagram showing the effect of mixed-color luminescence in an embodiment provided by the present application is shown;

[0033] Figure 3 A schematic diagram showing another mixed-color luminescence effect in an embodiment provided by the present application is shown;

[0034] Figure 4 A schematic diagram showing another mixed-color luminescence effect in an embodiment provided by the present application is shown;

[0035] Figure 5 A schematic diagram of a timing sequence of gate power-on in an embodiment provided by the present application is shown;

[0036] Figure 6 A structural schematic diagram of a manufacturing process of an array substrate in an embodiment provided by the present application is shown;

[0037] Figure 7 A schematic diagram of the GOA principle in an embodiment provided by the present application is shown.

[0038] Description of reference numerals:

[0039] 10-first sub-pixel group; 20-second sub-pixel group; 30-third sub-pixel group; 11-first sub-pixel; 12-second sub-pixel; 13-third sub-pixel; 310-data line; 410-gate line; 500-pixel arrangement period; 101-substrate; 102-first electrode; 103-first insulating layer; 104-active layer; 105-source and drain; 106-second insulating layer; 107-second electrode. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] In display devices such as liquid crystal displays and light-emitting diode displays (LEDs), array substrates are used to complete light emission. Taking liquid crystal displays as an example, each pixel unit may include a thin film transistor and a pixel electrode, and the liquid crystal deflection operation is driven by transmitting a driving signal through a data line and a scanning signal through a gate line. For example, the data line may be connected to the source of the transistor, the gate line may be connected to the gate of the transistor, and the pixel electrode may be connected to the drain of the transistor.

[0042] As the resolution of the display panel increases, the number of data lines used to provide drive signals for each pixel unit also increases accordingly, and the performance and cost of the driver chip (Display Driver IC) that provides drive signals for the data lines also increase accordingly. The traditional single-gate line design scheme drives the pixel units arranged in an array through a one-to-one combination of gate lines and data lines. In order to reduce the cost of the driver chip and improve the binding yield of the driver chip, the relevant technology proposes to set two gate lines between each row of pixel units extending along a first direction on the display panel, and set a data line between every two columns of pixel units along a second direction intersecting with the first direction, so as to realize dual-gate drive. Specifically, in a single-gate array substrate, multiple single gate lines and multiple data lines can be insulated, overlapped and enclosed to form multiple array-arranged pixel units, and the combination of gate lines and data lines can drive the light emission of sub-pixels in different pixel units. In a dual-gate array substrate, multiple groups of dual-gate lines and multiple data lines can be insulated, overlapped and enclosed to form multiple array-arranged sub-pixel groups. Each sub-pixel group includes 2 sub-pixels, i.e., pixel points. The data lines drive two adjacent columns of pixel units, which can reduce the number of data lines by half, thereby reducing the performance requirements for the driver chip, and then reducing the cost of the array substrate and the display panel.

[0043] Compared with the gate type array substrate, the gates in the dual-gate array substrate are doubled, and the charging time of each gate line will be halved. In the array substrate with high display refresh rate such as 120Hz or 144Hz, the charging time of the gate line will be further reduced. If the charging time of each gate line is insufficient, it will lead to insufficient charge of the pixel, affecting the display performance of the array substrate. In order to ensure the charging rate of the gate line, the relevant technology proposes to pre-charge the gate line, that is, charge the gate of the previous row to open the gate of the next row in advance to write the data of the previous row, so as to realize the early charging of the charge, thereby increasing the charging rate of the gate.

[0044] Since there are differences in luminous intensity and charging between sub-pixels that emit light of different colors, it is necessary to set the electrical connection method between the sub-pixel and the gate line or data line according to the luminous color of the sub-pixel. For example, in a related technology, since the red sub-pixel and the green sub-pixel are brighter than the blue sub-pixel, if the red sub-pixel and the green sub-pixel are not opened on the same row of gates, it will easily cause the function of the array substrate to be inconsistent due to the charging difference. Therefore, in this related technology, the red sub-pixel and the green sub-pixel in the dual-gate array substrate are often designed to open the same row of gates, thereby reducing the charging difference between the sub-pixels.

[0045] However, the inventors have found that in the above-mentioned array substrate with gate precharge, when performing a mixed color display of a specific color, the difference in the precharge level between the sub-pixels emitting the same color light may cause a difference in the luminous intensity of the sub-pixels emitting the same color light, which in turn causes problems such as vertical stripes on the display screen, resulting in a decrease in the display performance of the array substrate. For example, in an array substrate provided by a related technology, the sub-pixels can be arranged in the direction of the gate line extension in the manner of RGBRGBRGB... to achieve traditional RGB combination luminescence. When performing a specific mixed color luminous display, since the gates of the sub-pixels in each row and column may have differences in the Data data corresponding to the previous row when precharging, and the levels corresponding to the precharging are different, the sub-pixels emitting the same color light will also have differences in luminous intensity. For example, the green sub-pixel and the blue sub-pixel emit light, and the red sub-pixel does not emit light, so that the display of the color of the Windows system startup screen can be realized, and the gates of the blue sub-pixels or green sub-pixels distributed in each row and column may have differences in the Data data corresponding to the previous row when precharging. Specifically, when the sub-pixel point corresponding to the previous row of the current sub-pixel is a red sub-pixel, the written Data is low, the charge written by the pre-charge of the current sub-pixel is insufficient, and the luminous intensity is low. When the sub-pixel point corresponding to the previous row of the current sub-pixel is not a red sub-pixel, the written Data is high, the charge written by the pre-charge of the current sub-pixel is insufficient, and the luminous intensity is high. When the blue sub-pixel is not turned on at the same time as the red sub-pixel or the green sub-pixel, a column of blue sub-pixels may be brighter and the adjacent column of blue sub-pixels may be darker, which may cause vertical stripes on the array substrate and the display panel.

[0046] In order to improve the above-mentioned problems, the embodiments of the present application provide an array substrate, a display panel and a display device, which abandon the traditional pixel arrangement method of RGBRGBRGB... In a dual-gate array substrate, the light emission of two pixel units of three primary color pixels is realized by a first sub-pixel group, a second sub-pixel group and a third sub-pixel group that are alternately arranged in sequence, and the two sub-pixels emitting the first color light are adjacently arranged between two adjacent pixel units and can realize mixed fuzzy light emission, so as to cooperate with the light emission of the sub-pixels in the first sub-pixel and the third sub-pixel group on both sides, each forming a pixel unit, and partially or completely solving the problem of vertical stripes on the display of the array substrate caused by uneven brightness of the sub-pixels emitting the first color light, thereby improving the display performance of the array substrate.

[0047] The embodiments of the present application are described below with reference to the accompanying drawings.

[0048] like Figure 1 As shown, Figure 1 FIG. 1 shows a schematic diagram of the arrangement and connection of an array substrate in an embodiment provided by the present application. Figure 1 An embodiment of the present application provides an array substrate, comprising: a plurality of data lines 310 arranged along a first direction, a plurality of gate lines 410 arranged along a second direction, and a plurality of sub-pixel groups in which two adjacent gate lines among the plurality of gate lines 410 are insulated and overlapped with the data lines 310.

[0049] Each sub-pixel group includes two sub-pixels.

[0050] In an optional implementation, two sub-pixels in each sub-pixel group may be arranged along the first direction.

[0051] Specifically, the data line 310 can be electrically connected to the sub-pixel to provide a data signal, including Figure 1 The gate line 410 can be electrically connected to the sub-pixel to provide a scanning signal, including Figure 1 gate1, gate2, etc.

[0052] The first direction intersects with the second direction. Specifically, the first direction and the second direction may be perpendicular to each other. For ease of understanding, the first direction may be defined as a direction extending in a transverse direction, and the second direction may be defined as a direction extending in a longitudinal direction.

[0053] Specifically, two adjacent gate lines 410 may form a gate line group in pairs, and a gate line group may be provided between adjacent sub-pixel groups arranged along the second direction to implement a dual-gate array substrate, whereby the gate line group may be electrically connected to the sub-pixels on both sides.

[0054] The sub-pixel groups include: a first sub-pixel group 10, a second sub-pixel group 20 and a third sub-pixel group 30 which are alternately arranged in sequence along a first direction.

[0055] The sub-pixels in the second sub-pixel group 20 are used to emit the first color light.

[0056] The two sub-pixels in the first sub-pixel group are used to emit the second color light and the third color light respectively, and the two sub-pixels in the third sub-pixel group are used to emit the second color light and the third color light respectively.

[0057] Accordingly, the sub-pixel emitting the first color light may be the first sub-pixel 11 , the sub-pixel emitting the second color light may be the second sub-pixel 12 , and the sub-pixel emitting the first color light may be the third sub-pixel 13 .

[0058] Exemplarily, a sub-pixel emitting blue light may be a blue sub-pixel.

[0059] Considering that the sub-pixel can realize the light emission of the pixel unit by combining three primary colors, in some optional embodiments, the first color light, the second color light and the third color light can be one of red light, green light and blue light respectively. Among them, any pixel unit can include a first sub-pixel 11, a second sub-pixel 12 and a third sub-pixel 13.

[0060] Exemplarily, the first sub-pixel group 10, the second sub-pixel group 20 and the third sub-pixel group 30 are alternately arranged in sequence along the first direction, and the arrangement of the sub-pixels along the first direction can be based on six sub-pixels in the first sub-pixel group 10, the second sub-pixel group 20 and the third sub-pixel group 30 as one pixel arrangement period 500. Exemplarily, the arrangement of the sub-pixels along the first direction in each pixel arrangement period 500 can be the second sub-pixel 12, the third sub-pixel 13, the first sub-pixel 11, the first sub-pixel 11, the third sub-pixel 13, and the second sub-pixel 12.

[0061] Through the above-mentioned embodiments, the light emission of two pixel units of the three-primary color pixel point is realized by the first sub-pixel group 10, the second sub-pixel group 20 and the third sub-pixel group 30 which are alternately arranged in sequence, and the two sub-pixels emitting the first color light are adjacently arranged between two adjacent pixel units and can realize mixed fuzzy light emission, so as to cooperate with the light emission of the sub-pixels in the first sub-pixel 11 and the third sub-pixel group 30 on both sides, each forming a pixel unit, partially or completely solving the problem of vertical stripes on the display of the array substrate caused by uneven brightness of the sub-pixels emitting the first color light, thereby improving the display performance of the array substrate.

[0062] Specifically, the array substrate provided by the above embodiment can also be used for emitting light including only a first color light and another color light. For example, when only the first color light and the second color light are emitted, the first color light is emitted in a mixed and fuzzy manner, and the second color light is also emitted in a more uniform second color light after mixing along the second direction due to partial high-level pre-charging and partial low-level pre-charging, thereby achieving regional uniform light emission, avoiding the occurrence of vertical stripes and other display defects, improving the light emission uniformity of the array substrate, and improving the display performance of the array substrate.

[0063] like Figure 2 As shown, Figure 2 FIG. 1 is a schematic diagram showing a mixed color luminescence effect in an embodiment provided by the present application. Figure 2 , the present application exemplarily proposes a mixed color luminescence method, in which the first sub-pixel 11 and the third sub-pixel group 30 emit light together. Since the first sub-pixel 11 in a column adjacent to data2 is pre-charged and written with the high-level data signal of the first sub-pixel 11 in another column, the luminous intensity is relatively high, which is indicated by "good" in the figure. Since the first sub-pixel 11 in a column adjacent to data3 is pre-charged and written with the low-level data signal of the second sub-pixel 12 on both sides, the luminous intensity is relatively low, which is indicated by "bad" in the figure. The two columns of first sub-pixels 11 can achieve mixed fuzzy luminescence and harmonize the luminous brightness with each other, while the third sub-pixel 13 is partially pre-charged and written with the low-level signal of the second sub-pixel 12, and partially pre-charged and written with the high-level signal of the first sub-pixel 11, which has "good" and "bad" and presents periodic changes along the second direction, and can also achieve the luminous brightness harmony between adjacent rows, thereby achieving visually uniform luminescence.

[0064] like Figure 3 As shown, Figure 3 FIG. 2 is a schematic diagram showing another mixed color luminescence effect in an embodiment provided by the present application. Figure 3 , the present application exemplarily proposes another mixed-color luminescence method, in which the first sub-pixel 11 and the second sub-pixel group 20 emit light together. Since the first sub-pixels 11 in a column adjacent to data2 are pre-charged and written with the high-level data signal of the first sub-pixels 11 in another column, the luminous intensity is relatively high, which is indicated by "good" in the figure. The first sub-pixels 11 in a column adjacent to data3 are pre-charged and written with the high-level data signal of the second sub-pixels 12 on both sides, and the luminous intensity is also relatively high, which is indicated by "good" in the figure. The second sub-pixel 12 is pre-charged and written with the low-level signal of the third sub-pixel 13, and the luminous brightness is relatively "poor". In this way, there are "good" first sub-pixels 11 and "poor" second sub-pixels 12 in any pixel unit, and uniform luminescence of the array substrate can be achieved.

[0065] like Figure 4 As shown, Figure 4FIG. 2 is a schematic diagram showing another mixed color luminescence effect in an embodiment provided by the present application. Figure 4 , the present application exemplarily proposes another mixed color luminescence method, in which the second sub-pixel 12 and the third sub-pixel 30 are combined to emit light. Since all the second sub-pixels 12 are pre-charged and written with the high-level data signal of the third sub-pixel 13, the luminous intensity is relatively high, which is indicated by "good" in the figure. The third sub-pixel 13 is partially pre-charged and written with the low-level signal of the first sub-pixel 11, and partially pre-charged and written with the high-level signal of the second sub-pixel 12, which has "good" and "bad" and presents periodic changes along the second direction, and can also achieve the coordination of the luminous brightness between adjacent rows, thereby achieving visually uniform luminescence.

[0066] When a single sub-pixel emits light, for example, only the first sub-pixel 11 emits light, the pre-charged signals written are all low-level signals, and the light emission intensity of all the first sub-pixels 11 is low, so uniform light emission can be achieved.

[0067] When all sub-pixels emit light, for example, the first sub-pixel 11, the third sub-pixel 13 and the second sub-pixel 12 emit light, all sub-pixels are charged and written with high-level signals, and the light emission intensity of all sub-pixels is high, and uniform light emission can also be achieved.

[0068] Sub-pixels with relatively low luminous intensity can be more conducive to achieving mixed blurred luminescence. To this end, in an optional embodiment, the present application also provides an array substrate, wherein the luminous intensity of the sub-pixels in the first sub-pixel group 10 and / or the third sub-pixel group 30 is higher than the luminous intensity of the sub-pixels in the second sub-pixel group 20.

[0069] Considering that in some related technologies of three-primary color display, compared with red sub-pixels and green sub-pixels, the luminous intensity of blue sub-pixels is lower, it can be more suitable for realizing mixed fuzzy luminescence. To this end, the first color light can be set to blue light. In some optional embodiments, the first color light includes blue light, the second color light includes red light, and the third color light includes green light.

[0070] The above embodiment does not limit the arrangement order of the second sub-pixel 12 and the third sub-pixel 13 in the second sub-pixel group 20 or the third sub-pixel group 30. Accordingly, the second color light and the third color light may also be set to one of red and green. To this end, in another optional embodiment, the first color light includes blue light, the second color light includes green light, and the third color light includes red light.

[0071] In order to further improve the display performance of the array substrate, it is possible to consider setting a symmetrical pixel arrangement within a pixel arrangement period 500. To this end, in an optional embodiment, the present application further provides an array substrate, wherein the sub-pixels in each sub-pixel group are arranged along a first direction.

[0072] Along the first direction, two sub-pixels in the first sub-pixel group 10 are used to emit the second color light and the third color light in sequence, and two sub-pixels in the third sub-pixel group 30 are used to emit the third color light and the second color light in sequence.

[0073] Through the above embodiments, since the two pixel units within a pixel arrangement period 500 can achieve symmetry of sub-pixel light emission, illustratively, for the case where only the first color light and the third color light are emitted in the dual-gate design, for example, when the first color light includes blue light, the second color light includes red light, and the third color light includes green light, only blue light and green light are emitted to achieve mixed color emission, and the blue light can achieve mixed blurred emission, and because the emission intensity of blue light is lower than that of the other two colors, the mixed blurred effect will be better. Within a pixel arrangement period 500, the green light on both sides of the blue light can partially achieve high-level pre-charging and partially achieve low-level pre-charging, and green light is emitted after mixing along the second direction, which can further achieve regional visual uniformity, thereby further avoiding display defects such as vertical stripes when the array substrate emits blue and green mixed light, such as when displaying the color of the Windows boot screen, and improving the uniformity of display emission.

[0074] Taking into account that sub-pixels of different luminous colors have different luminous intensities, in order to reduce the charging differences between sub-pixels, in an optional embodiment, the present application also provides an array substrate, wherein, in the sub-pixel group between adjacent gate lines 410, the sub-pixels for emitting light of the same color in the first sub-pixel group 10 and the third sub-pixel group 30 are electrically connected to the gate lines 410 on the same side, respectively.

[0075] Through the above embodiment, the sub-pixels emitting the same color light in the first sub-pixel group 10 and the third sub-pixel group 30 can be turned on by the gate of the same row, further reducing or avoiding the charging difference of the sub-pixels, thereby improving the light emission uniformity and display effect of the array substrate.

[0076] In order to further improve the light emitting uniformity of the array substrate, in an optional embodiment, the present application also provides an array substrate, wherein the sub-pixels in each sub-pixel group are electrically connected to the data line 310 on the same side of the sub-pixel group and the gate lines 410 on both sides of the sub-pixel group.

[0077] Subpixel groups arranged along the second direction and located between the same group of adjacent gate lines are alternately electrically connected to data lines on both sides, and subpixel groups arranged along the first direction and located between the same group of adjacent data lines are electrically connected to the data lines on the same side.

[0078] A group of gate lines may be two adjacent gate lines with a sub-pixel group disposed therebetween, and a group of data lines may be two adjacent data lines.

[0079] Through the above-mentioned embodiments, sub-pixels of the same luminous color can still be arranged along the second direction, and one sub-pixel in any sub-pixel group can be pre-charged when the gate of another sub-pixel is opened to write the data signal. Since the sub-pixel groups arranged along the second direction are alternately electrically connected to the data lines 310 on both sides, and the sub-pixel groups arranged along the first direction are respectively electrically connected to the data lines 310 on the same side, one of the sub-pixels A in the second sub-pixel group 20 is affected by the lighting of another sub-pixel B, and a high level can be written during pre-charging, thereby achieving a higher luminous brightness. The influence of sub-pixel B on whether the sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 are lit or not can be offset by mixed fuzzy light emission with sub-pixel A. Furthermore, the pre-charging of the sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 can be associated with the second sub-pixel group 20. Then, when the sub-pixels in the second sub-pixel group 20 emit light, the light-emitting brightness of the sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 can be guaranteed to a certain extent, and due to the symmetrical design, the light-emitting uniformity of the array substrate is improved.

[0080] Furthermore, for different sub-pixel group types, specific implementation methods may be included to electrically connect the sub-pixels with the gate lines 410 and the data lines 310 to form thin film transistor switches at different positions:

[0081] In an optional implementation, the gate line has a set power-on timing sequence.

[0082] In the first sub-pixel group or the third sub-pixel group, the sub-pixels adjacent to the second sub-pixel group are used to be electrically connected to a gate line with a relatively earlier power-on timing among the gate lines adjacent to both sides of the current sub-pixel group.

[0083] In some optional embodiments, the gate line power-on timing may increase sequentially along the second direction.

[0084] In the second sub-pixel group, the sub-pixels adjacent to the first sub-pixel group are used to be electrically connected to a gate line with a relatively later power-on timing among the gate lines adjacent to both sides of the current first sub-pixel group.

[0085] Through the above embodiments, the pre-charging of every other row of sub-pixels close to the second sub-pixel group 20 in the first sub-pixel group 10 or the third sub-pixel group 30 can be associated with the second sub-pixel group 20. Then, when the sub-pixels in the second sub-pixel group 20 emit light, the luminous brightness of the sub-pixels can be guaranteed to a certain extent. In addition, by setting the sub-pixels and the gate lines that are electrically connected in combination with the power-on timing of the gate lines, and combining the symmetrical design of the sub-pixels in a pixel arrangement period in the above embodiments, the luminous uniformity of the sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 can also be improved, thereby improving the luminous uniformity of the array substrate and avoiding display defects such as vertical stripes.

[0086] Accordingly, in another optional implementation, in the first sub-pixel group 10 or the third sub-pixel group 30 , the sub-pixel close to the second sub-pixel group 20 is electrically connected to the gate line 410 located on one side of the sub-pixel along the second direction.

[0087] In the second sub-pixel group 20 , the sub-pixel close to the first sub-pixel group 10 is electrically connected to the gate line 410 away from the sub-pixel on one side along the second direction.

[0088] Through the above embodiments, the pre-charging of every other row of sub-pixels close to the second sub-pixel group 20 in the first sub-pixel group 10 or the third sub-pixel group 30 can be associated with the second sub-pixel group 20. Then, when the sub-pixel in the second sub-pixel group 20 is luminous, the luminous brightness of the sub-pixel can be guaranteed to a certain extent. Due to the symmetrical design, the luminous uniformity of the sub-pixels in the first sub-pixel group 10 or the third sub-pixel group 30 is improved, thereby improving the luminous uniformity of the array substrate and avoiding display defects such as vertical stripes.

[0089] like Figure 5 As shown, Figure 5 FIG. 1 shows a schematic diagram of a gate power-on timing in an embodiment provided by the present application. Figure 5 To this end, in an optional implementation, the present application further provides an array substrate, which further includes: an integrated gate drive circuit (GOA).

[0090] The integrated gate driving circuit is used to control the power-on timing and power-on duration of each gate line 410 .

[0091] Among them, along the second direction, the power-on timing of each gate line 410 is set by the integrated gate driving circuit to be successively increased, and the power-on time periods of two adjacent gate lines 410 overlap with each other and the overlapping time period of the power-on of two adjacent gate lines 410 is equal to two-thirds of the power-on time length.

[0092] Exemplarily, since the number of gate lines 410 in the dual-gate design is doubled, when the gate charging frequency is set to 100 Hz, the power-on time of any gate line 410 excluding pre-charging is 1H, which can be 4.6us, and the power-on time including pre-charging can be 3 times of 4.6us, that is, 3H.

[0093] Each data line 310 also has a corresponding level, such as V1 and V2, for writing data signals.

[0094] The above embodiment can improve the charging efficiency of the gate line 410 through pre-charging, avoid the situation where the pixel charge is insufficient, and ensure the display performance of the array substrate. In addition, combined with the above embodiment, the charging difference between different sub-pixels and the pre-charging difference caused by the color mixing effect of the two sub-pixels have been avoided to a certain extent, ensuring the uniformity of the light emission of the array substrate.

[0095] The embodiment of the present application also provides an example of GOA driving, in which when the Gate side adopts the GOA design, the Data signal is halved under the DualGate design, so that the Data COF on the Source side is halved, reducing the production cost. The corresponding principle is explained by taking the 19T1C GOA architecture as an example. Figure 7 , Figure 7 FIG. 2 shows a schematic diagram of a GOA principle in an embodiment provided by the present application. Figure 7 As shown,

[0096] When STV1 comes, the entire GOA is prompted to start working, connect to the Input, M1 is turned on, VGH charges the PU point, and CLK1 is low at this time.

[0097] When CLK1 becomes high level, due to the effect of C capacitor, PU becomes higher, thereby turning on M13 and M13, outputting CLK high level, GOUT and GOUTC output high level respectively.

[0098] The output GOUT opens the gate to charge the pixels in the AA area, and the output GOUTC is given to the next row as INPUT, and the outputs are output in sequence to realize the function of GOA (shift register).

[0099] GOUT and GOUTC are separated because GOUT is used to open the gate of the AA area to charge the AA area, and GOUTC is used as a shift register cascade signal, which does not affect the AA area and only works for GOA.

[0100] VDD1 and VDD2 are staggered to control PD. When PU is low, PD can reduce noise, making PU low so as not to affect OUT. This is equivalent to two sets of circuits staggered to control PD (VDD2 is low when VDD1 is high, and VDD1 is low when VDD2 is high). The purpose of staggering VDD1 and VDD2 is because TFT will be damaged if it is affected by bias (always high level).

[0101] Taking the FHD (1920*1080) pixel resolution Dual Gate array substrate as an example, there are 1080 rows of Gate in total, and DualGate doubles to 2160 rows of Gate. The 6CLK GOA Gate1 to Gate2160 are output in sequence with a 6CLK cycle. Figure 5 As shown, the Precharge time is increased by 2H, the high and low levels are 3H respectively, and the written Data signal is 1H.

[0102] Through the above embodiments, the array substrate provided by the present application uses a dual-gate design. On the basis of a pixel arrangement using Z-inversion on the substrate 101 on one side of the TFT, three sub-pixel groups along the first direction are used as a pixel arrangement period 500. A pixel arrangement period 500 includes two pixel units. The first sub-pixels 11 of the two pixel units are adjacent and located in the same sub-pixel group. The mixed fuzzy light emission of the first sub-pixels 11 can be effectively avoided to avoid the problem of uneven brightness caused by the difference in pre-charge levels, thereby achieving uniform light emission of the array substrate.

[0103] like Figure 6 As shown, Figure 6 FIG. 1 is a schematic diagram showing a structure of an array substrate in a manufacturing process in an embodiment provided by the present application. Figure 6 Based on the same inventive concept, the embodiment of the present application further provides a method for manufacturing an array substrate, comprising:

[0104] Step S601 , providing a substrate 101 , and manufacturing a first electrode 102 on the substrate 101 .

[0105] The substrate 101 may be a glass substrate.

[0106] The first electrode 102 may be a common electrode, and the material may be indium tin oxide (ITO). The common electrode may be patterned by coating, exposure, development, and wet etching in sequence, and may be a whole pattern in a sub-pixel.

[0107] Step S602 , forming a gate line 410 on the first electrode 102 , and forming a first insulating layer 103 on the gate line 410 .

[0108] The material of the gate line 410 may include Mo—Al—Mo, and the pattern of the gate line 410 may be formed by coating, exposure, development, and wet etching in sequence. The first insulating material may include SiNx.

[0109] Specifically, the first insulating layer 103 may be a gate insulating layer.

[0110] Step S603 , forming an active layer 104 on the first insulating layer 103 , and forming source and drain electrodes 105 on the active layer 104 .

[0111] Specifically, through step S603, a mask (4Mask) process can be adopted to form the source and drain electrodes 105, the channel and the Tx line of the TFT through one dry etching and one wet etching to form the TFT.

[0112] Among them, the 4Mask process can deposit the active layer and the source and drain electrodes 105 together, and only one mask is performed after coating the PR glue, so as to form a partial exposure in the channel area. Among them, the source electrode can be etched out first, and the channel can be exposed after ashing.

[0113] Step S604 , forming a second insulating layer 106 on the source and drain electrodes 105 .

[0114] The second insulating layer 106 may be an inorganic layer (PVX) and may include SiNx, which may be obtained by exposure, development and etching. It may also be provided with vias, including connecting vias for pixel electrodes and half vias for electrically connecting gates or data lines 310 to sub-pixels.

[0115] Step S605 , forming a second electrode 107 on the second insulating layer 106 .

[0116] The second electrode 107 may be a pixel electrode, may include indium tin oxide, and may be patterned by plating, exposure, development, and wet etching.

[0117] Through the above embodiments, the method for manufacturing the array substrate provided by the present application has the following advantages:

[0118] (1) The array substrate manufactured by the method in the above embodiment also has all the advantages of the array substrate in the above embodiment.

[0119] (2) The above-mentioned manufacturing method can be based on the manufacturing method provided by the relevant technology, without changing the manufacturing process of each stacked layer. It can improve the light uniformity of the array substrate by only changing the arrangement and position of the sub-pixels, reduce or avoid the display defects such as vertical stripes, thereby improving the display performance of the array substrate. It has the characteristics of simplicity, high efficiency and low cost, and is conducive to the large-scale production of array substrates.

[0120] Based on the same inventive concept, an embodiment of the present application further provides a display panel, including the array substrate in the above embodiment.

[0121] To this end, in an optional implementation, the present application further provides an array substrate, wherein the array substrate further includes: a color filter layer.

[0122] The color filter layer includes a plurality of filter units arranged in an array, and the colors of the filter color resists of the plurality of filter units correspond one to one to the luminous colors of the sub-pixels.

[0123] Specifically, the color filter layer, ie, the color filter film, the filter color resist may include a red filter color resist, a green filter color resist, and a blue filter color resist.

[0124] Exemplarily, the red filter color resist may correspond to a red sub-pixel.

[0125] Through the above embodiments, the color filter layer can adopt a corresponding color resistance arrangement, and two pixel units are composed of six sub-pixels arranged along the first direction. Each pixel unit is also composed of RGB color resistance to ensure the basic luminous display function of the display panel.

[0126] In an optional example, corresponding to the arrangement of sub-pixels in the array substrate, the color filter layer can adopt a color resistance arrangement of RGBBGR. Table 1 is a color resistance arrangement table provided in an embodiment of the present application. Referring to Table 1, the color resistances of the data lines 3101 to 3106 in the same row are RGBBGR respectively, and the light emission of the two pixel units RGB and BGR can be realized respectively.

[0127]

[0128] In the embodiment of the present application, the one-to-one correspondence between the color of the filter color resist of the filter unit and the luminous color of the sub-pixel may refer to the correspondence between the filter color resist of the filter unit and the luminous light path of the sub-pixel.

[0129] Furthermore, the orthographic projection of the filter color resist of the filter unit on the array substrate may overlap with the sub-pixel of the corresponding luminous color.

[0130] The embodiment of the present application further provides a display panel, comprising an array substrate manufactured by the method in the above embodiment.

[0131] Based on the same inventive concept, an embodiment of the present application further provides a display device, comprising the display panel in the above embodiment.

[0132] Specifically, the display panel may include an LCD display panel, and specifically may also include a TFT-LCD display panel.

[0133] Specifically, considering that the array substrate in the above embodiments can be used to avoid failures in the display function or touch function of the display device, thereby improving the display effects of various display products, the display device may include display panels, smart watches, mobile phones, tablet computers, display screens of VR devices, or computer monitors and other products.

[0134] Based on the same inventive concept, an embodiment of the present application further provides a display device, where the display device includes the display apparatus in the above embodiment.

[0135] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0136] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0137] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0138] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0139] In this application, the terms "comprises", "includes" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or terminal device including the element.

[0140] Finally, it should be noted that specific examples are used herein to illustrate the principles and implementation methods of the present application, and the description of the above embodiments is only used to help understand the technical solution and its core ideas of the present application. Although the preferred embodiments of the present application have been described, once the technical personnel in the field know the basic creative concepts, they can make additional changes and modifications to these embodiments. Therefore, the attached claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: A plurality of data lines arranged along a first direction, a plurality of gate lines arranged along a second direction, and a plurality of sub-pixel groups surrounded by two adjacent gate lines of the plurality of gate lines being insulated and overlapped with the data lines; Each sub-pixel group includes two sub-pixels; The sub-pixel groups include: a first sub-pixel group, a second sub-pixel group and a third sub-pixel group which are alternately arranged in sequence along the first direction; Among them, the sub-pixels in the second sub-pixel group are used to emit the first color light; the two sub-pixels in the first sub-pixel group are used to emit the second color light and the third color light respectively, and the two sub-pixels in the third sub-pixel group are used to emit the second color light and the third color light respectively.

2. The array substrate according to claim 1, characterized in that: The two sub-pixels in each of the sub-pixel groups are arranged along the first direction; Along the first direction, two sub-pixels in the first sub-pixel group are used to emit the second color light and the third color light in sequence, and two sub-pixels in the third sub-pixel group are used to emit the third color light and the second color light in sequence.

3. The array substrate according to claim 2, characterized in that: The first color light includes blue light, the second color light includes red light, and the third color light includes green light.

4. The array substrate according to claim 1, characterized in that: In the sub-pixel groups between adjacent gate lines, the sub-pixels in the first sub-pixel group and the third sub-pixel group for emitting light of the same color are electrically connected to the gate lines on the same side, respectively.

5. The array substrate according to claim 4, characterized in that: The sub-pixels in each of the sub-pixel groups are electrically connected to the data lines on the same side of the sub-pixel group and the gate lines on both sides of the sub-pixel group; The sub-pixel groups arranged along the second direction and located between the same group of gate lines are electrically connected to the data lines on both sides alternately, and the sub-pixel groups arranged along the first direction and located between the same group of data lines are electrically connected to the data lines on the same side respectively.

6. The array substrate according to claim 5, characterized in that: The gate line has a set power-on timing; In the first sub-pixel group or the third sub-pixel group, the sub-pixels adjacent to the second sub-pixel group are used to be electrically connected to a gate line with a relatively earlier power-on timing among the gate lines adjacent to both sides of the current sub-pixel group; In the second sub-pixel group, the sub-pixels adjacent to the first sub-pixel group are used to be electrically connected to a gate line with a relatively later power-on timing among the gate lines adjacent to both sides of the current first sub-pixel group.

7. The array substrate according to claim 1, characterized in that: The luminous intensity of the sub-pixels in the first sub-pixel group and / or the third sub-pixel group is higher than the luminous intensity of the sub-pixels in the second sub-pixel group.

8. The array substrate according to any one of claims 1 to 7, characterized in that: Also includes: Integrated gate drive circuit; The integrated gate drive circuit is used to control the power-on timing and power-on duration of each gate line; Among them, along the second direction, the power-on timing of each gate line is set by the integrated gate driving circuit to be successively increased, and the power-on time periods of two adjacent gate lines overlap with each other and the overlapping time period of two adjacent gate lines is equal to two-thirds of the power-on time length.

9. A display panel, characterized in that: include: An array substrate as claimed in any one of claims 1 to 8.

10. The display panel according to claim 9, characterized in that: Also includes: Color filter layer; The color filter layer includes a plurality of filter units arranged in an array, and the colors of the filter color resists of the plurality of filter units correspond one to one with the luminous colors of the sub-pixels.

11. A display device, characterized in that: include: A display panel as claimed in any one of claims 9 to 10.

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