Display panels and display devices

Abstract

This application discloses a display panel and display device. Scan lines and data line groups are intersected to form multiple pixel regions, and a pixel electrode group is correspondingly disposed in a pixel region. Each data line group includes a first data line and a second data line, and each pixel electrode group includes a first pixel electrode and a second pixel electrode. In a first direction, the first pixel electrode and the second pixel electrode are alternately arranged, as are the first data line and the second data line. The first data line connects to the second pixel electrode of the first pixel row and the first pixel electrode of the second pixel row, and the second data line connects to the first pixel electrode of the first pixel row and the second pixel electrode of the second pixel row. The display panel and display device of this application adopt a data line group layout, which reduces the wiring area in the first direction to improve the aperture ratio.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] Based on the patent document disclosed in CN108628049B, the data lines are designed in a rectangular wave shape due to the indentation between adjacent sub-pixel regions and the row alignment arrangement with intervals. Furthermore, since a data line is provided between every two adjacent sub-pixel regions, and a distance needs to be set from both sides of each data line to the adjacent pixel electrode, the wiring area of ​​the data line is increased, thereby reducing the aperture ratio. Summary of the Invention

[0003] This application provides a display panel and display device that can improve the aperture ratio.

[0004] This application provides a display panel, including an array substrate and a counter substrate disposed opposite to the array substrate, wherein the array substrate includes:

[0005] Multiple scan lines and multiple data line groups are provided, with the data line groups arranged along a first direction, the scan lines extending along the first direction, and the multiple scan lines arranged along a second direction intersecting the first direction; the multiple scan lines and multiple data line groups are intersected to form multiple pixel regions; and

[0006] Multiple pixel electrode groups are provided, with one pixel electrode group correspondingly disposed in one pixel region. The multiple pixel electrode groups are arranged along a first direction to form a pixel row. The pixel row includes a first pixel row and a second pixel row, which are arranged along a second direction. In the second direction, a pixel electrode group of the first pixel row is correspondingly disposed between two adjacent pixel electrode groups of the second pixel row.

[0007] Each of the data line groups includes a first data line and a second data line, and each of the pixel electrode groups includes a first pixel electrode and a second pixel electrode. In the first direction, the first pixel electrode and the second pixel electrode are arranged alternately, and the first data line and the second data line are arranged alternately. The first data line connects the second pixel electrode of the first pixel row and the first pixel electrode of the second pixel row, and the second data line connects the first pixel electrode of the first pixel row and the second pixel electrode of the second pixel row.

[0008] Optionally, in some embodiments of this application, the first data line includes a first routing portion, a second routing portion, and a third routing portion. The first routing portion is correspondingly disposed in the first pixel row, the third routing portion is correspondingly disposed in the second pixel row, and the second routing portion is correspondingly disposed between the first pixel row and the second pixel row and connected to the first routing portion and the third routing portion. The second data line includes a fourth routing portion, a fifth routing portion, and a sixth routing portion. The fourth routing portion is correspondingly disposed in the first pixel row, the sixth routing portion is correspondingly disposed in the second pixel row, and the fifth routing portion is correspondingly disposed between the first pixel row and the second pixel row and connected to the fourth routing portion and the sixth routing portion.

[0009] The first trace portion is connected to the second pixel electrode of the first pixel row, the third trace portion is connected to the first pixel electrode of the second pixel row, the fourth trace portion is connected to the first pixel electrode of the first pixel row, and the sixth trace portion is connected to the second pixel electrode of the second pixel row.

[0010] In the first direction, the second trace portion is located on one side of the fifth trace portion, and in the second direction, the second trace portion and the fifth trace portion are arranged without overlap.

[0011] Optionally, in some embodiments of this application, the first trace, the third trace, the fourth trace, and the sixth trace all extend along the second direction, and the second trace and the fifth trace all extend along the first direction;

[0012] In the first direction, the second wiring portion and the fifth wiring portion are aligned.

[0013] Optionally, in some embodiments of this application, the opposing substrate includes a black matrix layer, the black matrix layer includes a first light-shielding strip and a second light-shielding strip, the first light-shielding strip extends along a first direction, the second light-shielding strip extends along a second direction, and a plurality of the first light-shielding strips and a plurality of the second light-shielding strips are cross-connected to form a plurality of openings, a portion of the plurality of openings is facing the first pixel electrode, and another portion of the plurality of openings is facing the second pixel electrode;

[0014] The second light-shielding strip includes a first light-shielding part and a second light-shielding part. In the first direction, the width of the first light-shielding part is greater than the width of the second light-shielding part. In the first direction, the first light-shielding part and the second light-shielding part are arranged alternately. In the second direction, the first light-shielding part and the second light-shielding part are connected alternately.

[0015] In the display panel viewed from above, the first light-shielding strip covers the scan line, the second trace portion, and the fifth trace portion. The first light-shielding portion covers the portion of the data line group located between two adjacent groups of pixel electrode groups in the first direction. The second light-shielding portion covers the area between the first pixel electrode and the second pixel electrode in the pixel electrode group.

[0016] Optionally, in some embodiments of this application, the array substrate further includes a plurality of thin-film transistor groups. The thin-film transistor groups are disposed between two adjacent pixel electrode groups and located in the corner region of the pixel electrode groups. Each thin-film transistor group includes a first thin-film transistor and a second thin-film transistor. The control terminals of the first thin-film transistor and the second thin-film transistor are connected to the scan line. The input terminal of the first thin-film transistor is connected to the first data line, and the input terminal of the second thin-film transistor is connected to the second data line. In the first pixel row, the output terminal of the first thin-film transistor is connected to the second pixel electrode, and the output terminal of the second thin-film transistor is connected to the first pixel electrode. In the second pixel row, the output terminal of the first thin-film transistor is connected to the first pixel electrode, and the output terminal of the second thin-film transistor is connected to the second pixel electrode.

[0017] The first thin-film transistor and the second thin-film transistor are arranged alternately in a row along the first direction; in each group of thin-film transistors, the first thin-film transistor is disposed on the side of the first data line away from the second data line, and the second thin-film transistor is disposed on the side of the second data line away from the first data line.

[0018] Optionally, in some embodiments of this application, the display panel further includes a plurality of spacers, and the array substrate includes a common trace extending along the first direction, the common trace and the spacers being disposed between the first pixel row and the second pixel row;

[0019] In the display panel viewed from above, at least one of the common trace, the scan line, and the data line group partially overlaps with the spacer, which is located at the intersection of the first light-shielding strip and the second light-shielding strip.

[0020] Optionally, in some embodiments of this application, a third light-shielding portion is connected to both sides of the intersection of the first light-shielding strip and the second light-shielding strip; in the display panel from a top-view perspective, the third light-shielding portion and portions of the first light-shielding strip and the second light-shielding strip respectively connected to the third light-shielding portion cover the padding material as a whole.

[0021] Optionally, in some embodiments of this application, each pixel region is a dual-pixel domain region, with the first pixel electrode and the second pixel electrode each corresponding to one pixel domain region.

[0022] Optionally, in some embodiments of this application, the display panel further includes a plurality of spacers adjacent to the scan lines. In the display panel viewed from above, in the first direction, the first data line and the second data line in the same data line group partially overlap with the same spacer.

[0023] Each pixel region is a four-pixel domain region, and the four pixel domain regions are arranged in a matrix along the first direction and the second direction. In the second direction, the liquid crystal tilt directions of the two pixel domain regions are different.

[0024] The array substrate also includes a common trace that extends along the first direction. In the display panel viewed from above, the common trace is disposed between two adjacent pixel domains in the second direction.

[0025] Optionally, in some embodiments of this application, in the first direction, third light-shielding parts are connected to both sides of the first light-shielding part, and in the display panel from a top-view perspective, the first light-shielding part and the third light-shielding parts on both sides are used as a whole to cover the pad.

[0026] Optionally, in some embodiments of this application, the spacer is formed on the opposing substrate, and in the display panel viewed from above, the spacer is located outside the thin-film transistor array.

[0027] Optionally, in some embodiments of this application, the spacer is formed on the opposing substrate, and the array substrate includes an alignment film whose alignment direction is parallel to the first direction.

[0028] Optionally, in some embodiments of this application, multiple pixel electrode groups are co-formed on the pixel electrode layer, and the array substrate further includes a common electrode layer. The pixel electrode layer and the common electrode layer are co-formed on different layers. The common electrode layer includes multiple common electrodes, and one of the common electrodes is correspondingly disposed in one of the pixel regions. In the display panel from a top-view perspective, one of the common electrodes simultaneously overlaps with the first pixel electrode and the second pixel electrode of the same pixel electrode group.

[0029] A slit is provided in the pixel electrode group and the common electrode closer to the opposing substrate; in the pixel electrode group of the display panel from a top view, the pattern formed by all the slits in the first pixel electrode and the pattern formed by all the slits in the second pixel electrode are axially symmetrical to each other.

[0030] Accordingly, this application also provides a display device, which includes the display panel described in any of the above embodiments.

[0031] The display panel and display device of this application adopt a data line group layout, so that there is no data line between the first pixel electrode and the second pixel electrode in the pixel electrode group, which greatly reduces the distance between the first pixel electrode and the second pixel electrode in the pixel electrode group. Although a data line is added between the pixel electrode groups, the small distance between the first data line and the second data line reduces the wiring area in the first direction, thereby improving the aperture ratio. Attached Figure Description

[0032] Figure 1 This is a top view schematic diagram of the display panel provided in the embodiment of this application;

[0033] Figure 2 This is a cross-sectional view of the display panel provided in an embodiment of this application;

[0034] Figure 3 yes Figure 1 An enlarged schematic view of part M in the diagram;

[0035] Figure 4 yes Figure 3 Schematic diagram of the common electrode structure;

[0036] Figure 5 This is a schematic diagram of a display panel frame provided in an embodiment of this application;

[0037] Figure 6 Based on Figure 3 A schematic diagram of the structure of the black matrix layer;

[0038] Figure 7 yes Figure 1 Another enlarged schematic view of section M;

[0039] Figure 8 Based on Figure 7 A schematic diagram of the structure of the black matrix layer;

[0040] Figure 9 yes Figure 1 Another enlarged schematic view of part M in the diagram;

[0041] Figure 10 Based on Figure 9 A schematic diagram of the structure of the black matrix layer;

[0042] Figure 11 yes Figure 1 Another enlarged schematic view of part M in the diagram;

[0043] Figure 12 yes Figure 11 Schematic diagram of the common electrode structure;

[0044] Figure 13 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0045] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific implementation methods described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, the embodiments can be combined with each other but will not be described in detail one by one. Unless otherwise stated, the directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device; the terms "first," "second," "third," etc. are only used as markings and do not impose numerical requirements or establish a sequence.

[0046] This application provides a display panel and a display device, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0047] exist Figure 1 and Figure 2 In the first direction F1, it may be a direction parallel to one side of the display panel 100 in a plan view, and for example, it may be the lateral direction of the display panel 100. The second direction F2 may be a direction parallel to the other side of the display panel 100 in a plan view, and it may be the longitudinal direction of the display panel 100. The third direction F3 may be the thickness direction of the display panel 100. Optionally, in some embodiments, the first direction F1 and the second direction F2 may not intersect perpendicularly.

[0048] The display panel 100 may have a rectangular shape in a plan view, but the implementation is not limited to this. In some embodiments, the display panel 100 may have a rectangular shape with vertical corners or rounded corners in a plan view. The display panel 100 may include two short sides arranged in a first direction F1 and two long sides arranged in a second direction F2 in a plan view.

[0049] It should be noted that, according to the embodiment, the display panel 100 is a liquid crystal display panel, which includes an array substrate 10, an opposing substrate 20, and liquid crystal disposed between the array substrate 10 and the opposing substrate 20. Optionally, the array substrate 10 can be a driving architecture based on fringe field switching (FFS) technology, an in-plane switching (IPS) technology, vertical alignment (VA) technology, or a twisted nematic (TN) technology, etc. Optionally, the opposing substrate 20 may have a color filter layer formed on it, or it may not have a color filter layer; for example, the color filter layer may be formed in the array substrate 10.

[0050] Please refer to Figure 2 The display panel 100 of the following embodiment will be described based on the edge field switching technology driving architecture of the array substrate 10.

[0051] In some embodiments, the array substrate 10 and the opposing substrate 20 are disposed opposite to each other. The array substrate 10 includes a first substrate 11, a thin film transistor structure layer 12, a pixel electrode layer 13, a common electrode layer 14, and an alignment film 15. The opposing substrate 20 includes a second substrate 21 and a black matrix layer 22, the black matrix layer 22 being disposed on the side of the second substrate 21 near the array substrate 10.

[0052] It should be noted that the pixel electrode layer 13 and the common electrode layer 14 are disposed in different layers. The pixel electrode layer 13 can be disposed in the same layer as one of the thin film layers in the thin film transistor structure layer 12, or it can be disposed in a different layer from the thin film transistor structure layer 12. In the embodiments of this application, there are no restrictions on the positional relationship between the film layers 13, the common electrode layer 14 and the thin film transistor structure layer 12, as long as the edge field switching technology can be satisfied.

[0053] The embodiments described below with reference to the accompanying drawings will be described in detail, but are not limited thereto.

[0054] exist Figure 2In the first substrate 11, a thin film transistor structure layer 12 is disposed on the first substrate 11, a pixel electrode layer 13 is disposed on the same layer as the data lines (12a and 12b) in the thin film transistor structure layer 12, an insulating layer 16 covers the pixel electrode layer 13 and the thin film transistor structure layer 12, a common electrode layer 14 is disposed on the side of the insulating layer 16 away from the first substrate 11, and an alignment film 15 is disposed on the side of the common electrode layer 14 away from the first substrate 11.

[0055] It should be noted that the thin-film transistor structure layer 12 includes multiple thin-film transistors (t1 and t2), and the multiple thin-film transistors can be at least one of top-gate type, bottom-gate type, dual-gate type, and vertical channel type.

[0056] exist Figure 2 In this design, the source and drain of the thin-film transistor are formed directly on the active layer. The pixel electrode layer 13 is directly connected to the drain. A slit 14a is formed on the common electrode layer 14, and the slit 14a is configured to assist in adjusting the tilt angle of the liquid crystal molecules.

[0057] In some embodiments of this application, the pixel electrode layer 13 is disposed on the side of the common electrode layer 14 away from the first substrate 11, and a slit 14a is formed on the pixel electrode layer 13.

[0058] Please refer to Figure 3 , Figure 3 What is shown is Figure 1 An enlarged schematic view of part M in the diagram.

[0059] The array substrate 10 includes multiple scan lines 121, multiple data line groups 122, and multiple pixel electrode groups 131.

[0060] Multiple data line groups 122 are arranged along a first direction F1, and scan lines 121 extend along the first direction F1. Multiple scan lines 121 are arranged along a second direction F2 that intersects with the first direction F1. The multiple scan lines 121 and multiple data line groups 122 are arranged intersecting to form multiple pixel regions 1a.

[0061] A pixel electrode group 131 is correspondingly disposed in a pixel region 1a. Multiple pixel electrode groups 131 are arranged along a first direction F1 to form pixel rows, the pixel rows including a first pixel row p1 and a second pixel row p2. The first pixel row p1 and the second pixel row p2 are arranged along a second direction F2. In the second direction F2, a pixel electrode group 131 of the first pixel row p1 is correspondingly disposed between two adjacent pixel electrode groups 131 of the second pixel row p2.

[0062] Each data line group 122 includes a first data line 12a and a second data line 12b. Each pixel electrode group 131 includes a first pixel electrode 13a and a second pixel electrode 13b. In the first direction F1, the first pixel electrode 13a and the second pixel electrode 13b are arranged alternately, and the first data line 12a and the second data line 12b are arranged alternately. The first data line 12a connects to the second pixel electrode 13b of the first pixel row p1 and the first pixel electrode 13a of the second pixel row p2, and the second data line 12b connects to the first pixel electrode 13a of the first pixel row p1 and the second pixel electrode 13b of the second pixel row p2.

[0063] The display panel 100 of this application embodiment adopts a data line group 122 layout, so that there is no data line between the first pixel electrode 13a and the second pixel electrode 13b in the pixel electrode group 131, which greatly reduces the distance between the first pixel electrode 13a and the second pixel electrode 13b in the pixel electrode group 131. Although a data line is added between the pixel electrode groups 131, in the first direction F1, the distance between the two data lines (12a and 12b) in the same data line group 122 is smaller than the distance from the data line to its nearest pixel electrode. That is, the distance between the first data line 12a and the second data line 12b is smaller, thereby reducing the wiring area in the first direction F1 and improving the aperture ratio.

[0064] In some embodiments, the first data line 12a and the second data line 12b may also be configured in different layers. In the first direction F1, the first data line 12a and the second data line 12b may be smaller, and the first data line 12a and the second data line 12b may even at least partially overlap to further reduce the distance between the first data line 12a and the second data line 12b in the first direction F1 and improve the aperture ratio.

[0065] In some embodiments of this application, the array substrate 10 further includes a plurality of thin-film transistor groups 12c, which are disposed between two adjacent pixel electrode groups 131 and located in the corner region of the pixel electrode groups 131. Each thin-film transistor group 12c includes a first thin-film transistor t1 and a second thin-film transistor t2. The control terminals of the first thin-film transistor t1 and the second thin-film transistor t2 are connected to the scan line 121, the input terminal of the first thin-film transistor t1 is connected to the first data line 12a, and the input terminal of the second thin-film transistor t2 is connected to the second data line 12b. In the first pixel row p1, the output terminal of the first thin-film transistor t1 is connected to the second pixel electrode 13b, and the output terminal of the second thin-film transistor t2 is connected to the first pixel electrode 13a. In the second pixel row p2, the output terminal of the first thin-film transistor t1 is connected to the first pixel electrode 13a, and the output terminal of the second thin-film transistor t2 is connected to the second pixel electrode 13b.

[0066] The first thin-film transistor t1 and the second thin-film transistor t2 are arranged alternately in a row along the first direction F1.

[0067] It is understandable that in the same thin-film transistor group 12c, a first thin-film transistor t1 and a second thin-film transistor t2 share a gate. That is, a first thin-film transistor t1 and a second thin-film transistor t2 are grouped together side by side to form a thin-film transistor group 12c by sharing a gate, which reduces the overall layout area of ​​the thin-film transistors and thus increases the aperture ratio.

[0068] Secondly, in the first direction F1, the side-by-side arrangement of the first thin-film transistor t1 and the second thin-film transistor t2 further reduces the layout area in the second direction F2 and increases the aperture ratio.

[0069] Optionally, in some embodiments of this application, in each thin-film transistor group 12c, the first thin-film transistor t1 is disposed on the side of the first data line 12a away from the second data line 12b, and the second thin-film transistor t2 is disposed on the side of the second data line 12b away from the first data line 12a.

[0070] Understandably, by placing the data line group 122 between the two thin-film transistors in the thin-film transistor group 12c, the distance between the first data line 12a and the second data line 12b in the data line group 122 is reduced, thereby increasing the aperture ratio.

[0071] Optionally, in some embodiments of this application, the first data line 12a includes a first routing portion a1, a second routing portion a2, and a third routing portion a3. The first routing portion a1 is correspondingly disposed in the first pixel row p1, the third routing portion a3 is correspondingly disposed in the second pixel row p2, and the second routing portion a2 is correspondingly disposed between the first pixel row p1 and the second pixel row p2 and connected to the first routing portion a1 and the third routing portion a3. The second data line 12b includes a fourth routing portion b1, a fifth routing portion b2, and a sixth routing portion b3. The fourth routing portion b1 is correspondingly disposed in the first pixel row p1, the sixth routing portion b3 is correspondingly disposed in the second pixel row p2, and the fifth routing portion b2 is correspondingly disposed between the first pixel row p1 and the second pixel row p2 and connected to the fourth routing portion b1 and the sixth routing portion b3.

[0072] The first routing section a1 connects to the second pixel electrode of the first pixel row p1, the third routing section a3 connects to the first pixel electrode of the second pixel row p2, the fourth routing section b1 connects to the first pixel electrode of the first pixel row p1, and the sixth routing section b3 connects to the second pixel electrode of the second pixel row p2.

[0073] In the first direction F1, the second routing section a2 is located on one side of the fifth routing section b2. In the second direction F2, the second routing section a2 and the fifth routing section b2 are arranged without overlap.

[0074] It is understandable that arranging the second wiring section a2 and the fifth wiring section b2 along the first direction F1 can reduce their layout area in the second direction F2 and increase the opening ratio.

[0075] Optionally, in some embodiments of this application, the first trace a1, the third trace a3, the fourth trace b1, and the sixth trace b3 all extend along the second direction F2. The second trace a2 and the fifth trace b2 both extend along the first direction F1. In the first direction F1, the second trace a2 and the fifth trace b2 are aligned.

[0076] It is understandable that the second wiring section a2 and the fifth wiring section b2 are aligned and overlapped in the first direction F1, so that the layout area of ​​the second wiring section a2 and the fifth wiring section b2 in the second direction F2 is further reduced, thereby increasing the opening ratio.

[0077] Optionally, in some embodiments of this application, the display panel 100 further includes a plurality of spacers 17. The spacers 17 are adjacent to the scan lines 121. In the display panel 100 viewed from above, in the first direction F1, the first data line 12a and the second data line 12b in the same data line group 122 partially overlap with the same spacer 17.

[0078] It is understood that the spacer 17 can be formed on the array substrate 10 or on the opposing substrate 20. The spacer 17 is disposed between the first data line 12a and the second data line 12b, and extends to the left and right such that the spacer 17 partially overlaps with the first data line 12a and the second data line 12b of the data line group 122, so as to reduce the light-transmitting area occupied by the spacer 17 and thereby improve the aperture ratio.

[0079] Optionally, in the first direction F1, the width of the spacer 17 is less than or equal to the width of the data cable group 122, that is, the spacer 17 is completely set within the layout area of ​​the data cable group 122, avoiding the spacer 17 occupying additional layout area, so as to improve the opening ratio.

[0080] Optionally, in some embodiments of this application, the spacer 17 is formed on the opposing substrate 20. In the display panel 100 viewed from above, the spacer 17 is located outside the thin-film transistor group 12c.

[0081] Understandably, since the terrain of the thin-film transistor array 12c is relatively uneven, if the spacer 17 is correspondingly placed at the thin-film transistor array 12c, the contact area between the spacer 17 and the array substrate 10 will be small, reducing the support performance of the spacer 17. Therefore, the spacer 17 is placed on the outside of the thin-film transistor array 12c to increase the contact area between the spacer 17 and the array substrate 10, thereby improving the support performance of the spacer 17.

[0082] Optionally, in some embodiments of this application, a spacer 17 is formed on the opposing substrate 20. The array substrate 10 includes an alignment film 15, the alignment direction of which is parallel to a first direction F1.

[0083] It is important to understand that under the action of external force, the spacer 17 and the array substrate 10 will slide relative to each other. When the spacer 17 slides along the left and right direction (first direction F1), compared to the sliding direction of the spacer 17 being perpendicular to the alignment direction of the alignment film 15, the sliding direction of the spacer 17 is the same as the alignment direction of the alignment film 15. This can reduce the interference of the spacer 17 on the alignment direction of the alignment film 15, thereby reducing the risk of red and blue spots.

[0084] Optionally, in some embodiments of this application, each pixel region 1a is a four-pixel domain region, and the four pixel domain regions are arranged in a matrix along the first direction F1 and the second direction F2. In the second direction F2, the liquid crystal tilt directions of the two pixel domain regions are different.

[0085] The array substrate 10 also includes a common trace 124, which extends along a first direction F1. In the display panel 100 viewed from above, the common trace 124 is disposed between two adjacent pixel domains in a second direction F2.

[0086] It is important to understand that the liquid crystals in the two pixel domains are tilted in different directions, resulting in an irregular arrangement of liquid crystal molecules at the boundary between the two pixel domains, which easily leads to the formation of dark patterns. Therefore, by placing the common trace 124 at the boundary between the two pixel domains, dark patterns can be used to cover the common trace 124, thereby improving the aperture ratio.

[0087] In some embodiments of this application, multiple pixel electrode groups 131 are co-formed on the pixel electrode layer 13. The array substrate 10 also includes a common electrode layer 14 connected to a common trace 124. The pixel electrode layer 13 and the common electrode layer 14 are co-formed. The common electrode layer 14 includes multiple common electrodes 141, with one common electrode 141 correspondingly disposed within a pixel region 1a. In the display panel 100 viewed from above, one common electrode 141 simultaneously overlaps with the first pixel electrode 13a and the second pixel electrode 13b of the same pixel electrode group 131.

[0088] A slit 14a is provided on the one closer to the opposing substrate 20 between the pixel electrode group 131 and the common electrode 141.

[0089] Combination Figure 2 Since the common electrode 141 is closer to the opposing substrate 20, the slit 14a is formed on the common electrode 141. In this embodiment, one common electrode 141 overlaps with two pixel electrodes simultaneously, which reduces the number of vias 14b connecting the common electrode 141 to the common trace 124.

[0090] Optionally, via 14b is disposed between the first pixel electrode 13a and the second pixel electrode 13b.

[0091] Optional, please refer to Figure 4 , Figure 4 What is shown is Figure 3 A schematic diagram of the structure of the common electrode 141. The four-pixel domain region includes a first domain region c1, a second domain region c2, a third domain region c3, and a fourth domain region c4. The first domain region c1 and the second domain region c2 correspond to the first pixel electrode 13a, and the third domain region c3 and the fourth domain region c4 correspond to the second pixel electrode 13b.

[0092] The first domain region c1 and the second domain region c2 are arranged along the second direction F2, the third domain region c3 and the fourth domain region c4 are arranged along the second direction F2, the first domain region c1 and the third domain region c3 are arranged along the first direction F1, and the second domain region c2 and the fourth domain region c4 are arranged along the first direction F1.

[0093] The extension direction of slit 14a intersects the alignment direction (first direction F1) of alignment film 15. In the first domain region c1, multiple slits 14a extend along the fourth direction F4. In the second domain region c2, multiple slits 14a extend along the fifth direction F5. In the third domain region c3, multiple slits 14a extend along the sixth direction F6. In the fourth domain region c4, multiple slits 14a extend along the seventh direction F7.

[0094] Understandably, a pixel region 1a has four pixel domains, which can expand the viewing angle of the display panel 100.

[0095] In some embodiments, the positions of the first pixel electrode 13a and the second pixel electrode 13b can be interchanged. For example, the first domain region c1 of the corresponding first pixel electrode 13a and the third domain region c3 of the corresponding second pixel electrode 13b are interchanged, and the second domain region c2 of the corresponding first pixel electrode 13a and the fourth domain region c4 of the corresponding second pixel electrode 13b are interchanged; the corresponding slit 14a is also interchanged along with the domain regions.

[0096] The extension directions of the boundary between the first domain c1 and the second domain c2 and the boundary between the third domain c3 and the fourth domain c4 are aligned. The common route 124 passes through the boundary between the first domain c1 and the second domain c2 and the boundary between the third domain c3 and the fourth domain c4.

[0097] Optionally, in some embodiments of this application, in the pixel electrode group 131 of the display panel 100 from a top-view perspective, the pattern formed by all the slits 14a in the first pixel electrode 13a and the pattern formed by all the slits 14a in the second pixel electrode 13b are axially symmetrical patterns.

[0098] In other words, the slit 14a pattern in the first domain c1 and the slit 14a pattern in the third domain c3 are symmetrically arranged, and the slit 14a pattern in the second domain c2 and the slit 14a pattern in the fourth domain c4 are symmetrically arranged to improve the brightness uniformity at the horizontal viewing angle.

[0099] Please refer to Figure 5 , Figure 5 This diagram illustrates the driving architecture of a display panel 100 according to one or more embodiments of this application. In some embodiments of this application, in the second direction F2, the first pixel electrode 13a and the second pixel electrode 13b are alternately arranged in a pixel column. In the same frame, the voltage polarity of the first data line 12a and the voltage polarity of the second data line 12b are opposite. For example, the first data line 12a is connected to a positive voltage, and the second data line 12b is connected to a negative voltage; or, the first data line 12a is connected to a negative voltage, and the second data line 12b is connected to a positive voltage.

[0100] It should be noted that, since the first data line 12a connects to the second pixel electrode 13b of the first pixel row p1 and the first pixel electrode 13a of the second pixel row p2, and the second data line 12b connects to the first pixel electrode 13a of the first pixel row p1 and the second pixel electrode 13b of the second pixel row p2, the voltage polarities of the first pixel electrode 13a and the second pixel electrode 13b are the same in the same pixel column, and the voltage polarities of the first pixel electrode 13a and the second pixel electrode 13b are opposite in the same pixel row, thereby achieving the column flipping effect, reducing horizontal crosstalk, and improving the display effect.

[0101] Please refer to Figure 6In some embodiments of this application, the black matrix layer 22 includes a first light-shielding strip 221 and a second light-shielding strip 222. The first light-shielding strip 221 extends along a first direction F1, and the second light-shielding strip 222 extends along a second direction F2. Multiple first light-shielding strips 221 and multiple second light-shielding strips 222 are intersected to form multiple openings 223. A portion of the multiple openings 223 faces the first pixel electrode 13a, and another portion of the multiple openings 223 faces the second pixel electrode 13b.

[0102] The second light-shielding strip 222 includes a first light-shielding portion 22a and a second light-shielding portion 22b. In the first direction F1, the width k1 of the first light-shielding portion 22a is greater than the width k2 of the second light-shielding portion 22b. In the first direction F1, the first light-shielding portion 22a and the second light-shielding portion 22b are arranged alternately. In the second direction F2, the first light-shielding portion 22a and the second light-shielding portion 22b are alternately connected.

[0103] Secondly, the wider first light-shielding portion 22a and the narrower second light-shielding portion 22b are alternately connected in the second direction F2, making the edge of the second light-shielding strip 222 non-linear, thus reducing the risk of vertical lines appearing on the display panel 100. Optionally, both sides of the second light-shielding strip 222 are non-linear to further reduce the risk of vertical lines appearing on the display panel 100.

[0104] In addition, the wider first light-shielding portion 22a and the narrower second light-shielding portion 22b are alternately arranged in the first direction F1 and the second direction F2, which improves the uniformity of the display.

[0105] Combination Figure 3 and Figure 6 In the display panel 100 viewed from above, the first light-shielding strip 221 covers the scan line 121, the second trace a2, and the fifth trace b2. The first light-shielding portion 22a covers the portion of the data line group 122 located between two adjacent pixel electrode groups 131 in the first direction F1. The second light-shielding portion 22b covers the area between the first pixel electrode 13a and the second pixel electrode 13b in the pixel electrode group 131. The second light-shielding portion 22b also covers the via 14b.

[0106] It should be noted that the portion of the first light-shielding part 22a covering the data line group 122 located between two adjacent groups of pixel electrode groups 131 in the first direction F1 can be: the first light-shielding part 22a in odd-numbered rows covers the first routing part a1 and the fourth routing part b1, and the first light-shielding part 22a in even-numbered rows covers the third routing part a3 and the sixth routing part b3.

[0107] Secondly, because the data line group 122 is positioned between two adjacent pixel electrode groups 131 in the first direction F1, the distance between adjacent pixel electrode groups 131 is relatively large, while the distance between two pixel electrodes within the same pixel electrode group 131 is relatively small. Therefore, based on the consideration of maximum aperture ratio, the width k1 of the first light-shielding part 22a is made greater than the width k2 of the second light-shielding part 22b. Furthermore, because the width k1 of the first light-shielding part 22a is greater than the width k2 of the second light-shielding part 22b, the edge of the second light-shielding strip 222 is non-linear in the second direction F2, reducing the risk of vertical lines appearing on the display panel 100 and improving the uniformity of the display.

[0108] In some embodiments of this application, in the first direction F1, third light-shielding portions 22c are connected to both sides of the first light-shielding portion 22a. In the display panel 100 viewed from above, the first light-shielding portion 22a and the third light-shielding portions 22c on both sides are used as a whole to cover a pad 17.

[0109] Understandably, the first light-shielding portion 22a covers the middle area of ​​the pad 17, and the third light-shielding portion 22c covers both sides of the pad 17, so that the first light-shielding portion 22a and the third light-shielding portion 22c cover the entire pad 17. Furthermore, because the third light-shielding portion 22c connects to both sides of the first light-shielding portion 22a, the edge of the second light-shielding strip 222 is more uneven in the second direction F2, reducing the risk of vertical lines appearing on the display panel 100.

[0110] Figure 7 What is shown is Figure 1 Another enlarged schematic view of section M; Figure 8 Based on Figure 7 A schematic diagram of the structure of the black matrix layer 22.

[0111] exist Figure 7 and Figure 8 In this document, parts that differ from the embodiments described above will be described to avoid redundancy.

[0112] Reference Figure 7 and Figure 8 The common trace 124 and the spacer 17 are positioned between the first pixel row p1 and the second pixel row p2.

[0113] In the display panel 100 viewed from above, a portion of the spacers 17 near the scan line 121 partially overlaps with the common trace 124, and the via 14b at least partially overlaps with the common trace 124. The first light-shielding strip 221 also covers the common trace 124, and the first light-shielding strip 221 also covers at least a portion of the via 14b.

[0114] It is understood that placing the common trace 124 adjacent to the scan line 121 can improve the aperture ratio. Optionally, in some embodiments, the common trace 124 may also be arranged to at least partially overlap with the second trace portion a2 and the fifth trace portion b2 simultaneously to improve the aperture ratio.

[0115] Figure 9 What is shown is Figure 1 Another enlarged schematic view of part M in the diagram; Figure 10 Based on Figure 9 A schematic diagram of the structure of the black matrix layer 22.

[0116] exist Figure 9 and Figure 10 In this document, parts that differ from the embodiments described above will be described to avoid redundancy.

[0117] Reference Figure 9 and Figure 10 In some embodiments of this application, the common trace 124 and the spacer 17 are disposed between the first pixel row p1 and the second pixel row p2.

[0118] In the display panel 100 viewed from above, at least one of the common trace 124, scan line 121 and data line group 122 is partially overlapped with the spacer 17, which is located at the intersection of the first light-shielding strip 221 and the second light-shielding strip 222.

[0119] It is understandable that by placing the spacer 17 between the first pixel row p1 and the second pixel row p2, and partially overlapping with the traces of the array substrate 10, the light-transmitting area occupied by the spacer 17 is reduced, thereby increasing the aperture ratio.

[0120] Spacer 17 is disposed between the second wiring section a2 and the fifth wiring section b2. Spacer 17 partially overlaps with the common wiring 124 and also partially overlaps with the data cable group 122.

[0121] In some embodiments, the spacer 17 located further away from the thin-film transistor group 12c may also be partially overlapped with the scan line 121, so that the spacer 17 located further away from the thin-film transistor group 12c is completely disposed in the layout area between the scan line 121 and the common trace 124, thereby avoiding the spacer 17 occupying additional layout area and improving the aperture ratio.

[0122] In some embodiments, the common routing 124 may also be configured to at least partially overlap with the second routing portion a2 and the fifth routing portion b2 simultaneously to improve the opening ratio.

[0123] Optionally, in some embodiments of this application, a third light-shielding portion 22c is connected to both sides of the intersection of the first light-shielding strip 221 and the second light-shielding strip 222. In the display panel 100 viewed from above, the third light-shielding portion 22c and portions of the first light-shielding strip 221 and the second light-shielding strip 222 respectively connected to the third light-shielding portion 22c are collectively covered by a padding material 17.

[0124] The spacer 17 includes a first spacer 171 and a second spacer 172, which are arranged alternately along a first direction F1 and an alternately along a second direction F2.

[0125] The first spacer 171 is located near the thin-film transistor group 12c, and the second spacer 172 is located away from the thin-film transistor group 12c. A portion of the second spacer 172 is disposed between the first trace a1 and the fourth trace b1, and partially overlaps with both traces a1 and b1. A portion of the second spacer 172 is disposed between the third trace a3 and the sixth trace b3, and partially overlaps with both traces a3 and b3, to improve the aperture ratio.

[0126] Figure 11 What is shown is Figure 1 Another enlarged schematic view of part M in the diagram; Figure 12 What is shown is Figure 11 A schematic diagram of the structure of the common electrode 141.

[0127] Figure 11 and Figure 12 The implementation methods shown are the same as Figure 9 and Figure 10 The difference in the implementation shown is that each pixel region 1a is a dual-pixel domain region, and the first pixel electrode 13a and the second pixel electrode 13b each correspond to a pixel domain region.

[0128] exist Figure 11 and Figure 12 In the image, the dual-pixel domain region includes a first domain region c1 and a second domain region c2. The first domain region c1 corresponds to the first pixel electrode 13a, and the second domain region c2 corresponds to the second pixel electrode 13b. The first domain region c1 and the second domain region c2 are arranged along a first direction F1 and a second direction F2.

[0129] The extension direction of slit 14a intersects the alignment direction (first direction F1) of alignment film 15. In the first domain region c1, multiple slits 14a extend along the fourth direction F4. In the second domain region c2, multiple slits 14a extend along the fifth direction F5.

[0130] The first pixel electrode 13a and the second pixel electrode 13b are both set as single-domain regions, which eliminates the dark ripples in the middle of the dual-domain pixel electrode and further improves the aperture ratio and light transmittance.

[0131] In some embodiments of this application, the slit 14a pattern of the first domain c1 and the slit 14a pattern of the second domain c2 are arranged symmetrically to each other to improve the brightness uniformity of the horizontal viewing angle.

[0132] Secondly, the first domain region c1 and the second domain region c2 are arranged along the first direction F1 and the second direction F2, so that the four adjacent pixel electrodes are arranged opposite each other to form a pixel overlapping unit, so that the pixel overlapping unit has four pixel domain regions, thereby expanding the viewing angle of the display panel 100.

[0133] Please refer to Figure 13 , Figure 13 The diagram shown is a structural schematic of a display device 1000 according to an embodiment of this application. Accordingly, this application also provides a display device 1000, which includes the display panel 100 described in any of the above embodiments.

[0134] It should be noted that the structure of the display panel 100 of the display device 1000 in this application embodiment is similar to or the same as the structure of the display panel 100 of the above embodiments. Please refer to [link / reference] for details. Figures 1 to 12 The relevant explanations will not be repeated here.

[0135] Optionally, the display device 1000 can be applied to and used in a variety of products, including, for example, televisions, laptops, monitors, billboards, Internet of Things devices, and portable electronic devices including mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players, navigation devices, and ultra-mobile personal computers.

[0136] Furthermore, the display device 1000 according to some embodiments can be applied to and used within wearable devices, including smartwatches, watch phones, glasses-type displays, and head-mounted displays (HMDs). Additionally, according to some embodiments, the display device 1000 can be applied to instrument panels for automobiles, displays in central dashboards or central information displays (CIDs) arranged on instrument panels, interior mirror displays replacing side mirrors, and displays for entertainment systems arranged on the back of the front seats for rear-seat passengers in automobiles.

[0137] The display device 1000 of this application embodiment adopts a data line group 122 layout, so that there is no data line between the first pixel electrode 13a and the second pixel electrode 13b in the pixel electrode group 131, which greatly reduces the distance between the first pixel electrode 13a and the second pixel electrode 13b in the pixel electrode group 131. Although a data line is added between the pixel electrode groups 131, the small distance between the first data line 12a and the second data line 12b reduces the wiring area in the first direction F1, thereby improving the aperture ratio.

[0138] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, comprising an array substrate and a counter substrate disposed opposite to the array substrate, characterized in that, The array substrate includes: Multiple scan lines and multiple data line groups are provided, with the data line groups arranged along a first direction, the scan lines extending along the first direction, and the multiple scan lines arranged along a second direction intersecting the first direction; the multiple scan lines and multiple data line groups are intersected to form multiple pixel regions; and Multiple pixel electrode groups are provided, with one pixel electrode group correspondingly disposed in one pixel region. The multiple pixel electrode groups are arranged along a first direction to form a pixel row. The pixel row includes a first pixel row and a second pixel row, which are arranged along a second direction. In the second direction, a pixel electrode group of the first pixel row is correspondingly disposed between two adjacent pixel electrode groups of the second pixel row. Each of the data line groups includes a first data line and a second data line, and each of the pixel electrode groups includes a first pixel electrode and a second pixel electrode. In the first direction, the first pixel electrode and the second pixel electrode are arranged alternately, and the first data line and the second data line are arranged alternately. The first data line connects the second pixel electrode of the first pixel row and the first pixel electrode of the second pixel row, and the second data line connects the first pixel electrode of the first pixel row and the second pixel electrode of the second pixel row.

2. The display panel according to claim 1, characterized in that, The first data line includes a first routing section, a second routing section, and a third routing section. The first routing section is correspondingly disposed in the first pixel row, and the third routing section is correspondingly disposed in the second pixel row. The second routing section is correspondingly disposed between the first pixel row and the second pixel row and is connected to the first routing section and the third routing section. The second data line includes a fourth routing section, a fifth routing section, and a sixth routing section. The fourth routing section is correspondingly disposed in the first pixel row, the sixth routing section is correspondingly disposed in the second pixel row, and the fifth routing section is correspondingly disposed between the first pixel row and the second pixel row and is connected to the fourth routing section and the sixth routing section. The first trace portion is connected to the second pixel electrode of the first pixel row, the third trace portion is connected to the first pixel electrode of the second pixel row, the fourth trace portion is connected to the first pixel electrode of the first pixel row, and the sixth trace portion is connected to the second pixel electrode of the second pixel row. In the first direction, the second trace portion is located on one side of the fifth trace portion, and in the second direction, the second trace portion and the fifth trace portion are arranged without overlap.

3. The display panel according to claim 2, characterized in that, The first trace portion, the third trace portion, the fourth trace portion and the sixth trace portion all extend along the second direction, and the second trace portion and the fifth trace portion all extend along the first direction; In the first direction, the second wiring portion and the fifth wiring portion are aligned.

4. The display panel according to claim 3, characterized in that, The opposing substrate includes a black matrix layer, the black matrix layer includes a first light-shielding strip and a second light-shielding strip, the first light-shielding strip extends along a first direction, the second light-shielding strip extends along a second direction, and a plurality of the first light-shielding strips and a plurality of the second light-shielding strips are cross-connected to form a plurality of openings, a portion of the plurality of openings is facing the first pixel electrode, and another portion of the plurality of openings is facing the second pixel electrode; The second light-shielding strip includes a first light-shielding part and a second light-shielding part. In the first direction, the width of the first light-shielding part is greater than the width of the second light-shielding part. In the first direction, the first light-shielding part and the second light-shielding part are arranged alternately. In the second direction, the first light-shielding part and the second light-shielding part are connected alternately. In the display panel viewed from above, the first light-shielding strip covers the scan line, the second trace portion, and the fifth trace portion. The first light-shielding portion covers the portion of the data line group located between two adjacent groups of pixel electrode groups in the first direction. The second light-shielding portion covers the area between the first pixel electrode and the second pixel electrode in the pixel electrode group.

5. The display panel according to claim 4, characterized in that, The array substrate further includes multiple thin-film transistor groups, which are disposed between two adjacent pixel electrode groups and located in the corner region of the pixel electrode groups. Each thin-film transistor group includes a first thin-film transistor and a second thin-film transistor. The control terminals of the first thin-film transistor and the second thin-film transistor are connected to the scan line. The input terminal of the first thin-film transistor is connected to the first data line, and the input terminal of the second thin-film transistor is connected to the second data line. In the first pixel row, the output terminal of the first thin-film transistor is connected to the second pixel electrode, and the output terminal of the second thin-film transistor is connected to the first pixel electrode. In the second pixel row, the output terminal of the first thin-film transistor is connected to the first pixel electrode, and the output terminal of the second thin-film transistor is connected to the second pixel electrode; The first thin-film transistor and the second thin-film transistor are arranged alternately in a row along the first direction; in each group of thin-film transistors, the first thin-film transistor is disposed on the side of the first data line away from the second data line, and the second thin-film transistor is disposed on the side of the second data line away from the first data line.

6. The display panel according to claim 5, characterized in that, The display panel further includes a plurality of spacers, and the array substrate includes a common trace extending along the first direction, the common trace and the spacers being disposed between the first pixel row and the second pixel row; In the display panel viewed from above, at least one of the common trace, the scan line, and the data line group partially overlaps with the spacer, which is located at the intersection of the first light-shielding strip and the second light-shielding strip.

7. The display panel according to claim 6, characterized in that, A third light-shielding part is connected to both sides of the intersection of the first light-shielding strip and the second light-shielding strip; in the display panel viewed from above, the third light-shielding part and the portions of the first light-shielding strip and the second light-shielding strip connected to the third light-shielding part respectively cover the pad as a whole.

8. The display panel according to claim 7, characterized in that, Each pixel region is a dual-pixel domain region, with the first pixel electrode and the second pixel electrode each corresponding to one pixel domain region.

9. The display panel according to claim 5, characterized in that, The display panel also includes a plurality of spacers adjacent to the scan lines. In the display panel viewed from above, in the first direction, the first data line and the second data line in the same data line group partially overlap with the same spacer.

10. The display panel according to claim 9, characterized in that, Each pixel region is a four-pixel domain region, and the four pixel domain regions are arranged in a matrix along the first direction and the second direction. In the second direction, the liquid crystal tilt directions of the two pixel domain regions are different. The array substrate also includes a common trace that extends along the first direction. In the display panel viewed from above, the common trace is disposed between two adjacent pixel domains in the second direction.

11. The display panel according to claim 10, characterized in that, The array substrate further includes a common trace, which extends along the first direction and is disposed between the common trace and the spacer between the first pixel row and the second pixel row. In the display panel viewed from above, a portion of the spacers near the scan line overlaps with the common trace, and the first light-shielding strip covers the common trace.

12. The display panel according to claim 9, characterized in that, In the first direction, third light-shielding parts are connected to both sides of the first light-shielding part. In the display panel viewed from above, the first light-shielding part and the third light-shielding parts on both sides form a whole and cover the pad.

13. The display panel according to any one of claims 6-12, characterized in that, The spacer is formed on the opposing substrate, and in the display panel viewed from above, the spacer is located outside the thin-film transistor array.

14. The display panel according to any one of claims 6-12, characterized in that, The spacer is formed on the opposing substrate, and the array substrate includes an alignment film whose alignment direction is parallel to the first direction.

15. The display panel according to claim 14, characterized in that, Multiple pixel electrode groups are co-located on the pixel electrode layer. The array substrate also includes a common electrode layer connected to a common trace. The pixel electrode layer and the common electrode layer are co-located on different layers. The common electrode layer includes multiple common electrodes, and one common electrode is correspondingly disposed in one pixel region. In the display panel viewed from above, one common electrode simultaneously overlaps with the first pixel electrode and the second pixel electrode of the same pixel electrode group. A slit is provided in the pixel electrode group and the common electrode closer to the opposing substrate. In the pixel electrode group of the display panel viewed from above, the pattern formed by all the slits in the first pixel electrode and the pattern formed by all the slits in the second pixel electrode are axially symmetrical to each other.

16. The display panel according to any one of claims 5-12, characterized in that, In the second direction, the first pixel electrode and the second pixel electrode are arranged alternately in a pixel column, and a plurality of pixel columns are arranged along the first direction, wherein, in the same frame, the voltage polarity of the first data line and the voltage polarity of the second data line are opposite.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 1-16.

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