Mask manufacturing method

Abstract

A mask manufacturing method is provided. The mask manufacturing method includes: obtaining a first optical proximity corrected (OPCed) design layout by performing a first OPC on an optical proximity correction (OPC) target design layout; performing reverse subdivision on the OPC target design layout based on the first OPCed design layout to generate a first segment; performing a reverse correction to assign a first deviation of the first OPCed design layout to the first segment of the OPC target design layout; determining a full-chip representative deviation based on the segment grouping of the first segment; applying the full-chip representative deviation to an entire chip area; preparing mask data based on the full-chip representative deviation that has been applied to the entire chip area; and exposing a mask substrate based on the mask data.

Description

Technical Field

[0001] The present disclosure and inventive concepts thereof relate to mask manufacturing methods, and more particularly, to optical proximity correction (OPC) methods and mask manufacturing methods using these OPC methods. Background Art

[0002] In semiconductor processes, a photolithography process using a mask may be performed to form a pattern on a semiconductor substrate such as a wafer. The mask may be referred to as a pattern transfer body having an opaque material pattern shape formed on a transparent base material. Such a mask may be manufactured by designing a desired circuit, designing a layout of the circuit, and transmitting the design data obtained by optical proximity correction (OPC) as mask tape-out (MTO) design data. Thereafter, mask data preparation (MDP) may be performed based on the MTO design data, and an exposure process, etc. may be performed on the mask substrate. Summary of the invention

[0003] The present disclosure and inventive concepts thereof provide optical proximity correction (OPC) methods that improve (eg, enable maintaining) full-chip deviation uniformity, and mask manufacturing methods including these OPC methods.

[0004] The present disclosure and the inventive concept thereof are not limited to those mentioned above, and those skilled in the art will clearly understand the present disclosure and the inventive concept thereof through the following description.

[0005] According to one aspect of the present invention, a mask manufacturing method is provided, the mask manufacturing method comprising: obtaining a first optical proximity correction (OPCed) design layout by performing a first OPC on an optical proximity correction (OPC) target design layout; performing reverse dissection on the OPC target design layout based on the first OPCed design layout to generate a first segment; performing reverse correction to assign a first deviation of the first OPCed design layout to the first segment of the OPC target design layout; determining a full-chip representative deviation based on segment grouping of the first segment; applying the full-chip representative deviation to an entire chip area; preparing mask data based on the full-chip representative deviation that has been applied to the entire chip area; and exposing a mask substrate based on the mask data.

[0006] According to another aspect of the present invention, a mask manufacturing method is provided, the mask manufacturing method comprising: obtaining a first optical proximity correction (OPCed) design layout by performing a first OPC on an optical proximity correction (OPC) target design layout; performing reverse segmentation on the OPC target design layout based on the first OPCed design layout to generate a first segment; performing reverse correction to assign a first deviation of the first OPCed design layout to the first segment of the OPC target design layout; performing segment grouping by grouping the first segments having the same environment into a first group; determining a patch representative deviation for the first group of each patch; determining a full-chip representative deviation for the first group in the entire chip area; applying the full-chip representative deviation to the entire chip area to generate a final OPCed design layout; preparing mask data based on the final OPCed design layout; and exposing a mask substrate based on the mask data.

[0007] According to another aspect of the present invention, a mask manufacturing method is provided, the mask manufacturing method comprising: obtaining a first optical proximity correction (OPCed) design layout by performing a first OPC on an optical proximity correction (OPC) target design layout; performing reverse splitting on the OPC target design layout based on the first OPCed design layout to generate a first segment; performing reverse correction to assign a first deviation of the first OPCed design layout to the first segment of the OPC target design layout; determining a full-chip representative deviation based on the segment grouping of the first segment; applying the full-chip representative deviation to the entire chip area to obtain a final OPCed design layout; preparing data about the final OPCed design layout as mask tape-out (MTO) design data; preparing mask data based on the MTO design data; and exposing a mask substrate based on the mask data. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a flow chart schematically illustrating the operation of an optical proximity correction (OPC) method according to some embodiments;

[0010] Figure 2A , Figure 2B and Figure 2C It is illustrated in Figure 1 A conceptual diagram of the operation of obtaining a first optical proximity corrected (OPCed) design layout in the OPC method shown in FIG.

[0011] Figure 3A , Figure 3B and Figure 3C is a conceptual diagram illustrating the concept of deviation consistency in a full chip;

[0012] Figure 4A and Figure 4B It is illustrated in Figure 1 A conceptual diagram of the operation of performing reverse splitting in the OPC method shown in FIG.

[0013] Figure 5A and Figure 5B The diagram shows Figure 4B A conceptual diagram showing an abnormal situation in the operation of generating a split point;

[0014] Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E It is illustrated in Figure 1 A conceptual diagram of the operation of performing reverse correction in the OPC method shown in FIG.

[0015] Figure 7 It is illustrated in Figure 1 A conceptual diagram of an internalized OPC target design layout generated after performing a reverse correction in the OPC method shown in FIG.

[0016] Fig. 8A , Figure 8B and Figure 8C It is illustrated in Figure 1 A flowchart and a conceptual diagram of the operation of calculating the full chip representative deviation in the OPC method shown in FIG.

[0017] Fig.9A and Fig. 9B It is illustrated in Figure 1 A conceptual diagram of the operation of applying a full chip representative bias to the entire chip area in the OPC method shown in FIG.

[0018] Fig. 10A and Fig. 10B It's a picture. Figure 1 A conceptual diagram showing the results of a practical application of the OPC method; and

[0019] Fig.11 is a flow chart schematically illustrating the operation of a mask manufacturing method including an OPC method according to some embodiments. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the accompanying drawings, unless otherwise clearly stated, the same reference numerals may denote the same elements, and repeated descriptions thereof may be omitted.

[0021] Figure 1is a flow chart schematically illustrating the operation of an optical proximity correction (OPC) method according to some embodiments.

[0022] refer to Figure 1 According to some embodiments, in an OPC method, a first optical proximity corrected (OPCed) design layout may be obtained by applying a first OPC to an OPC target design layout (operation S110). The OPC target design layout may refer to a design layout of a target pattern to be formed on a substrate such as a wafer. The target pattern may be formed on the substrate by transferring a pattern of a mask (mask pattern) to the substrate via an exposure process. Therefore, the OPC target design layout may refer to a layout of a mask pattern corresponding to the target pattern to be formed on the substrate. In addition, because the mask pattern may be scaled down and projected onto the substrate (wafer), the mask pattern may have a larger size than the target pattern on the substrate.

[0023] In addition, the first OPC may refer to a basic OPC or a commercial OPC that is generally used in a mask manufacturing method. Furthermore, according to some embodiments, in an OPC method, the second OPC may refer to a concept including all operations performed on a first OPCed design layout for deviation consistency (to be described later). Therefore, a second OPC may be performed on the first OPCed design layout to obtain a second OPCed design layout. Figure 2A , Figure 2B and Figure 2C The operation S110 of obtaining a first OPCed design layout is further described.

[0024] Thereafter, the OPC target design layout (e.g., the internal OPC target design layout iOPC-TG, which will be described below) can be reversely split (operation S120) based on the first OPCed design layout. Operation S120 and subsequent operations of performing reverse splitting can be used to assign the same deviation to segments with the same environment. In principle (or theoretically), within the first OPCed design layout of the full chip, segments with the same environment (which will be further described below) have the same deviation. However, in the first OPCed design layout of the full chip, segments with the same environment may have different deviations, and in this case, mask quality errors may occur. Such a situation in which segments with the same environment have different deviations can be referred to as a full chip deviation consistency problem or a full chip consistency problem. The term "deviation" can be simply defined as the difference or distance between a segment of the OPC target design layout and a corresponding segment of the first OPCed design layout (generated by the first OPC based on the OPC target design layout (e.g., the internal OPC target design layout iOPC-TG, which will be described below)).

[0025] refer to Figure 3A, Figure 3B and Figure 3C Describe the full chip consistency problem. In addition, refer to Figure 4A and Figure 4B The operation S120 of performing reverse splitting is further described.

[0026] After performing the reverse segmentation, reverse correction may be performed to assign deviations to the segments generated by the reverse segmentation (operation S130). The reverse correction may be an operation of calculating deviations for each segment generated by the reverse segmentation. Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E Further description of reverse correction. In this article, calculation can refer to determination or generation. For example, calculating A based on B can refer to determining A based on B or generating A based on B.

[0027] After performing the reverse correction, the full-chip representative deviation may be calculated based on the segment grouping (operation S140). Segment grouping may refer to an operation of grouping segments having the same environment. In addition, the calculation of the full-chip representative deviation may be performed by calculating a representative deviation for each patch (patch representative deviation) and then calculating a representative deviation for all patches (full-chip representative deviation). For reference, in an operation such as an operation of calculating deviations for each segment, the full chip may be divided into a plurality of patches in a checkered pattern. Reference Fig. 8A , Figure 8B and Figure 8C The calculation of the full-chip representativeness deviation is further described.

[0028] After calculating the full-chip representative deviation, the full-chip representative deviation can be applied to the entire chip area (operation S150). By applying the full-chip representative deviation to the entire chip area, a second OPCed design layout can be obtained. As described above, the operations additionally performed on the first OPCed design layout for deviation consistency can correspond to the second OPC. For example, the second OPC (i.e., the operation for deviation consistency) may include an operation S120 for performing reverse segmentation, an operation S130 for performing reverse correction, an operation S140 for calculating the full-chip representative deviation, and an operation S150 for applying the full-chip representative deviation to the entire chip area.

[0029] According to some embodiments, in the OPC method, the second OPCed design layout may correspond to the final OPCed design layout. In addition, according to some embodiments, the OPC method may perform a second OPC on the first OPCed design layout obtained by the first OPC (basic OPC or commercial OPC) to obtain a second OPCed design layout, and the second OPCed design layout may solve the problem of full chip consistency. In other words, the second OPCed design layout may improve (e.g., maintain) full chip consistency so that all segments having the same environment in the entire chip area may have the same deviation value.

[0030] Figure 2A , Figure 2B and Figure 2C It is illustrated in Figure 1 A conceptual diagram of operation S110 of obtaining a first OPCed design layout in the OPC method shown in FIG. Figure 1 Description given.

[0031] refer to Figure 2A According to some embodiments, in operation S110 of obtaining a first OPCed design layout of the OPC method, a design layout of a target pattern to be formed on a substrate, i.e., an OPC target design layout OPC-TG, may be provided (e.g., input). The OPC target design layout OPC-TG may have, for example, a right-angle design layout. A right-angle design layout may refer to a layout in which edges are formed only by straight lines. For example, Figure 2A As shown, the OPC target design layout OPC-TG may have a rectangular shape extending in the horizontal direction. However, the shape of the OPC target design layout OPC-TG is not limited to the rectangular shape.

[0032] refer to Figure 2B, thereafter, the edge of the OPC target design layout OPC-TG may be divided into a plurality of segments Sg (referred to as forward segments Sg) according to a predetermined division rule. The division rule may include the position of the division point DP (referred to as the forward division point DP), the length of the segment Sg (forward segment Sg), etc. The segment Sg generated by performing the first OPC on the OPC target design layout (or before the first OPC is applied to the OPC target design layout) may be referred to as the forward segment Sg. The segment Sg generated by performing the second OPC on the OPC target design layout (e.g., by reverse division) (during the second OPC on the OPC target design layout (e.g., by reverse division)) may be referred to as the reverse segment Sg. The division point DP generated by performing the first OPC on the OPC target design layout (or before the first OPC is applied to the OPC target design layout) may be referred to as the forward division point DP. The split point DP generated by performing the second OPC on the OPC target design layout (e.g., the internal OPC target design layout iOPC-TG, which will be described below) (or during the second OPC on the OPC target design layout (e.g., the internal OPC target design layout iOPC-TG, which will be described below)) may be referred to as a reverse split point DP. In some embodiments, the forward segment Sg and the reverse segment Sg may refer to a portion of the OPC target design layout OPC-TG (e.g., the internal OPC target design layout iOPC-TG) between (adjacent) forward split points and reverse split points DP, respectively.

[0033] refer to Figure 2C , after the OPC target design layout OPC-TG is divided into segments Sg (forward segments), the first OPC can be performed on the OPC target design layout OPC-TG to generate the first OPCed design layout OPC-OP. In short, the first OPC (e.g., basic OPC or commercial OPC) can be performed by inputting the data about the OPC target design layout OPC-TG into the OPC model and extracting the simulation profile via simulation. For reference, each piece of basic data can be sent to the OPC model as input data. Basic data can include data about the OPC target design layout OPC-TG (e.g., forward split point DP and / or forward segment Sg). In addition, basic data can include information data such as the thickness, refractive index and dielectric constant of photoresist (PR) materials, source map data about the type of lighting system, etc. However, basic data is not limited to this. The simulation profile can be the result of the simulation performed using the OPC model, and can correspond to the shape of the target pattern formed on the wafer by the exposure process using a mask. A first OPC (eg, basic OPC or commercial OPC) may be performed to make the simulated profile become as similar as possible to the shape of the target pattern.

[0034] In general, the shape of the simulation profile (initial simulation profile) may significantly deviate from the shape of the target pattern. Therefore, in order to reduce (e.g., minimize) the difference between the shape of the simulation profile and the target pattern, the simulation profile and the target pattern can be compared with each other, and the position of each segment of the OPC target design layout OPC-TG (the position of the forward segment Sg) can be changed (together with the change of the position of the forward split point DP) to generate a new OPC design layout. Thereafter, data about the new OPC design layout can be input into the OPC model, and a new simulation profile can be extracted again by simulation. These processes can be repeated until the set conditions are met. For example, conditions can be set based on edge placement error (EPE) values ​​or repetition times. That is, the operation of extracting the simulation profile can be repeated until the EPE value is less than or equal to the set reference value, or until the repetition number reaches the set reference number. The term "EPE" can refer to the difference between the simulation profile at the evaluation point and the target pattern. In addition, the reference number can be set based on the average simulation number or the maximum simulation number until the EPE reaches the reference value by using the simulation of the OPC model. Finally, the OPC design layout finally generated through this iterative operation may correspond to the OPCed design layout, ie, the first OPCed design layout OPC-OP obtained through the OPC method according to some embodiments.

[0035] Figure 3A , Figure 3B and Figure 3C is a conceptual diagram illustrating the concept of deviation consistency in a full chip. Figure 3A The diagram shows the shape of the full chip FC. Figure 3B The pattern RP included in the full chip FC is illustrated, and Figure 3C A first OPCed design layout (eg, first OPCed design layout OPC-OP) of the full-chip FC and deviations of patterns RP located at positions ①, ②, ③, and ④ are illustrated.

[0036] refer to Figure 3A , Figure 3B and Figure 3C , the patterns RP included in the full chip FC may have the same shape and may be as Figure 3B As shown in FIG. 1 , the patterns RP at positions ①, ②, ③, and ④ may all have the same shape and the same environment. Therefore, in principle (or in theory), all segments (e.g., the forward segments Sg) at the same (corresponding) points in the patterns RP at positions ①, ②, ③, and ④ should have the same deviation. However, as Figure 3CAs shown, in the first OPCed design layout (e.g., the first OPCed design layout OPC-OP), the segments at the same (corresponding) lower points at positions ①, ②, ③, and ④ (e.g., the forward segment Sg) may all have different deviations. For example, the lower segment of the pattern RP at position ① may have a deviation of 2.65, the lower segment of the pattern RP at position ② may have a deviation of 2.55, the lower segment of the pattern RP at position ③ may have a deviation of 2.60, and the lower segment of the pattern RP at position ④ may have a deviation of 2.75. As shown in Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E As in the deviation allocation operation shown in , the term "deviation" may refer to a distance by which a segment (e.g., forward segment Sg) of an OPC target design layout (e.g., OPC target design layout OPC-TG) will be moved, and may be defined as a difference between a corresponding segment (portion) of the OPC target design layout (e.g., OPC target design layout OPC-TG) and a first OPCed design layout (e.g., first OPCed design layout OPC-OP).

[0037] As described above, the situation in which the segments (corresponding to the forward segment Sg) with the same environment in the first OPCed design layout of the full chip have different deviations can be referred to as the full chip consistency problem. In general, additional correction operations can be performed later to solve the full chip consistency problem. The full chip consistency problem will now be further described. Various techniques have been applied to improve mask quality, and one of such techniques is to improve (e.g., maintain) mask consistency. In general, simulation for OPC is performed by setting the grid of the OPC model to meet both runtime and OPC consistency. However, due to the grid dependency problem of the OPC model, consistency differences will occur depending on the position, and therefore the mask quality will deteriorate. Various techniques such as unit OPC technology have been applied to overcome consistency differences. However, due to runtime and technical problems, such techniques are still only used to improve (e.g., maintain) consistency in selected areas, rather than improving (e.g., maintaining) consistency in the entire area. Therefore, due to the full chip consistency problem, mask quality degradation will still occur.

[0038] Figure 4A and Figure 4B It is illustrated in Figure 1 1 is a conceptual diagram of an operation 120 for performing reverse splitting in an OPC method. Figure 5A and Figure 5B The diagram shows Figure 4B A conceptual diagram of an abnormal situation in the operation of generating a split point is shown. Reference may be briefly given or omitted here. Figure 1Description given.

[0039] refer to Figure 4A According to some embodiments, in the operation S120 of performing reverse splitting in the OPC method, first, the OPC target design layout OPC-TG can be superimposed on the first OPCed design layout OPC-OP. In some embodiments, the first OPCed design layout OPC-OP can be generated based on the OPC target design layout OPC-TG by the first OPC. Figure 4B As shown, in general, the edge of the OPC target design layout OPC-TG (e.g., the internal OPC target design layout iOPC-TG, which will be described below) can be positioned inside the first OPCed design layout OPC-OP. In addition, the positions of the vertices of the OPC target design layout OPC-TG (e.g., the positions of the four vertices of the rectangle) can remain substantially unchanged. For example, the first OPCed design layout OPC-OP can have vertices that are arranged at positions substantially the same as the corresponding vertices of the OPC target design layout OPC-TG. Therefore, the OPC target design layout OPC-TG can be superimposed on the first OPCed design layout OPC-OP based on the vertices of the OPC target design layout OPC-TG. Here, vertices can each refer to the points where adjacent straight edges meet each other.

[0040] refer to Figure 4B , thereafter, the vertices of the first OPCed design layout OPC-OP may be projected onto an OPC target design layout OPC-TG (e.g., an internal OPC target design layout iOPC-TG, which will be described below). This projection may generate a plurality of splitting points DP (reverse splitting points DP) on the edge of the OPC target design layout OPC-TG. The splitting points DP (reverse splitting points DP) generated by the vertices of the first OPCed design layout OPC-OP projected onto the OPC target design layout OPC-TG may be substantially the same as the splitting points DP (forward splitting points DP) that divide the edge of the OPC target design layout OPC-TG into segments Sg (forward segments Sg) in the first OPC. Ultimately, the operation S120 of performing reverse splitting may correspond to an operation of reversely looking up the splitting points DP (forward segments Sg) used when dividing the edge of the OPC target design layout OPC-TG into segments Sg (forward segments Sg) in the first OPC.

[0041] When a split point DP (reverse split point DP) is generated in (on) an OPC target design layout OPC-TG (e.g., an internal OPC target design layout iOPC-TG, which will be described below) by performing the reverse splitting operation S120, a segment Sg (reverse segment Sg) may be defined by the split point DP (reverse split point DP). That is, a straight edge portion of the OPC target design layout OPC-TG between adjacent split points DP (adjacent reverse split points DP) may correspond to the segment Sg (reverse segment Sg). In some embodiments, the reverse segment Sg may be (substantially) the same as the corresponding forward segment Sg.

[0042] In some embodiments, the first OPCed design layout OPC-OP may not include vertices corresponding to the split points DP (forward split points DP) of the OPC target design layout OPC-TG. For example, the points corresponding to the vertices of the first OPCed design layout OPC-OP may exist as collinear points on the edges of the first OPCed design layout OPC-OP. In this case, the split points DP (reverse split points DP) corresponding to the vertices of the first OPCed design layout OPC-OP may not be generated by projecting the vertices. For example, referring to Figure 4B In the horizontal center portion of the first OPCed design layout OPC-OP, the upper long straight edge and the lower long straight edge do not have vertices, and therefore, a split point (e.g., reverse split point DP) corresponding to a vertex may not be generated. As a result, some of the forward split points DP may not correspond to the reverse split points DP.

[0043] As described above, when it is impossible to generate some of the split points (some of the reverse split points DP corresponding to the forward split points DP) by projecting the vertices, it is possible to generate the reverse split points DP by referring to the following: Figure 5A and Figure 5B Describes the calculations used to generate the mesh points.

[0044] refer to Figure 5A and Figure 5B , as Figure 5A As shown, when the first OPCed design layout OPC-OP1 is obtained by performing the first OPC on the OPC target design layout OPC-TG1, all the splitting points DP (forward splitting points DP) can be set at the vertices on the edges of the first OPCed design layout OPC-OP1. Therefore, all the splitting points DP (reverse splitting points DP) can be generated on the OPC target design layout OPC-TG1 (e.g., the internal OPC target design layout iOPC-TG, which will be described below) by projecting the vertices of the first OPCed design layout OPC-OP1.

[0045] However, when Figure 5BAs shown, when the first OPCed design layout OPC-OP2 is obtained by performing the first OPC on the OPC target design layout OPC-TG1, some of the splitting points DP (some of the forward splitting points DP) may not be set at the vertices on the edge of the first OPCed design layout OPC-OP2. That is, the point corresponding to the upper splitting point DP (upper forward splitting point DP) may exist as a collinear point CP on the upper straight edge of the first OPCed design layout OPC-OP2. Therefore, the splitting point DP (reverse splitting point DP) corresponding to the collinear point CP may be generated on the OPC target design layout OPC-TG1 (e.g., the internal OPC target design layout iOPC-TG, which will be described below) without projecting the vertex.

[0046] In general, the minimum segment length and the maximum segment length are set in the division rule for defining the segment. For example, the second OPC may include a division rule for the minimum segment length and the maximum segment length for the first OPCed design layout (e.g., the first OPCed design layout OPC-OP2). Therefore, the split point (reverse split point DP) corresponding to the collinear point CP can be generated by calculation using the minimum segment and the maximum segment. For example, when the segment length is set to range from 1 to less than 2 and the first OPCed design layout OPC-OP2 has a straight edge with a length of 2, the midpoint of the straight edge divided into two equal parts (i.e., the parts with a length of 1 each) can correspond to the collinear point CP, and the corresponding split point DP (the corresponding reverse split point DP) can be generated by projecting the collinear point CP. When the first OPCed design layout OPC-OP2 has a straight edge with a length of 3, the straight edge can be divided into three equal parts (i.e., the parts with a length of 1 each), and two collinear points CP and two split points DP (two reverse split points DP) corresponding to the two collinear points CP can be generated. When the first OPCed design layout OPC-OP2 has a straight edge with a length of 2.4, the straight edge can be divided into two equal parts (i.e., parts with a length of 1.2 each), and a collinear point CP and a split point DP (a reverse split point DP) corresponding to the collinear point CP can be generated.

[0047] Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E It is illustrated in Figure 1 A conceptual diagram of operation S130 of performing reverse correction in the OPC method shown in FIG. Figure 1 Description given.

[0048] refer to Fig. 6AAccording to some embodiments, in operation S130 of performing reverse correction in the OPC method, first, a query box QB may be generated for each segment Sg (reverse segment Sg) defined by a dividing point DP (reverse dividing point DP). Fig. 6A As indicated by the dotted rectangle in FIG. , the query box QB may have a rectangular shape including the corresponding segment (i.e., the first segment Sg_A). The query box QB may be generated based on the set maximum correction value Mco. In addition, the maximum correction value Mco may be the same in the upward and downward directions relative to the first segment Sg_A. In some embodiments, the first segment Sg_A may be a part of the reverse segment Sg.

[0049] like Fig. 6A As shown, the query box QB may include at least a portion of the adjacent pattern (of the first OPCed design layout OPC-OP). However, in some embodiments, the query box QB may only include the pattern corresponding to the first segment Sg_A (of the first OPCed design layout OPC-OP). That is, whether the query box QB includes a portion of the adjacent pattern (of the first OPCed design layout OPC-OP) may be determined based on the set maximum correction value Mco. In addition, hereinafter, the design layout (OPC target design layout OPC-TG) in which (on which) the split point DP (reverse split point DP) and the segment Sg (reverse segment Sg) are generated may be referred to as the internalized OPC target design layout iOPC-TG.

[0050] refer to Figure 6B , after the query box QB is generated, all deviations included in the query box QB can be extracted. As described above, the term "deviation" refers to the difference or distance between a segment (a portion) of the first OPCed design layout OPC-OP and a segment (reverse segment Sg) corresponding to the portion of the internalized OPC target design layout iOPC-TG, and therefore, the deviation may correspond to an edge portion of the first OPCed design layout OPC-OP included in the query box QB. Figure 6B In FIG. 1 , the extracted deviation and the first segment Sg_A are indicated by thick solid lines. In addition, Figure 6B and the following Figure 6C , Fig.6D and Fig. 6E Only the corresponding portion inside the query box QB is shown, while the query box QB is not shown.

[0051] refer to Figure 6C , after extracting all deviations included in the query box QB, all vertical deviations perpendicular to the first segment Sg_A can be removed. Figure 6C As indicated by the thick solid line in FIG, after the vertical deviation is removed, only the horizontal deviation extending in the horizontal direction may remain.

[0052] refer to Fig.6D , thereafter, the direction of the first segment Sg_A and the remaining deviations can be set. The direction of the first segment Sg_A and the remaining deviations can be set to be clockwise or counterclockwise relative to the edge of the entire pattern. According to some embodiments, the OPC method can set the direction of the first segment Sg_A and the remaining deviations to be clockwise. Therefore, the direction of the segment (e.g., the first segment Sg_A) or the deviation on the upper side of the pattern can be to the right, while the direction of the segment or the deviation on the lower side of the pattern can be to the left. For reference, the term "pattern" refers to a concept indicating the form of a layout, and can encompass both the first OPCed design layout OPC-OP and the internalized OPC target design layout iOPC-TG.

[0053] After setting the directions of the first segment Sg_A and the remaining deviations, all deviations whose directions are different from the direction of the first segment Sg_A can be removed. Fig.6D As indicated by the thick arrow in , all left deviations indicated by X can be removed. Therefore, after removing some deviations according to the direction of the deviation, only two right deviations can remain.

[0054] refer to Fig. 6E , the deviation Bs closest to the first segment Sg_A can be selected. For example, when the reference FIG. 6A to FIG. 6D When the described operation retains one deviation, the remaining deviation can be assigned as the deviation of the first segment Sg_A. However, when in reference FIG. 6A to FIG. 6D When a plurality of deviations remain after the described operation, one of the deviations that is closest to the first segment Sg_A may be selected, and the selected deviation may be assigned as the deviation of the first segment Sg_A. Fig. 6E As indicated by the thick arrow in , the deviation of the other pattern portion indicated by X among the two deviations may be removed. Therefore, the deviation adjacent to the first segment Sg_A may be selected and allocated as the deviation Bs of the first segment Sg_A.

[0055] Figure 7 It is a diagram showing the Figure 1 A conceptual diagram of the internalized OPC target design layout iOPC-TG generated after the described OPC method performs the reverse correction. References may be briefly given or omitted here. Figures 1 to 6E Description given.

[0056] refer to Figure 7 , after performing the reverse correction, the deviations can be respectively assigned to the segments (reverse segments Sg) of the internalized OPC target design layout iOPC-TG. Figure 7, the upper pattern may be the first OPCed design layout OPC-OP, and the lower pattern may correspond to a (final) internalized OPC target design layout iOPC-TG generated by performing reverse splitting and reverse correction on the first OPCed design layout OPC-OP.

[0057] Fig. 8A , Figure 8B and Figure 8C It is illustrated in the reference Figure 1 A flowchart and conceptual diagram describing the operation of calculating full-chip representative deviation in the OPC method.

[0058] refer to Fig. 8A and Figure 8B According to some embodiments, in operation S140 of calculating the full chip representative deviation in the OPC method, first, the same segments (e.g., the same reverse segments Sg) may be grouped (operation S142). The same segments may refer to segments having the same environment in a pattern having the same shape. For example, in Figure 8B In the embodiment, four patterns having the same shape may be repeatedly arranged. Therefore, the segments of each of the four patterns may have the same environment. For example, the segments Sg_a of the four patterns may be identical to each other. Similarly, the segments Sg_b of the four patterns may be identical to each other, and the segments Sg_c of the four patterns may also be identical to each other. Therefore, the segments Sg_a of the four patterns may be grouped into a group, the segments Sg_b of the four patterns may be grouped into another group, and the segments Sg_c of the four patterns may be grouped into another group.

[0059] In addition, after the first OPC, that is, after the basic OPC or the commercial OPC, the deviations of the segments included in the same group may be different from each other due to consistency issues. For example, the segments Sg_a of the four patterns belonging to the first group may have deviation values ​​of A1, A2, A3, and A4 that are different from each other. In addition, the segments Sg_b of the four patterns may have different deviation values ​​(e.g., B1, B2, B3, and B4), and the segments Sg_c of the four patterns may have different deviation values ​​(e.g., C1, C2, C3, and C4).

[0060] refer to Fig. 8A and Figure 8C, after grouping these segments (e.g., segments Sg_a, Sg_b, and Sg_c), the patch representative deviation can be calculated for the same group of each patch (operation S144). As described above, when the full chip is divided in a checkered pattern, the term "patch" can refer to a small quadrilateral portion including the checkered pattern. In general, thousands or more of repeated patterns can be on the full chip. In addition, although the number of patterns varies depending on the number of patches, tens to hundreds of repeated patterns can be arranged in each patch. Therefore, for ease of calculation, before calculating the full chip representative deviation for the full chip, the patch representative deviation can be calculated for each patch.

[0061] like Figure 8C As shown, a representative deviation may be calculated for a segment Sg_a of a plurality of patterns within a patch, a representative deviation may be calculated for a segment Sg_b of a plurality of patterns within a patch, and a representative deviation may be calculated for a segment Sg_c of a plurality of patterns within a patch. According to some embodiments, in the OPC method, a patch representative deviation of each patch may be obtained by calculating an average value of the deviations. Thus, average value A may be calculated as a representative deviation of segment Sg_a, average value B may be calculated as a representative deviation of segment Sg_b, and average value C may be calculated as a representative deviation of segment Sg_c. The patch representative deviation may be calculated by a representative deviation of corresponding deviations of the same group within a patch (e.g., a representative deviation of segment Sg_a, a representative deviation of segment Sg_b, or a representative deviation of segment Sg_c).

[0062] In addition, the method of obtaining the patch representative deviation of each patch is not limited to the average method. For example, the patch representative deviation of each patch may be obtained using a minimum value, a maximum value, a priority value, etc. The method of using the minimum value may be a method of setting the minimum value among all deviations as the representative deviation, and the method of using the maximum value may be the opposite of the method of using the minimum value. In addition, the method of using the priority value may be a method of assigning a specific priority value to each segment and setting the priority value as the representative deviation.

[0063] After calculating the patch representative deviation for each patch, the full chip representative deviation can be calculated for the same group in the entire chip area (operation S146). Because the patch representative deviation for each patch is calculated, the full chip representative deviation can be easily calculated using the patch representative deviation for each patch. The full chip representative deviation can also be calculated using, for example, an average deviation value, a minimum deviation value, a maximum deviation value, and / or a priority value. In addition, the deviation used to calculate the full chip representative deviation can be a patch representative deviation previously calculated for each patch.

[0064] Fig.9A and Fig. 9B It is illustrated in the reference Figure 1 A conceptual diagram of operation S150 of applying a full chip representative deviation to an entire chip area in the described OPC method. Reference may be briefly given or omitted here. Figures 1 to 8C Description given.

[0065] refer to Fig.9A According to some embodiments, in operation S150 of applying a full chip representative deviation to an entire chip area in an OPC method, a previously calculated full chip representative deviation may be applied to a segment of a pattern in the entire chip area. Fig.9A As shown, average value A may be applied to pattern segment Sg_a, average value B may be applied to pattern segment Sg_b, and average value C may be applied to pattern segment Sg_c. Average value A, average value B, and average value C may each correspond to a full-chip representative deviation of a corresponding segment.

[0066] Fig. 9B The diagram shows the full chip representative deviation applied to Figure 3A The results obtained by full chip FC are shown in FIG. Fig. 9B The results of the second OPCed design layout are shown in Figure 2. Fig. 9B As shown, in the result of the second OPCed design layout, the lower segments of the patterns at positions ①, ②, ③ and ④ of the full-chip FC may all have the same deviation of 2.65. Therefore, it can be understood that the full-chip consistency problem can be solved by the OPC method according to some embodiments of the present disclosure.

[0067] Fig. 10A and Fig. 10B The reference is shown in the figure Figure 1 A conceptual diagram describing the results of a practical application of the OPC method. References may be briefly given here or omitted. Figures 1 to 9B Description given.

[0068] Fig. 10A Two patches each including a plurality of patterns are illustrated, and the patterns in the two patches have the same shape and the same environment. Therefore, a segment of a pattern with a deviation of 5.65 in the left patch and a segment of a pattern with a deviation of 5.80 in the right patch may be included in the same segment group. Fig. 10A The results of the first OPCed design layout of all patches for the two patches shown in can show that the same segment group has a total of eight deviations as shown in Table 1 below.

[0069] [Table 1]

[0070]

[0071]

[0072] Fig. 10B It is illustrated in Fig. 10A , and the deviation can be changed from 5.65 to 5.8 by the OPC method according to some embodiments. That is, according to some embodiments, the OPC method can be applied to the segment group so that the corresponding segments of the pattern of the patch can all have a deviation of 5.8 as an average value.

[0073] According to some embodiments, based on the first OPCed design layout and the segmentation information, the OPC method can take the deviations of the first OPCed design layout, set the average of these deviations as the representative deviation of the segments with the same environment, and apply the representative deviation to the entire chip area, thereby maintaining full-chip consistency across the entire chip area. In addition, according to some embodiments, the OPC method can be applied not only to Manhattan-type OPC, but also to free-form OPC including curved shapes to maintain full-chip consistency. In addition, according to some embodiments, the OPC method can be used to maintain full-chip consistency across the entire chip area by using the results of all types of OPC, such as extreme ultraviolet (EUV) OPC and machine learning OPC and basic OPC. That is, the OPC method can solve all inconsistency problems regardless of the type of OPC tool or OPC result.

[0074] Fig.11 1 is a flowchart schematically illustrating the operation of a mask manufacturing method including an OPC method according to some embodiments. Fig.11 and Figure 1 given, and may be given briefly or omitted here. Figures 1 to 10B Description given.

[0075] refer to Fig.11 According to some embodiments, first, a mask manufacturing method including an OPC method (hereinafter referred to as a "mask manufacturing method") may sequentially perform operations S210 of obtaining a first OPCed design layout to S250 of applying a full-chip representative deviation to an entire chip area. Operations S210 of obtaining a first OPCed design layout to S250 of applying a full-chip representative deviation to an entire chip area may be performed in accordance with a reference. Figure 1 The operation S110 of obtaining the first OPCed design layout in the described OPC method to the operation S150 of applying the full chip representative deviation to the entire chip area are substantially the same. Therefore, the description thereof may be omitted. In addition, as described above, the second OPCed design layout may be obtained by applying the full chip representative deviation to the entire chip area.

[0076] After obtaining the second OPCed design layout, mask tape-out (MTO) design data may be prepared (e.g., delivered to a mask production team) (operation S260). Generally speaking, preparing MTO design data may refer to starting (requesting) mask production by handing over data about the final design layout obtained by the OPC method to a mask production process (or a mask production team). Therefore, according to some embodiments, in the mask manufacturing method, the MTO design data may ultimately refer to the final (e.g., second) OPCed design layout or data about the final (e.g., second) OPCed design layout. The MTO design data may have a graphic data format used in electronic design automation (EDA) software, etc. For example, the MTO design data may have a data format such as Graphic Data System II (GDS2) or Open Artwork System Interchange Standard (OASIS).

[0077] After that, mask data preparation (MDP) may be performed (operation S270). For example, MDP may include: i) format conversion called fracturing; ii) addition (enhancement) of barcodes for mechanical reading, standard mask patterns for inspection, online photomask data review (job deck), etc.; and iii) automatic and manual verification. Online photomask data review may refer to generating a text file of a series of instructions on information such as arrangement of multiple mask files, standard dose or exposure speed or method.

[0078] Format conversion (i.e., segmentation) may refer to a process of preparing MTO design data in a format for an electron beam exposure machine by segmenting the MTO design data for each region. The segmentation of the MTO design data may include data manipulation such as scaling, data resizing, data rotation, pattern reflection, or color inversion. In the format conversion by segmentation, data about a large number of systematic errors that may occur somewhere during the transition from the design data to the image on the wafer may be corrected.

[0079] Correction of data regarding systematic errors may be referred to as mask process correction (MPC), and may include line width adjustment referred to as critical dimension (CD) adjustment, improving pattern placement accuracy, etc. Therefore, segmentation may help improve the quality of the final mask, and may also be a process performed in advance for mask process correction. Systematic errors may be caused by distortions occurring in exposure processes, mask development processes, etching processes, wafer imaging processes, etc.

[0080] In addition, the MDP may include MPC. As described above, MPC refers to a process for correcting errors (i.e., systematic errors) that may occur during an exposure process. The exposure process may be an overall concept that encompasses electron beam writing, development, etching, baking, and the like. In addition, data processing may be performed before the exposure process. Data processing may be a preprocessing process for mask data, and may include syntax checking for mask data, exposure time prediction, and the like.

[0081] After the MDP, the mask substrate may be exposed based on the mask data (operation S280). Exposure may refer to, for example, electron beam writing. Electron beam writing may be performed by, for example, a grayscale writing method using a multi-beam mask writer (MBMW). In addition, a variable shape beam (VSB) exposure machine may also be used to perform electron beam writing.

[0082] In addition, after the MDP, a process of converting the mask data into pixel data may be performed before the exposure process. The pixel data may be data directly used in actual exposure, and may include data on the shapes to be exposed and data on the doses respectively assigned to the shapes. The data on the shapes may be bitmap data obtained by converting the shape data (vector data) through rasterization or the like.

[0083] After the exposure process, a series of processes may be performed to completely manufacture the mask. The series of processes may include, for example, development, etching, and cleaning. In addition, the series of processes for mask manufacturing may include a measurement process, a defect inspection process, or a defect repair process. In addition, the series of processes for mask manufacturing may include a pellicle application process. When it is checked after the final cleaning and testing process that there are no contaminating particles or chemical spots on the mask, a pellicle application process may be performed to attach the pellicle so as to protect the mask from subsequent contamination during the delivery of the mask and the usable life of the mask.

[0084] According to some embodiments, in a mask manufacturing method, the OPC method may perform a second OPC on a first OPCed design layout obtained by a first OPC (basic OPC) to obtain a second OPCed design layout, and the second OPCed design layout may improve (e.g., maintain) full chip consistency. Therefore, according to some embodiments, the mask manufacturing method may be used to manufacture a reliable mask capable of maintaining full chip consistency.

[0085] In this article, the block diagrams and / or flowcharts of the methods, devices (systems and / or devices) and / or computer program products implemented by computers are used to describe the exemplary embodiments. It should be understood that the blocks of the block diagrams and / or flowcharts and the combination of the blocks in the block diagrams and / or flowcharts can be implemented by computer program instructions executed by one or more computer circuits. These computer program instructions can be provided to the processor circuits of general-purpose computer circuits, special-purpose computer circuits and / or other programmable data processing circuits to produce a machine, so that the instructions executed by the processors of the computers and / or other programmable data processing devices transform and control transistors, values ​​stored in memory locations, and other hardware components within such circuit systems to implement the functions / behaviors specified in the block diagrams and / or one or more flowchart blocks, and thereby create means (functions) and / or structures for implementing the functions / behaviors specified in the block diagrams and / or (one or more) flowchart blocks.

[0086] The flow chart and block diagram in each figure illustrate the architecture, function and operation of the possible implementation of the system, method and computer program product according to various aspects of the present disclosure.In this regard, each frame in the flow chart or block diagram can represent a module, segment or part of a code, and the code includes one or more executable instructions for implementing the specified (one or more) logical functions.It should also be noted that in some alternative implementations, the function indicated in the frame may not occur in the order indicated in each figure.For example, depending on the function involved, two frames shown in succession can actually be run substantially concurrently, or sometimes these frames can be run in reverse order.It should also be noted that the combination of each frame illustrated in the block diagram and / or flow chart and each frame in the block diagram and / or flow chart can be implemented by a combination of a system based on dedicated hardware or dedicated hardware and computer instructions that performs a specified function or behavior.

[0087] According to some embodiments, various operations of the methods described herein may be performed by a processor, processor circuit, circuit, system, apparatus, machine, etc., including any combination of firmware, hardware, and / or software used in conjunction with a memory to store intermediate values ​​and / or results of the various operations. For example, obtaining a first optical proximity corrected (OPCed) design layout by performing a first OPC on the OPC target design layout, performing reverse segmentation on the OPC target design layout based on the first OPCed design layout to generate a first segment, performing reverse correction to assign a first deviation of the first OPCed design layout to the first segment of the OPC target design layout, determining a full-chip representative deviation based on the segment grouping of the first segment, and / or applying the full-chip representative deviation to the entire chip area may be performed by the processor.

[0088] While the present disclosure and inventive concepts thereof have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A mask manufacturing method, the mask manufacturing method comprising: Obtaining a design layout after first optical proximity correction by performing a first optical proximity correction on an optical proximity correction target design layout; performing a reverse splitting on the optical proximity correction target design layout based on the first optical proximity corrected design layout to generate a first segment; performing a reverse correction to assign a first deviation of the first optical proximity corrected design layout to the first segment of the optical proximity correction target design layout; determining a full-chip representative deviation based on the segment grouping of the first segment; applying the full-chip representative bias to the entire chip area; preparing mask data based on the full-chip representative deviations that have been applied to the entire chip area; as well as The mask substrate is exposed based on the mask data.

2. The mask manufacturing method according to claim 1, wherein: Executing the reverse segmentation includes: superimposing the optical proximity correction target design layout on the design layout after the first optical proximity correction; and The vertices of the first optical proximity corrected design layout are projected onto the optical proximity correction target design layout to generate first dividing points, and the first dividing points divide the optical proximity correction target design layout to generate the first segment of the optical proximity correction target design layout.

3. The mask manufacturing method according to claim 2, wherein: Obtaining the design layout after the first optical proximity correction includes: Dividing the optical proximity correction target design layout into second segments through second dividing points; implementing a first optical proximity correction model on the optical proximity correction target design layout to generate a simulation profile; and moving the second segment of the optical proximity correction target design layout by comparing the second segment of the optical proximity correction target design layout with the simulated profile, Wherein, when performing the reverse splitting, when the vertex of the design layout after the first optical proximity correction corresponds to the second splitting point, the first splitting point is generated at the same position as the second splitting point.

4. The mask manufacturing method according to claim 3, wherein: In performing the reverse splitting, when the vertex of the first optical proximity corrected design layout does not correspond to the second splitting point, the first splitting point is generated by calculation based on a minimum segment length and a maximum segment length of the first optical proximity corrected design layout.

5. The mask manufacturing method according to claim 1, wherein: In performing the reverse correction, one of the first deviations is determined by a query box having a maximum deviation size.

6. The mask manufacturing method according to claim 1, wherein: Performing the reverse correction includes: generating a query box for the first segment of the optical proximity correction target design layout; and When one of the first segments in the query box includes an inner segment, one of the first deviations in the query box is assigned to the inner segment.

7. The mask manufacturing method according to claim 6, wherein: Assigning one of the first deviations in the query box to the inner segment includes: removing a vertical deviation from among the first deviations in the query frame, wherein the vertical deviation is perpendicular to the inner segment; removing different direction deviations from among the first deviations in the query frame, wherein the different direction deviations are in a direction different from a direction of the inner segment; and When the query box includes a plurality of same-direction deviations among the first deviations in the query box, a deviation closest to the inner segment among the plurality of same-direction deviations is selected, wherein the plurality of same-direction deviations are in the same direction as the inner segment.

8. The mask manufacturing method according to claim 1, wherein: Determining the full chip representative deviation includes: performing the segment grouping by grouping the first segments of the optical proximity correction target design layout having the same environment into a first group; determining a patch representative deviation for each patch of said first set; and The full-chip representative deviation is determined for the first group in the entire chip area.

9. The mask manufacturing method according to claim 8, wherein: The patch representative deviation is determined by an average value, a minimum value, a maximum value and / or a priority value of corresponding deviations among the first deviations in the first group of each patch, and The full-chip representative deviation is determined by an average value, a minimum value, a maximum value and / or a priority value of the corresponding deviations among the first deviations in the first group in the entire chip area.

10. The mask manufacturing method according to claim 1, wherein: obtaining a second optical proximity corrected design layout by applying the full-chip representative deviation to the entire chip area, and Wherein, in the design layout after the second optical proximity correction, parts having the same environment in the entire chip area have the same deviation.

11. A mask manufacturing method, the mask manufacturing method comprising: Obtaining a design layout after first optical proximity correction by performing a first optical proximity correction on an optical proximity correction target design layout; performing a reverse splitting on the optical proximity correction target design layout based on the first optical proximity corrected design layout to generate a first segment; performing a reverse correction to assign a first deviation of the first optical proximity corrected design layout to the first segment of the optical proximity correction target design layout; performing segment grouping by grouping the first segments having the same environment into a first group; determining a patch representative deviation for each patch of said first group; determining a full chip representative deviation for the first group in the entire chip area; applying the full-chip representative deviation to the entire chip area to generate a final optical proximity corrected design layout; preparing mask data based on the final optical proximity corrected design layout; as well as The mask substrate is exposed based on the mask data.

12. The mask manufacturing method according to claim 11, wherein: Executing the reverse segmentation includes: superimposing the optical proximity correction target design layout on the design layout after the first optical proximity correction; and The vertices of the first optical proximity corrected design layout are projected onto the optical proximity corrected target design layout to generate first dividing points, and the first dividing points divide the optical proximity corrected target design layout to generate the first segments.

13. The mask manufacturing method according to claim 11, wherein: Performing the reverse correction includes: generating a query box for the first segment; When one of the first segments in the query box includes an inner segment, removing a vertical deviation among the first deviations in the query box, wherein the vertical deviation is perpendicular to the inner segment; removing different direction deviations from among the first deviations in the query frame, wherein the different direction deviations are in a direction different from a direction of the inner segment; and When the query box includes a plurality of same-direction deviations among the first deviations in the query box and the plurality of same-direction deviations are in the same direction as the inner segment, a deviation closest to the inner segment among the plurality of same-direction deviations is selected.

14. The mask manufacturing method according to claim 11, wherein: The patch representative deviation is determined based on an average value, a minimum value, a maximum value and / or a priority value of corresponding deviations among the first deviations in the first group of each patch, and The full-chip representative deviation is determined based on an average value, a minimum value, a maximum value and / or a priority value of the corresponding deviations among the first deviations in the first group in the entire chip area.

15. A mask manufacturing method, the mask manufacturing method comprising: Obtaining a design layout after first optical proximity correction by performing a first optical proximity correction on an optical proximity correction target design layout; performing a reverse splitting on the optical proximity correction target design layout based on the first optical proximity corrected design layout to generate a first segment; performing a reverse correction to assign a first deviation of the first optical proximity corrected design layout to the first segment of the optical proximity correction target design layout; determining a full-chip representative deviation based on the segment grouping of the first segment; applying the full-chip representative deviation to the entire chip area to obtain a final optical proximity corrected design layout; preparing data on the final optical proximity corrected design layout as mask tape-out design data; Preparing mask data based on the mask tape-out design data; as well as The mask substrate is exposed based on the mask data.

16. The mask manufacturing method according to claim 15, wherein: Executing the reverse segmentation includes: superimposing the optical proximity correction target design layout on the design layout after the first optical proximity correction; and The vertices of the first optical proximity corrected design layout are projected onto the optical proximity correction target design layout to generate first dividing points, and the first dividing points divide the optical proximity correction target design layout to generate the first segment of the optical proximity correction target design layout.

17. The mask manufacturing method according to claim 15, wherein: Performing the reverse correction includes: generating a query box for the first segment; When one of the first segments in the query box includes an inner segment, removing a vertical deviation among the first deviations in the query box, wherein the vertical deviation is perpendicular to the inner segment; removing different direction deviations from among the first deviations in the query frame, wherein the different direction deviations are in a direction different from a direction of the inner segment; and When the query box includes a plurality of same-direction deviations among the first deviations in the query box, a deviation closest to the inner segment among the plurality of same-direction deviations is selected, wherein the plurality of same-direction deviations are in the same direction as the inner segment.

18. The mask manufacturing method according to claim 15, wherein: Determining the full chip representative deviation includes: performing segment grouping by grouping the first segments having the same environment into a first group; determining a patch representative deviation for each patch of said first set; and The full-chip representative deviation is determined for the first group in the entire chip area.

19. The mask manufacturing method according to claim 18, wherein: The patch representative deviation is determined by an average value, a minimum value, a maximum value and / or a priority value of corresponding deviations among the first deviations in the first group of each patch, and The full-chip representative deviation is determined by an average value, a minimum value, a maximum value and / or a priority value of the corresponding deviations among the first deviations in the first group in the entire chip area.

20. The mask manufacturing method according to claim 15, wherein: The final optical proximity corrected design layout is obtained by applying the full-chip representative deviation to the entire chip area, and Parts of the final optical proximity corrected design layout having the same environment in the entire chip area have the same deviation.

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