Voltage control circuit and method, chip and electronic equipment

Abstract

The invention provides a voltage control circuit and method, a chip and electronic equipment, and the circuit comprises a selection input SEL module which is electrically connected with the input end of a receiving path, and is used for inputting an analog voltage signal to the receiving path, so as to enable the receiving path to enter a voltage offset detection mode; the receiving path comprises at least one cascaded differential amplifier and a serial-parallel conversion module which is electrically connected with the output end of the last stage of differential amplifier; the digital control module is electrically connected with the output end of the serial-to-parallel conversion module and is used for receiving the offset voltage detection signal transmitted by the serial-to-parallel conversion module in the voltage offset detection mode and generating a voltage elimination signal when the offset voltage detection signal does not meet a preset condition; and the voltage elimination module is used for eliminating the offset voltage in the receiving path when receiving the voltage elimination signal transmitted by the digital control module. Through the circuit, the elimination efficiency of the offset voltage in the receiving path can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a voltage control circuit, method, chip, and electronic device. Background Art

[0002] In the receiving path, multiple differential amplifiers are usually included, such as variable gain amplifiers (VGA), continuous-time linear equalizers (CTLE), and decision feedback equalizers (DFE), which have structures similar to differential amplifiers.

[0003] However, due to manufacturing defects and other factors, differential amplifiers inevitably generate offset voltages, which can lead to data errors in the receiving path. Related technologies typically eliminate this offset voltage by eliminating the offset voltage of a single-pole amplifier, but this approach struggles to effectively eliminate the offset voltage across the entire receiving path. Summary of the Invention

[0004] The present application provides a voltage control circuit, method, chip and electronic device to at least solve the above problems.

[0005] According to one aspect of the present application, a voltage control circuit is provided, comprising a selection input SEL module, a digital control module, and a voltage elimination module, wherein:

[0006] The select input SEL module is electrically connected to the input end of the receiving path and is used to input an analog voltage signal to the receiving path to cause the receiving path to enter a voltage offset detection mode; wherein the receiving path includes at least one cascaded differential amplifier and a serial-to-parallel conversion module electrically connected to the output end of the last differential amplifier stage;

[0007] The digital control module is electrically connected to the output end of the serial-to-parallel conversion module, and is used to receive the offset voltage detection signal transmitted by the serial-to-parallel conversion module in the voltage offset detection mode, and generate a voltage elimination signal when the offset voltage detection signal does not meet a preset condition;

[0008] The voltage elimination module is electrically connected to the digital control module and any one stage of differential amplifier in the receiving path, and is used to eliminate the offset voltage in the receiving path when receiving the voltage elimination signal transmitted by the digital control module.

[0009] In one embodiment, the SEL module is also electrically connected to the digital control module, configured to receive a detection control signal transmitted by the digital control module, and input an analog voltage signal to the receiving path according to the detection control signal, so that the receiving path enters a voltage imbalance detection mode.

[0010] In one embodiment, the digital control module is further configured to generate a voltage normal signal when the offset voltage detection signal meets a preset condition;

[0011] The SEL module is further configured to receive a normal voltage signal transmitted by the digital control module, and input a normal voltage signal to the receiving path according to the normal voltage signal, so that the receiving path enters a normal operating mode.

[0012] In one embodiment, the SEL module includes a first switch combination, a second switch combination and a DC power supply; the first switch combination includes a first switch and a second switch, and the second switch combination includes a third switch and a fourth switch; wherein,

[0013] One end of the first switch is connected to a first signal input terminal for inputting a normal voltage signal to the receiving path, and the other end of the first switch is connected to a non-inverting input terminal of a first-stage amplifier in the receiving path; one end of the second switch is connected to a second signal input terminal for inputting a normal voltage signal to the receiving path, and the other end of the second switch is connected to an inverting input terminal of the first-stage amplifier in the receiving path;

[0014] One end of the third switch is connected to the wire between the first switch and the non-inverting input terminal, and the other end thereof is connected to the fourth switch; one end of the fourth switch is connected to the wire between the second switch and the inverting input terminal, and the other end thereof is connected to the third switch;

[0015] One end of the DC power supply is grounded, and the other end thereof is connected to the wire between the third switch and the fourth switch;

[0016] When a normal voltage signal is received, the first switch combination is closed and the second switch combination is opened, so that the first signal input end and the second signal input end respectively input normal voltage signals to the receiving path; and when a detection control signal is received, the first switch combination is opened and the second switch combination is closed, so that the DC power supply respectively inputs analog voltage signals to the receiving path.

[0017] In one embodiment, the switches in the first switch combination and / or the second switch combination are transmission gate switches, wherein the transmission gate switch includes a PMOS transistor and an NMOS transistor connected in parallel.

[0018] In one embodiment, the voltage elimination module includes a first current group and a second current group;

[0019] The first current group is connected to the non-inverting output terminal of any one-stage differential amplifier, and is used to output a compensation current to the non-inverting output terminal when receiving a voltage cancellation signal transmitted by the digital control module; the second current group is connected to the inverting output terminal of any one-stage differential amplifier, and is used to output a compensation current to the inverting output terminal when receiving a voltage cancellation signal transmitted by the digital control module;

[0020] The compensation current is used to eliminate the offset voltage within a preset elimination level range, so that the offset voltage detection signal meets a preset condition.

[0021] In one embodiment, the first current group includes at least one first current source group, each of which includes a fifth switch and a first current source; the second current group includes at least one second current source group, each of which includes a sixth switch and a second current source;

[0022] One end of the fifth switch is connected to the non-inverting output terminal of the any one-stage differential amplifier, and the other end of the fifth switch is connected to the first current source. The voltage cancellation signal includes a first control signal for the fifth switch, so as to close the fifth switch and output a compensation current to the non-inverting output terminal based on the first current source connected to the fifth switch. One end of the sixth switch is connected to the inverting output terminal of the any one-stage differential amplifier, and the other end of the sixth switch is connected to the second current source. The voltage cancellation signal includes a second control signal for the sixth switch, so as to close the sixth switch and output a compensation current to the inverting output terminal based on the second current source connected to the sixth switch.

[0023] In one embodiment, the voltage elimination module includes a reference current source, a first transistor, at least one first adjustable current group, each first adjustable current group includes a seventh switch and a second transistor, and at least one second adjustable current group, each second adjustable current group includes an eighth switch and a third transistor; wherein,

[0024] The drain of the first transistor is connected to the reference current source, and the gate and source of the first transistor are connected to the gate and source of the second transistor and the third transistor, respectively. The first transistor is configured to form a first current mirror circuit and a second current mirror circuit with the second transistor and the third transistor, respectively, so that the second transistor and the third transistor can output corresponding compensation currents based on the reference current source, respectively. The compensation current is configured to eliminate the offset voltage within a preset elimination level range, so that the offset voltage detection signal meets a preset condition.

[0025] One end of the seventh switch is connected to the inverting output terminal of the any one-stage differential amplifier, and the other end of the seventh switch is connected to the drain of the second transistor, and the voltage cancellation signal includes a third control signal for the seventh switch, so as to close the seventh switch and output a compensation current to the inverting output terminal based on the second transistor;

[0026] One end of the eighth switch is connected to the non-inverting output end of the any one-stage differential amplifier, and the other end thereof is connected to the drain of the third transistor. The voltage cancellation signal includes a fourth control signal for the eighth switch, so as to close the eighth switch and output a compensation current to the non-inverting output end based on the third transistor.

[0027] In one embodiment, the seventh switch and the eighth switch are NMOS transistors; wherein the drain of the NMOS transistor is connected to the non-inverting output terminal or the reverse output terminal of the differential amplifier of any one stage, the source thereof is connected to the corresponding first current mirror circuit or the second current mirror circuit, and the gate thereof is connected to the digital control module for receiving the third control signal or the fourth control signal transmitted by the digital control module.

[0028] In one embodiment, the circuit further comprises:

[0029] a blocking switch connected to the input end and the output end of the other one-stage or multi-stage differential amplifiers except the any one-stage differential amplifier;

[0030] The digital control module is further configured to transmit a fifth control signal to the blocking switch to disconnect the blocking switch and connect all differential amplifiers in the receiving path in sequence; the voltage elimination module is specifically configured to eliminate offset voltages of all differential amplifiers in the receiving path when all differential amplifiers are connected in sequence;

[0031] or,

[0032] The digital control module is further configured to transmit a sixth control signal to the blocking switch to close the blocking switch and short-circuit the differential amplifier connected to the blocking switch. The voltage elimination module is further configured to eliminate the offset voltage of the differential amplifier that is not short-circuited in the receiving path when the corresponding differential amplifier is short-circuited.

[0033] In one embodiment, the at least one cascaded differential amplifier includes one or any combination of the following: a variable gain amplifier VGA, a continuous time linear equalizer CTLE, and a decision feedback equalizer DFE.

[0034] According to another aspect of the present application, a voltage control method is provided, including a selection input SEL module, a digital control module, and a voltage elimination module, the method comprising:

[0035] The SEL module inputs an analog voltage signal to the receiving path to cause the receiving path to enter a voltage offset detection mode; wherein the receiving path includes at least one cascaded differential amplifier and a serial-to-parallel conversion module electrically connected to the output end of the last differential amplifier;

[0036] In the voltage offset detection mode, the digital control module receives the offset voltage detection signal transmitted by the serial-to-parallel conversion module, and generates a voltage elimination signal when the offset voltage detection signal does not meet a preset condition;

[0037] The voltage elimination module eliminates the offset voltage in the receiving path when receiving the voltage elimination signal transmitted by the digital control module.

[0038] According to another aspect of the present application, a chip is provided, comprising the voltage control circuit and a receiving path electrically connected to the voltage control circuit, wherein the receiving path comprises at least one cascaded differential amplifier and a serial-to-parallel conversion module electrically connected to the output end of the last-stage differential amplifier.

[0039] According to another aspect of the present application, an electronic device is provided, comprising the voltage control circuit.

[0040] The voltage control circuit, method, chip, and electronic device provided herein utilize an SEL module to input analog voltage information into a receiving path, thereby entering the receiving path's offset voltage detection mode. In this offset voltage detection mode, the digital control module utilizes the offset voltage detection signal to determine whether an offset voltage exists in the receiving path. If an offset voltage exists, the voltage cancellation module eliminates the overall offset voltage in the receiving path. This eliminates the need for adding separate compensation circuit structures to each differential amplifier stage, significantly improving the voltage cancellation efficiency in the receiving path. Furthermore, based on the SEL module's control input, the offset voltage detection process does not affect the receiving path's transceiver functions, achieving the goal of eliminating offset voltage without degrading the receiving-end circuit's performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0042] Figure 1 A possible schematic diagram of the receiving path;

[0043] Figure 2aThis is one of the structural diagrams of a voltage control circuit provided in an embodiment of the present application;

[0044] Figure 2b This is a second structural diagram of a voltage control circuit provided in an embodiment of the present application;

[0045] Figure 3a This is a third structural diagram of a voltage control circuit provided in an embodiment of the present application;

[0046] Figure 3b This is a fourth structural diagram of a voltage control circuit provided in an embodiment of the present application;

[0047] Figure 3c This is a fifth structural diagram of a voltage control circuit provided in an embodiment of the present application;

[0048] Figure 4a One of the circuit structure diagrams of the SEL module 21;

[0049] Figure 4b This is the second circuit structure diagram of the SEL module 21;

[0050] Figure 5a This is one of the circuit structure diagrams of the voltage elimination module 22;

[0051] Figure 5b This is the second circuit structure diagram of the voltage elimination module 22;

[0052] Figure 5c The third circuit structure diagram of the voltage elimination module 22;

[0053] Figure 6 A schematic structural diagram of another voltage control circuit provided in an embodiment of the present application;

[0054] Figure 7 A schematic flow chart of a voltage control method provided in an embodiment of the present application;

[0055] Figure 8 This is a schematic structural diagram of an offset voltage elimination chip provided in an embodiment of the present application;

[0056] Figure 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0057] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0058] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0059] Taking a high-speed transceiver link as an example, the receiving path of a high-speed transceiver link usually includes multiple differential amplifiers, such as Figure 1 As shown, the structure of the receiving path may include a variable gain amplifier (VGA) for adjusting the low-frequency gain; a continuous time linear equalizer (CTLE) for achieving high-frequency compensation; a decision feedback equalizer (DFE) for eliminating inter-symbol interference; and a serial-to-parallel conversion module connected after the differential amplifier to convert serial high-speed data after passing through the differential amplifier operational amplifier into parallel low-speed data.

[0060] VGAs, CTLEs, and DFEs all have structures similar to differential amplifiers. However, due to manufacturing defects, differential amplifiers inevitably generate offset voltages. For example, due to manufacturing defects, the two input terminals of the differential amplifier are asymmetrical. In this case, even if the differential input voltages are the same, the differential output voltages will be different. In other words, the differential amplifier generates an output offset voltage. Multiple differential amplifiers may generate multiple offset voltages simultaneously. Therefore, eliminating the offset voltage of the differential amplifier is important for improving the accuracy of sampled data.

[0061] In related technologies, the primary consideration is eliminating the offset voltage of a single-stage amplifier. For example, a compensation module is incorporated into a single-stage differential amplifier to eliminate the offset voltage of the single-stage differential amplifier. If voltage cancellation is required for multiple differential amplifiers simultaneously, voltage cancellation must be performed separately for each stage of the differential discharger, resulting in extremely low voltage cancellation efficiency for the entire receiving path. Furthermore, voltage cancellation for each stage of the differential amplifier requires integrating a separate compensation module for each stage, which necessitates the introduction of a complex compensation circuit structure into the existing path. This results in high power consumption and area in the receiving path, leading to excessively high costs.

[0062] In view of this, embodiments of the present application provide a voltage control circuit, method, chip, and electronic device. A selection input SEL module is electrically connected to a receiving path for inputting an analog voltage signal into the receiving path to cause the receiving path to enter a voltage offset detection mode. A digital control module is electrically connected to a serial-to-parallel conversion module in the receiving path. In the voltage offset detection mode, the digital control module receives an offset voltage detection signal transmitted by the serial-to-parallel conversion module and generates a voltage cancellation signal when the offset voltage detection signal does not meet a preset condition. A voltage cancellation module is electrically connected to the digital control module and any differential amplifier stage in the receiving path, respectively, for eliminating the offset voltage in the receiving path upon receiving the voltage cancellation signal transmitted by the digital control module. During this process, the SEL module inputs an analog voltage signal into the receiving path, causing the receiving path to enter an offset voltage detection mode. In this offset voltage detection mode, the digital control module uses the offset voltage detection signal to determine whether an offset voltage exists in the receiving path. If an offset voltage exists, the voltage cancellation module eliminates the total offset voltage in the receiving path. This eliminates the need to add separate compensation circuit structures to each differential amplifier stage, significantly improving the voltage cancellation efficiency in the receiving path. Furthermore, based on the control input of the SEL module, this embodiment enters a normal operating mode after performing offset voltage cancellation in the offset voltage detection mode, achieving the effect of eliminating offset voltage without degrading the performance of the receiving end circuit.

[0063] The voltage control circuit provided in the embodiments of the present application can be applied to high-speed transceiver link application scenarios. The following describes in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems, in conjunction with the accompanying drawings and specific embodiments. It should be noted that these specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0064] Figure 2a A schematic diagram of a voltage control circuit according to an embodiment of the present invention is shown in FIG. Figure 2a As shown, the voltage control circuit 20 includes a selection input SEL module 21 , a digital control module 22 and a voltage elimination module 23 .

[0065] Combine Figure 2b As shown, the selection input SEL module 21 is electrically connected to the input end of the receiving path 10 and is used to input an analog voltage signal to the receiving path 10 to enable the receiving path 10 to enter a voltage offset detection mode; wherein, the receiving path 10 includes at least one cascaded differential amplifier and a serial-to-parallel conversion module electrically connected to the output end of the last differential amplifier.

[0066] In this embodiment, receiving path 10 includes a variable gain amplifier (VGA) 11, a continuous time linear equalizer (CTLE) 12, and a decision feedback equalizer (DFE) 13, which are connected in sequence, and a serial-to-parallel conversion module 14 electrically connected to the output of decision feedback equalizer (DFE) 13. It should be noted that in some embodiments, the differential amplifier may also be of other cascade configurations or other types, which are not specifically limited in this embodiment.

[0067] In this embodiment, to improve the efficiency of offset voltage detection, the analog voltage signals can be two identical voltage signals. That is, two identical voltage signals are input to the two input terminals of the receiving path. If the voltage information of the two outputs after the differential amplifier is different, it indicates that an offset voltage has occurred. The two input terminals are the non-inverting input terminal (Input-Positive, INP) and the inverting input terminal (Input-Negative, INN).

[0068] The digital control module 22 is electrically connected to the serial-to-parallel conversion module 14 and is configured to receive an offset voltage detection signal transmitted by the serial-to-parallel conversion module 14 in a voltage offset detection mode, and generate a voltage elimination signal when the offset voltage detection signal does not meet a preset condition.

[0069] The voltage elimination module 23 is electrically connected to the digital control module and any differential amplifier in the receiving path, and is used to eliminate the offset voltage in the receiving path when receiving the voltage elimination signal transmitted by the digital control module.

[0070] In this embodiment, the receiving path 10 can include two operating modes: a voltage offset detection mode and a normal operating mode. Optionally, in the voltage offset detection mode, the serial-to-parallel conversion module 14 of the receiving path 10 does not output parallel low-speed data, but instead outputs an offset voltage detection signal to the digital control module 22 based on the outputs of each differential amplifier stage. In the normal operating mode, the serial-to-parallel conversion module 14 of the receiving path 10 outputs low-speed parallel data to the corresponding circuit structure in accordance with the normal operating mode.

[0071] In one implementation, the serial-to-parallel conversion module 14 includes a trigger. In voltage offset detection mode, it can calculate the ratio of 1s to 0s in the parallel data. The offset voltage detection signal carries this 1-to-0 ratio data and transmits the offset voltage detection signal to the digital control module 22. The digital control module 22 determines whether the ratio data meets a preset condition. For example, if the ratio of 1s to 0s exceeds a certain threshold, such as greater than 50% or less than 50%, it is considered that an offset voltage exists in the receiving path 10. The digital control module 22 then generates a voltage cancellation signal, which controls the voltage cancellation module 23 to eliminate the offset voltage in the path. After multiple rounds of adjustment, the ratio of 1s to 0s in the parallel data output by the serial-to-parallel conversion module is finally controlled to meet the preset condition, indicating that the offset voltage of the entire receiving path has been eliminated. The receiving path enters normal operating mode and outputs parallel low-speed data to the corresponding circuit structure.

[0072] It should be noted that those skilled in the art may adaptively set the preset conditions in combination with actual applications and existing technologies, and this embodiment does not specifically limit this.

[0073] In this embodiment, the voltage cancellation module 23 may be a current compensation structure. After receiving the voltage cancellation signal transmitted by the digital control module 22, it can eliminate the total offset voltage generated by each differential amplifier stage in the receiving path in the form of a compensation current, thereby improving the efficiency of offset voltage cancellation. The voltage cancellation module 23 can be connected to any stage of the differential amplifier, and optionally, connected to the output terminal of any stage of the differential amplifier.

[0074] In one embodiment, to improve the integration of offset voltage, the SEL module of this embodiment is controlled by a digital control module without requiring any external signals, thereby enabling flexible switching between a receiving path voltage offset detection mode and a normal operating mode. Specifically, the SEL module 21 is also electrically connected to the digital control module 22, configured to receive a detection control signal transmitted by the digital control module 22 and, based on the detection control signal, input an analog voltage signal to the receiving path 10 to cause the receiving path to enter the voltage offset detection mode.

[0075] According to the principle of eliminating offset voltage introduced above, this embodiment provides two possible examples, such as Figure 3a-3c shown. Figure 3a In the embodiment, the voltage elimination module 23 can be connected to the output end of the VGA 11 and integrated in the VGA 11 to receive the voltage elimination signal generated by the digital control module 22 to eliminate the offset voltage of the entire receiving path; Figure 3bIn the embodiment, the voltage elimination module 23 can be connected to the output terminal of the CTLE 12 and integrated in the CTLE 12 to receive the voltage elimination signal generated by the digital control module 22 to eliminate the offset voltage of the entire receiving path; Figure 3c In the embodiment, the offset voltage cancellation module 23 is integrated into the DFE 13 and receives the voltage cancellation signal generated by the digital control module 22, thereby eliminating the offset voltage of the entire receiving path. In other examples, other connection methods can also be used. This embodiment does not specifically limit the specific connection method of the voltage cancellation module 23.

[0076] Furthermore, in order to achieve efficient entry into a normal working state after the offset voltage in the receiving path is eliminated, the digital control module 22 of this embodiment is further configured to generate a voltage normal signal when the offset voltage detection signal meets a preset condition;

[0077] The SEL module 21 is further configured to receive a normal voltage signal transmitted by the digital control module 22 and input a normal voltage signal to the receiving path 10 according to the normal voltage signal, so that the receiving path 10 enters a normal working mode.

[0078] In this embodiment, the SEL module 21 is used to control two different working modes of the receiving path 10. After completing the offset voltage elimination in the offset voltage detection mode, the normal working mode is entered, thereby achieving the effect of eliminating the offset voltage without reducing the performance of the receiving end circuit.

[0079] The following is a detailed introduction to possible implementations of the SEL module 21:

[0080] In one embodiment, the SEL module 21 adopts a circuit structure of two switch combinations and a DC voltage source. For example, the two switch combinations may include four switches, such as Figure 4a As shown, it includes a first switch combination 211, a second switch combination 212 and a DC power supply DC; the first switch combination 211 includes a first switch SW1 and a second switch SW2, and the second switch combination 212 includes a third switch SW3 and a fourth switch SW4; wherein,

[0081] One end of the first switch SW1 is connected to a first signal input terminal (INP) for inputting a normal voltage signal to the receiving path 10, and the other end thereof is connected to a non-inverting input terminal (output OUTP, corresponding to the non-inverting input terminal INP of the differential amplifier) ​​of the first stage amplifier in the receiving path 10; one end of the second switch SW2 is connected to a second signal input terminal (INN) for inputting a normal voltage signal to the receiving path, and the other end thereof is connected to an inverting input terminal (input OUTN of SW2, corresponding to the inverting input terminal INN of the differential amplifier) ​​of the first stage amplifier in the receiving path;

[0082] One end of the third switch SW3 is connected to the wire between the first switch SW1 and the non-inverting input terminal (i.e., the output terminal OUTP), and the other end thereof is connected to the fourth switch SW4; one end of the fourth switch SW4 is connected to the wire between the second switch SW2 and the inverting input terminal (i.e., the output OUTN), and the other end thereof is connected to the third switch SW3;

[0083] One end of the DC power supply DC is grounded, and the other end thereof is connected to the wire between the third switch SW3 and the fourth switch SW4;

[0084] When a normal voltage signal is received, the first switch combination 211 is closed and the second switch combination 212 is opened, so that the first signal input terminal INP and the second signal input terminal INN respectively input normal voltage signals to the receiving path 10; and when a detection control signal is received, the first switch combination 211 is opened and the second switch combination 212 is closed, so that the DC power supply DC respectively inputs analog voltage signals to the receiving path 10.

[0085] In other words, when SW1 and SW2 are closed at the same time and SW3 and SW4 are opened at the same time, OUTP and INP corresponding to SW1 and SW2 are connected, OUTN and INN are connected, the DC voltage source DC is disconnected from OUTP and OUTN, and a normal voltage signal is input to the receiving path 10 via INP and INN; when SW1 and SW2 are opened at the same time and SW3 and SW4 are closed at the same time, OUTP and OUTN are connected, and are also connected to the DC voltage source DC, that is, the voltages of OUTP and OUTN are the same, both equal to the voltage of the DC source, which is equivalent to using a DC power supply to input an analog voltage signal to the receiving path 10.

[0086] Optionally, the switches in the first switch combination 211 and / or the second switch combination 212 are transmission gate switches, wherein the transmission gate switch includes a PMOS transistor and an NMOS transistor connected in parallel.

[0087] In this embodiment, the transmission gate switch utilizes the complementary characteristics of PMOS and NMOS transistors. The two MOS transistors are arranged symmetrically. The substrate of the PMOS transistor is connected to a high voltage level, and the substrate of the NMOS transistor is connected to a 0V voltage. The gates of the two MOS transistors serve as control terminals, and are respectively connected to a pair of mutually inverted control signals C and Cinvert. In this way, the resistance of the conductive channel can be controlled by controlling the potential difference between the gate and substrate of the MOS transistor.

[0088] In one implementation, if Figure 4bAs shown, the two gates of the transmission gate switch are connected to PUP and PUPx, which are a pair of inverted signals. Resistors R1 and R2 between the power supply VDD and ground divide the voltage to generate Vdc. When PUP is high (power supply voltage) and PUPx is low (ground voltage), switches SW3 and SW4 are turned on, and SW1 and SW2 are turned off. At this time, V OUTP =V OUTN = Vdc. Enter the offset voltage cancellation mode. When PUPx is high (power supply voltage) and PUP is low (ground voltage), switches SW1 and SW2 are turned on, and SW3 and SW4 are turned off. At this time, V OUTP =V INP 、V OUTN =V INN , enter normal working mode.

[0089] In some embodiments, the switch may also adopt a single PMOS or a single NMOS as a switch, or other complex switch structures, which is not specifically limited in this embodiment.

[0090] In the above circuit structure, efficient switching between different modes of the receiving path can be achieved using a relatively simple circuit structure.

[0091] The following is a detailed introduction to possible implementations of the voltage elimination module 23:

[0092] In one embodiment, a compensation current is input to the corresponding output terminal of the differential amplifier in the form of a current group to eliminate the offset voltage so that the voltages of the two output terminals are the same, such as Figure 5a As shown, the voltage elimination module 23 includes a first current group 231 and a second current group 232;

[0093] The first current group 231 is connected to the non-inverting output terminal OUTP of any one-stage differential amplifier, and is used to output the OUTP compensation current to the non-inverting output terminal when receiving the voltage cancellation signal transmitted by the digital control module 22; the second current group 232 is connected to the inverting output terminal OUTN of any one-stage differential amplifier, and is used to output the compensation current to the inverting output terminal OUTN when receiving the voltage cancellation signal transmitted by the digital control module 22;

[0094] The compensation current is used to eliminate the offset voltage within a preset elimination level range, so that the offset voltage detection signal meets a preset condition.

[0095] It should be noted that those skilled in the art may adaptively set the preset elimination magnitude range in combination with actual applications. For example, the offset voltage may be eliminated to within 0 or 0.2, so that the offset voltage can be ignored.

[0096] Furthermore, the first current group 231 includes at least one first current source group, each of which includes a fifth switch and a first current source; the second current group 232 includes at least one second current source group, each of which includes a sixth switch and a second current source;

[0097] One end of the fifth switch is connected to the non-inverting output terminal of the any one-stage differential amplifier, and the other end of the fifth switch is connected to the first current source. The voltage cancellation signal includes a first control signal for the fifth switch, so as to close the fifth switch and output a compensation current to the non-inverting output terminal based on the first current source connected to the fifth switch. One end of the sixth switch is connected to the inverting output terminal of the any one-stage differential amplifier, and the other end of the sixth switch is connected to the second current source. The voltage cancellation signal includes a second control signal for the sixth switch, so as to close the sixth switch and output a compensation current to the non-inverting output terminal based on the second current source connected to the sixth switch.

[0098] In this embodiment, the offset voltage elimination module 23 can be directly added to the output end of the differential amplifier, and can be added to the output end of the VGA 11, CTLE 12 or DFE 13. In one embodiment, Figure 5b As shown, the fifth switch includes P1, P2...PN, etc., the first current source includes I1, I2...IN, etc. The sixth switch includes N1, N2...NN, the first current source includes I1, I2...IN, etc. The switches in the first current group 231 and the second current group 232 can be selectively controlled by one or more of the switches according to the control information sent by the digital control module 22.

[0099] It can be understood that in this embodiment, by providing multiple fifth switches and corresponding first current sources, as well as multiple sixth switches and corresponding second current sources, advanced current compensation can be achieved, effectively avoiding the problem of compensating for excessive current at one time, which results in compensating for the current offset voltage but adding a new offset voltage, thereby making the voltage elimination method more refined.

[0100] In another embodiment, a current mirror is used to further improve the elimination efficiency of the offset voltage. Figure 5c As shown, the voltage elimination module 23 includes a reference current source I0, a first transistor M0, at least one first adjustable current group 51, each first adjustable current group 51 includes a seventh switch and a second transistor, and at least one second adjustable current group 52, each second adjustable current group 52 includes an eighth switch and a third transistor.

[0101] Optionally, the seventh and eighth switches are NMOS transistors; the seventh switch includes MN1, MN2, ..., MNN, and the eighth switch includes MM1, MM2, ..., MMN. Each switch can be controlled by a control signal carried by the offset voltage cancellation signal of the digital control module 22. The second transistors include M1, M2, ..., MN, and the third transistors include MC1, MC2, ..., MCN.

[0102] The drain of the first transistor M0 is connected to the reference current source I0, and the gate and source of the first transistor M0 are respectively connected to the gate and source of the second transistor (M1, M2...MN) and the third transistor (MC1, MC2...MCN), and are used to form a first current mirror circuit and a second current mirror circuit with the second transistor (M1, M2...MN) and the third transistor (MC1, MC2...MCN), respectively, so that the second transistor (M1, M2...MN) and the third transistor (MC1, MC2...MCN) can respectively output corresponding compensation currents based on the reference current source I0; wherein the compensation current is used to eliminate the offset voltage within a preset elimination magnitude range, so that the offset voltage detection signal meets preset conditions.

[0103] One end of the seventh switch is connected to the inverting output terminal of the any one-stage differential amplifier, and the other end of the seventh switch is connected to the drain of the second transistor, and the voltage cancellation signal includes a third control signal for the seventh switch, so as to close the seventh switch and output a compensation current to the inverting output terminal based on the second transistor;

[0104] One end of the eighth switch is connected to the non-inverting output end of the any one-stage differential amplifier, and the other end thereof is connected to the drain of the third transistor. The voltage cancellation signal includes a fourth control signal for the eighth switch, so as to close the eighth switch and output a compensation current to the non-inverting output end based on the third transistor.

[0105] Optionally, when the seventh switch and the eighth switch use NMOS tubes, the drain of the seventh switch (MN1, MN2...MNN) is connected to the inverting output terminal OUTN of the any one-stage differential amplifier, and its source is connected to the corresponding first current mirror circuit; the drain of the eighth switch (MM1, MM2...MMN) is connected to the non-inverting output terminal OUTP of the any one-stage differential amplifier, and its source is connected to the corresponding second current mirror circuit, and the gates of the seventh switch (MN1, MN2...MNN) and the eighth switch (MM1, MM2...MMN) are connected to the digital control module 22 for receiving the third control signal or the fourth control signal transmitted by the digital control module 22.

[0106] Figure 5c In the example, a current mirror structure is used, so that the circuit structures in the two dotted boxes are equivalent to two variable current sources. By adjusting the magnitude of the variable current, the offset voltage of OUTP and OUTN can be adjusted. Among them, the first current mirror structure composed of M0 and M1, M2, ..., MN can have a mirror current ratio of 1:2:...:2 N The second current mirror structure composed of M0 and MC1, MC2, ..., MCN can also have a mirror current ratio of 1:2:...:2 N MN1, MN2, ..., MNN and MM1, MM2, ..., MMN are switches composed of NMOS.

[0107] In this embodiment, a variable current source with a current mirror structure is used to achieve efficient current compensation in the circuit structure, while reducing current elements and simplifying the circuit structure.

[0108] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the structure of another voltage control circuit provided in an embodiment of the present application. Based on the above embodiment, a blocking switch is added to achieve offset voltage cancellation for some differential amplifiers in the receiving path, thereby achieving the purpose of eliminating the offset voltage of each amplifier stage separately, thereby achieving the purpose of eliminating multi-stage offset voltage. Specifically, the voltage control circuit also includes:

[0109] The blocking switch 61 is respectively connected to the input end and the output end of the other one-stage or multi-stage differential amplifiers except the any one-stage differential amplifier.

[0110] The digital control module 22 is further configured to transmit a fifth control signal to the blocking switch to disconnect the blocking switch and connect all differential amplifiers in the receiving path in sequence; the voltage elimination module is specifically configured to eliminate the offset voltage of all differential amplifiers in the receiving path when all differential amplifiers are connected in sequence; or

[0111] The digital control module 22 is further configured to transmit a sixth control signal to the blocking switch to close the blocking switch and short-circuit the differential amplifier corresponding to the blocking switch. The voltage elimination module is further configured to eliminate the offset voltage of the differential amplifier that is not short-circuited in the receiving path when the corresponding differential amplifier is short-circuited.

[0112] For example, Figure 6 Specifically, when the voltage elimination module 23 is integrated into the VGA, the blocking switch 51 is added across the CTLE 12 . In other examples, the blocking switch 51 may be added across the DFE 13 , or across the CTLE and DFE 13 , or in other connection modes.

[0113] In this embodiment, blocking switches are added across the differential amplifiers other than those not connected to the offset voltage cancellation module 23. By closing the blocking switches, the differential amplifiers are short-circuited. The offset voltage cancellation module 23 is used to detect and eliminate the offset of one or more differential amplifiers not short-circuited, thereby effectively improving the flexibility of receiving offset voltage elimination.

[0114] The embodiment of the present application also provides a voltage control method, including a selection input SEL module, a digital control module and a voltage elimination module, such as Figure 7 As shown, the method includes steps S701-S703:

[0115] Step S701: The SEL module inputs an analog voltage signal to a receiving path to cause the receiving path to enter a voltage offset detection mode; wherein the receiving path includes at least one cascaded differential amplifier and a serial-to-parallel conversion module electrically connected to the output end of the last differential amplifier stage;

[0116] Step S702: In the voltage offset detection mode, the digital control module receives the offset voltage detection signal transmitted by the serial-to-parallel conversion module, and generates a voltage elimination signal when the offset voltage detection signal does not meet a preset condition;

[0117] Step S703 : When the voltage elimination module receives the voltage elimination signal transmitted by the digital control module, the voltage elimination module eliminates the offset voltage in the receiving path.

[0118] This embodiment also provides a chip, such as Figure 8 As shown, it includes the voltage control circuit 81 and a receiving path 82 electrically connected to the voltage control circuit 81, and the receiving path includes at least one cascaded differential amplifier and a serial-to-parallel conversion module electrically connected to the output end of the last stage differential amplifier.

[0119] The embodiment of the present application also provides a computer-readable storage medium, which enables the computer to execute the voltage control method when the computer program code runs on the computer.

[0120] Among them, the computer-readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

[0121] The relevant explanations can be understood by referring to the corresponding descriptions and effects in the corresponding device embodiments, and will not be elaborated here.

[0122] The present application also provides an electronic device. Figure 9As shown, it includes: a processor 91, and a memory 92 that is communicatively connected to the processor 91;

[0123] The memory 92 stores computer-executable instructions;

[0124] The processor 91 executes the computer-executable instructions stored in the memory 92 to implement the voltage control method. The memory 92 and the processor 91 are connected via a bus 93 .

[0125] The relevant explanations can be understood by referring to the corresponding descriptions and effects in the corresponding device embodiments, and will not be elaborated here.

[0126] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0127] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0128] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A voltage control circuit, characterized in that: It includes a selection input SEL module, a digital control module and a voltage elimination module, wherein: The SEL module is electrically connected to the input end of the receiving path and is used to input an analog voltage signal to the receiving path so that the receiving path enters a voltage offset detection mode; wherein the receiving path includes at least one cascaded differential amplifier and a serial-to-parallel conversion module electrically connected to the output end of the last differential amplifier; The digital control module is electrically connected to the output end of the serial-to-parallel conversion module, and is used to receive the offset voltage detection signal transmitted by the serial-to-parallel conversion module in the voltage offset detection mode, and generate a voltage elimination signal when the offset voltage detection signal does not meet the preset condition; The voltage elimination module is electrically connected to the digital control module and any one stage of differential amplifier in the receiving path respectively, and is used to eliminate the offset voltage in the receiving path when receiving the voltage elimination signal transmitted by the digital control module.

2. The voltage control circuit according to claim 1, characterized in that: The SEL module is also electrically connected to the digital control module, and is used to receive a detection control signal transmitted by the digital control module, and input an analog voltage signal to the receiving path according to the detection control signal, so that the receiving path enters a voltage imbalance detection mode.

3. The voltage control circuit according to claim 2, characterized in that: The digital control module is also used to generate a voltage normal signal when the offset voltage detection signal meets a preset condition; The SEL module is further used to receive a normal voltage signal transmitted by the digital control module, and input a normal voltage signal to the receiving path according to the normal voltage signal, so that the receiving path enters a normal working mode.

4. The voltage control circuit according to claim 3, characterized in that: The SEL module includes a first switch combination, a second switch combination and a DC power supply; the first switch combination includes a first switch and a second switch, and the second switch combination includes a third switch and a fourth switch; wherein, One end of the first switch is connected to a first signal input terminal for inputting a normal voltage signal to the receiving path, and the other end thereof is connected to a non-inverting input terminal of a first-stage amplifier in the receiving path; one end of the second switch is connected to a second signal input terminal for inputting a normal voltage signal to the receiving path, and the other end thereof is connected to an inverting input terminal of the first-stage amplifier in the receiving path; One end of the third switch is connected to the wire between the first switch and the non-inverting input terminal, and the other end thereof is connected to the fourth switch; one end of the fourth switch is connected to the wire between the second switch and the inverting input terminal, and the other end thereof is connected to the third switch; One end of the DC power supply is grounded, and the other end thereof is connected to the wire between the third switch and the fourth switch; When a normal voltage signal is received, the first switch combination is closed and the second switch combination is opened, so that the first signal input terminal and the second signal input terminal respectively input a normal voltage signal to the receiving path; and when a detection control signal is received, the first switch combination is opened and the second switch combination is closed, so that the DC power supply respectively inputs an analog voltage signal to the receiving path.

5. The voltage control circuit according to claim 4, characterized in that: The switches in the first switch combination and / or the second switch combination are transmission gate switches, wherein the transmission gate switch includes a PMOS transistor and an NMOS transistor connected in parallel.

6. The voltage control circuit according to any one of claims 1 to 5, characterized in that: The voltage elimination module includes a first current group and a second current group; The first current group is connected to the in-phase output terminal of any one-stage differential amplifier, and is used to output a compensation current to the in-phase output terminal when receiving a voltage elimination signal transmitted by the digital control module; the second current group is connected to the inverting output terminal of any one-stage differential amplifier, and is used to output a compensation current to the inverting output terminal when receiving a voltage elimination signal transmitted by the digital control module; The compensation current is used to eliminate the offset voltage within a preset elimination magnitude range, so that the offset voltage detection signal meets a preset condition.

7. The voltage control circuit according to claim 6, characterized in that: The first current group includes at least one first current source group, each of which includes a fifth switch and a first current source; the second current group includes at least one second current source group, each of which includes a sixth switch and a second current source; One end of the fifth switch is connected to the in-phase output terminal of the any-stage differential amplifier, and the other end of the fifth switch is connected to the first current source. The voltage elimination signal includes a first control signal for the fifth switch, so that the fifth switch is closed, and a compensation current is output to the in-phase output terminal based on the first current source connected to the fifth switch; one end of the sixth switch is connected to the inverting output terminal of the any-stage differential amplifier, and the other end of the sixth switch is connected to the second current source. The voltage elimination signal includes a second control signal for the sixth switch, so that the sixth switch is closed, and a compensation current is output to the inverting output terminal based on the second current source connected to the sixth switch.

8. The voltage control circuit according to any one of claims 1 to 5, characterized in that: The voltage elimination module includes a reference current source, a first transistor, at least one first adjustable current group, each of which includes a seventh switch and a second transistor, and at least one second adjustable current group, each of which includes an eighth switch and a third transistor; wherein, The drain of the first transistor is connected to the reference current source, and the gate and source of the first transistor are connected to the gate and source of the second transistor and the third transistor respectively, so as to form a first current mirror circuit and a second current mirror circuit with the second transistor and the third transistor respectively, so that the second transistor and the third transistor can output corresponding compensation currents based on the reference current source respectively; wherein the compensation current is used to eliminate the offset voltage within a preset elimination magnitude range, so that the offset voltage detection signal meets a preset condition; One end of the seventh switch is connected to the inverting output end of the any one-stage differential amplifier, and the other end is connected to the drain of the second transistor, and the voltage elimination signal includes a third control signal for the seventh switch, so that the seventh switch is closed and a compensation current is output to the inverting output end based on the second transistor; One end of the eighth switch is connected to the in-phase output end of the any one-stage differential amplifier, and the other end is connected to the drain of the third transistor. The voltage elimination signal includes a fourth control signal to the eighth switch to close the eighth switch and output a compensation current to the in-phase output end based on the third transistor.

9. The voltage control circuit according to claim 8, characterized in that: The seventh switch and the eighth switch use NMOS transistors; wherein the drain of the NMOS tube is connected to the positive output terminal or the negative output terminal of the any one-stage differential amplifier, the source thereof is connected to the corresponding first current mirror circuit or the second current mirror circuit, and the gate thereof is connected to the digital control module, for receiving the third control signal or the fourth control signal transmitted by the digital control module.

10. The voltage control circuit according to any one of claims 1 to 5, characterized in that: Also includes: A blocking switch, which is respectively connected to the input end and the output end of the other one-stage or multiple-stage differential amplifiers except the any one-stage differential amplifier; The digital control module is further used to transmit a fifth control signal to the blocking switch to disconnect the blocking switch and connect all differential amplifiers in the receiving path in sequence; the voltage elimination module is specifically used to eliminate the offset voltage of all differential amplifiers in the receiving path when all differential amplifiers are connected in sequence; or, The digital control module is also used to transmit a sixth control signal to the blocking switch to close the blocking switch and short-circuit the differential amplifier corresponding to the blocking switch. The voltage elimination module is also used to eliminate the offset voltage of the differential amplifier that is not short-circuited in the receiving path when the corresponding differential amplifier is short-circuited.

11. A voltage control method, characterized in that: The method comprises a selection input SEL module, a digital control module and a voltage elimination module, and the method comprises: The SEL module inputs an analog voltage signal to the receiving path so that the receiving path enters a voltage imbalance detection mode; wherein the receiving path includes at least one cascaded differential amplifier and a serial-to-parallel conversion module electrically connected to the output end of the last differential amplifier; In the voltage offset detection mode, the digital control module receives the offset voltage detection signal transmitted by the serial-to-parallel conversion module, and generates a voltage elimination signal when the offset voltage detection signal does not meet a preset condition; The voltage elimination module eliminates the offset voltage in the receiving path when receiving the voltage elimination signal transmitted by the digital control module.

12. A chip, characterized in that: It comprises a voltage control circuit as described in any one of claims 1 to 10, and a receiving path electrically connected to the voltage control circuit, wherein the receiving path comprises at least one cascaded differential amplifier and a serial-to-parallel conversion module electrically connected to the output end of the last stage differential amplifier.

13. An electronic device, characterized in that: Comprising the voltage control circuit as described in any one of claims 1-10.

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