High-voltage LDO circuit and chip

Abstract

The invention provides a high-voltage LDO circuit and a chip, and relates to the technical field of electronics, the circuit comprises a current mirroring circuit, a voltage stabilizing circuit, a voltage feedback circuit and an adjusting circuit, the current mirroring circuit is used for mirroring a preset current provided by a constant current source to obtain a target mirroring current, and the target mirroring current is input to the input end of the voltage stabilizing circuit; the output end of the voltage stabilizing circuit is electrically connected with the control end of the adjusting circuit, and the voltage stabilizing circuit is used for stabilizing the voltage of the control end of the adjusting circuit within a first preset voltage range; the voltage feedback circuit is connected between the control end of the adjusting circuit and the output end of the adjusting circuit, and the voltage feedback circuit is used for adjusting the voltage of the control end of the adjusting circuit based on the output voltage of the adjusting circuit, so that the voltage of the output end of the adjusting circuit is stabilized within a second preset voltage range. According to the technical scheme, the effect of simplifying the overall design of the high-voltage LDO circuit is achieved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a high-voltage LDO circuit and chip. Background Art

[0002] In the design of modern electronic equipment, the design of high-voltage LDO circuits has received increasing attention and is widely used in many electronic products and systems. While maintaining the output voltage stable, it can also efficiently adjust the input voltage to the required output voltage, greatly improving the performance and reliability of electronic equipment. As electronic equipment develops towards miniaturization, high current and low power consumption, high-voltage LDO circuits, as one of the indispensable power modules, have also become the focus of attention for their integration and control performance. However, due to the complex design of the high-voltage LDO circuits in related technologies, complex reference circuits, error amplifiers, etc. are often used, such as Figure 1 As shown, VREF is the reference voltage ( Figure 1 The reference voltage circuit is not shown in the figure), which leads to difficulty in internal integration and increases the chip area. It can be seen that the high-voltage LDO circuit in the related art has technical problems such as complex circuit and large circuit area. Summary of the invention

[0003] The purpose of this application is to overcome the above technical problems. This application provides a high-voltage LDO circuit and chip.

[0004] In a first aspect, the present application provides a high-voltage LDO circuit, comprising: a current mirror circuit, a voltage stabilizing circuit, a voltage feedback circuit, and an adjustment circuit, wherein an input end of the current mirror circuit is electrically connected to a constant current source, and an output end of the current mirror circuit is electrically connected to an input end of the voltage stabilizing circuit, wherein the current mirror circuit is used to mirror a preset current provided by the constant current source to obtain a target mirror current, and the target mirror current is input to the input end of the voltage stabilizing circuit; the output end of the voltage stabilizing circuit is electrically connected to a control end of the adjustment circuit, and the voltage stabilizing circuit is used to stabilize the control end voltage of the adjustment circuit within a first preset voltage range; the voltage feedback circuit is connected between the control end of the adjustment circuit and the output end of the adjustment circuit, and the voltage feedback circuit is used to adjust the voltage of the control end of the adjustment circuit based on the output voltage of the adjustment circuit, so that the output end voltage of the adjustment circuit is stabilized within a second preset voltage range.

[0005] By adopting the above technical solution, the high-voltage LDO circuit includes a current mirror circuit, a voltage stabilizing circuit, a voltage feedback circuit and an adjustment circuit, wherein the current mirror circuit provides a target mirror current to the voltage stabilizing circuit, and the voltage stabilizing circuit is used to provide a voltage within a first preset voltage range to the control end of the adjustment circuit, thereby avoiding the problem of a more complex circuit and a larger chip area occupied by the reference voltage circuit in the related art, and the voltage feedback circuit adjusts the voltage of the control end of the adjustment circuit according to the output voltage of the adjustment circuit, so that the output voltage of the adjustment circuit is stabilized within the second preset voltage range, thereby ensuring the stability of the output voltage. It also reduces the dependence on the error amplifier, thereby simplifying the overall design of the high-voltage LDO circuit, making the high-voltage LDO circuit easier to integrate into miniaturized electronic devices, helping to reduce the chip area and improve the integration. By adopting a combination of a current mirror circuit, a voltage stabilizing circuit, a voltage feedback circuit and an adjustment circuit, the output voltage can be controlled more accurately, ensuring that the output voltage is stable within a preset range, and improving the performance and reliability of the LDO circuit.

[0006] Optionally, the voltage stabilizing circuit includes a first NLDMOS tube, a first voltage stabilizing tube, a second voltage stabilizing tube and a first resistor, wherein the drain of the first NLDMOS tube is electrically connected to the gate of the first NLDMOS tube, the source of the first NLDMOS tube is electrically connected to the negative electrode of the first voltage stabilizing tube, the positive electrode of the first voltage stabilizing tube is electrically connected to the negative electrode of the second voltage stabilizing tube, and the positive electrode of the second voltage stabilizing tube is electrically connected to the ground terminal through the first resistor, wherein the drain of the first NLDMOS tube serves as the input end of the voltage stabilizing circuit, and the gate of the first NLDMOS tube serves as the output end of the voltage stabilizing circuit.

[0007] By adopting the above technical solution, the voltage stabilizing circuit includes a first NLDMOS tube, a first voltage stabilizing tube, a second voltage stabilizing tube and a first resistor connected in series in sequence, so that the voltage stabilizing circuit can provide a relatively stable reference voltage to the control end of the adjustment circuit, that is, a voltage within a first preset voltage range. In the related art, the reference voltage circuit in the high-voltage LDO circuit is generally very complex. Compared with the traditional complex reference voltage circuit, the combination of the high-voltage LDO circuit of the present technical solution simplifies the circuit structure, reduces the number of required components, and reduces the complexity and cost of the design.

[0008] Optionally, the current mirror circuit includes: a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube, wherein the drain of the first NMOS tube is electrically connected to the gate of the first NMOS tube, the gate of the first NMOS tube is electrically connected to the gate of the second NMOS tube, the source of the first NMOS tube and the source of the second NMOS tube are both electrically connected to the ground terminal, and the drain of the first NMOS tube is electrically connected to the constant current source; the drain of the second NMOS tube is electrically connected to the drain of the first PMOS tube, the drain of the first PMOS tube is electrically connected to the gate of the first PMOS tube, the gate of the first PMOS tube is electrically connected to the gate of the second PMOS tube, and the source of the first PMOS tube and the source of the second PMOS tube are both electrically connected to the power supply terminal, wherein the drain of the second PMOS tube serves as the output end of the current mirror circuit.

[0009] By adopting the above technical solution, a current mirror circuit is formed by the first NMOS tube, the second NMOS tube, the first PMOS tube and the second PMOS tube, and the preset current provided by the constant current source is mirrored to provide a stable current for the voltage stabilization circuit, thereby achieving precise control of the current. By designing a current mirror circuit including NMOS and PMOS transistors, current stability under different operating voltages and load conditions can be achieved. This design utilizes the basic principle of the current mirror, that is, using the current-voltage characteristics of the transistor to copy or mirror a current, thereby ensuring the stability and accuracy of the output current.

[0010] Optionally, the current mirror circuit also includes: a third NMOS tube and a second NLDMOS tube, the drain of the first NMOS tube is electrically connected to the constant current source through the third NMOS tube, and the drain of the second NMOS tube is electrically connected to the drain of the first PMOS tube through the second NLDMOS tube, wherein the source of the third NMOS tube is electrically connected to the drain of the first NMOS tube, the drain of the third NMOS tube is electrically connected to the constant current source, and the drain of the third NMOS tube is electrically connected to the gate of the third NMOS tube; the gate of the second NLDMOS tube is electrically connected to the gate of the third NMOS tube, the source of the second NLDMOS tube is electrically connected to the drain of the second NMOS tube, and the drain of the second NLDMOS tube is electrically connected to the drain of the first PMOS tube.

[0011] By adopting the above technical solution, the accuracy and stability of the current mirror are improved by connecting the third NMOS tube and the second NLDMOS tube in series, and the reliability and anti-interference ability of the circuit are enhanced. In the current mirror circuit, it is more common to use two tubes, such as the first NMOS tube and the second NMOS tube. The technical solution is implemented by adding the third NMOS tube and the second NLDMOS tube, that is, using four MOS tubes. This series structure can make the current mirror more accurate.

[0012] Optionally, the adjustment circuit includes a third NLDMOS tube, wherein the gate of the third NLDMOS tube is electrically connected to the output end of the voltage stabilizing circuit, the drain of the third NLDMOS tube is electrically connected to the power supply end, and the source of the third NLDMOS tube serves as the output end of the adjustment circuit.

[0013] By adopting the above technical solution, the adjustment circuit adopts a third NLDMOS tube, and the gate of the third NLDMOS tube is electrically connected to the output end of the voltage stabilizing circuit, such as the gate of the first NLDMOS tube mentioned above. The source of the third NLDMOS tube serves as the output end of the adjustment circuit and also as the output end of the entire high-voltage LDO circuit, and is used to output a voltage within a second preset voltage range. By adopting the third NLDMOS tube as the main component of the adjustment circuit, the output voltage can be more effectively controlled and the accuracy of voltage adjustment can be improved. By fine-tuning the gate voltage of the third NLDMOS tube, the conduction degree of the third NLDMOS tube can be changed to adjust the output voltage, thereby achieving precise adjustment of the output voltage and improving the accuracy and stability of the output voltage.

[0014] Optionally, the adjustment circuit further includes a third voltage regulator tube, wherein the positive electrode of the third voltage regulator tube is electrically connected to the source electrode of the third NLDMOS tube, and the negative electrode of the third voltage regulator tube is electrically connected to the gate electrode of the third NLDMOS tube.

[0015] By adopting the above technical solution, by connecting the third voltage regulator tube in parallel between the gate and source of the third NLDMOS tube, the third NLDMOS tube can be protected. Thus, while ensuring the stability of the output voltage, the third NLDMOS tube is effectively protected to prevent damage caused by too low output voltage, further improving the reliability and stability of the circuit. By introducing the third voltage regulator tube, the output voltage stability of the high-voltage LDO circuit can be significantly improved, and the output voltage fluctuation caused by factors such as input voltage fluctuation, load current change or temperature change can be reduced.

[0016] Optionally, the voltage feedback circuit includes a second resistor, a third resistor and a fourth NLDMOS tube, wherein the first end of the second resistor is electrically connected to the source of the third NLDMOS tube, the second end of the second resistor is electrically connected to the ground terminal through the third resistor, the second end of the second resistor is also electrically connected to the gate of the fourth NLDMOS tube, the drain of the fourth NLDMOS tube is electrically connected to the gate of the third NLDMOS tube, and the source of the fourth NLDMOS tube is electrically connected to the ground terminal.

[0017] By adopting the above technical solution, effective feedback of the output voltage of the adjustment circuit is achieved through the voltage division of the second resistor and the third resistor. When the output voltage exceeds the preset range, for example, is not within the second preset voltage range, the conduction degree of the fourth NLDMOS tube can be adjusted through the voltage division of the third resistor, and then the control end (that is, the gate voltage) of the third NLDMOS tube can be adjusted, so as to ensure that the output voltage of the adjustment circuit is stable within the second preset voltage range; that is, the fourth NLDMOS tube is used as a regulating element to fine-tune the gate voltage of the third NLDMOS tube, thereby enhancing the stability of the output voltage.

[0018] Optionally, the high-voltage LDO circuit further includes a first capacitor, wherein the first capacitor is connected between the output terminal of the adjustment circuit and the ground terminal.

[0019] By adopting the above technical solution, the first capacitor serves as the output high-frequency filter capacitor of the high-voltage LDO circuit, and plays a role in voltage stabilization and filtering. It can effectively filter out high-frequency noise in the output voltage, ensure the stability and purity of the output voltage, and thus improve the reliability of the entire circuit. It avoids the need for multi-stage amplification inside the high-voltage LDO circuit in the related art, and the inability to integrate capacitors inside the chip, resulting in only external capacitors outside the high-voltage LDO circuit, which increases the number of devices and causes the chip to become larger in size.

[0020] Optionally, the above-mentioned high-voltage LDO circuit also includes an undervoltage protection circuit and a fourth NMOS tube, the fourth NMOS tube is connected between the input end of the current mirror circuit and the constant current source, wherein the undervoltage protection circuit is electrically connected to the gate of the fourth NMOS tube, the source of the fourth NMOS tube is electrically connected to the input end of the current mirror circuit, and the drain of the fourth NMOS tube is electrically connected to the constant current source, wherein the undervoltage protection circuit is configured to control the fourth NMOS tube to be in an off state when the voltage at the power supply end of the high-voltage LDO circuit is less than or equal to a preset voltage threshold, and to control the fourth NMOS tube to be in an on state when the voltage at the power supply end of the high-voltage LDO circuit is greater than the preset voltage threshold.

[0021] By adopting the above technical solution, the high-voltage LDO circuit integrates the undervoltage protection circuit and the fourth NMOS tube. The undervoltage protection circuit can control the fourth NMOS tube to turn off when the voltage at the power supply end is lower than the preset voltage threshold, thereby cutting off the connection between the input end of the current mirror circuit and the constant current source, avoiding the erroneous operation of the circuit under the undervoltage state, and improving the reliability of the system. When the voltage at the power supply end is higher than the preset voltage threshold, the fourth NMOS tube is turned on, ensuring the current supply under normal working conditions, and ensuring the stable operation of the high-voltage LDO circuit.

[0022] In a second aspect of the present application, a chip is also provided, comprising any of the above-mentioned high-voltage LDO circuits.

[0023] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages: 1. By adopting a combination of current mirror circuit, voltage stabilization circuit, voltage feedback circuit and adjustment circuit, the output voltage can be controlled more accurately to ensure that the output voltage is stable within a preset range, thereby improving the performance and reliability of the LDO circuit, avoiding the problem of complex circuits and large chip area caused by the use of reference voltage circuits in related technologies, and reducing the dependence on the error amplifier, thereby simplifying the overall design of the high-voltage LDO circuit; 2. By using the third NLDMOS tube as the main component of the adjustment circuit, the output voltage can be controlled more effectively and the accuracy of voltage adjustment can be improved. By fine-tuning the gate voltage of the third NLDMOS tube, the conduction degree of the third NLDMOS tube can be changed to adjust the output voltage, thereby achieving accurate adjustment of the output voltage and improving the accuracy and stability of the output voltage; 3. It avoids the problem that the high-voltage LDO circuit in the related technology needs multiple stages of amplification, and the capacitor cannot be integrated inside the chip, so that the capacitor can only be connected to the outside of the high-voltage LDO circuit, which increases the number of devices and also causes the chip to become larger in size. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of a high voltage LDO circuit in the related art; Figure 2 It is a framework diagram of a high-voltage LDO circuit provided in an embodiment of the present application; Figure 3 This is a schematic diagram of a high-voltage LDO circuit provided in an embodiment of the present application; Figure 4 This is a waveform diagram of a high-voltage LDO input and output provided in an embodiment of the present application.

[0025] Description of reference numerals: The first resistor R1, the second resistor R2, the third resistor R3, the first capacitor C1, the first NMOS tube N1, the second NMOS tube N2, the third NMOS tube N3, the fourth NMOS tube N4, the first PMOS tube P1, the second PMOS tube P2, the first NLDMOS tube NLD1, the second NLDMOS tube NLD2, the third NLDMOS tube NLD3, the fourth NLDMOS tube NLD4, the first voltage regulator tube D1, the second voltage regulator tube D2, and the third voltage regulator tube D3. DETAILED DESCRIPTION

[0026] In order to enable technicians in this field to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0027] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.

[0028] In the description of the embodiments of the present application, the term "plurality" means two or more. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0029] Some professional terms or nouns involved in the embodiments of this application are now explained: LDO: Low Dropout Regulator, also known as low dropout linear regulator; NLDMOS: Lateral Double-diffused Metal Oxide Semiconductor, N-type lateral double diffused MOS tube.

[0030] The following is combined with Figure 2-Figure 4 The embodiments of the present application are described in detail.

[0031] The present application provides a high voltage LDO circuit, referring to Figure 2 , Figure 2 : is a framework diagram of a high-voltage LDO circuit provided in an embodiment of the present application, the high-voltage LDO circuit includes: a current mirror circuit, a voltage stabilization circuit, a voltage feedback circuit, and an adjustment circuit, wherein: The input end of the current mirror circuit is electrically connected to the constant current source, and the output end of the current mirror circuit is electrically connected to the input end of the voltage stabilizing circuit, wherein the current mirror circuit is used to mirror the preset current provided by the constant current source to obtain a target mirror current, and the target mirror current is input to the input end of the voltage stabilizing circuit; The output end of the voltage stabilizing circuit is electrically connected to the control end of the regulating circuit, and the voltage stabilizing circuit is used to stabilize the voltage of the control end of the regulating circuit within a first preset voltage range; The voltage feedback circuit is connected between the control end of the adjustment circuit and the output end of the adjustment circuit. The voltage feedback circuit is used to adjust the voltage of the control end of the adjustment circuit based on the output voltage of the adjustment circuit so that the output end voltage of the adjustment circuit is stabilized within a second preset voltage range.

[0032] In the above embodiment, the high-voltage LDO circuit includes a current mirror circuit, a voltage stabilizing circuit, a voltage feedback circuit and an adjustment circuit, wherein the current mirror circuit provides a target mirror current to the voltage stabilizing circuit, and the voltage stabilizing circuit is used to provide a voltage within a first preset voltage range to the control end of the adjustment circuit, thereby avoiding the problem of a more complex circuit and a larger chip area occupied by the reference voltage circuit in the related art, and the voltage feedback circuit adjusts the voltage of the control end of the adjustment circuit according to the output voltage of the adjustment circuit, so that the output voltage of the adjustment circuit is stabilized within the second preset voltage range, thereby ensuring the stability of the output voltage. It also reduces the dependence on the error amplifier, thereby simplifying the overall design of the high-voltage LDO circuit, making the high-voltage LDO circuit easier to integrate into miniaturized electronic devices, helping to reduce the chip area and improve the integration. By adopting a combination of a current mirror circuit, a voltage stabilizing circuit, a voltage feedback circuit and an adjustment circuit, the output voltage can be controlled more accurately, ensuring that the output voltage is stable within a preset range, and improving the performance and reliability of the LDO circuit. The above-mentioned voltage stabilizing circuit provides a stable voltage within the first preset voltage range for the control end of the adjustment circuit, which is equivalent to providing a reference voltage, thereby avoiding the problem of a more complex reference voltage circuit and a larger chip (or PCB board) area occupied in the related art. The high-voltage LDO circuit in the embodiment of the present application does not need to rely on the error amplifier, and can fine-tune the voltage of the control end of the adjustment circuit, thereby adjusting the output end voltage of the adjustment circuit, so that the output voltage is stable within the second preset voltage range. The above-mentioned first preset voltage range can be within the first percentage range of the first voltage, for example, the first voltage is 13V (or other voltage), and the first percentage is 3% (or other percentage); the above-mentioned second preset voltage range can be within the second percentage range of the second voltage, for example, the second voltage is 12V (or other voltage), and the second percentage is 1% (or other percentage). The simplified circuit design helps to reduce the power consumption of the circuit during operation, which is in line with the current trend of electronic equipment to develop in the direction of low power consumption. The design of the voltage stabilization circuit and the voltage feedback circuit ensures that the control end voltage and the output end voltage of the adjustment circuit can work stably within the preset range, thereby improving the stability and reliability of the LDO circuit. The simplified circuit design reduces unnecessary power consumption components, reduces the overall power consumption of the circuit during operation, and helps to extend the battery life and service life of electronic equipment. By optimizing the circuit design, the use of complex components is reduced, the manufacturing cost is reduced, and the high-voltage LDO circuit is more economical and practical.

[0033] In an optional embodiment, if Figure 3As shown, the voltage stabilizing circuit includes a first NLDMOS tube NLD1, a first voltage stabilizing tube D1, a second voltage stabilizing tube D2 and a first resistor R1, wherein the drain of the first NLDMOS tube NLD1 is electrically connected to the gate of the first NLDMOS tube NLD1, the source of the first NLDMOS tube NLD1 is electrically connected to the negative electrode of the first voltage stabilizing tube D1, the positive electrode of the first voltage stabilizing tube D1 is electrically connected to the negative electrode of the second voltage stabilizing tube D2, and the positive electrode of the second voltage stabilizing tube D2 is electrically connected to the ground terminal through the first resistor R1, wherein the drain of the first NLDMOS tube NLD1 serves as the input end of the voltage stabilizing circuit, and the gate of the first NLDMOS tube NLD1 serves as the output end of the voltage stabilizing circuit.

[0034] In the above embodiment, the voltage stabilizing circuit includes a first NLDMOS tube NLD1, a first voltage stabilizing tube D1, a second voltage stabilizing tube D2 and a first resistor R1 connected in series in sequence, so that the voltage stabilizing circuit can provide a relatively stable reference voltage to the control end of the adjustment circuit, that is, a voltage within a first preset voltage range. Taking the output voltage required by the high-voltage LDO circuit design as 12V as an example, the reference voltage provided by the voltage stabilizing circuit can be a voltage of about 13V, or 13V fluctuates by a first percentage (such as 3%, or other), while the reference voltage circuit in the high-voltage LDO circuit in the related art is generally very complex. Compared with the traditional complex reference voltage circuit, the combination of the high-voltage LDO circuit in this embodiment simplifies the circuit structure, reduces the number of required components, and reduces the complexity and cost of the design. The voltage stabilizing circuit realizes a simplified design of the voltage stabilizing circuit through the combination of the first NLDMOS tube NLD1, the first voltage stabilizing tube D1, the second voltage stabilizing tube D2 and the first resistor R1, ensures that the voltage at the control end of the adjustment circuit is stable within the first preset voltage range, improves the stability of the output voltage, and thus improves the overall performance of the high-voltage LDO circuit. Taking the output voltage of the high-voltage LDO circuit as 12V as an example, for example, the voltage values ​​of the first voltage regulator tube D1 and the second voltage regulator tube D2 are both 6V, and the first resistor R1 plays a current limiting role, which can stabilize the gate voltage of the first NLDMOS tube NLD1 at about 13V, or 13V fluctuates up and down by a first percentage. Through the synergistic effect of the first NLDMOS tube NLD1, the first voltage regulator tube D1 and the second voltage regulator tube D2, the control terminal voltage of the adjustment circuit can be more effectively stabilized within the first preset voltage range, ensuring the stability and accuracy of the output voltage; due to the reduced number of components and compact structure, this voltage regulator circuit is easier to integrate into miniaturized electronic devices, which helps to improve the overall integration of the device. The low on-resistance characteristic of the first NLDMOS tube NLD1 helps to reduce the power consumption of the circuit during operation, which is in line with the current trend of electronic devices developing towards low power consumption.

[0035] In an optional embodiment, the current mirror circuit includes: a first NMOS tube N1, a second NMOS tube N2, a first PMOS tube P1 and a second PMOS tube P2, wherein the drain of the first NMOS tube N1 is electrically connected to the gate of the first NMOS tube N1, the gate of the first NMOS tube N1 is electrically connected to the gate of the second NMOS tube N2, the source of the first NMOS tube N1 and the source of the second NMOS tube N2 are both electrically connected to the ground terminal, and the drain of the first NMOS tube N1 is electrically connected to the constant current source; the drain of the second NMOS tube N2 is electrically connected to the drain of the first PMOS tube P1, the drain of the first PMOS tube P1 is electrically connected to the gate of the first PMOS tube P1, the gate of the first PMOS tube P1 is electrically connected to the gate of the second PMOS tube P2, the source of the first PMOS tube P1 and the source of the second PMOS tube P2 are both electrically connected to the power supply terminal, wherein the drain of the second PMOS tube P2 serves as the output end of the current mirror circuit.

[0036] In the above embodiment, a current mirror circuit is formed by the first NMOS tube N1, the second NMOS tube N2, the first PMOS tube P1 and the second PMOS tube P2, and the preset current provided by the constant current source is mirrored to provide a stable current for the voltage stabilization circuit, thereby realizing accurate control of the current. By designing a current mirror circuit including NMOS and PMOS transistors, current stability under different working voltages and load conditions can be achieved. The design utilizes the basic principle of the current mirror, that is, the current-voltage characteristics of the transistor are used to copy or mirror a current, thereby ensuring the stability and accuracy of the output current. Due to the structure of gate voltage clamping (such as the gate and drain of the first NMOS tube N1 and the first PMOS tube P1 are electrically connected), this current mirror circuit can achieve high-precision current replication, reducing the influence of factors such as process deviation or temperature change on the current replication accuracy. The design is suitable for a wider input voltage range, because the combination of NMOS and PMOS transistors can work stably at different voltage levels, ensuring the stability and reliability of the current mirror circuit. By designing the current path and transistor size, the static current can be optimized and unnecessary power consumption can be reduced, which is particularly important for battery-powered portable electronic devices.

[0037] In an optional embodiment, if Figure 3As shown, the current mirror circuit also includes: a third NMOS tube N3 and a second NLDMOS tube NLD2, the drain of the first NMOS tube N1 is electrically connected to the constant current source through the third NMOS tube N3, and the drain of the second NMOS tube N2 is electrically connected to the drain of the first PMOS tube P1 through the second NLDMOS tube NLD2, wherein the source of the third NMOS tube N3 is electrically connected to the drain of the first NMOS tube N1, the drain of the third NMOS tube N3 is electrically connected to the constant current source, and the drain of the third NMOS tube N3 is electrically connected to the gate of the third NMOS tube N3; the gate of the second NLDMOS tube NLD2 is electrically connected to the gate of the third NMOS tube N3, the source of the second NLDMOS tube NLD2 is electrically connected to the drain of the second NMOS tube N2, and the drain of the second NLDMOS tube NLD2 is electrically connected to the drain of the first PMOS tube P1.

[0038] In the above embodiment, if Figure 3 As shown, by connecting the third NMOS tube N3 and the second NLDMOS tube NLD2 in series respectively, the accuracy and stability of the current mirror are improved, and the reliability and anti-interference ability of the circuit are enhanced. In the current mirror circuit, it is more common to use two tubes, such as the above-mentioned use of only the first NMOS tube N1 and the second NMOS tube N2. This embodiment is implemented by adding the third NMOS tube N3 and the second NLDMOS tube NLD2, that is, using 4 MOS tubes. This series structure can make the current mirror more accurate. The improved current mirror circuit can more accurately copy the reference current (that is, the preset current provided by the constant current source) and reduce the current error caused by factors such as process deviation, temperature change or power supply fluctuation. By expanding the structure of the current mirror circuit, the accuracy of the current mirror is improved, the stability and reliability of the circuit are enhanced, and the technical effects of improving circuit performance, optimizing circuit layout and wiring, and improving design flexibility are achieved.

[0039] In an optional embodiment, if Figure 3 As shown, the adjustment circuit includes a third NLDMOS tube NLD3, wherein the gate of the third NLDMOS tube NLD3 is electrically connected to the output end of the voltage stabilizing circuit, the drain of the third NLDMOS tube NLD3 is electrically connected to the power supply end, and the source of the third NLDMOS tube NLD3 serves as the output end of the adjustment circuit.

[0040] In the above embodiment, the adjustment circuit adopts the third NLDMOS tube NLD3, and the gate of the third NLDMOS tube NLD3 is electrically connected to the output end of the voltage stabilizing circuit, such as the gate of the first NLDMOS tube NLD1 mentioned above. The source of the third NLDMOS tube NLD3 serves as the output end of the adjustment circuit and also as the output end of the entire high-voltage LDO circuit, and is used to output a voltage within the second preset voltage range. By adopting the third NLDMOS tube NLD3 as the main component of the adjustment circuit, the output voltage can be more effectively controlled and the accuracy of voltage adjustment can be improved. The third NLDMOS tube NLD3 performs well in high-voltage applications and can handle large current and voltage differences while maintaining low power consumption and high efficiency. NLDMOS tubes generally have good thermal stability and temperature stability and can maintain stable performance within a wide operating temperature range. Therefore, using it as the core component of the adjustment circuit helps to enhance the stability of the entire high-voltage LDO circuit. By fine-tuning the gate voltage of the third NLDMOS tube NLD3, the conduction degree of the third NLDMOS tube NLD3 can be changed to adjust the output voltage, thereby achieving precise adjustment of the output voltage and improving the accuracy and stability of the output voltage.

[0041] In an optional embodiment, if Figure 3 As shown, the adjustment circuit further includes a third voltage regulator tube D3, wherein the anode of the third voltage regulator tube D3 is electrically connected to the source of the third NLDMOS tube NLD3, and the cathode of the third voltage regulator tube D3 is electrically connected to the gate of the third NLDMOS tube NLD3.

[0042] In the above embodiment, by connecting the third voltage regulator D3 in parallel between the gate and source of the third NLDMOS tube NLD3, the third NLDMOS tube NLD3 can be protected. Thus, while ensuring the stability of the output voltage, the third NLDMOS tube NLD3 is effectively protected to prevent damage caused by too low output voltage, further improving the reliability and stability of the circuit. The introduction of the third voltage regulator D3 provides an additional voltage stabilization mechanism for the adjustment circuit. The voltage regulator has the characteristic of keeping the voltage at both ends constant within a specific voltage range. When the source voltage of the third NLDMOS tube NLD3 fluctuates, the third voltage regulator D3 can keep the voltage at both ends of its gate and source relatively stable, thereby enhancing the stability of the output voltage. In some cases, when the input voltage or load current changes greatly, it may be difficult to completely stabilize the output voltage by relying solely on the third NLDMOS tube NLD3. By introducing the third voltage regulator D3, a more robust voltage adjustment mechanism can be constructed, so that the circuit can maintain a stable output voltage within a wider working range. By introducing the third voltage regulator D3, the output voltage stability of the high-voltage LDO circuit can be significantly improved, and the output voltage fluctuation caused by factors such as input voltage fluctuation, load current change or temperature change can be reduced. Therefore, the third voltage regulator D3 is used in combination with the third NLDMOS tube NLD3 to optimize the dynamic performance of the adjustment circuit, so that it can respond to changes in input voltage or load current more quickly, thereby better stabilizing the output voltage.

[0043] In an optional embodiment, if Figure 3 As shown, the voltage feedback circuit includes a second resistor R2, a third resistor R3 and a fourth NLDMOS tube NLD4, wherein a first end of the second resistor R2 is electrically connected to a source of the third NLDMOS tube NLD3, a second end of the second resistor R2 is electrically connected to a ground terminal through the third resistor R3, a second end of the second resistor R2 is also electrically connected to a gate of the fourth NLDMOS tube NLD4, a drain of the fourth NLDMOS tube NLD4 is electrically connected to a gate of the third NLDMOS tube NLD3, and a source of the fourth NLDMOS tube NLD4 is electrically connected to the ground terminal.

[0044] In the above embodiment, effective feedback of the output voltage of the adjustment circuit is achieved through the voltage division of the second resistor R2 and the third resistor R3. When the output voltage exceeds the preset range, for example, is not within the second preset voltage range, the conduction degree of the fourth NLDMOS tube NLD4 can be adjusted by the voltage division of the third resistor R3, and then the control end (that is, the gate voltage) of the third NLDMOS tube NLD3 can be adjusted, so as to ensure that the output voltage of the adjustment circuit is stable within the second preset voltage range; that is, the fourth NLDMOS tube NLD4 is used as a regulating element to fine-tune the gate voltage of the third NLDMOS tube NLD3, thereby enhancing the stability of the output voltage. In practical applications, the second resistor R2 and the third resistor R3 may be appropriately selected so that the fourth NLDMOS tube NLD4 is initially in a slightly conductive state. When the output voltage is relatively large, such as 12.5V (greater than 12V), the divided voltage of the third resistor R3 is greater than 1V (or 0.7V, or other), so that the conductive degree of the fourth NLDMOS tube NLD4 is greater, the current is also increased, and the gate voltage of the third NLDMOS tube NLD3 is reduced, which also causes the conductive degree of the third NLDMOS tube NLD3 to be reduced, thereby reducing the output voltage of the adjustment circuit; conversely, when the output voltage is relatively small, such as 11V (less than 12V), the divided voltage of the third resistor R3 is reduced, so that the conductive degree of the fourth NLDMOS tube NLD4 is reduced or turned off, so that the gate voltage of the third NLDMOS tube NLD3 is increased, resulting in an increase in the conductive degree of the third NLDMOS tube NLD3, thereby increasing the output voltage of the adjustment circuit. By constructing a feedback loop consisting of a second resistor R2, a third resistor R3 and a fourth NLDMOS tube NLD4, it is possible to accurately detect the output voltage and feed back the detection result to the adjustment circuit (third NLDMOS tube NLD3). This feedback mechanism helps to ensure that the output voltage is stable near a preset value, such as within a second preset voltage range. The fourth NLDMOS tube NLD4 is a key component of the feedback circuit, and its gate voltage changes with the change of the output voltage, and then through the connection between its drain and the gate of the third NLDMOS tube NLD3, the working state of the third NLDMOS tube NLD3 is quickly adjusted to respond to the change of the output voltage. This fast dynamic response helps to improve the efficiency and stability of voltage adjustment. It also avoids the problem that the high-voltage LDO circuit in the related art needs to rely on the error amplifier, resulting in a relatively complex circuit and a large circuit area, and also causes the problem that the high-voltage LDO circuit in the related art is not easy to be integrated into the high-voltage driver chip.

[0045] In an optional embodiment, if Figure 3 As shown, the high-voltage LDO circuit further includes a first capacitor C1 , wherein the first capacitor C1 is connected between the output terminal of the adjustment circuit and the ground terminal.

[0046] In the above embodiment, the first capacitor C1 serves as the output high-frequency filter capacitor of the high-voltage LDO circuit, and plays a role in voltage stabilization and filtering. It can effectively filter out the high-frequency noise in the output voltage, ensure the stability and purity of the output voltage, and thus improve the reliability of the entire circuit. The addition of the first capacitor C1 helps to isolate the noise from the power supply or other circuit parts, and reduce their interference with the output voltage of the high-voltage LDO circuit. The high-voltage LDO circuit in the embodiment of the present application can be integrated inside the high-voltage driver chip, as a part of the circuit inside the high-voltage driver chip, avoiding the need for multi-stage amplification inside the high-voltage LDO circuit in the related art, and the inability to integrate capacitors inside the chip, resulting in only external capacitors outside the high-voltage LDO circuit, increasing the number of devices, and causing the chip to become larger in size.

[0047] In an optional embodiment, if Figure 3 As shown, the above-mentioned high-voltage LDO circuit also includes an undervoltage protection circuit and a fourth NMOS tube N4, and the fourth NMOS tube N4 is connected between the input end of the current mirror circuit and the constant current source, wherein the undervoltage protection circuit is electrically connected to the gate of the fourth NMOS tube N4, the source of the fourth NMOS tube N4 is electrically connected to the input end of the current mirror circuit, and the drain of the fourth NMOS tube N4 is electrically connected to the constant current source, wherein the undervoltage protection circuit is configured to control the fourth NMOS tube N4 to be in a closed state when the voltage at the power supply end of the high-voltage LDO circuit is less than or equal to a preset voltage threshold, and to control the fourth NMOS tube N4 to be in a conducting state when the voltage at the power supply end of the high-voltage LDO circuit is greater than the preset voltage threshold.

[0048] In the above embodiment, the high-voltage LDO circuit integrates an undervoltage protection circuit and a fourth NMOS tube N4. The undervoltage protection circuit can control the fourth NMOS tube N4 to turn off when the voltage at the power supply end is lower than the preset voltage threshold, thereby cutting off the connection between the input end of the current mirror circuit and the constant current source, avoiding the erroneous operation of the circuit under the undervoltage state, and improving the reliability of the system. When the voltage at the power supply end is higher than the preset voltage threshold, the fourth NMOS tube N4 is turned on, ensuring the current supply under normal working conditions, and ensuring the stable operation of the high-voltage LDO circuit. During the operation of the high-voltage LDO circuit, if the voltage at the power supply end is lower than a certain safety threshold, continuing to work may cause damage to circuit components or performance degradation. The introduction of the undervoltage protection circuit and the fourth NMOS tube N4 can effectively prevent this from happening. By automatically detecting the voltage at the power supply end and controlling the on and off of the fourth NMOS tube N4, the undervoltage protection circuit gives the high-voltage LDO circuit a stronger self-protection capability, enabling it to remain safe and stable under harsh power supply conditions. By introducing the undervoltage protection mechanism, the high-voltage LDO circuit can automatically stop working when the power supply voltage is unstable or too low, avoiding performance degradation or damage caused by continuous operation in a low-voltage state and improving the overall reliability of the system.

[0049] The present application also provides a chip, comprising the high-voltage LDO circuit in any of the aforementioned embodiments.

[0050] For example, a high-voltage driver chip, wherein the power end of the high-voltage LDO circuit is connected to the power pin of the chip, the ground end of the high-voltage LDO circuit is connected to the ground pin of the chip, and the high-voltage LDO circuit provides a stable output voltage inside the high-voltage driver chip.

[0051] It should be noted that the above-described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application will be described in detail below in conjunction with specific embodiments.

[0052] In the related art, firstly, the high-voltage driver chip does not have a high-voltage LDO inside, and basically two independent chips are used to implement it, that is, the high-voltage driver chip and the high-voltage LDO are separated. Secondly, the high-voltage LDO circuit is relatively complicated. For integrating the high-voltage LDO circuit inside the high-voltage driver chip, it is necessary to increase the chip area greatly, and an external capacitor is required at the output end of the LDO, which will greatly increase the cost. In the prior art, the high-voltage driver chip and the high-voltage LDO chip are used for solution design separately, which will increase the area of ​​the solution board PCB, increase the product appearance, and increase the cost. The ordinary high-voltage LDO circuit structure is relatively complicated, and a reference circuit, an error amplifier, a capacitor and a PMOS type adjustment tube are used. If it is used for integration inside the high-voltage driver chip, on the one hand, the cost of the high-voltage driver chip will be greatly increased. On the other hand, the LDO output also requires an external capacitor, which increases the external device, increases the number of chip pins, and causes the chip appearance to become larger.

[0053] like Figure 1 As shown in the figure, the high-voltage LDO circuit is implemented by a reference circuit, an error amplifier, a PMOS adjustment tube, a resistor and a capacitor. In the high-voltage LDO circuit chip, the reference circuit in the circuit is relatively complex and occupies a considerable amount of chip area. The adjustment tube in the circuit must use a PMOS tube, which has a relatively weak current. If a large current passes through it, a very large tube will be used to achieve it. This structure often uses multi-stage amplification, and a certain amount of compensation capacitor is required internally, which causes the circuit response to become slower and increases the instability of the circuit. Therefore, a large capacitor is often connected to the output port of the LDO. The above situations will greatly increase the chip area and increase the cost.

[0054] The embodiment of the present application provides a high-voltage LDO circuit and an integrated chip for high-voltage driving, a high-voltage LDO circuit with no load capacitance integrated inside a high-voltage driving chip, and mainly composed of a voltage regulator tube, a resistor, a high-voltage PMOS tube, a low-voltage NMOS tube and a high-voltage NLDMOS tube device.

[0055] Figure 3 This is a schematic diagram of a high voltage LDO circuit provided in an embodiment of the present application. Figure 3 The principle of the high-voltage LDO circuit in the embodiment of the present application is explained.

[0056] The undervoltage protection circuit of the high-voltage LDO is mainly composed of the undervoltage protection circuit inside the high-voltage drive circuit and the fourth NMOS tube N4 of the 5V low voltage.

[0057] The current mirror circuit of the high-voltage LDO is mainly composed of a third NMOS tube N3 with a low voltage of 5V, a second NLDMOS tube NLD2 with a high voltage of 24V, a first NMOS tube N1 with a low voltage of 5V, a second NMOS tube N2 with a low voltage of 5V, a first PMOS tube P1 with a high voltage of 24V, and a second PMOS tube P2 with a high voltage of 24V.

[0058] The voltage stabilizing circuit of the high-voltage LDO is mainly composed of a 24V high-voltage first NLDMOS tube NLD1, a first voltage stabilizing tube D1, a second voltage stabilizing tube D2, and a first resistor R1.

[0059] The voltage feedback circuit of the high-voltage LDO is mainly composed of a second resistor R2, a third resistor R3, and a fourth NLDMOS tube NLD4 of 24V high voltage.

[0060] The adjustment circuit of the high-voltage LDO is mainly composed of a 24V high-voltage third NLDMOS tube NLD3 and a third voltage regulator tube D3. The high-voltage third NLDMOS tube NLD3 adopts a 6V low-open gate-source withstand voltage and a 24V drain-source withstand voltage, so that the tube area of ​​the third NLDMOS tube NLD3 is relatively small and can achieve a relatively large current output. Since the gate source of the tube of the third NLDMOS tube NLD3 is a low-voltage structure, the third voltage regulator tube D3 is required to protect it to prevent the output voltage from being too low and damaging the tube of the third NLDMOS tube NLD3.

[0061] The high-frequency output filtering of the high-voltage LDO is mainly performed by the internal small capacitor first capacitor C1 for voltage stabilization and filtering.

[0062] The working principle of the high-voltage LDO circuit inside the high-voltage driver chip of the present invention is as follows: When the external power supply is turned on and the voltage rises, the entire chip is still in the undervoltage protection state, so the undervoltage protection module outputs a low level. At this time, the low-voltage fourth NMOS tube N4 is in the off state, and the high-voltage LDO circuit has not started working. When the external power supply voltage rises to a value greater than the undervoltage protection value, the undervoltage protection module outputs a high level, turning on the fourth NMOS tube N4, so that the bias current of IB can provide current to the LDO branch. Figure 3The bias current IB is equivalent to the preset current provided by the aforementioned constant current source. In the mirror current circuit, it is more common to use two tubes, such as the first NMOS tube N1 and the second NMOS tube N2. In this embodiment, 4 NMOS tubes are used, specifically including the first NMOS tube N1, the second NMOS tube N2, the third NMOS tube N3 and the second NLDMOS tube NLD2. This series structure can make the IB current mirror more accurate. In this embodiment, a 6V voltage regulator tube is used, such as the first voltage regulator tube D1, the second voltage regulator tube D2, etc. When the current of IB is mirrored to the first NLDMOS tube NLD1, and the voltage of VCC24 is greater than 13V, the voltage regulator circuit of this branch starts to work, and the gate voltage of the third NLDMOS tube NLD3 is stabilized at 13V. At this time, the third NLDMOS tube NLD3 can be turned on, so that the port outputting VCC12 outputs 12V. The voltage feedback network takes a suitable ratio of the second resistor R2 to the third resistor R3, so that the fourth NLDMOS tube NLD4 is in a slightly conductive state. When the port output of VCC12 is greater than 12V, the fourth NLDMOS tube NLD4 is turned on to reduce the gate voltage of the third NLDMOS tube NLD3, thereby reducing the output port voltage.

[0063] Figure 4 It is a waveform diagram of a high-voltage LDO input and output provided in an embodiment of the present application, which includes voltage waveforms of a power supply voltage VCC24 and an output voltage VCC12, and ultimately obtains a stable output voltage.

[0064] It should be noted that the above VCC24 is equivalent to the above power supply terminal, such as 24V, and VCC12 corresponds to the above output voltage, such as 12V. In this embodiment, only the power supply voltage of 24V and the output voltage of 12V are used as an example for explanation, and other power supply voltages or output voltages may also be used. Figure 3 The high-voltage LDO circuit shown can be integrated into a high-voltage driver chip.

[0065] Through the embodiment of the present application, the high-voltage LDO circuit is integrated inside the high-voltage driver chip. First, the scheme design is simplified, the PCB board area is reduced, the product appearance is reduced, and the product is light and portable. Second, the chip integration is improved, the area of ​​the high-voltage LDO chip is reduced, and the cost of the chip is reduced.

[0066] Compared with the related art, the high-voltage LDO circuit integrated inside the high-voltage driver chip provided in the embodiment of the present application has the following beneficial effects: 1) It avoids the high-voltage driver chip in the prior art, which has no high-voltage LDO inside and is basically implemented by two chips. The embodiment of the present application integrates the high-voltage LDO inside the high-voltage driver, simplifies the external PCB board area, reduces the product appearance, and makes it more portable; 2) The high-voltage LDO circuit of the embodiment of the present application adopts a voltage regulator tube inside, simplifies the internal reference circuit function, and more conveniently achieves the voltage stabilization effect; 3) The high-voltage LDO circuit of the embodiment of the present application adopts an NLDMOS type adjustment tube inside. This tube has a relatively strong conduction current capability, high voltage resistance, and a short channel. In this way, when a large current output is required, only a smaller tube width-to-length ratio is required; 4) The high-voltage LDO of the embodiment of the present application adopts a one-stage amplification inside, avoiding the need for multiple stages of amplification inside, which can simplify the compensation circuit inside the LDO, increase the output stability, and avoid the use of external output capacitors.

[0067] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0068] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0069] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0070] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0071] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned memory includes: various media that can store program codes, such as USB flash drives, mobile hard drives, magnetic disks or optical disks.

[0072] The above is only an exemplary embodiment of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification and the truth of practice, those skilled in the art will easily think of other embodiments of the present disclosure.

[0073] This application is intended to cover any modifications, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field not recorded in the present disclosure.

Claims

1. A high voltage LDO circuit, characterized in that: include: Current mirror circuit, voltage stabilization circuit, voltage feedback circuit, adjustment circuit, among which, The input end of the current mirror circuit is electrically connected to the constant current source, and the output end of the current mirror circuit is electrically connected to the input end of the voltage stabilizing circuit, wherein the current mirror circuit is used to mirror the preset current provided by the constant current source to obtain a target mirror current, and the target mirror current is input to the input end of the voltage stabilizing circuit; The output end of the voltage stabilizing circuit is electrically connected to the control end of the regulating circuit, and the voltage stabilizing circuit is used to stabilize the voltage of the control end of the regulating circuit within a first preset voltage range; The voltage feedback circuit is connected between the control end of the adjustment circuit and the output end of the adjustment circuit. The voltage feedback circuit is used to adjust the voltage of the control end of the adjustment circuit based on the output voltage of the adjustment circuit so that the output end voltage of the adjustment circuit is stabilized within a second preset voltage range.

2. The high voltage LDO circuit according to claim 1, characterized in that: The voltage stabilizing circuit includes a first NLDMOS tube, a first voltage stabilizing tube, a second voltage stabilizing tube and a first resistor, wherein: The drain of the first NLDMOS tube is electrically connected to the gate of the first NLDMOS tube, the source of the first NLDMOS tube is electrically connected to the negative electrode of the first voltage regulator tube, the positive electrode of the first voltage regulator tube is electrically connected to the negative electrode of the second voltage regulator tube, and the positive electrode of the second voltage regulator tube is electrically connected to the ground terminal through the first resistor, wherein the drain of the first NLDMOS tube serves as the input end of the voltage regulator circuit, and the gate of the first NLDMOS tube serves as the output end of the voltage regulator circuit.

3. The high voltage LDO circuit according to claim 1, characterized in that: The current mirror circuit includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a second PMOS transistor, wherein: The drain of the first NMOS tube is electrically connected to the gate of the first NMOS tube, the gate of the first NMOS tube is electrically connected to the gate of the second NMOS tube, the source of the first NMOS tube and the source of the second NMOS tube are both electrically connected to the ground terminal, and the drain of the first NMOS tube is electrically connected to the constant current source; The drain of the second NMOS tube is electrically connected to the drain of the first PMOS tube, the drain of the first PMOS tube is electrically connected to the gate of the first PMOS tube, the gate of the first PMOS tube is electrically connected to the gate of the second PMOS tube, the source of the first PMOS tube and the source of the second PMOS tube are both electrically connected to the power supply end, wherein the drain of the second PMOS tube serves as the output end of the current mirror circuit.

4. The high voltage LDO circuit according to claim 3, characterized in that: The current mirror circuit further includes: a third NMOS tube and a second NLDMOS tube, the drain of the first NMOS tube is electrically connected to the constant current source through the third NMOS tube, and the drain of the second NMOS tube is electrically connected to the drain of the first PMOS tube through the second NLDMOS tube, wherein: The source of the third NMOS tube is electrically connected to the drain of the first NMOS tube, the drain of the third NMOS tube is electrically connected to the constant current source, and the drain of the third NMOS tube is electrically connected to the gate of the third NMOS tube; The gate of the second NLDMOS tube is electrically connected to the gate of the third NMOS tube, the source of the second NLDMOS tube is electrically connected to the drain of the second NMOS tube, and the drain of the second NLDMOS tube is electrically connected to the drain of the first PMOS tube.

5. The high voltage LDO circuit according to claim 1, characterized in that: The adjustment circuit includes a third NLDMOS tube, wherein: The gate of the third NLDMOS tube is electrically connected to the output end of the voltage stabilizing circuit, the drain of the third NLDMOS tube is electrically connected to the power supply end, and the source of the third NLDMOS tube serves as the output end of the adjustment circuit.

6. The high voltage LDO circuit according to claim 5, characterized in that: The adjustment circuit further includes a third voltage regulator tube, wherein the positive electrode of the third voltage regulator tube is electrically connected to the source electrode of the third NLDMOS tube, and the negative electrode of the third voltage regulator tube is electrically connected to the gate electrode of the third NLDMOS tube.

7. The high voltage LDO circuit according to claim 6, characterized in that: The voltage feedback circuit includes a second resistor, a third resistor and a fourth NLDMOS transistor, wherein: The first end of the second resistor is electrically connected to the source of the third NLDMOS tube, the second end of the second resistor is electrically connected to the ground terminal through the third resistor, the second end of the second resistor is also electrically connected to the gate of the fourth NLDMOS tube, the drain of the fourth NLDMOS tube is electrically connected to the gate of the third NLDMOS tube, and the source of the fourth NLDMOS tube is electrically connected to the ground terminal.

8. The high voltage LDO circuit according to any one of claims 1 to 7, characterized in that: The high-voltage LDO circuit further includes a first capacitor, wherein the first capacitor is connected between an output terminal of the adjustment circuit and a ground terminal.

9. The high voltage LDO circuit according to any one of claims 1 to 7, characterized in that: The high-voltage LDO circuit also includes an undervoltage protection circuit and a fourth NMOS tube, wherein the fourth NMOS tube is connected between the input end of the current mirror circuit and the constant current source, wherein: The undervoltage protection circuit is electrically connected to the gate of the fourth NMOS tube, the source of the fourth NMOS tube is electrically connected to the input end of the current mirror circuit, and the drain of the fourth NMOS tube is electrically connected to the constant current source, wherein the undervoltage protection circuit is configured to control the fourth NMOS tube to be in a closed state when the voltage at the power supply end of the high-voltage LDO circuit is less than or equal to a preset voltage threshold, and to control the fourth NMOS tube to be in a conducting state when the voltage at the power supply end of the high-voltage LDO circuit is greater than the preset voltage threshold.

10. A chip, characterized in that: A high voltage LDO circuit comprising any one of claims 1 to 9.

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