Table clearing processing method, electronic device and medium for multi-access source flow table

Abstract

The present application relates to the field of computer technology and provides a table clearing processing method, electronic device and medium for multi-access source flow tables. The table clearing processing method provides an optimized pipelined table clearing operation process, splits the table clearing operation process of multiple access sources for any address in the first flow table and provides corresponding special pipelines, and also provides a read command generator, a write command judger and a multi-access source conflict processor through special hardware design, effectively avoiding conflicts that may be caused by multiple access sources performing table clearing processing and modifying data on the same flow table, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of hardware performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a table clearing processing method, electronic equipment and medium for a multi-access source flow table. Background Art

[0002] In the technical fields of cloud computing, data centers, artificial intelligence, etc., large-scale flow tables are used to meet business needs such as message forwarding, data reading and writing, and remote direct memory access. Among them, for the same flow table, there may be multiple access sources, such as network devices with data access rights, external users with data read and write rights, etc. Each entry in the flow table may have access data corresponding to different access sources. Sometimes a certain access source needs to perform table clearing processing, that is, clearing the data belonging to the access source in the flow table. In the stage of performing table clearing processing for a certain access source, there may be other access sources that modify the data. For example, for the same data, if the access source to be cleared is written before other access sources, it may cause unclean table clearing. For another example, for the same data, if the access source to be cleared is written later than other access sources, it may cause the data of other access sources to be not updated in time. Therefore, for the table clearing processing of multi-access source flow tables, it is necessary to consider the situation that other access sources access and modify data during the table clearing processing stage, and as the data specifications of the flow table increase, the problem of table clearing processing performance also needs to be considered. In the prior art, a single-address serial traversal table clearing method is generally used. During the table clearing process for a certain address, if other access sources are found to be operating, the current table clearing action is suspended until the operations of other access sources are completed, and then the table clearing operation of the address is re-initiated. However, the table clearing processing scheme in the prior art is highly dependent on the processing delay of address read and write access. When the address read and write access cycle is long, the overall performance is poor, and as the number of access sources increases, the overall performance is also poor.

[0003] To this end, the present application provides a table clearing processing method, electronic device and medium for multi-access source flow tables. Through an optimized pipelined table clearing operation process and a special hardware design, it effectively avoids conflicts that may be caused by multiple access sources performing table clearing processing and modifying data on the same flow table, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of hardware performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay. Summary of the invention

[0004] In the first aspect, the present application provides a table clearing processing method for a multi-access source flow table. The table clearing processing method includes: determining multiple access sources associated with a first flow table, wherein the table clearing operation process of each of the multiple access sources for any address in the first flow table includes sequentially performing an address reading operation, a data waiting operation, a data comparison operation, and a data write-back operation; providing an address reading pipeline for pipeline processing of the address reading operations performed by each of the multiple access sources, providing a data waiting pipeline for pipeline processing of the data waiting operations performed by each of the multiple access sources, providing a data comparison pipeline for pipeline processing of the data comparison operations performed by each of the multiple access sources, and providing a data write-back pipeline for pipeline processing of the data write-back operations performed by each of the multiple access sources; through a read command generator, in response to a first table clearing instruction of the first access source among the multiple access sources for the first flow table, traversing the addresses in the first flow table corresponding to the first table clearing instruction, thereby generating a first address reading command corresponding to the first table clearing instruction, wherein the first address reading command is used for the address reading The pipeline and the data waiting pipeline are used to obtain the first response data corresponding to the first table clearing instruction; through the write command determiner, based on the analysis and comparison result of the first response data, the data including the first access source in the first response data is invalidated and the data not including the first access source in the first response data is discarded, thereby generating a first data write-back command corresponding to the first table clearing instruction, and the first data write-back command is used for the data write-back pipeline to perform the data write-back operation corresponding to the first table clearing instruction; through the multi-access source conflict processor, at least during the period from the receipt of the first table clearing instruction of the first access source by the read command generator to the completion of the execution of the first data write-back command, the access requests to the first flow table of other access sources except the first access source among the multiple access sources are monitored, and when there is a conflict between the access requests to the first flow table of the other access sources and the first table clearing instruction, the read command generator is cooperated to perform a conflict avoidance operation.

[0005] Through the first aspect of the present application, through the optimized design of the pipelined table clearing operation process and the special hardware design, the conflicts that may be caused by multiple access sources performing table clearing processing and modifying data on the same flow table can be effectively avoided, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of the hardware in performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay.

[0006] In a possible implementation of the first aspect of the present application, through the multi-access source conflict processor, when the access address of the access request of the other access source to the first flow table overlaps with the address corresponding to the first table clearing instruction in the first flow table, it is determined that there is a conflict between the access request of the other access source to the first flow table and the first table clearing instruction.

[0007] In a possible implementation of the first aspect of the present application, through the multi-access source conflict processor, when the access address of the access request of the other access source to the first flow table overlaps with the preset address range in the first flow table relative to the address corresponding to the first table clearing instruction, it is determined that there is a conflict between the access request of the other access source to the first flow table and the first table clearing instruction.

[0008] In a possible implementation manner of the first aspect of the present application, the preset address range in the first flow table relative to the address corresponding to the first table clearing instruction is an address within a previous preset range of the address corresponding to the first table clearing instruction.

[0009] In a possible implementation of the first aspect of the present application, through the multi-access source conflict processor, when there is a conflict between the access request of the other access source to the first flow table and the first table clearing instruction, it cooperates with the read command generator to perform a conflict avoidance operation, including: determining the current conflicting address of the access request of the other access source to the first flow table relative to the first table clearing instruction, rolling back the read command generator to the current conflicting address, and re-traversing the address corresponding to the first table clearing instruction in the first flow table from the current conflicting address.

[0010] In a possible implementation of the first aspect of the present application, through the multi-access source conflict processor, when there is a conflict between the access request of the other access source to the first flow table and the first table clearing instruction, it cooperates with the read command generator to perform a conflict avoidance operation, and also includes: determining the conflict interval in the access address of the access request of the other access source to the first flow table relative to the first table clearing instruction, clearing the part of the first address read command corresponding to the conflict interval, clearing the part of the first response data corresponding to the conflict interval, and clearing the part of the first data write back command corresponding to the conflict interval.

[0011] In a possible implementation of the first aspect of the present application, through the multi-access source conflict processor, when there is a conflict between the access request of the other access source to the first flow table and the first clear table instruction, it cooperates with the read command generator to perform a conflict avoidance operation, and also includes: clearing the part corresponding to the conflict interval in the data write back operation corresponding to the first clear table instruction.

[0012] In a possible implementation of the first aspect of the present application, the first address read command is stored in a read command first-in-first-out memory, the first response data is stored in an address first-in-first-out memory, and the first data write back command is stored in a write back command first-in-first-out memory.

[0013] In a possible implementation of the first aspect of the present application, the address read pipeline and the data wait pipeline obtain the first response data based on the state of the read command first-in-first-out memory.

[0014] In a possible implementation of the first aspect of the present application, the read command generator is configured to, when the read command first-in-first-out memory is full, suspend generating the first address read command until the read command first-in-first-out memory has free space.

[0015] In a possible implementation manner of the first aspect of the present application, the data write-back pipeline executes the data write-back operation corresponding to the first table clear instruction based on the state of the write-back command first-in-first-out memory.

[0016] In a possible implementation of the first aspect of the present application, the write command determiner, based on the analysis and comparison results of the first response data, invalidates the data of the first response data including the first access source and discards the data of the first response data not including the first access source, thereby generating a first data write back command corresponding to the first table clearing instruction, including: for the data of the first access source included in the first response data, refreshes the first access source to an invalid value, and keeps the data of other access sources among the multiple access sources except the first access source unchanged, and then writes them to the write back command first-in-first-out memory in combination with the address obtained from the address first-in-first-out memory; for the data of the first response data not including the first access source, discards the data of the first response data not including the first access source and the address obtained from the address first-in-first-out memory, and does not write them to the write back command first-in-first-out memory.

[0017] In a possible implementation manner of the first aspect of the present application, the processing delay of the first table clear instruction does not depend on the processing delay of address read and write access.

[0018] In a possible implementation manner of the first aspect of the present application, the multiple access sources are multiple physical functional devices, and the first flow table is a hash table.

[0019] In a possible implementation of the first aspect of the present application, the multiple access sources include a second access source, which is different from the first access source, and the time when the second access source initiates the access request to the first flow table is earlier than or later than the time when the read command generator receives the first table clearing instruction from the first access source.

[0020] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0021] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0022] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A flowchart of a method for clearing a multi-access source flow table provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a table clearing processing device for a multi-access source flow table provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0028] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0029] Figure 1 A flowchart of a method for clearing a multi-access source flow table provided in an embodiment of the present application is provided. Figure 1 As shown, the surface clearing treatment method includes the following steps.

[0030] Step S101: determine multiple access sources associated with the first flow table, wherein the clearing operation process of each of the multiple access sources for any address in the first flow table includes sequentially performing an address reading operation, a data waiting operation, a data comparison operation and a data write-back operation.

[0031] Step S103: providing an address read pipeline for pipeline processing of address read operations performed by each of the multiple access sources, providing a data wait pipeline for pipeline processing of data wait operations performed by each of the multiple access sources, providing a data comparison pipeline for pipeline processing of data comparison operations performed by each of the multiple access sources, and providing a data write-back pipeline for pipeline processing of data write-back operations performed by each of the multiple access sources.

[0032] Step S105: Through a read command generator, in response to a first table clear instruction of the first flow table issued by a first access source among the multiple access sources, the addresses corresponding to the first table clear instruction in the first flow table are traversed to generate a first address read command corresponding to the first table clear instruction, wherein the first address read command is used for the address read pipeline and the data wait pipeline to obtain first response data corresponding to the first table clear instruction.

[0033] Step S107: Through the write command determiner, based on the analysis and comparison result of the first response data, the data including the first access source in the first response data is invalidated and the data not including the first access source in the first response data is discarded, thereby generating a first data write back command corresponding to the first table clearing instruction, and the first data write back command is used in the data write back pipeline to perform the data write back operation corresponding to the first table clearing instruction.

[0034] Step S109: Through a multi-access source conflict processor, at least during the period from when the read command generator receives the first table clearing instruction of the first access source to when the first data write back command is executed, monitor the access requests to the first flow table from other access sources among the multiple access sources except the first access source, and when there is a conflict between the access requests to the first flow table from the other access sources and the first table clearing instruction, cooperate with the read command generator to perform a conflict avoidance operation.

[0035] Figure 1 The table clearing processing method for multi-access source flow tables shown is applied to technical fields such as cloud computing, data centers, and artificial intelligence. In these technical fields, flow tables and hardware offload acceleration technologies are widely used to provide functions and services such as flow table lookup, flow table clearing processing, data access, and data modification. Each entry in the flow table may have access data corresponding to different access sources. Sometimes a certain access source needs to perform table clearing processing, that is, to clear the data belonging to the access source in the flow table. In the stage of performing table clearing processing for a certain access source, there may be other access sources that modify the data. For example, for the same data, if the access source to be cleared is written before other access sources, it may cause the table to be cleared uncleanly. For another example, for the same data, if the access source to be cleared is written later than other access sources, it may cause the data of other access sources to be not updated in time. Therefore, for the table clearing processing of multi-access source flow tables, it is necessary to consider the situation that other access sources access and modify data during the table clearing processing stage, and as the data specifications of the flow table increase, it is also necessary to consider the problem of table clearing processing performance. In the case where multiple access sources may perform table clearing and data modification on the same flow table at the same time, if a single-address serial traversal table clearing method is used and the current table clearing action is suspended when other access sources are found to be operating on the current address, the overall table clearing performance will be highly dependent on the processing delay of address read and write access. When the address read and write access cycle is long, the overall performance will be poor, and as the number of access sources increases, the overall performance will also be poor. For this reason, Figure 1 The table clearing method for multi-access source flow tables shown in the figure effectively avoids conflicts that may be caused by multiple access sources performing table clearing and data modification on the same flow table through an optimized pipelined table clearing operation process and a dedicated hardware design, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of hardware performing table clearing on large-scale flow tables and reducing the overall table clearing delay. The following is a detailed description.

[0036] refer to Figure 1In step S101, multiple access sources associated with the first flow table are determined, wherein the clearing operation flow of each of the multiple access sources for any address in the first flow table includes sequentially performing an address reading operation, a data waiting operation, a data comparison operation, and a data write-back operation. Here, the multiple access sources may be any access source that has the authority to access and modify the data in the first flow table and perform clearing processing, such as a physical function (PF) device, a network device with data access rights, an external user with data read and write rights, etc. There are multiple table entries in the first flow table, and the data of each table entry may correspond to multiple access sources. For example, a table entry may contain data belonging to a physical function device and data belonging to another physical function device at the same time. The clearing processing based on a certain access source generally sets the data belonging to the access source to zero, keeps the data that does not belong to the access source, and then writes the updated data back to the table entry. As hardware offload acceleration technology is widely used to improve data forwarding performance, the first flow table and related functions such as clearing processing, data access, and data modification are generally offloaded to hardware and executed by hardware as the main body. Therefore, if the table clearing process is completed by software, there will be losses caused by the interaction between software and hardware, and it will be difficult to meet the synchronization requirements between different access sources. Figure 1The table clearing processing method for multi-access source flow tables shown is specifically for hardware unloading acceleration technology, and provides an optimized and streamlined table clearing operation process, so as to cooperate with the special hardware design, so that the hardware is used as the main body to clear the first flow table deployed on the hardware, with good table clearing processing performance and low processing delay. It should be understood that a table clearing processing method, electronic device and medium for multi-access source flow tables provided in the specific embodiment of the present application support hardware unloading acceleration technology, which can be used for hardware-deployed table clearing processing solutions, such as based on special message transceiver hardware, intelligent network card, data processing unit (DPU), to achieve high-performance table clearing of multiple access sources, and can also be used for software deployment, software and hardware combined deployment table clearing processing solutions. In step S101, the table clearing operation process of each of the multiple access sources for any address in the first flow table includes sequentially executing address reading operation, data waiting operation, data comparison operation and data write-back operation. Here, the table clearing operation process initiated by any access source for any address in the first flow table is logically split to cooperate with the subsequent optimized design of the pipelined table clearing operation process. Among them, the table clearing operation process initiated by any access source to any address in the first flow table includes sequentially executing the address reading operation, data waiting operation, data comparison operation and data write-back operation. Here, taking address A as an example, the address reading operation means initiating a read request to address A in order to obtain the data of address A for analysis. The data waiting operation means waiting for the response of the data of address A. The data comparison operation means obtaining the data of address A and performing a comparison, so as to determine whether it is necessary to perform the corresponding access source clearing on the data of address A based on the access source that initiated the table clearing processing request. The data write-back operation means that if it is determined that the data of address A needs to be cleared, the data belonging to the access source in the data of address A is set to zero (or invalidated), and the data that does not belong to the access source is kept, and then the updated data is written back to the table entry. It can be seen that if other access sources are detected to be operating on address A, such as accessing data or modifying data, during the process of the access source performing the table clearing operation process on address A, a conflict avoidance operation needs to be performed. Specifically, during the stage of performing table clearing for a certain access source, there may be other access sources modifying data. For example, for the same data, if the access source to be cleared is written before other access sources, it may cause incomplete table clearing. For another example, for the same data, if the access source to be cleared is written later than other access sources, it may cause the data of other access sources not to be updated in time. This point is explained in detail below.

[0037] Continue to refer Figure 1In step S103, an address read pipeline is provided for pipeline processing of the address read operations performed by each of the multiple access sources, a data wait pipeline is provided for pipeline processing of the data wait operations performed by each of the multiple access sources, a data comparison pipeline is provided for pipeline processing of the data comparison operations performed by each of the multiple access sources, and a data write-back pipeline is provided for pipeline processing of the data write-back operations performed by each of the multiple access sources. As described above, the table clearing operation process initiated by any access source to any address in the first flow table includes sequentially executing the address read operation, the data wait operation, the data comparison operation and the data write-back operation. The table clearing operation process initiated by any access source to any address in the first flow table is logically split, and then four different types of pipelines are provided for pipeline processing of the split operations. Specifically, an address read pipeline is specifically provided for the address read operation, a data wait pipeline is specifically provided for the data wait operation, a data comparison pipeline is specifically provided for the data comparison operation, and a data write-back pipeline is specifically provided for the data write-back operation. In this way, by providing an optimized pipelined table clearing operation process, the table clearing operation process of multiple access sources for any address in the first flow table is split into four types of operations, and four corresponding special pipelines are provided. This makes the overall table clearing performance independent of the processing delay of data reading, data comparison and data writing, that is, it greatly reduces the processing delay of address read and write access and the impact of the address read and write access cycle on the table clearing performance, which is conducive to improving the performance of hardware in performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay.

[0038] Continue to refer Figure 1, in step S105, through the read command generator, in response to the first clear table instruction of the first flow table issued by the first access source among the multiple access sources, the address corresponding to the first clear table instruction in the first flow table is traversed, thereby generating a first address read command corresponding to the first clear table instruction, wherein the first address read command is used for the address read pipeline and the data wait pipeline to obtain the first response data corresponding to the first clear table instruction. On the basis of the above-mentioned optimized pipelined clear table operation process, the clear table operation process of each of the multiple access sources for any address in the first flow table is split into four types of operations, and four corresponding special pipelines are provided. For this purpose, it is necessary to provide corresponding hardware design in combination with the pipelined clear table operation process, so that conflict avoidance can be achieved in the clear table processing. Specifically, the special hardware design includes three parts, namely, a read command generator, a write command judger and a multi-access source conflict processor. Here, after the read command generator receives a table clearing instruction from a certain access source (such as a physical functional device), it starts to start the generation of read commands, continuously traverses the address (such as accumulation), generates a read command corresponding to the address, and writes it into a special memory, such as a special first-in-first-out (FIFO) memory for storing address read commands, until all addresses are traversed. In some embodiments, the read command generator can further improve the table clearing performance through two special processings, such as suspending the generation of read commands until there is free space when it is found that the memory used to store address read commands is full, and for example, it can cooperate with a multi-access source conflict processor to perform conflict avoidance, which is described in detail below.

[0039] Continue to refer Figure 1In step S107, the write command determiner invalidates the data including the first access source in the first response data and discards the data not including the first access source in the first response data based on the analysis and comparison result of the first response data, thereby generating a first data write-back command corresponding to the first table clearing instruction, and the first data write-back command is used by the data write-back pipeline to perform the data write-back operation corresponding to the first table clearing instruction. Here, the write command determiner analyzes and compares the data obtained by the traversal address to determine whether there is data of the table clearing access source (for example, a physical functional device), that is, to determine whether there is data belonging to the access source that initiates the table clearing processing request in the data obtained according to the address read command. If the judgment result contains data of the table clearing access source, the corresponding data can be refreshed to an invalid value, and the data belonging to other access sources is kept unchanged, that is, the data including the first access source in the first response data is invalidated, and combined with the obtained address, it is written into the data write-back command. Conversely, if the judgment result does not contain data of the table clearing access source, the current data and the obtained address can be discarded, that is, the data write-back command is not written, that is, the data not including the first access source in the first response data is discarded. Here, the first address read command is used for the address read pipeline and the data wait pipeline to obtain the first response data corresponding to the first table clearing instruction. Therefore, the first address read command may point to multiple addresses, and the first response data also includes data from multiple addresses, or corresponds to multiple table entries in the first flow table. Here, the write command determiner can determine which data in the first response data has a table clearing access source and which data does not have a table clearing access source through analysis and comparison, and make corresponding subsequent processing, that is, invalidate the data in the first response data that includes the first access source and discard the data in the first response data that does not include the first access source.

[0040] Continue to refer Figure 1In step S109, through the multi-access source conflict processor, at least during the period from when the read command generator receives the first table clearing instruction of the first access source to when the first data write-back command is executed, the access requests of other access sources other than the first access source to the first flow table among the multiple access sources are monitored, and when there is a conflict between the access requests of the other access sources to the first flow table and the first table clearing instruction, the processor cooperates with the read command generator to perform a conflict avoidance operation. In the table clearing access source clearing stage, there are other access sources that modify data at any time (may be written first and then read, or may be read first and then write), so that the table clearing access source and other access sources obtain the same data, which eventually leads to the occurrence of hash conflicts. For example, for the same data, if the table clearing access source writes before other access sources, the table clearing is not clean; for another example, for the same data, if the table clearing access source writes later than other access sources, the data of other access sources is not updated. Here, through a special hardware design, there are a read command generator, a write command judger and a multi-access source conflict processor. The multi-access source conflict processor is used to monitor the access status of other access sources in real time during the table clearing stage of the table clearing access source. If it is determined that there may be a hash conflict, for example, other access addresses fall within the range of the current table clearing address and the previous address of the table clearing access source, then a conflict avoidance operation is triggered. To this end, through the multi-access source conflict processor, at least during the period from the read command generator receiving the first table clearing instruction of the first access source to the completion of the execution of the first data write back command, the access requests of other access sources other than the first access source in the multiple access sources to the first flow table are monitored, so that the access status of other access sources is monitored in real time during the table clearing stage of the table clearing access source. Furthermore, when there is a conflict between the access request of the other access sources to the first flow table and the first table clearing instruction, the multi-access source conflict processor cooperates with the read command generator to perform a conflict avoidance operation. In this way, based on the above-mentioned optimized pipelined table clearing operation process, the table clearing operation process of multiple access sources for any address in the first flow table is split into four types of operations, and four corresponding special pipelines are provided. In addition, the corresponding hardware design is provided in combination with the pipelined table clearing operation process, so that conflict avoidance can be achieved in the table clearing processing.

[0041] In conclusion, Figure 1 The table clearing method for multi-access source flow tables shown in the figure effectively avoids the conflicts that may be caused by multiple access sources performing table clearing and data modification on the same flow table through an optimized pipelined table clearing operation process and a special hardware design, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of hardware in performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay.

[0042] Figure 2 A schematic diagram of a table clearing device for a multi-access source flow table provided in an embodiment of the present application. Figure 2 As shown, the table clearing processing device 200 includes a read command generator 201, a write command determiner 203, and a multiple access source conflict processor 205. The table clearing processing device 200 also includes a read command FIFO memory 211, an address FIFO memory 213, and a write back command FIFO memory 215. Figure 2 The table clearing processing device shown is used for the table clearing processing method of a multi-access source flow table, and includes the following steps. Determine multiple access sources associated with a first flow table, wherein the table clearing operation process of each of the multiple access sources for any address in the first flow table includes sequentially performing an address reading operation, a data waiting operation, a data comparison operation, and a data write-back operation; provide an address reading pipeline for pipeline processing of the address reading operations performed by each of the multiple access sources, provide a data waiting pipeline for pipeline processing of the data waiting operations performed by each of the multiple access sources, provide a data comparison pipeline for pipeline processing of the data comparison operations performed by each of the multiple access sources, and provide a data write-back pipeline for pipeline processing of the data write-back operations performed by each of the multiple access sources; through a read command generator 201, in response to a first table clearing instruction of the first flow table by a first access source among the multiple access sources, traverse the addresses in the first flow table corresponding to the first table clearing instruction, thereby generating a first address reading command corresponding to the first table clearing instruction, wherein the first address reading command is used for the address reading pipeline and the data waiting pipeline. to obtain first response data corresponding to the first table clearing instruction; through a write command determiner 203, based on the analysis and comparison result of the first response data, invalidate the data of the first access source included in the first response data and discard the data of the first response data not including the first access source, thereby generating a first data write-back command corresponding to the first table clearing instruction, and the first data write-back command is used by the data write-back pipeline to perform the data write-back operation corresponding to the first table clearing instruction; through a multi-access source conflict processor 205, at least during the period from when the first table clearing instruction of the first access source is received from the read command generator 201 to when the first data write-back command is executed, monitor the access requests to the first flow table of other access sources except the first access source among the multiple access sources, and when there is a conflict between the access requests to the first flow table of the other access sources and the first table clearing instruction, cooperate with the read command generator 201 to perform a conflict avoidance operation. The first address read command is stored in a read command FIFO memory 211 , the first response data is stored in an address FIFO memory 213 , and the first data write back command is stored in a write back command FIFO memory 215 .

[0043] Figure 2 The table clearing processing device 200 shown, through an optimized pipelined table clearing operation process and a special hardware design, effectively avoids conflicts that may be caused by multiple access sources performing table clearing processing and modifying data on the same flow table, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of hardware performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay.

[0044] refer to Figure 1 and Figure 2 In a possible implementation, through the multi-access source conflict processor, when the access address of the access request of the other access source to the first flow table overlaps with the address corresponding to the first table clearing instruction in the first flow table, it is determined that there is a conflict between the access request of the other access source to the first flow table and the first table clearing instruction. When other access addresses fall on the current table clearing address of the table clearing access source, that is, when the access address of the access request of the other access source to the first flow table overlaps with the address corresponding to the first table clearing instruction in the first flow table, the multi-access source conflict processor determines that there may be a conflict and performs a conflict avoidance operation. In this way, through the optimized design of the pipelined table clearing operation process and the special hardware design, the conflict that may be caused by multiple access sources performing table clearing processing and modifying data on the same flow table is effectively avoided, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of hardware in performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay.

[0045] In some embodiments, through the multi-access source conflict processor, when the access address of the access request of the other access source to the first flow table overlaps with the preset address range in the first flow table relative to the address corresponding to the first clear table instruction, it is determined that there is a conflict between the access request of the other access source to the first flow table and the first clear table instruction. Here, in order to better avoid conflicts, based on the address corresponding to the first clear table instruction, the preset address range in the first flow table relative to the address corresponding to the first clear table instruction is specified. Therefore, when the access address of the access request of the other access source to the first flow table falls into the specified preset address range, the multi-access source conflict processor determines that there may be a conflict and performs a conflict avoidance operation. In this way, through the optimized design of the pipelined clear table operation process and the special hardware design, the conflicts that may be caused by multiple access sources performing clear table processing and modifying data on the same flow table are effectively avoided, so that the clear table performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of hardware performing clear table processing on large-scale flow tables and reducing the overall clear table processing delay.

[0046] In some embodiments, the preset address range in the first flow table relative to the address corresponding to the first table clearing instruction is an address within the previous preset range of the address corresponding to the first table clearing instruction. When other access addresses fall within the range of the current table clearing address and the previous address of the table clearing access source, the multi-access source conflict processor determines that there may be a conflict and performs a conflict avoidance operation. In this way, through the optimized design of the pipelined table clearing operation process and the special hardware design, the conflicts that may be caused by multiple access sources performing table clearing processing and modifying data on the same flow table are effectively avoided, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of the hardware in performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay.

[0047] In a possible implementation, through the multi-access source conflict processor, when there is a conflict between the access request of the other access sources to the first flow table and the first table clearing instruction, it cooperates with the read command generator to perform a conflict avoidance operation, including: determining the current conflicting address of the access request of the other access sources to the first flow table relative to the first table clearing instruction, rolling back the read command generator to the current conflicting address, and traversing the address corresponding to the first table clearing instruction in the first flow table from the current conflicting address again. As described above, the read command generator cooperates with the multi-access source conflict processor to perform conflict avoidance. In response to the first table clearing instruction of the first access source among the multiple access sources to the first flow table, the read command generator traverses the address corresponding to the first table clearing instruction in the first flow table, thereby generating a first address read command corresponding to the first table clearing instruction. Therefore, when the multi-access source conflict processor detects a conflict between the access request of other access sources to the first flow table and the first table clearing instruction, for example, when it is found that the access address of other access sources falls within the address range of the table clearing access source, the table clearing address is rolled back, and the table clearing access is initiated again from the address where the conflict occurs, that is, the read command generator is rolled back to the current conflicting address, and the address corresponding to the first table clearing instruction in the first flow table is traversed again from the current conflicting address. In this way, through the optimized design of the pipelined table clearing operation process and the special hardware design, the conflicts that may be caused by multiple access sources performing table clearing processing and modifying data on the same flow table are effectively avoided, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of hardware in performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay.

[0048] In some embodiments, through the multi-access source conflict processor, when there is a conflict between the access request of the other access source to the first flow table and the first table clearing instruction, it cooperates with the read command generator to perform a conflict avoidance operation, and also includes: determining the conflict interval in the access address of the access request of the other access source to the first flow table relative to the first table clearing instruction, clearing the part corresponding to the conflict interval in the first address read command, clearing the part corresponding to the conflict interval in the first response data, and clearing the part corresponding to the conflict interval in the first data write back command. The read command generator cooperates with the multi-access source conflict processor to perform conflict avoidance. In the table clearing stage of the table clearing access source, the access status of other access sources is monitored in real time. If other access addresses fall within the range of the current table clearing address and the previous address of the table clearing access source, there may be a hash conflict, triggering a conflict avoidance operation. The conflict avoidance operation includes triggering the read command generator to roll back the table clearing address to the address currently accessed by other access sources, and then re-initiating the table clearing access from the conflicting address. For the first address read command that has been generated, in order to avoid the first address read command and the downstream modules such as the address read pipeline and the data waiting pipeline completing the address read operation, thereby obtaining the data in the conflict interval. To this end, the conflict avoidance operation also includes clearing the part of the first address read command corresponding to the conflict interval, clearing the part of the first response data corresponding to the conflict interval, and clearing the part of the first data write back command corresponding to the conflict interval. In this way, by clearing the commands that have been generated but fall into the conflict interval, hash conflicts between other access sources and table clearing access sources can be effectively avoided.

[0049] In some embodiments, through the multi-access source conflict processor, when there is a conflict between the access request of the other access sources to the first flow table and the first table clearing instruction, it cooperates with the read command generator to perform a conflict avoidance operation, and also includes: clearing the part corresponding to the conflict interval in the data write-back operation corresponding to the first table clearing instruction. The read command generator cooperates with the multi-access source conflict processor to perform conflict avoidance. In the table clearing stage of the table clearing access source, the access status of other access sources is monitored in real time. If other access addresses fall within the range of the current table clearing address and the previous address of the table clearing access source, there may be a hash conflict, triggering a conflict avoidance operation. The conflict avoidance operation includes triggering the read command generator to roll back the table clearing address to the address currently accessed by other access sources, and then re-initiating the table clearing access from the conflicting address. For the first address read command that has been generated, in order to avoid the first address read command and the downstream module, such as the address read pipeline and the data waiting pipeline, completing the address read operation, thereby obtaining data in the conflict interval. To this end, the conflict avoidance operation also includes clearing the portion of the first address read command corresponding to the conflict interval, clearing the portion of the first response data corresponding to the conflict interval, and clearing the portion of the first data write-back command corresponding to the conflict interval. In this way, by clearing the commands that have been generated but fall into the conflict interval, hash conflicts between other access sources and the table clearing access source can be effectively avoided. Further, in order to avoid conflicts caused by the addresses of the read and write operations being performed downstream falling into the conflict interval, the portion of the data write-back operation corresponding to the first table clearing instruction corresponding to the conflict interval is cleared. In this way, through the optimized design of the pipelined table clearing operation process and the special hardware design, the conflicts that may be caused by multiple access sources performing table clearing processing and modifying data on the same flow table are effectively avoided, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of hardware in performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay.

[0050] In a possible implementation, the first address read command is stored in a read command FIFO memory, the first response data is stored in an address FIFO memory, and the first data write-back command is stored in a write-back command FIFO memory. In this way, the storage and management of commands are realized through the FIFO memory, which is conducive to combining the optimized design of the pipelined table clearing operation process, so that the overall table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, that is, the processing delay of address read and write access and the influence of the address read and write access cycle on the table clearing performance are greatly reduced, which is conducive to improving the performance of hardware in performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay.

[0051] In some embodiments, the address read pipeline and the data wait pipeline obtain the first response data based on the state of the read command FIFO memory, which is conducive to improving pipeline processing efficiency and table clearing performance.

[0052] In some embodiments, the read command generator is configured to, when the read command FIFO memory is full, suspend the generation of the first address read command until there is free space in the read command FIFO memory, which is beneficial to improving the pipeline processing efficiency and table clearing performance.

[0053] In some embodiments, the data write-back pipeline executes the data write-back operation corresponding to the first table clearing instruction based on the state of the write-back command FIFO memory, which is beneficial to improving the pipeline processing efficiency and table clearing performance.

[0054] In some embodiments, the write command determiner invalidates the data including the first access source in the first response data and discards the data not including the first access source in the first response data based on the analysis and comparison results of the first response data, thereby generating a first data write-back command corresponding to the first table clearing instruction, including: for the data including the first access source in the first response data, refreshing the first access source to an invalid value, and keeping the data of other access sources except the first access source among the multiple access sources unchanged, and then writing them to the write-back command first-in-first-out memory in combination with the address obtained from the address first-in-first-out memory; for the data not including the first access source in the first response data, discarding the data not including the first access source in the first response data and the address obtained from the address first-in-first-out memory, and not writing them to the write-back command first-in-first-out memory. The write command determiner analyzes and compares the data obtained from the traversal address to determine whether there is data of the table clearing access source (for example, a physical functional device), that is, determining whether there is data of the access source that initiates the table clearing processing request in the data obtained according to the address read command. If the judgment result contains data of the table clearing access source, the corresponding data can be refreshed to an invalid value, and the data belonging to other access sources are kept unchanged, that is, the data of the first access source included in the first response data is invalidated, and combined with the obtained address, it is written into the data write-back command. Conversely, if the judgment result does not contain data of the table clearing access source, the current data and the obtained address can be discarded, that is, the data write-back command is not written, that is, the data not including the first access source in the first response data is discarded. Here, the first address read command is used for the address read flow and the data waiting flow to obtain the first response data corresponding to the first table clearing instruction. Therefore, the first address read command may point to multiple addresses, and the first response data also includes data from multiple addresses, or corresponds to multiple entries in the first flow table. Here, the write command determiner can determine which data in the first response data has the table clearing access source and which does not have the table clearing access source through analysis and comparison, and make corresponding subsequent processing, that is, invalidate the data including the first access source in the first response data and discard the data not including the first access source in the first response data. In this way, through the optimized design of pipelined table clearing operation process and specialized hardware design, the conflicts that may be caused by multiple access sources performing table clearing and data modification on the same flow table can be effectively avoided, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is conducive to improving the performance of hardware table clearing for large-scale flow tables and reducing the overall table clearing processing delay.

[0055] In a possible implementation, the processing delay of the first table clearing instruction is independent of the processing delay of the address read and write access. The table clearing operation process initiated by any access source to any address in the first flow table includes sequentially executing an address read operation, a data wait operation, a data comparison operation, and a data write-back operation. The table clearing operation process initiated by any access source to any address in the first flow table is logically split, and then four different types of pipelines are provided for pipeline processing of the split operations. Specifically, an address read pipeline is provided specifically for the address read operation, a data wait pipeline is provided specifically for the data wait operation, a data comparison pipeline is provided specifically for the data comparison operation, and a data write-back pipeline is provided specifically for the data write-back operation. In this way, by providing an optimized pipelined table clearing operation process, the table clearing operation process of multiple access sources for any address in the first flow table is split into four types of operations, and four corresponding special pipelines are provided. This makes the overall table clearing performance independent of the processing delay of data reading, data comparison and data writing, that is, it greatly reduces the processing delay of address read and write access and the impact of the address read and write access cycle on the table clearing performance, which is conducive to improving the performance of hardware in performing table clearing processing on large-scale flow tables and reducing the overall table clearing processing delay.

[0056] In a possible implementation manner, the multiple access sources are multiple physical functional devices, and the first flow table is a hash table. This is conducive to adapting to the needs of various application environments.

[0057] In a possible implementation, the multiple access sources include a second access source, the second access source is different from the first access source, and the initiation time of the access request of the second access source to the first flow table is earlier or later than the time when the read command generator receives the first table clearing instruction from the first access source. In this way, it is helpful to avoid hash conflicts between the first access source and the second access source, and through the optimized pipelined table clearing operation process and special hardware design, it is effectively avoided that conflicts may be caused by multiple access sources performing table clearing processing and data modification on the same flow table, so that the table clearing performance does not depend on the processing delay of data reading, data comparison and data writing, which is helpful to improve the performance of hardware performing table clearing processing on large-scale flow tables and reduce the overall table clearing processing delay.

[0058] Figure 33 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application, and the computing device 300 includes: one or more processors 310, a communication interface 320 and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected via a bus 340. Optionally, the computing device 300 may also include an input / output interface 350, and the input / output interface 350 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 310 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 300 can refer to the specific details in the above-mentioned embodiments, such as the processor 310 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 300 may be used to implement part or all of the functions of one or more components in the above-mentioned apparatus embodiment. In addition, the communication interface 320 may be specifically used to perform the communication functions necessary to implement the functions of these apparatuses and components, and the processor 310 may be specifically used to perform the processing functions necessary to implement the functions of these apparatuses and components.

[0059] It should be understood that Figure 3 The computing device 300 may include one or more processors 310, and the multiple processors 310 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 310 may form a processor sequence or a processor array, or the multiple processors 310 may be divided into a main processor and an auxiliary processor, or the multiple processors 310 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 3 The computing device 300 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 300 may include Figure 3 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0060] The processor 310 may have a variety of specific implementation forms. For example, the processor 310 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 310 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 320 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0061] The memory 330 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 330 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 330 may also be used to store program codes and data, so that the processor 310 calls the program codes stored in the memory 330 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 3 Show more or fewer components, or have different component configurations.

[0062] The bus 340 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 340 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 340 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 3 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0063] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0064] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0065] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable storage medium.

[0066] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0067] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A method for clearing a multi-access source flow table, characterized in that: The table clearing treatment method comprises: Determine multiple access sources associated with the first flow table, wherein the clearing operation process of each of the multiple access sources for any address in the first flow table includes sequentially performing an address reading operation, a data waiting operation, a data comparison operation, and a data write-back operation; Providing an address read pipeline for pipeline processing of address read operations respectively performed by the multiple access sources, providing a data wait pipeline for pipeline processing of data wait operations respectively performed by the multiple access sources, providing a data comparison pipeline for pipeline processing of data comparison operations respectively performed by the multiple access sources, and providing a data write-back pipeline for pipeline processing of data write-back operations respectively performed by the multiple access sources; By means of a read command generator, in response to a first table clearing instruction of the first flow table from a first access source among the multiple access sources, traversing addresses corresponding to the first table clearing instruction in the first flow table, thereby generating a first address read command corresponding to the first table clearing instruction, wherein the first address read command is used for the address read pipeline and the data wait pipeline to obtain first response data corresponding to the first table clearing instruction; By means of a write command determiner, based on the analysis and comparison result of the first response data, the data including the first access source in the first response data is invalidated and the data not including the first access source in the first response data is discarded, thereby generating a first data write-back command corresponding to the first table clearing instruction, the first data write-back command being used in the data write-back pipeline to perform the data write-back operation corresponding to the first table clearing instruction; Through a multi-access source conflict processor, at least during the period from when the read command generator receives the first table clearing instruction of the first access source to when the first data write back command is executed, access requests to the first flow table from other access sources except the first access source among the multiple access sources are monitored, and when there is a conflict between the access requests to the first flow table from the other access sources and the first table clearing instruction, the processor cooperates with the read command generator to perform a conflict avoidance operation.

2. The surface clearing method according to claim 1, characterized in that: Through the multi-access source conflict processor, when the access address of the access request to the first flow table of the other access sources overlaps with the address corresponding to the first table clearing instruction in the first flow table, it is determined that there is a conflict between the access request to the first flow table of the other access sources and the first table clearing instruction.

3. The surface clearing method according to claim 2, characterized in that: Through the multi-access source conflict processor, when the access address of the access request of the other access source to the first flow table overlaps with the preset address range in the first flow table relative to the address corresponding to the first table clearing instruction, it is determined that there is a conflict between the access request of the other access source to the first flow table and the first table clearing instruction.

4. The surface clearing method according to claim 3, characterized in that: The preset address range in the first flow table relative to the address corresponding to the first table clearing instruction is an address within a previous preset range of the address corresponding to the first table clearing instruction.

5. The surface clearing method according to claim 1, characterized in that: By means of the multi-access source conflict processor, when there is a conflict between the access request of the other access sources to the first flow table and the first table clearing instruction, cooperating with the read command generator to perform a conflict avoidance operation, including: Determine the current conflicting address of the access request to the first flow table of the other access sources relative to the first table clearing instruction, roll back the read command generator to the current conflicting address, and traverse the address corresponding to the first table clearing instruction in the first flow table again from the current conflicting address.

6. The surface clearing method according to claim 5, characterized in that: By means of the multi-access source conflict processor, when there is a conflict between the access request of the other access sources to the first flow table and the first table clearing instruction, cooperating with the read command generator to perform a conflict avoidance operation, the process further includes: Determine the conflicting interval in the access address of the access request to the first flow table of the other access source relative to the first table clear instruction, clear the part corresponding to the conflicting interval in the first address read command, clear the part corresponding to the conflicting interval in the first response data, and clear the part corresponding to the conflicting interval in the first data write back command.

7. The surface clearing method according to claim 6, characterized in that: By means of the multi-access source conflict processor, when there is a conflict between the access request of the other access sources to the first flow table and the first table clearing instruction, cooperating with the read command generator to perform a conflict avoidance operation, the process further includes: The portion corresponding to the conflicting interval in the data write-back operation corresponding to the first table clearing instruction is cleared.

8. The surface clearing method according to claim 1, characterized in that: The first address read command is stored in a read command first-in-first-out memory, the first response data is stored in an address first-in-first-out memory, and the first data write-back command is stored in a write-back command first-in-first-out memory.

9. The surface clearing method according to claim 8, characterized in that: The address read pipeline and the data wait pipeline obtain the first response data based on the state of the read command first-in-first-out memory.

10. The surface clearing method according to claim 8, characterized in that: The read command generator is configured to, when the read command FIFO memory is full, suspend generating the first address read command until there is free space in the read command FIFO memory.

11. The surface clearing method according to claim 8, characterized in that: The data write-back pipeline executes a data write-back operation corresponding to the first table clear instruction based on the state of the write-back command first-in-first-out memory.

12. The surface clearing method according to claim 8, characterized in that: The write command determiner invalidates the data including the first access source in the first response data and discards the data not including the first access source in the first response data based on the analysis and comparison result of the first response data, thereby generating a first data write-back command corresponding to the first table clearing instruction, including: For the data of the first access source included in the first response data, the first access source is refreshed to an invalid value, and the data of other access sources except the first access source among the plurality of access sources are kept unchanged, and then, combined with the address obtained from the address first-in-first-out memory, the data is written into the write-back command first-in-first-out memory; For the data not including the first access source in the first response data, the data not including the first access source in the first response data and the address obtained from the address first-in-first-out memory are discarded, and are not written to the write-back command first-in-first-out memory.

13. The surface clearing method according to claim 1, characterized in that: The processing delay of the first table clear instruction does not depend on the processing delay of address read and write access.

14. The surface clearing method according to claim 1, characterized in that: The multiple access sources are multiple physical function devices, and the first flow table is a hash table.

15. The surface clearing method according to claim 1, characterized in that: The multiple access sources include a second access source, which is different from the first access source, and the time when the second access source initiates the access request to the first flow table is earlier than or later than the time when the read command generator receives the first table clearing instruction from the first access source.

16. An electronic device, characterized in that: The electronic device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 15 when executing the computer program.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 15.

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