Board card layout optimization method and system, computer equipment and storage medium

Abstract

The invention discloses a board card layout optimization method and system, computer equipment and a storage medium, and relates to the technical field of board cards, and the method comprises the steps: obtaining a board card model, and importing the board card model into finite element software to obtain a board card strain cloud picture obtained through the simulation of the finite element software; marking an area exceeding a preset strain range in the board card strain cloud picture as a standard exceeding area; obtaining a board card device layout map, and setting the board card strain cloud map and the board card device layout map to be superposed, compared and analyzed, so as to obtain an overproof device at a position overlapped with the projection position of the overproof area in the board card device layout map; and moving the standard-exceeding device to a position which is not overlapped with the standard-exceeding area. According to the application, the strain distribution condition in the process that the board card is impacted and the connector is plugged is analyzed and simulated through finite element simulation, and the placement position of the component is adjusted according to the simulation analysis result, so that the component layout of the board card is ensured to meet the strain requirement.

Description

Technical Field

[0001] The present application relates to the technical field of boards and cards, and in particular to a board and card layout optimization method, system, computer equipment and storage medium. Background Art

[0002] As the core component of modern electronic devices, circuit boards are covered with various components to support different functions. There are many electronic components arranged on the board, which will cause the board to deform when it is hit or accidentally dropped during transportation. At the same time, the components integrated on the board will also deform, resulting in large strain. In addition, when plugging and unplugging the cable connector, the board will deform during the process of plugging and unplugging the cable end connector, which will also cause strain on the components on the board.

[0003] In some related technologies, in order to solve the strain problem on the board, the devices on the board are usually tested during the board layout stage of research and development, and then the locations where the strain problems occur are revised and tested multiple times to form a board that meets the strain requirements. The above method greatly increases the research and development cycle, increases the research and development cost, and the efficiency of the board layout optimization process is low. Summary of the invention

[0004] In order to solve at least one of the problems mentioned in the above background technology, the present application provides a board layout optimization method, system, computer equipment and storage medium, which simulates the strain distribution of the board when it is subjected to impact and the connector during plugging and unplugging through finite element simulation analysis, and adjusts the placement of components according to the simulation analysis results to ensure that the component layout of the board meets the strain requirements.

[0005] The specific technical solutions provided by the embodiments of this application are as follows:

[0006] In a first aspect, a board layout optimization method is provided, the method comprising:

[0007] Obtaining a board model, and importing the board model into finite element software to obtain a board strain cloud diagram obtained by finite element software simulation;

[0008] Mark the area in the board strain cloud diagram that exceeds the preset strain range as an over-standard area;

[0009] Obtain a board device layout diagram, set the board strain cloud diagram and the board device layout diagram to be superimposed for comparative analysis, so as to obtain the exceeding components at a position in the board device layout diagram that overlaps with the projection position of the exceeding area;

[0010] Move the exceeding-standard device to a position that does not overlap with the exceeding-standard area.

[0011] In a specific embodiment, a board model is obtained, and the board model in the finite element software is meshed to generate board mesh units; boundary parameters and load parameters of the board mesh unit simulation process are set through the finite element software to obtain the board strain cloud diagram.

[0012] In a specific embodiment, the board strain cloud map includes a first board cloud map and a second board cloud map; marking an area in the first board cloud map that exceeds a first preset strain value as a chip exceeding the standard area, and marking an area in the second board cloud map that exceeds a second preset strain value as a capacitor exceeding the standard area; obtaining the chip position in the board device layout map, and determining whether the chip position is located in an overlapping projection area between the chip exceeding the standard area and the board device layout map;

[0013] If so, confirm that the chip is located in the over-standard area, and move the over-standard device to the board position corresponding to the non-exceeding area in the board strain cloud map; or, if not, the chip is not located in the over-standard area; obtain the capacitance in the board device layout map, and set the capacitor to have a first side length and a second side length in the overlapping plane of the board strain cloud map and the board device layout map, wherein the first side length is greater than or equal to the second side length; divide the second board cloud map into a first side length direction cloud map and a second side length direction cloud map according to the first side length and the second side length of the capacitor; combine the first side length direction cloud map with the board device layout map for comparative analysis to obtain the over-standard capacitance in the first direction; combine the second side length direction cloud map with the board device layout map for comparative analysis to obtain the over-standard capacitance in the second direction.

[0014] In a specific embodiment, the first side length direction cloud map includes a first capacitance exceeding standard area, the second side length direction cloud map includes a second capacitance exceeding standard area, and the method further includes:

[0015] Set the first side length cloud map to overlap and compare with the board device layout diagram for analysis, and determine whether there is a capacitor exceeding the first direction at a position overlapping with the first capacitor exceeding the standard area in the board device layout diagram; if so, adjust the capacitor exceeding the standard in the first direction to rotate the first angle or move the capacitor exceeding the standard in the first direction to a position not overlapping with the first capacitor exceeding the standard area; or, if not, do not adjust the position of the capacitor exceeding the standard in the first direction.

[0016] In a specific embodiment, the second side length direction cloud map is set to overlap and compare and analyze with the board device layout diagram to determine whether there is a capacitor exceeding the second direction at a position overlapping with the second capacitor exceeding the standard area in the board device layout diagram; if so, the capacitor exceeding the second direction is adjusted to rotate a second angle or moved to a position not overlapping with the second capacitor exceeding the standard area; or, if not, the position of the capacitor exceeding the second direction is not adjusted.

[0017] In a specific embodiment, if the capacitor exceeding the standard in the first direction and the capacitor exceeding the standard in the second direction correspond to capacitors at the same position in the board device layout diagram; move the capacitors at the same position to a position that does not overlap with the first capacitor exceeding the standard area and the second capacitor exceeding the standard area.

[0018] In a specific embodiment, the area of ​​the exceeding standard region in the board strain cloud map is calculated. If the area of ​​the exceeding standard region exceeds a preset value, the support of the board structure is adjusted; the adjusted board structure is obtained, and the updated board strain cloud map is obtained again through finite element software simulation.

[0019] In a second aspect, a board layout optimization system is provided, which is used to implement the board layout optimization method as described above, and the system includes:

[0020] A simulation unit, used for acquiring a board model, and importing the board model into finite element software to obtain a board strain cloud diagram obtained by finite element software simulation;

[0021] A marking unit, used for marking the area beyond the preset strain range in the board strain cloud diagram as an over-standard area;

[0022] An analysis unit is used to obtain a board device layout diagram, and set the board strain cloud diagram to be superimposed and compared with the board device layout diagram to obtain the exceeding components at a position in the board device layout diagram that overlaps with the projection position of the exceeding area;

[0023] A processing unit is used to move the exceeding-standard device to a position that does not overlap with the exceeding-standard area.

[0024] In a third aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0025] Step A: obtaining a board model, and importing the board model into finite element software to obtain a board strain cloud diagram obtained by finite element software simulation;

[0026] Step B: marking the area in the board strain cloud diagram that exceeds the preset strain range as an over-standard area;

[0027] Step C: obtaining a board device layout diagram, setting the board strain cloud diagram and the board device layout diagram to be superimposed for comparative analysis, so as to obtain the exceeding components at the overlapping position of the exceeding area projection position in the board device layout diagram;

[0028] Step D: moving the exceeding-standard device to a position that does not overlap with the exceeding-standard area.

[0029] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0030] Step A: obtaining a board model, and importing the board model into finite element software to obtain a board strain cloud diagram obtained by finite element software simulation;

[0031] Step B: marking the area in the board strain cloud diagram that exceeds the preset strain range as an over-standard area;

[0032] Step C: obtaining a board device layout diagram, setting the board strain cloud diagram and the board device layout diagram to be superimposed for comparative analysis, so as to obtain the exceeding components at the overlapping position of the exceeding area projection position in the board device layout diagram;

[0033] Step D: moving the exceeding-standard device to a position that does not overlap with the exceeding-standard area.

[0034] The embodiments of the present application have the following beneficial effects:

[0035] 1. The solution provided in the embodiment of the present application first simulates the board model through finite element software to obtain the board strain cloud map, and marks the area in the board strain cloud map that exceeds the preset strain range as the over-standard area, and then overlaps and compares the board layout map with the board strain cloud map to obtain the components in the board layout map that overlap with the projection of the over-standard area, and moves this component to a position that does not overlap with the over-standard area, so as to optimize and adjust the components laid out on the boards in the production and R&D stages, simulate the strain distribution of the board when it is impacted and the connector is plugged in and out through finite element simulation analysis, and adjust the placement of the components according to the simulation analysis results to ensure that the component layout of the board meets the strain requirements.

[0036] 2. Further, the corresponding first side length direction cloud map and second side length direction cloud map are simulated respectively according to the two side length directions of the capacitor on the board, and different exceeding standard areas exceeding the preset value in the two direction cloud maps are marked, and the cloud maps in the two directions are compared and analyzed with the board device layout diagram respectively to obtain the exceeding standard capacitance in the first direction and the exceeding standard capacitance in the second direction, and the exceeding standard capacitance in the two directions is adjusted by rotating a certain angle, or the exceeding standard capacitance is directly moved out of the exceeding standard area, and the above process is used to realize further accurate simulation and adjustment of the board strain, thereby ensuring that the components on the board can work normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A schematic diagram of an application environment according to the present application is shown;

[0039] Figure 2 A schematic diagram of a board layout optimization method according to the present application is shown;

[0040] Figure 3 A schematic diagram of a finite element model of a board in this application is shown;

[0041] Figure 4 A schematic diagram showing a cloud diagram of a first board in the present application is shown;

[0042] Figure 5 Shows the layout diagram of the board device according to the present application;

[0043] Figure 6 A schematic diagram showing the overlap of the first board cloud diagram and the board device layout diagram according to the present application is shown;

[0044] Figure 7 A schematic diagram showing a first side length direction cloud diagram according to the present application;

[0045] Figure 8 A schematic diagram showing the overlap of the first capacitance exceeding standard area in the board device layout diagram according to the present application is shown;

[0046] Fig. 9 A schematic diagram of a finite element model of a board with a power board according to the present application is shown;

[0047] Fig.10 A schematic diagram showing a principal strain cloud diagram according to the present application is shown;

[0048] Fig.11 A schematic diagram showing the superposition of the principal strain cloud diagram and the board device layout diagram according to the present application is shown;

[0049] Fig.12 A schematic diagram showing the position of the buffer pad configured on the board according to the present application;

[0050] Fig.13 A schematic diagram showing a second side length direction cloud diagram according to the present application;

[0051] Fig.14 A schematic diagram showing the superposition of the second side length direction cloud map and the board device layout map according to the present application is shown;

[0052] Fig.15 A schematic diagram of a board layout optimization system according to the present application is shown;

[0053] Fig.16 A schematic diagram showing a computer device according to the present application. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0055] The board layout optimization method provided in this application can be applied to Figure 1 In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The terminal 102 is configured with finite element software to simulate the board model through the finite element software to obtain the board strain cloud map; mark the area exceeding the preset strain range in the board strain cloud map as the over-standard area; obtain the board device layout map, set the board strain cloud map and the board device layout map to overlay and compare and analyze, so as to obtain the over-standard device in the board device layout map that overlaps with the projection position of the over-standard area; move the over-standard device to a position that does not overlap with the over-standard area. Among them, the terminal 102 can be but is not limited to various personal computers, laptops, smart phones, tablet computers and portable wearable devices, and the server 104 can be implemented with an independent server or a server cluster composed of multiple servers.

[0056] In one embodiment, Figure 2 As shown, a board layout optimization method is provided, which is applied to Figure 1 The terminal in is used as an example to illustrate, including the following steps:

[0057] Step 101: Obtain a board model, and import the board model into finite element software to obtain a board strain cloud diagram obtained by finite element software simulation.

[0058] Specifically, it includes obtaining a board model, meshing the board model in the finite element software to generate a board mesh unit; setting boundary parameters and load parameters of the board mesh unit simulation process through the finite element software to obtain the board strain cloud diagram.

[0059] Import the board model into the finite element software, take the board as the 50G impact strain diagram, and specifically select the finite element analysis software as hypermesh. Use the finite element software to clean up the geometry of the board model, divide the shell unit mesh to generate no less than two layers of body unit mesh, and set the unit type to C3D8I. Further, obtain the main components on the board, including CPU, radiator, memory, and connector, etc., and model the above components and connect the above modeled devices to the mainboard according to the actual board layout, configure the material properties of each component, and keep the weight of each component consistent with the actual weight, so as to obtain the following Figure 3 The finite element model of the board.

[0060] The above-mentioned board finite element model is saved as an inp file and imported into the post-processing software abaqus for analysis. The analysis mode is selected as Dynamic Explicit, the total calculation time is 0.015s, the general contact and contact properties are set, and a "50G, 11ms" square wave impact is applied to the mainboard bolt hole to simulate the mainboard face-down impact. The gravity load is set and the simulation calculation is submitted; by viewing the simulation results in the abaqus post-processing, the board strain cloud diagram is extracted.

[0061] Step 102: Mark the area in the board strain cloud diagram that exceeds the preset strain range as an over-standard area.

[0062] Set a preset strain range value. For example, set the strain verification standard of the chip on the board to no more than 1200 microstrain, the strain verification standard of the capacitor 0402 package to no more than 1400 microstrain, the strain verification standard of the 0805-0603 package to no more than 700 microstrain, and the strain verification standard of the 1206-1210 package to no more than 450 microstrain. Based on the above parameters, mark the area in the board strain cloud map that exceeds the preset strain range as an out-of-standard area.

[0063] Step 103, obtaining a board device layout diagram, setting the board strain cloud diagram and the board device layout diagram to be superimposed for comparative analysis, so as to obtain the exceeding components at the position overlapping with the projection position of the exceeding area in the board device layout diagram;

[0064] Step 104: Move the exceeding-standard device to a position that does not overlap with the exceeding-standard area.

[0065] In order to achieve further accurate analysis of the strain changes of different components on the board and ensure that the components on the board remain in normal operation, different types of components on the board are analyzed separately. The board strain cloud map is set to include a first board cloud map and a second board cloud map; the area in the first board cloud map that exceeds the first preset strain value is marked as a chip exceeding the standard area, and the area in the second board cloud map that exceeds the second preset strain value is marked as a capacitor exceeding the standard area.

[0066] Obtain the chip position in the board device layout diagram, and determine whether the chip position is located in the overlapping projection area of ​​the chip over-standard area and the board device layout diagram; if so, confirm that the chip is located in the over-standard area, and move the over-standard device to the board position corresponding to the non-over-standard area in the board strain cloud diagram; or, if not, the chip is not located in the over-standard area, and the chip position is not adjusted at this time.

[0067] For example, Figure 4 As shown in FIG. 1 , it is a cloud diagram of the first board obtained by finite element software simulation, in which the marked chip exceeding standard area is the area where the micro strain exceeds 1200; Figure 5 As shown in the figure, it is a layout diagram of the board device, in which the marked position is the position of the BGA chip in the board. By setting the first board cloud image to be transparent, the first board cloud image is overlapped with the board device layout diagram and placed as shown in FIG. Figure 6 As shown, according to Figure 6 It can be seen that this board includes two BGA chips. By comparing the BGA chips with the chip over-standard area one by one, it can be found that both BGA chips are not placed in the chip over-standard area, which further indicates that the chips in this board meet the corresponding strain requirements and the chip position does not need to be adjusted.

[0068] In a specific embodiment, since the capacitors on the board are usually in the shape of a cuboid, in order to accurately simulate the strain of capacitors placed in different directions, so as to accurately adjust the strain at the location of the capacitor, the capacitor in the board device layout diagram is obtained, and the capacitor is set to have a first side length and a second side length in the overlapping plane of the board strain cloud map and the board device layout diagram, wherein the first side length is greater than or equal to the second side length; according to the first side length and the second side length of the capacitor, the second board cloud map is divided into a first side length direction cloud map and a second side length direction cloud map; the first side length direction cloud map is combined with the board device layout diagram for comparative analysis to obtain the capacitor exceeding the standard in the first direction.

[0069] In this embodiment, the first side length direction cloud map includes a first capacitance exceeding standard area, and the first side length direction cloud map is combined with the board device layout map for comparative analysis to obtain the first direction exceeding standard capacitance, specifically including: setting the first side length cloud map and the board device layout map for overlapping comparative analysis to determine whether there is a capacitance exceeding standard in the first direction at a position overlapping with the first capacitance exceeding standard area in the board device layout map; if so, adjusting the capacitance exceeding standard in the first direction to rotate a first angle or moving the capacitance exceeding standard in the first direction to a position not overlapping with the first capacitance exceeding standard area; or, if not, not adjusting the position of the capacitance exceeding standard in the first direction.

[0070] Exemplarily, the first direction corresponds to Figure 7 The Z-axis direction of the first side length direction cloud map is obtained by finite element software simulation, and the area where the microstrain is greater than 700 in the first side length direction cloud map is marked. The board device layout map is overlapped with the first capacitance exceeding the standard area to analyze whether there is excessive capacitance in the first direction. The comparison results are as follows Figure 8 As shown in the figure, the comparison results are used to verify the 0805-0603 package capacitors and the capacitors placed along the Z-axis direction. It can be seen that the three connected capacitors in the upper part of the figure are located in the strain exceeding area. Therefore, these three capacitors need to be moved out of the first capacitor exceeding area or rotated 90°; the two capacitors at the bottom are not placed in the strain exceeding area and meet the strain requirements. Therefore, the position and direction of the capacitors at the bottom do not need to be adjusted.

[0071] In a specific embodiment, the second side length direction cloud map is combined with the board device layout diagram for comparative analysis to obtain the second direction excessive capacitance, wherein the second side length direction cloud map includes the second capacitance excessive area; specifically comprising: setting the second side length direction cloud map and the board device layout diagram to overlap and compare and analyze, and judging whether there is a second direction excessive capacitance at a position overlapping with the second capacitance excessive area in the board device layout diagram; if so, adjusting the second direction excessive capacitance to rotate a second angle or moving the second direction excessive capacitance to a position not overlapping with the second capacitance excessive area; or, if not, not adjusting the second direction excessive capacitance position.

[0072] In this embodiment, the process of plugging the power board into the board has a great impact on the strain state on the board. For example, the geometric model of the power board is imported into the finite element software hypermesh, and the geometry is cleaned up, the shell unit mesh is divided, and the volume unit mesh is generated. The unit type is set to C3D8I. The main components on the power board, such as the connector, are modeled. The connector and the power board are connected at the same node. The material tray under the power board is modeled. The power board and the tray are connected by bolts. The material properties of each component are set to keep the weight of each component consistent with the actual weight. The finite element model of the board with the power board obtained by simulation is as follows: Fig. 9 shown.

[0073] The finite element model of the board with the power board is saved as an inp file and imported into the post-processing software abaqus. The analysis step is set, and Static General is selected to constrain the bottom surface of the tray. The lower surface of the rubber pad is connected to the tray tie, and the upper surface of the rubber pad is in surface-to-surface contact with the board. The corresponding insertion force is applied to the connector. The design value of the power connector insertion force is 8N / pin. The strain change of the power board when the connector is inserted is simulated, and the simulation calculation is submitted. Check the simulation results in the abaqus post-processing and extract the following Fig.10 The principal strain cloud diagram shown in the figure shows that the marked over-standard area is the area with microstrain above 450.

[0074] At the same time, if Fig.11 As shown, a board device layout diagram is obtained, in which the position of the BGA chip is marked, and the principal strain cloud diagram is superimposed and compared with the board device layout diagram, it can be seen that the chip is not placed in the strain exceeding standard area, and the strain placement requirements are met, and the chip position does not need to be adjusted; if there is a device located in the exceeding standard area, the chip is moved to a position that does not overlap with the exceeding standard area at this time, and a buffer pad is also set on the board, and the buffer pad is configured around the power connector, and several buffer pads can be set; the exceeding standard difference of the exceeding standard area is obtained, and the thickness of the buffer pad is set according to the exceeding standard difference, so as to realize the regulation of the strain on the board through the setting of the buffer pad, so that the board and the components on the board meet the strain requirements.

[0075] It should be noted that if Fig.12 As shown, the buffer pad in this embodiment is selected as a rubber pad, and the buffer pad can be pre-configured around the power connector according to the position of the power connector, and the position and thickness of the buffer pad can be further adjusted after the strain result comparison and analysis.

[0076] In a specific embodiment, if the capacitor exceeding the standard in the first direction and the capacitor exceeding the standard in the second direction correspond to capacitors at the same position in the board device layout diagram; move the capacitors at the same position to a position that does not overlap with the first capacitor exceeding the standard area and the second capacitor exceeding the standard area.

[0077] For example, Fig.13 As shown, extract the second side length direction cloud map in the simulation result, where the second side length direction corresponds to the X-axis direction in this embodiment, and the marked area is the second capacitance exceeding the standard; and superimpose and compare the second side length direction cloud map with the board device layout diagram to obtain the following Fig.14 From the overlapped graph shown, it can be seen that the capacitors in the X-axis direction are not placed in the second capacitance exceeding standard area, so the strain requirement is met and there is no need to adjust the capacitor position and direction.

[0078] In this embodiment, the area of ​​the exceeding standard region in the board strain cloud map is calculated. If the area of ​​the exceeding standard region exceeds a preset value, the support of the board structure is adjusted; the adjusted board structure is obtained, and the updated board strain cloud map is obtained again through finite element software simulation.

[0079] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0080] In one embodiment, Fig.15 As shown, a board layout optimization system is provided, which is used to implement the board layout optimization method as described above, and the system includes:

[0081] A simulation unit, used for acquiring a board model, and importing the board model into finite element software to obtain a board strain cloud diagram obtained by finite element software simulation;

[0082] A marking unit, used for marking the area beyond the preset strain range in the board strain cloud diagram as an over-standard area;

[0083] An analysis unit is used to obtain a board device layout diagram, and set the board strain cloud diagram to be superimposed and compared with the board device layout diagram to obtain the exceeding components at a position in the board device layout diagram that overlaps with the projection position of the exceeding area;

[0084] A processing unit is used to move the exceeding-standard device to a position that does not overlap with the exceeding-standard area.

[0085] In a specific embodiment, the simulation unit is also used to obtain a board model, and to mesh the board model in the finite element software to generate a board mesh unit; the boundary parameters and load parameters of the board mesh unit simulation process are set through the finite element software to obtain the board strain cloud map.

[0086] In a specific embodiment, the analysis unit is also used for the board strain cloud map to include a first board cloud map and a second board cloud map; marking the area in the first board cloud map that exceeds the first preset strain value as the chip exceeding the standard area, and marking the area in the second board cloud map that exceeds the second preset strain value as the capacitor exceeding the standard area; obtaining the chip position in the board device layout map, and determining whether the chip position is located in the overlapping projection area of ​​the chip exceeding the standard area and the board device layout map; if so, confirming that the chip is located in the exceeding standard area, and moving the exceeding device to the board position corresponding to the non-exceeding area in the board strain cloud map; or, if not , then the chip is not located in the over-standard area; obtain the capacitance in the board device layout diagram, and set the capacitance to have a first side length and a second side length in the overlapping plane of the board strain cloud map and the board device layout diagram, wherein the first side length is greater than or equal to the second side length; according to the first side length and the second side length of the capacitor, divide the second board cloud map into a first side length direction cloud map and a second side length direction cloud map; combine the first side length direction cloud map with the board device layout diagram for comparative analysis to obtain the over-standard capacitance in the first direction; combine the second side length direction cloud map with the board device layout diagram for comparative analysis to obtain the over-standard capacitance in the second direction.

[0087] In a specific embodiment, the first side length direction cloud map includes a first capacitance exceeding standard area, and the second side length direction cloud map includes a second capacitance exceeding standard area. The analysis unit is also used to set the first side length cloud map and the board device layout map for overlapping comparative analysis to determine whether there is a capacitance exceeding the standard in the first direction at a position overlapping with the first capacitance exceeding standard area in the board device layout map; if so, adjust the capacitance exceeding the standard in the first direction to rotate a first angle or move the capacitance exceeding the standard in the first direction to a position not overlapping with the first capacitance exceeding standard area; or, if not, do not adjust the position of the capacitance exceeding the standard in the first direction.

[0088] In a specific embodiment, the analysis unit is also used to set up an overlapping comparison analysis between the second side length direction cloud map and the board device layout diagram to determine whether there is a capacitor exceeding the second direction at a position overlapping with the second capacitor exceeding the standard area in the board device layout diagram; if so, adjust the capacitor exceeding the second direction to rotate a second angle or move the capacitor exceeding the second direction to a position that does not overlap with the second capacitor exceeding the standard area; or, if not, do not adjust the position of the capacitor exceeding the second direction.

[0089] In a specific embodiment, the processing unit is also used to move the capacitor at the same position to a position that does not overlap with the first capacitor exceeding the standard area and the second capacitor exceeding the standard area if the capacitor exceeding the standard in the first direction and the capacitor exceeding the standard in the second direction correspond to capacitors at the same position in the board device layout diagram.

[0090] In a specific embodiment, the analysis unit is also used to calculate the area of ​​the exceeding standard region in the board strain cloud map. If the area of ​​the exceeding standard region exceeds a preset value, the board structure is supported and adjusted; the adjusted board structure is obtained, and the updated board strain cloud map is obtained again through finite element software simulation.

[0091] For the specific definition of the board layout optimization system, please refer to the definition of the board layout optimization method above, which will not be repeated here. Each module in the above-mentioned board layout optimization system can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0092] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig.16 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store preset strain range data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a board layout optimization method is implemented.

[0093] Those skilled in the art will understand that Fig.16 The structure shown is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0094] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0095] Step 201, obtaining a board model, and importing the board model into finite element software to obtain a board strain cloud diagram obtained by finite element software simulation;

[0096] Step 202, marking the area in the board strain cloud diagram that exceeds the preset strain range as an over-standard area;

[0097] Step 203, obtaining a board device layout diagram, setting the board strain cloud diagram and the board device layout diagram to be superimposed for comparative analysis, so as to obtain the exceeding components at the position overlapping with the projection position of the exceeding area in the board device layout diagram;

[0098] Step 204: Move the exceeding-standard device to a position that does not overlap with the exceeding-standard area.

[0099] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0100] The board model is obtained, and the board model in the finite element software is meshed to generate board mesh units; the boundary parameters and load parameters of the board mesh unit simulation process are set through the finite element software to obtain the board strain cloud diagram.

[0101] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0102] The board strain cloud map includes a first board cloud map and a second board cloud map; the area in the first board cloud map that exceeds the first preset strain value is marked as a chip exceeding the standard area, and the area in the second board cloud map that exceeds the second preset strain value is marked as a capacitor exceeding the standard area; the chip position in the board device layout map is obtained, and it is determined whether the chip position is located in the overlapping projection area of ​​the chip exceeding the standard area and the board device layout map; if so, it is confirmed that the chip is located in the exceeding standard area, and the exceeding device is moved to the board position corresponding to the non-exceeding area in the board strain cloud map; or, if not, the chip is not located in the exceeding standard area area; obtaining the capacitor in the board device layout diagram, setting the capacitor to have a first side length and a second side length in the overlapping plane of the board strain cloud map and the board device layout diagram, wherein the first side length is greater than or equal to the second side length; dividing the second board cloud map into a first side length direction cloud map and a second side length direction cloud map according to the first side length and the second side length of the capacitor; combining the first side length direction cloud map with the board device layout diagram for comparative analysis to obtain the capacitance exceeding the standard in the first direction; combining the second side length direction cloud map with the board device layout diagram for comparative analysis to obtain the capacitance exceeding the standard in the second direction.

[0103] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0104] The first side length direction cloud map includes a first capacitance exceeding standard area, and the second side length direction cloud map includes a second capacitance exceeding standard area. The first side length cloud map is set to overlap and compare with the board device layout diagram for analysis to determine whether there is a capacitance exceeding standard in the first direction at a position overlapping with the first capacitance exceeding standard area in the board device layout diagram; if so, the capacitance exceeding standard in the first direction is adjusted to rotate a first angle or moved to a position not overlapping with the first capacitance exceeding standard area; or, if not, the position of the capacitance exceeding standard in the first direction is not adjusted.

[0105] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0106] Set the second side length direction cloud map to overlap with the board device layout diagram for comparative analysis to determine whether there is a capacitor exceeding the second direction in the overlapping position with the second capacitor exceeding the standard area in the board device layout diagram; if so, adjust the capacitor exceeding the second direction to rotate the second angle or move the capacitor exceeding the second direction to a position that does not overlap with the second capacitor exceeding the standard area; or, if not, do not adjust the position of the capacitor exceeding the second direction.

[0107] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0108] If the capacitor exceeding the standard in the first direction and the capacitor exceeding the standard in the second direction correspond to capacitors at the same position in the board device layout diagram; move the capacitors at the same position to a position that does not overlap with the first capacitor exceeding the standard area and the second capacitor exceeding the standard area.

[0109] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0110] The area of ​​the exceeding area in the board strain cloud diagram is calculated. If the area of ​​the exceeding area exceeds a preset value, the board structure is supported and adjusted; the adjusted board structure is obtained, and an updated board strain cloud diagram is obtained again through finite element software simulation.

[0111] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0112] Step 301, obtaining a board model, and importing the board model into finite element software to obtain a board strain cloud diagram obtained by finite element software simulation;

[0113] Step 302, marking the area in the board strain cloud map that exceeds the preset strain range as an over-standard area;

[0114] Step 303, obtaining a board device layout diagram, setting the board strain cloud diagram and the board device layout diagram to be superimposed for comparative analysis, so as to obtain the exceeding components at the position overlapping with the projection position of the exceeding area in the board device layout diagram;

[0115] Step 304: Move the exceeding-standard device to a position that does not overlap with the exceeding-standard area.

[0116] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0117] The board model is obtained, and the board model in the finite element software is meshed to generate board mesh units; the boundary parameters and load parameters of the board mesh unit simulation process are set through the finite element software to obtain the board strain cloud diagram.

[0118] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0119] The board strain cloud map includes a first board cloud map and a second board cloud map; the area in the first board cloud map that exceeds the first preset strain value is marked as a chip exceeding the standard area, and the area in the second board cloud map that exceeds the second preset strain value is marked as a capacitor exceeding the standard area; the chip position in the board device layout map is obtained, and it is determined whether the chip position is located in the overlapping projection area of ​​the chip exceeding the standard area and the board device layout map; if so, it is confirmed that the chip is located in the exceeding standard area, and the exceeding device is moved to the board position corresponding to the non-exceeding area in the board strain cloud map; or, if not, the chip is not located in the exceeding standard area area; obtaining the capacitor in the board device layout diagram, setting the capacitor to have a first side length and a second side length in the overlapping plane of the board strain cloud map and the board device layout diagram, wherein the first side length is greater than or equal to the second side length; dividing the second board cloud map into a first side length direction cloud map and a second side length direction cloud map according to the first side length and the second side length of the capacitor; combining the first side length direction cloud map with the board device layout diagram for comparative analysis to obtain the capacitance exceeding the standard in the first direction; combining the second side length direction cloud map with the board device layout diagram for comparative analysis to obtain the capacitance exceeding the standard in the second direction.

[0120] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0121] The first side length direction cloud map includes a first capacitance exceeding standard area, and the second side length direction cloud map includes a second capacitance exceeding standard area. The first side length cloud map is set to overlap and compare with the board device layout diagram for analysis to determine whether there is a capacitance exceeding standard in the first direction at a position overlapping with the first capacitance exceeding standard area in the board device layout diagram; if so, the capacitance exceeding standard in the first direction is adjusted to rotate a first angle or moved to a position not overlapping with the first capacitance exceeding standard area; or, if not, the position of the capacitance exceeding standard in the first direction is not adjusted.

[0122] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0123] Set the second side length direction cloud map to overlap with the board device layout diagram for comparative analysis to determine whether there is a capacitor exceeding the second direction in the overlapping position with the second capacitor exceeding the standard area in the board device layout diagram; if so, adjust the capacitor exceeding the second direction to rotate the second angle or move the capacitor exceeding the second direction to a position that does not overlap with the second capacitor exceeding the standard area; or, if not, do not adjust the position of the capacitor exceeding the second direction.

[0124] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0125] If the capacitor exceeding the standard in the first direction and the capacitor exceeding the standard in the second direction correspond to capacitors at the same position in the board device layout diagram; move the capacitors at the same position to a position that does not overlap with the first capacitor exceeding the standard area and the second capacitor exceeding the standard area.

[0126] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0127] The area of ​​the exceeding area in the board strain cloud diagram is calculated. If the area of ​​the exceeding area exceeds a preset value, the board structure is supported and adjusted; the adjusted board structure is obtained, and an updated board strain cloud diagram is obtained again through finite element software simulation.

[0128] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0129] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A board layout optimization method, characterized in that: The method comprises: Obtaining a board model, and importing the board model into finite element software to obtain a board strain cloud diagram obtained by finite element software simulation; Mark the area in the board strain cloud diagram that exceeds the preset strain range as an over-standard area; Obtain a board device layout diagram, set the board strain cloud diagram and the board device layout diagram to be superimposed for comparative analysis, so as to obtain the exceeding components at a position in the board device layout diagram that overlaps with the projection position of the exceeding area; Move the exceeding-standard device to a position that does not overlap with the exceeding-standard area.

2. The board layout optimization method according to claim 1, characterized in that: The method further comprises: Obtaining a board model, and meshing the board model in the finite element software to generate board mesh units; The boundary parameters and load parameters of the board grid unit simulation process are set by the finite element software to obtain the board strain cloud diagram.

3. The board layout optimization method according to claim 1 or 2, characterized in that: The method further comprises: The board strain cloud map includes a first board strain cloud map and a second board strain cloud map; Mark the area in the first card cloud map that exceeds the first preset strain value as a chip exceeding the standard area, and mark the area in the second card cloud map that exceeds the second preset strain value as a capacitor exceeding the standard area; Obtain the chip position in the board device layout diagram, and determine whether the chip position is located in the overlapping projection area of ​​the chip over-standard area and the board device layout diagram; If yes, confirm that the chip is located in the exceeded area, and move the exceeded device to the board position corresponding to the non-exceeded area in the board strain cloud diagram; Alternatively, if no, the chip is not located in the excess area; Acquire a capacitor in the board device layout diagram, and set the capacitor to have a first side length and a second side length in the overlapping plane of the board strain cloud diagram and the board device layout diagram, wherein the first side length is greater than or equal to the second side length; According to the first side length and the second side length of the capacitor, dividing the second board cloud map into a first side length direction cloud map and a second side length direction cloud map; Comparing and analyzing the first side length direction cloud map with the board device layout map to obtain the excess capacitance in the first direction; The second side length direction cloud map is compared and analyzed with the board device layout map to obtain the excess capacitance in the second direction.

4. The board layout optimization method according to claim 3, characterized in that: The first side length direction cloud map includes a first capacitance exceeding standard area, the second side length direction cloud map includes a second capacitance exceeding standard area, and the method further includes: Setting the first side length cloud map to overlap and compare with the board device layout map for analysis, and determining whether there is a capacitance exceeding the first direction at a position overlapping with the first capacitance exceeding the standard region in the board device layout map; If so, adjusting the capacitor exceeding the standard in the first direction to rotate to a first angle or moving the capacitor exceeding the standard in the first direction to a position not overlapping with the capacitor exceeding the standard region; Alternatively, if it does not exist, the position of the capacitance exceeding the limit in the first direction is not adjusted.

5. The board layout optimization method according to claim 4, characterized in that: The method further comprises: Setting the second side length direction cloud map to overlap and compare with the board device layout map for analysis, and determining whether there is a capacitance exceeding the second direction at a position overlapping with the second capacitance exceeding the standard area in the board device layout map; If so, adjusting the second direction excessive capacitance to rotate to a second angle or moving the second direction excessive capacitance to a position that does not overlap with the second capacitance excessive area; Alternatively, if it does not exist, the position of the capacitance exceeding the limit in the second direction is not adjusted.

6. The board layout optimization method according to claim 5, characterized in that: The method further comprises: If the capacitance exceeding the standard in the first direction and the capacitance exceeding the standard in the second direction correspond to capacitance at the same position in the board device layout diagram; The capacitor at the same position is moved to a position that does not overlap with the first capacitance exceeding standard region and the second capacitance exceeding standard region.

7. The board layout optimization method according to claim 1 or 2, characterized in that: The method further comprises: Calculating the area of ​​the exceeding-standard region in the board strain cloud diagram, and if the area of ​​the exceeding-standard region exceeds a preset value, performing support adjustment on the board structure; The adjusted board structure is obtained, and the updated board strain cloud diagram is obtained again through finite element software simulation.

8. A board layout optimization system, used to implement the board layout optimization method according to any one of claims 1 to 7, characterized in that: The system comprises: A simulation unit, used for acquiring a board model, and importing the board model into finite element software to obtain a board strain cloud diagram obtained by finite element software simulation; A marking unit, used for marking the area beyond the preset strain range in the board strain cloud diagram as an over-standard area; An analysis unit is used to obtain a board device layout diagram, and set the board strain cloud diagram to be superimposed and compared with the board device layout diagram to obtain the exceeding components at a position in the board device layout diagram that overlaps with the projection position of the exceeding area; A processing unit is used to move the exceeding-standard device to a position that does not overlap with the exceeding-standard area.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images