Layout dependency effect measurement method and device

Abstract

The invention provides a method for measuring a layout dependency effect, which can determine a sequential relationship corresponding to an LDE influence factor according to reference layout simulation data and modified layout simulation data. The time sequence relation of the LED influence factors can completely reflect the influence of the LED on a circuit under a specific process, has high availability, and is beneficial for a designer to design and optimize a chip layout, improve the design reliability and shorten the design time.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method and device for measuring layout dependency effects. Background Art

[0002] With the advancement of integrated circuit manufacturing technology, the distance between semiconductor devices is getting closer and closer. These devices interact with each other due to manufacturing physical stress. This interaction between devices is called layout dependent effects (LDE). Layout dependent effects usually affect the performance of semiconductor devices. Due to the influence of layout dependent effects, the actual performance of semiconductor devices will deviate greatly from the intrinsic performance of the device itself. Since the reference performance in the standard cell library is more easily affected by the adjacent environment, and there is a greater performance difference between the actual performance of the tape-out test and the reference performance recorded in the standard cell library, the impact of layout dependent effects on standard cells, analog circuits, and IP circuits has become increasingly important in 12nm and more advanced processes.

[0003] In the prior art, manufacturers only provide very rough LDE parameters. For example, manufacturers generally only provide rough trends of MOS tube current as various LDE parameters change. However, in MOS tube circuit design, the MOS tube switch follows its flip characteristic curve, which is quite different from its current Idsat curve. Therefore, it is very difficult for circuit designers and layout designers to complete excellent analog circuits, static RAM and IP circuit designs. Summary of the invention

[0004] Based on the existing technology, the present application provides a method and device for measuring layout dependency effects, which can measure the timing relationship of LDE influencing factors so that designers can design chips according to the timing relationship of the LDE influencing factors and improve the reliability of the design.

[0005] The present application provides a method for measuring LDE, including:

[0006] Perform simulation test according to the reference layout of the test circuit to obtain reference layout simulation data;

[0007] Performing simulation test according to the modified layout of the test circuit to obtain simulation data of the modified layout; wherein the modified layout of the test circuit is obtained by modifying the LDE influence factor based on the reference layout;

[0008] The timing relationship corresponding to the LDE influencing factor is determined according to the reference layout simulation data and the modified layout simulation data.

[0009] The present application also provides a measuring device for LDE, the measuring device comprising:

[0010] A simulation test unit, used for performing simulation test according to a reference layout for LDE elimination of a test circuit to obtain simulation data of the reference layout for LDE elimination; performing simulation test according to a modified layout of the test circuit to obtain simulation data of the modified layout; wherein the modified layout of the test circuit is obtained by modifying a certain LDE influence factor on the basis of the reference layout for LDE elimination; and an LDE timing generation unit, used for determining the timing relationship corresponding to the LDE influence factor according to the obtained simulation data of the above two layouts.

[0011] The LDE measurement method and device provided in the present application respectively simulate and test the reference layout with LDE eliminated and the modified layout with LDE influencing factors added, and compare the simulation data based on the above two layouts to determine the timing relationship of the LDE influencing factors. The timing relationship of the LDE influencing factors can fully reflect the influence of LDE on the circuit under a specific process. Compared with the small amount of discrete data or the Idsat characteristic curve of the static MOS tube provided by the manufacturer, the timing relationship of the LDE influencing factors is highly usable, which helps designers design and optimize the chip layout, improve the reliability of the design, and shorten the design time. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram showing changes in various LDE influencing factors in an embodiment;

[0013] Figure 2 A schematic diagram of a test circuit layout in one embodiment;

[0014] Figure 3 is a flow chart of a method for measuring layout dependency effects in one embodiment;

[0015] Figure 4 is a flow chart of a method for measuring layout dependence effect in another embodiment;

[0016] Figure 5 A comparison diagram of the LDE impact factor before and after modification in an embodiment;

[0017] Figure 6 is a flow chart of a method for measuring process deviation in one embodiment;

[0018] Figure 7 A schematic diagram of the time sequence relationship of LDE impact factors in one embodiment;

[0019] Figure 8 A schematic diagram of the structure of an LDE measuring device in one embodiment;

[0020] Fig. 9 FIG. 4 is a schematic diagram of the structure of an LDE measuring device in another embodiment. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0023] It should be understood that the term "and / or" used in this article is only a description of the same field of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0024] It should be understood that, although the terms first, second, third, etc. may be used to describe preset ranges, etc. in the embodiments of the present application, these preset ranges should not be limited to these terms. These terms are only used to distinguish preset ranges from each other. For example, without departing from the scope of the embodiments of the present application, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0025] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0026] With the advancement of integrated circuit manufacturing technology, the distance between semiconductor devices on the chip is getting closer and closer. These devices affect each other due to manufacturing physical stress. This mutual influence between devices is called layout dependent effect (LDE). Layout dependent effect usually affects the performance of semiconductor devices. Therefore, in circuit layout design, how to reduce layout dependent effect becomes an issue worthy of attention.

[0027] Among them, semiconductor devices MOS tubes (such as CMOS transistors) are widely used in microprocessors, microcontrollers, analog circuits (such as image sensors, data converters and transceivers for communication, etc.), static memories and other digital logic circuits.

[0028] LDE includes shallow trench isolation effect (STI), well proximity effect (WPE), length of diffusion region effect (LOD), gate spacing effect (PSE), and diffusion region / active region spacing effect (OSE). Among them, STI is a physical stress effect that isolates adjacent semiconductor devices. It uses highly anisotropic reactive ion etching to cut an almost vertical groove on the surface. The sidewall of the groove is oxidized, and then polysilicon is deposited to fill the remaining part of the groove. The pressure brought by STI has an important impact on device performance, especially the current Idsat and threshold voltage Vth. STI is usually used in MOS tube process nodes of 250 nanometers and smaller. STI can change the speed of the transistor at the edge by ±30%. The different distances from STI to different MOS tubes have different effects on the performance of the device, which is called LOD. The hydrazine proximity effect refers to the effect of device parameter deviation caused by the device being close to the hydrazine (Well). It is mainly due to the different particle concentrations caused by light refraction, which changes the threshold voltage Vth of the transistor and affects the performance of the device. WPE can change the speed of the transistor by ±10%. The gate spacing effect refers to the effect of the spacing of the Poly on the performance of the device.

[0029] Due to the influence of LDE, the actual performance of MOS tubes may deviate from the reference performance recorded in the standard cell library. The reference performance of standard cells in the standard cell library is more susceptible to fluctuations caused by the adjacent environment, and there is a greater performance difference between the actual performance of the tape-out test and the reference performance recorded in the standard cell library. Therefore, in advanced processes above 12nm, the impact of LDE on circuit design such as standard cells, analog circuits, and IP circuits has become increasingly important.

[0030] In the prior art, foundries only provide very rough LDE parameters. For example, foundries generally only provide rough trends of MOS tube current changes with LDE. The LDE parameters provided by foundries are incomplete and highly discrete. Therefore, it is very difficult for circuit designers and layout designers to complete excellent analog circuits, static RAM and IP circuit designs.

[0031] Based on the above existing technology, the present application aims to provide a LDE measurement method and a measurement device, which can obtain the timing relationship corresponding to the LDE influencing factor based on the layout of the circuit design. The timing relationship of the LDE influencing factor can fully reflect the timing change and has high usability and reliability. In addition, the timing curve of the LDE influencing factor can be fed back to the designer to guide the design and optimization of circuit design, layout design, etc., thereby improving the reliability of the circuit design.

[0032] In order to better illustrate the technical solution of the present application, the process of integrated circuit design is first briefly described. Part of the usual circuit design process involves logic design, and then a circuit design is formed based on the logic design. Among them, the layout of the circuit design describes the features that will eventually be presented on the integrated circuit device, which is the designer converting the designed, simulated and optimized circuit into a series of geometric figures. The circuit design may include at least one functional unit, each functional unit is used to implement various logical functions, for example, the designer can use standard cells in the standard cell library to implement the design of various functional units. Each functional unit generally includes a layout unit (physical representation), and the "layout unit" of the functional unit describes the transistors and their interconnections contained in the particular functional unit, as well as the features of other functional and non-functional structures. The layout units corresponding to the multiple functional units of the circuit design will be used in the final layout.

[0033] In the integrated circuit design process, after completing the design of the above-mentioned final layout, the designer also needs to perform physical verification of the above-mentioned final layout. The physical verification of the layout includes circuit layout comparison check (LVS, Layout VsSchematic), design rule check (DRC, Design Rule Checking), electrical rule check (ERC, Electrical Rule Checking), etc. Among them, the design rule check is an important part of the physical verification of the layout. The design rule check includes checking whether the connection spacing, connection width, etc. meet the process requirements. The design rule check is used to ensure that the layout data can be produced. If all checks and verifications are correct, the final layout can be passed to the manufacturer for mask manufacturing.

[0034] In the process of circuit design, if there is at least one layout feature that is different between two sets of layouts, they are considered to be two different sets of circuit designs. Among them, the above-mentioned layout features may include LDE influencing factors, and the LDE influencing factors include but are not limited to one or more of shallow trench isolation effect, hydrazine proximity effect, diffusion region length effect, gate spacing effect, and diffusion region / active region spacing effect. For example, if the value of the LDE influencing factor of at least one "layout unit" in the two sets of layouts is different, the two sets of layouts are considered to be different. The embodiment of the present application can obtain multiple modified layouts by modifying the value of a certain LDE influencing factor in the layout multiple times, and obtain the timing relationship of the corresponding LDE influencing factors based on the simulation data of the multiple modified layouts and the simulation data of the layout with all LDE influencing factors eliminated.

[0035] Figure 1 Examples are given to illustrate the changes in LDE impact factors, where (a) illustrates the changes in OSE impact factors. When the values ​​of the horizontal spacing OD Space W or the vertical spacing OD Space L in the layout change, it is considered that the layout has changed. For example, the value of OD Space W increases or decreases along the W direction, or the value of OD Space L increases or decreases along the L direction. (b) illustrates the changes in LOD impact factors. When the values ​​of the diffusion area lengths SA and SB in the layout change, it is considered that the layout has changed. (c) illustrates the changes in WPE impact factors. When the distance SC between the device and the edge of the hydrazine in the layout changes, it is considered that the layout has changed. In all the examples of LDE impact factors mentioned above, only one item will change at a time, and there will be no simultaneous changes.

[0036] In order to achieve the timing measurement of the LDE impact factor, the present application provides a test circuit, which may include a ring oscillator and at least one functional unit, wherein the ring oscillator includes N inverters connected in series end to end to generate an oscillation frequency. The ring oscillator can be connected to at least one functional unit, and the functional unit is used to implement a specific logic function, including but not limited to a logic gate (such as an inverter), a register, a memory, etc. In this way, the output signal of the test circuit is a delay of an oscillation, so that the test circuit can use the oscillation frequency to characterize the current Idsat of the transistor.

[0037] like Figure 2 As shown, the layout of the test circuit may include multiple special layout units, wherein the special layout units respectively correspond to a functional unit of the test circuit, wherein the special layout units correspond to the ring oscillator N times, wherein each inverter of the ring oscillator can correspond to a special layout unit, and the layout design of the ring oscillator is formed by connecting the special layout units N times.

[0038] Optionally, the reference layout of the test circuit is a layout that eliminates the influence of LDE (called a golden layout). Generally, each LDE influence factor can change with its value, and when the value of the LDE influence factor reaches a threshold, the LDE influence factor tends to be stable and unchanged. The embodiment of the present application can determine the golden layout of the above-mentioned test circuit (i.e., the above-mentioned reference layout that eliminates the LDE influence factor) according to the threshold at which each LDE influence factor tends to be stable. Specifically, the embodiment of the present application can obtain the threshold of all LDE influence factors, and design the above-mentioned reference layout according to the threshold of all LDE influence factors, so that the value of each LDE influence factor in the reference layout is equal to the corresponding threshold. Furthermore, in the measurement process of the timing relationship of the LDE influence factor, the value of the LDE influence factor can be adjusted within the threshold range of the corresponding LDE influence factor.

[0039] Further, due to the increasing influence of resistance and capacitance (RC) under advanced technology, in the CMOS circuit layout design, the layout change of metal wires will greatly affect the flip delay of CMOS devices, and the environment in which CMOS devices are located has a very complex impact on their performance. Therefore, there is a great difference between the characteristic curve of the transistor and the real flip of the transistor in the CMOS layout, and theoretical data is difficult to support the actual design. Based on this, the reference layout of the test circuit can also be a layout that eliminates the influence of LDE and has a fixed resistance and capacitance, that is, in the measurement process of the timing relationship of the LDE influence factor, the reference layout of the test circuit in the embodiment of the present application and the resistance and capacitance of the modified layout remain unchanged. Thus, the embodiment of the present application can completely avoid the influence of the advanced process RC effect during the test process, and improve the reliability and availability of the test data.

[0040] The above-mentioned reference layout of the embodiment of the present application can be a layout that meets the design rule checking (DRC, Design Rule Checking) and tape-out conditions. The designer can deliver the reference layout to the manufacturer for tape-out, and perform real tests based on the test circuit after the tape-out to obtain real test data, so as to assist the early circuit design according to the real test data. For details, please refer to the description below.

[0041] Based on the above test circuit and reference layout design, the present application can modify at least one LDE impact factor of the reference layout corresponding to the test circuit, and determine the timing relationship of the LDE impact factor based on the simulation data of the reference layout and at least one modified layout. Figure 3 As shown, the present application provides a LDE measurement method 300 which may include:

[0042] S310, performing simulation test according to the reference layout of the test circuit to obtain reference layout simulation data;

[0043] The layout of the reference layout of the test circuit is as follows: Figure 2 As shown, the reference layout can be a golden layout that eliminates the influence of LDE. In the simulation test process, the test circuit is simulated by enabling the input signal of the test circuit, and the output signal flip of the test circuit based on the reference layout is obtained to obtain the delay required for one oscillation, that is, the reference layout simulation data.

[0044] S320. Perform simulation test according to the modified layout of the test circuit to obtain simulation data of the modified layout; wherein the modified layout of the test circuit is obtained by modifying the LDE influencing factor on the basis of the reference layout, and the above LDE influencing factor can be any one of the shallow trench isolation effect, the hydrazine proximity effect, the diffusion region / active region spacing effect, the diffusion region length effect, and the gate spacing effect.

[0045] The present application can modify at least one layout unit in the reference layout according to the LDE impact factor, obtain a corresponding modified layout, and perform simulation test on the modified layout. During the simulation test, the test circuit is simulated by enabling the input signal of the test circuit, and the output signal flip of the test circuit based on the modified layout is obtained, and the delay required for one oscillation is obtained, that is, the modified layout simulation data.

[0046] S330 , determining a timing relationship corresponding to the LDE influencing factor according to the reference layout simulation data and the modified layout simulation data.

[0047] The time series relationship corresponding to the LDE impact factor can be the time series relationship of the simulation data changing with the LDE impact factor. Specifically, the application can record the corresponding relationship between the value of the LDE impact factor and the corresponding simulation data, and determine the time series relationship corresponding to the LDE impact factor based on the corresponding relationship.

[0048] Furthermore, the embodiment of the present application can also calculate the ratio of the modified layout simulation data to the reference layout simulation data, and determine the timing relationship corresponding to the LDE influence factor based on the ratio and the corresponding value of the LDE influence factor.

[0049] Optionally, the timing relationship corresponding to the LDE impact factor can be presented in a variety of ways such as a timing curve, a bar graph or a list, which is not specifically limited here. Further, the timing relationship corresponding to the LDE impact factor can be presented to the designer in a visual manner, so that the designer can design and optimize the circuit design according to the timing relationship, thereby improving the reliability of the circuit design.

[0050] The method for measuring the LDE of a chip provided in the present application performs simulation tests on a reference layout and a modified layout with an LDE influencing factor added, and determines the timing relationship of the LDE influencing factor based on the simulation data of the reference layout and the simulation data of the modified layout. The timing relationship of the LDE influencing factor can fully reflect the influence of LDE on the circuit under a specific process. Compared with a small amount of discrete data or a characteristic curve of a static MOS tube provided by a manufacturer, the timing curve of the LDE influencing factor is highly usable, which helps designers design and optimize the chip layout, improves the reliability of the design, and shortens the design time.

[0051] In an optional embodiment, the embodiment of the present application can adjust any LDE impact factor that is desired to be tested, so as to accurately demonstrate the impact of the LDE impact factor on the circuit under the process conditions. Therefore, the embodiment of the present application may also include a layout modification step, which can obtain the current LDE impact factor, and modify the reference layout of the test circuit n times according to the current LDE impact factor, obtain n modified layouts, and perform simulation tests based on the reference layout and the modified layout, respectively, to determine the timing relationship of the LDE impact factor based on the results of the simulation test; wherein n is a positive integer greater than or equal to 1. The method of modifying the current LDE impact factor can be found in Figure 1 In the example, the current LDE impact factor is modified by adjusting the values ​​of the parameters related to the current LDE impact factor.

[0052] like Figure 4 As shown, the measurement method 400 of the embodiment of the present application may include:

[0053] S410, performing simulation test according to the reference layout of the test circuit to obtain reference layout simulation data;

[0054] The specific execution process of this test step can be found in Figure 3 The description of the illustrated embodiment will not be repeated here.

[0055] S420, obtaining the current LDE impact factor; wherein the current LDE impact factor may be any one of shallow trench isolation effect, hydrazine proximity effect, diffusion region length effect, gate spacing effect, and diffusion region / active region spacing effect. The designer may select any LDE impact factor for measurement according to the requirements.

[0056] S430, adjusting the value of the current LDE impact factor to obtain a modified layout;

[0057] Optionally, the modified layout is obtained by modifying the current LDE impact factor in at least one special layout unit of the reference layout. For example, the current LDE impact factor may be added to all special layout units of the reference layout to obtain the modified layout.

[0058] S440, perform simulation test according to the modified layout to obtain simulation data of the modified layout, and then repeat step S430 until n (n is a positive integer greater than or equal to 1) modifications are completed. Optionally, the embodiment of the present application can modify the reference layout in a manner of increasing or decreasing the value of the current LDE impact factor to obtain n versions of the modified layout. For example, the present application can modify the reference layout n times in a manner of increasing the value of the current LDE impact factor. Figure 5 As shown, Figure 5 A comparison of one of the modified layouts with the reference layout is shown, where Figure 5 The layout with LOD value A3B3 is the modified layout, and the layout with LOD value A9B9 is the reference layout that eliminates all LDE influencing factors.

[0059] Furthermore, for different LDE impact factors, the value of n can be different or the same, and is not specifically limited here. The embodiment of the present application can determine the number of modifications and the value range of the current LDE impact factor according to the value of the current LDE impact factor in the reference layout (i.e., the gloden layout) of the test circuit. Figure 5 As shown, the value of the reference layout is A9B9, then the value of the parameter in the modified layout can be A less than or equal to 9, B less than or equal to 9, where A and B represent parameters SA and SB respectively. Furthermore, the capacitance and resistance are kept unchanged during the above n modifications to avoid the RC effect of the advanced process affecting the timing measurement of the LDE influencing factor.

[0060] S450, determining the timing relationship corresponding to the current LDE impact factor according to the reference layout simulation data and the modified layout simulation data. As described above, the embodiment of the present application can record the corresponding relationship between at least one modified layout simulation data and the reference layout simulation data and the corresponding LDE impact factor, so as to determine the timing relationship corresponding to the LDE impact factor.

[0061] For example, the current LDE influencing factor may be LOD. The reference layout of the test circuit may be a layout in which the LOD influencing factor is eliminated, that is, in the embodiment of the present application, the SA and / or SB of the special layout unit may be set, and a simulation test may be performed based on the reference layout to obtain reference layout simulation data.

[0062] Then, the embodiment of the present application can modify the reference layout n times in a way that the numerical value of LOD increases, so as to obtain the corresponding modified layout. Specifically, in the first modification, each layout unit SA and / or SB in the reference layout in the test circuit can be changed to obtain the first modified layout, and then a simulation test can be performed based on the first modified layout to obtain the corresponding first modified layout simulation result, and the corresponding relationship between the simulation result and the current LOD value is recorded. After completing the first simulation, the LOD value can be increased to obtain the second modified layout. Afterwards, a simulation test can be performed based on the second modified layout to obtain the corresponding second modified layout simulation result, and the corresponding relationship between the simulation result and the current LOD value is recorded...Continue to adjust the LOD value to obtain the nth modified layout, and then a simulation test can be performed based on the nth modified layout to obtain the corresponding nth modified layout simulation result, and the corresponding relationship between the simulation result and the current LOD value is recorded. After completing the nth modification test, the timing relationship of LOD can be determined according to the simulation result of the reference layout and the simulation results of the n modified layouts.

[0063] The above measurement process can be performed on a PMOS tube in the test circuit, or it can be performed on an NMOS tube in the test circuit. The LOD timing relationship of the NMOS tube or the PMOS tube in the test circuit is obtained by the above measurement method, such as Figure 7 As shown, (a) is the LOD timing relationship diagram of the PMOS tube, and (b) is the LOD timing relationship diagram of the NMOS tube; A2-A9 in the figure represent the values ​​of SA, B1-B9 represent the values ​​of SB, the RO frequency (freq ratio) in the figure represents the ratio of the simulation data of the modified layout to the simulation data of the reference layout, and A9B9 in the figure are the simulation data corresponding to the reference layout. It can be seen that the timing relationship of the LDE influencing factor provided in the embodiment of the present application can fully reflect the influence of LDE on the circuit under a specific process. Compared with the small amount of discrete data or the characteristic curve of the static MOS tube provided by the manufacturer, the timing curve of the LDE influencing factor is highly usable, which helps designers to design and optimize the chip layout, improve the reliability of the design, and shorten the design time.

[0064] Furthermore, after completing the measurement of the time series relationship of one LDE influencing factor, the embodiment of the present application may also measure the time series relationship of other LDE influencing factors. Specifically, the above method also includes:

[0065] After determining the timing relationship corresponding to the current LDE impact factor, the current LDE impact factor is switched. Specifically, after determining the timing relationship of the current LDE impact shadow, the type of LDE impact factor can be switched, and the updated current LDE impact factor is executed. Figure 3Or the measurement method shown in Example 4.

[0066] Following the above example, after completing the timing relationship measurement of LOD, the embodiment of the present application can also measure the timing relationship of OSE, PSE or WPE, etc. The specific measurement method can refer to Figure 4 The description of the illustrated embodiment will not be repeated here.

[0067] Of course, in other embodiments, the embodiments of the present application can also simultaneously obtain multiple LDE impact factors, and implement layout modification steps according to the multiple LDE impact factors, obtain n modified layouts corresponding to each LDE impact factor, and perform simulation tests based on the reference layout and the modified layout corresponding to the corresponding LDE impact factor, so as to determine the timing relationship of the LDE impact factors based on the results of the simulation tests. The specific measurement process of each LDE impact factor can be found in Figure 3 or Figure 4 In this way, by adjusting multiple LDE impact factors at the same time, the process of measuring the timing relationship of the LDE impact factors can be accelerated.

[0068] In one embodiment, in the traditional measurement method, circuit engineers and layout engineers only design circuits based on simulation data, that is, circuit engineers and layout engineers complete the layout of all LDE influencing factors and simulate to obtain circuit data and make a rough judgment. Since the traditional measurement method does not take into account the process deviation in the tape-out process, it is difficult to evaluate the impact of process deviation on the timing relationship of LDE influencing factors.

[0069] Based on this, Figure 6 As shown, the embodiment of the present application can also tape out the reference layout and modified layout that meet the DRC rules and tape-out conditions, and evaluate the process deviation based on the actual test data of the tape-out. Specifically, the measurement method 600 of the embodiment of the present application can also include:

[0070] S610, obtaining real test data after tape-out based on the reference layout and the modified layout;

[0071] The reference layout and modified layout of the embodiment of the present application can be layouts that meet the design rule check and tape-out conditions. The designer can deliver the reference layout and modified layout to the manufacturer for tape-out, and conduct real tests based on the test circuit after tape-out to obtain real test data. Among them, the test based on the test circuit after tape-out is specifically to enable the input signal of the test circuit, obtain the output signal flip of the test circuit, and obtain the delay required for one oscillation, that is, the real test data.

[0072] S620: Compare the actual test data with the reference layout simulation data to obtain the process deviation.

[0073] The embodiment of the present application obtains real test data through on-chip testing after tape-out by using the production rules of the process of the manufacturer, and obtains the real deviation between the real test data and the simulation data, so that the process deviation can be fed back to the circuit design stage, which is beneficial for circuit designers and layout designers to optimize the chip layout.

[0074] like Figure 8 As shown, the present application also provides a measurement device for LDE, which can be an EDA tool. The measurement tool can include a simulation test unit 810 and an LDE timing generation unit 820, wherein:

[0075] The simulation test unit 810 is used to perform simulation test according to the reference layout of the test circuit to obtain reference layout simulation data; perform simulation test according to the modified layout of the test circuit to obtain modified layout simulation data; wherein the modified layout of the test circuit is obtained by modifying the LDE influence factor based on the reference layout. The LDE timing generation unit 820 is used to determine the timing relationship corresponding to the LDE influence factor according to the reference layout simulation data and the modified layout simulation data. wherein the reference layout is a layout that eliminates all LDE influence factors. the above-mentioned reference layout can be the reference layout determined according to the threshold value of all LDE influence factors.

[0076] In one embodiment, Fig. 9 As shown, the LDE measurement device of the present application may include a simulation test unit 910, an LDE timing generation unit 920 and a layout modification unit 930. The functions of the simulation test unit 910 and the LDE timing generation unit 920 are as follows: Figure 8 As shown in the embodiment. The layout modification unit 930 is used to obtain the current LDE impact factor, and to modify the reference layout n times by adjusting the current LDE impact factor to obtain a modified layout, so as to determine the timing relationship corresponding to the current LDE impact factor according to the simulation data of the modified layout; wherein n is a positive integer greater than or equal to 1. Specifically, the layout modification unit 930 can receive a modified value of the LDE impact factor input by a user, and modify the reference layout in a manner of increasing or decreasing the value of the current LDE impact factor to obtain the modified layout. For example, through the LDE impact factor selection box provided by the measuring device, the layout modification unit can receive a request for selecting the current LDE impact factor input by the user, and output the modified layout based on the modified value of the current LDE impact factor input by the user through the LDE impact factor edit box provided by the measuring device.

[0077] In one embodiment, the LDE influencing factors include one or more of shallow trench isolation effect, hydrazine proximity effect, diffusion region length effect, gate spacing effect, and diffusion region / active region spacing effect; the above-mentioned layout modification unit 930 is also used to switch the current LDE influencing factor after determining the timing relationship corresponding to the current LDE influencing factor. For example, after determining the timing relationship corresponding to the current LDE influencing factor, the layout modification unit can receive a user input request to switch the current LDE influencing factor, and switch the current LDE influencing factor based on the request. Afterwards, the layout modification unit 930 can modify the corresponding layout according to the modified value of the LDE influencing factor it receives to obtain a modified layout.

[0078] In another embodiment, the layout modification unit 930 is also used to simultaneously obtain multiple LDE impact factors, and implement layout modification steps according to the multiple LDE impact factors, respectively, to obtain n modified layouts corresponding to each LDE impact factor, and respectively perform simulation tests based on the reference layout and the modified layout corresponding to the corresponding LDE impact factor, so as to determine the timing relationship of the LDE impact factor based on the results of the simulation test. For example, through the multiple LDE impact factor edit boxes of the measuring device, the layout modification unit can receive multiple LDE modification requests input by the user (the modification request may include the modification value of the corresponding LDE impact factor), and then the layout modification unit can modify the corresponding layout according to the modification value of the LDE impact factor it receives to obtain the modified layout.

[0079] In one embodiment, the above-mentioned LDE timing generation units 820, 920 are used to calculate the ratio of the modified layout simulation data to the reference layout simulation data; and determine the timing relationship corresponding to the LDE impact factor according to the ratio and the value of the LDE impact factor.

[0080] In one embodiment, the above-mentioned measuring device also includes a process deviation calculation unit, and the process deviation calculation unit 940 is used to obtain real test data after tape-out based on the reference layout and the modified layout; compare the real test data with the reference layout simulation data and the modified layout simulation data to obtain the process deviation.

[0081] In one embodiment, the measuring device further includes a visual display unit 940, which can be used to display the current LDE impact factor and the time series relationship corresponding to the current LDE impact factor. Further, the visual display unit 940 can provide a user interaction interface such as an LDE impact factor selection box and at least one LDE impact factor edit box to facilitate the measurement of the above-mentioned LDE impact factor.

[0082] It should be clear that the working principle of the LDE measurement device in the embodiment of the present application is basically consistent with the execution process of the above-mentioned LDE influence factor measurement method. For details, please refer to the above description and will not be repeated here.

[0083] An embodiment of the present application further provides an LDE measurement tool, such as an EDA tool, which may include a processor and a memory, wherein the memory is used to store a computer program. When the processor executes the computer program, the measurement method in the above embodiment is implemented. For details, see Figure 3 and Figure 4 Description of the illustrated embodiment.

[0084] In addition, the embodiment of the present application may also provide a computer storable medium for storing a computer program. When the computer program is executed by one or more processors, the measurement method in the above embodiment may be implemented. Figure 3 and Figure 4 Description of the illustrated embodiment.

[0085] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for measuring layout dependency effects, characterized in that: The method comprises: Perform simulation test according to the reference layout of the test circuit to obtain reference layout simulation data; Performing simulation test according to the modified layout of the test circuit to obtain simulation data of the modified layout; wherein the modified layout of the test circuit is obtained by modifying the LDE influence factor based on the reference layout; The timing relationship corresponding to the LDE influencing factor is determined according to the reference layout simulation data and the modified layout simulation data.

2. The method according to claim 1, characterized in that The method further comprises: Get the current LDE impact factor; The reference layout is modified n times by adjusting the current LDE impact factor to obtain a modified layout, so as to determine the timing relationship corresponding to the current LDE impact factor according to the simulation data of the modified layout; wherein n is a positive integer greater than or equal to 1.

3. The method according to claim 2, characterized in that The step of modifying the reference layout n times by adjusting the current LDE impact factor to obtain a modified layout includes: The reference layout is modified in a manner of increasing or decreasing the value of the current LDE impact factor to obtain the modified layout.

4. The method according to claim 2 or 3, characterized in that: The LDE influencing factors include one or more of shallow trench isolation effect, hydrazine proximity effect, diffusion region length effect, gate spacing effect, and diffusion region / active region spacing effect; the method further includes: After determining the timing relationship corresponding to the current LDE impact factor, the current LDE impact factor is switched.

5. The method according to claim 4, characterized in that The reference layout is a layout that eliminates all LDE influencing factors.

6. The method according to any one of claims 1 to 5, characterized in that: The method comprises: Get the thresholds of all LDE impact factors; The reference layout is determined according to the threshold values ​​of all LDE influencing factors.

7. The method according to any one of claims 1 to 6, characterized in that: The determining, according to the reference layout simulation data and the modified layout simulation data, the timing relationship corresponding to the LDE influencing factor comprises: Calculating a ratio of the modified layout simulation data to the reference layout simulation data; According to the ratio and the value of the LDE impact factor, the time series relationship corresponding to the LDE impact factor is determined.

8. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: Acquire real test data after tape-out based on the reference layout and the modified layout; The actual test data is compared with the reference layout simulation data and the modified layout simulation data to obtain the process deviation.

9. The method according to any one of claims 1 to 8, characterized in that: The test circuit comprises: A ring oscillator, comprising N inverters connected in series end to end, for generating an oscillation frequency; and at least one functional unit, the at least one functional unit being connected to the ring oscillator; The layout of the ring oscillator and the at least one functional unit forms the reference layout or the modified layout; the output signal of the test circuit is used to characterize the reference layout simulation data and the modified layout simulation data.

10. A measurement device for layout-dependent effects, characterized in that: The measuring device comprises: A simulation test unit, used to perform simulation test according to a reference layout of a test circuit to obtain reference layout simulation data; perform simulation test according to a modified layout of the test circuit to obtain modified layout simulation data; wherein the modified layout of the test circuit is obtained by modifying the LDE influence factor based on the reference layout; and The LDE timing generation unit is used to determine the timing relationship corresponding to the LDE influencing factor according to the reference layout simulation data and the modified layout simulation data.

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