Memory device and pre-charging method thereof
By controlling the voltage difference between the on word line and the off word line during the precharge phase of the memory device, the problem of shrinking the read window caused by the hot carrier injection effect is solved, and the performance of the memory device is improved.
Patent Information
- Application Number
- CN202311067230.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-21
- Filing Date
- 2023-08-23
- Publication Date
- 2025-01-21
AI Technical Summary
The existing memory devices tend to cause a hot carrier injection effect during the pre-charge stage, thereby narrowing the reading window and affecting the performance of the memory devices.
By applying independently controlled multiple precharge voltages to a plurality of on word lines and targeting the on word line of these on word lines adjacent to the next adjacent target off word line of the off word line in a predetermined direction, The voltage difference from the target on word line to the next adjacent target off word line is less than the predetermined reference voltage difference.
The occurrence of the hot carrier injection effect is reduced, the reduction of the read window is reduced, the impact of programming interference is reduced, and the performance of the memory device is improved.
Smart Images
Figure CN119339753A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a memory device and a precharging method thereof. Background Art
[0002] As the storage density of memory devices increases, it is increasingly important to obtain a better read window. Program disturbance is a factor that affects the read window. Excessive write voltage, insufficient boosting channel at the inhibit cell, or abrupt slope of the boosting channel may reduce the read window, thereby affecting the performance of the memory device.
[0003] The sudden drop in the channel level may cause a hot carrier injection (HE) effect, which in turn leads to a smaller read window. In the current precharging method, the same voltage is applied to the word lines to be precharged. If the voltage difference between the adjacent precharged on word lines and precharged off word lines is too large, it will cause a hot carrier injection effect, which in turn leads to a smaller read window.
[0004] Figure 1 The hot carrier injection effect of the prior art is schematically shown. Figure 1 In FIG. 1 , CSL represents a common source line, GSL represents a global source line, SSL represents a string select line, and BL represents a bit line. Figure 1 As shown, in the precharge stage, the word lines WL0, WL4, WL5, ... are turned off; and the word lines WL1, WL2 and WL3 are turned on. Here, for example, the turn-off voltage applied to the word lines WL0, WL4, WL5, ... is 0V, and the turn-on voltage applied to the word lines WL1, WL2 and WL3 is 4.5V. It is assumed that the word lines WL0-WL3 are all in the erased state (eR) (with the lowest threshold voltage), and the word lines WL4 and WL5 are in the state G (with the highest threshold voltage). At the junction of the word lines WL3 and WL4, since the voltage difference is 4.5-0=4.5V, this large voltage difference will cause a hot carrier injection effect, thereby reducing the read window, causing program disturbance, and affecting the performance of the memory device.
[0005] Therefore, the industry strives to avoid the hot carrier injection effect to obtain a better read window, thereby increasing the performance of the memory device. Summary of the invention
[0006] According to one aspect of the present invention, a precharging method for a memory device is provided, comprising: applying a plurality of independently controlled precharging voltages to a plurality of turn-on word lines, wherein the precharging voltages are selected from a plurality of reference precharging voltages; and applying a plurality of turn-off voltages to a plurality of turn-off word lines, wherein, in a given direction, a target turn-on word line of the turn-on word lines is adjacent to a next adjacent target turn-off word line of the turn-off word lines; and a voltage difference from the target turn-on word line to the next adjacent target turn-off word line is less than a given reference voltage difference.
[0007] According to another aspect of the present invention, a memory device is provided, comprising: a memory array; a driving circuit coupled to and driving the memory array; and a memory control circuit coupled to and controlling the driving circuit. In a precharge phase, under the control of the memory control circuit, the driving circuit applies a plurality of independently controlled precharge voltages to a plurality of turn-on word lines of the memory array, the precharge voltages being selected from a plurality of reference precharge voltages; and under the control of the memory control circuit, the driving circuit applies a plurality of turn-off voltages to a plurality of turn-off word lines of the memory array. In a given direction, a target turn-on word line of the turn-on word lines is adjacent to a next adjacent target turn-off word line of the turn-off word lines; and a voltage difference from the target turn-on word line to the next adjacent target turn-off word line is less than a given reference voltage difference.
[0008] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 The hot carrier injection effect of the prior art is schematically illustrated.
[0010] Figure 2 The operating waveform diagram of the memory device according to an embodiment of the present invention is schematically shown.
[0011] FIG. 3A to FIG. 3D The operation diagram of the pre-charging stage according to an embodiment of the present invention is schematically shown.
[0012] FIG. 4A to FIG. 4E The operation diagram of the pre-charging stage according to an embodiment of the present invention is schematically shown.
[0013] Figure 5 The figure schematically shows a functional block diagram of a memory device according to an embodiment of the present invention.
[0014] Figure 6 The flowchart of the precharging method of the memory device according to an embodiment of the present invention is schematically shown.
[0015] Description of reference numerals:
[0016] CSL: Common Source Line
[0017] GSL: Global Source Line
[0018] SSL: string select line
[0019] BL: Bit Line
[0020] WL0~WL5、WLN-4~WLN+4:Word lines
[0021] 500: Memory device
[0022] 510: Memory control circuit
[0023] 520: Driving circuit
[0024] 530: Memory Array
[0025] 610, 620: Steps DETAILED DESCRIPTION
[0026] The technical terms in this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present invention has one or more technical features. Under the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.
[0027] Figure 2 The operating waveform diagram of the memory device according to an embodiment of the present invention is schematically shown. Figure 2 Several word lines WL0-WL5 are schematically shown, but it should be noted that the present invention is not limited thereto. In the following description, an example is given in which word lines WL1-WL3 are turned on and other word lines WL0, WL4, etc. are turned off during the precharge stage, but it should be noted that the present invention is not limited thereto. It is assumed here that word lines WL0-WL3 are all in the erased state (eR), while word lines WL4 and WL5 are in state G (with the highest threshold voltage). It is assumed here that word line WL2 is to be programmed, but it should be noted that the present invention is not limited thereto. The turn-off voltage applied to word lines WL0, WL4, WL5, etc. is 0V, but it should be noted that the present invention is not limited thereto. In the following, in the precharge stage, the word lines that are turned on (such as WL1-WL3, etc.) may also be referred to as "turn-on word lines"; and the word lines that are turned off (such as WL0, WL4, etc.) may also be referred to as "turn-off word lines". In the precharge stage, the common source line CSL and the global source line GSL are turned on, the string selection line SSL is turned off, and the bit line BL is turned on (inhibit string) or off (non-inhibit string) depending on whether it is an inhibit string.
[0028] like Figure 2 As shown, in the precharge stage, for example but not limited to, the precharge voltages applied to the turned-on word lines WL1-WL3 are 4.5V, 4.5V and 3V respectively. Then at the junction of word lines WL3 (turned on and having the lowest threshold voltage) and WL4 (turned off and having the highest threshold voltage), the voltage difference is 3-0=3V. This voltage difference is small, which will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of program disturbance, so that the performance of the memory device is less affected. In addition, in Figure 2 In the embodiment, the voltage of the common source line CSL decreases stepwise at the junction of the word lines WL3 (turned on and having the lowest threshold voltage) and WL4 (turned off and having the highest threshold voltage). Thus, the embodiment of the present invention can reduce the hot carrier injection effect as in the prior art.
[0029] In the programming phase, a programming voltage VPGM is applied to the word line WL2, and a pass voltage VPASS is applied to other word lines WL0-WL1, WL3-WL5, ... In the programming phase, the common source line CSL is turned on, while the global source line GSL and the string selection line SSL are turned off, and the bit line BL is turned on (disabled string) or off (non-disabled string) depending on whether it is a disabled string.
[0030] In other embodiments of the present invention, during the pre-charging stage, the pre-charging voltage applied to the conductive word lines may have more variations and is not limited to Figure 2 In the following description, some examples will be described, but it should be understood that the present invention is not limited thereto.
[0031] FIG. 3A to FIG. 3D The schematic diagram of the operation in the pre-charging stage according to an embodiment of the present invention is shown schematically. Figure 3A As shown, in the precharge stage, for example but not limited to, the precharge voltages applied to the turned-on word lines WL1-WL3 are respectively a high reference precharge voltage HV, a medium reference precharge voltage MV and a low reference precharge voltage LV, wherein HV>MV>LV. Figure 3AAs shown, at the junction of the on word line WL3 (also referred to as the "target on word line") and the next adjacent off word line WL4 (also referred to as the target off word line), the voltage difference is LV-0=LV. This voltage difference is small (that is, the voltage difference is smaller than a predetermined reference voltage difference), which will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window, reducing the impact of program disturbance, and making the performance of the memory device less affected. In one embodiment of the present invention, the target on word line is defined as the on word line adjacent to the off word line in a predetermined direction; and the target off word line is defined as the off word line adjacent to the on word line in a predetermined direction. In one embodiment of the present invention, the predetermined direction is from the common source line CSL to the bit line BL. The predetermined reference voltage difference is related to a voltage difference between a high reference precharge voltage HV and a low reference precharge voltage LV. In one example, the predetermined reference voltage difference is equal to a voltage difference between a high reference precharge voltage HV and a low reference precharge voltage LV.
[0032] like Figure 3B As shown, in the precharge stage, for example but not limited to, the precharge voltages applied to the turned-on word lines WL1-WL3 are respectively a high reference precharge voltage HV, a high reference precharge voltage HV and a medium reference precharge voltage MV. Figure 3B As shown, at the junction of the on word line WL3 (also called the "target on word line") and the next adjacent off word line WL4 (also called the target off word line), the voltage difference is MV-0=MV. This voltage difference is smaller, which will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of program disturbance, so that the performance of the memory device is less affected.
[0033] like Figure 3C As shown, in the precharge stage, for example but not limited to, the precharge voltages applied to the turned-on word lines WL1-WL3 are respectively a high reference precharge voltage HV, a middle reference precharge voltage MV, and a middle reference precharge voltage MV. Figure 3C As shown, at the junction of the on word line WL3 (also called the "target on word line") and the next adjacent off word line WL4 (also called the target off word line), the voltage difference is MV-0=MV. This voltage difference is smaller, which will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of program disturbance, so that the performance of the memory device is less affected.
[0034] like Figure 3D As shown, in the precharge stage, for example but not limited to, the precharge voltages applied to the turned-on word lines WL1-WL3 are respectively a high reference precharge voltage HV, a low reference precharge voltage LV and a medium reference precharge voltage MV. Figure 3DAs shown, at the junction of the on word line WL3 (also called the "target on word line") and the next adjacent off word line WL4 (also called the target off word line), the voltage difference is MV-0=MV. This voltage difference is smaller, which will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of program disturbance, so that the performance of the memory device is less affected.
[0035] The present invention may also have other different pre-charge voltages, which are organized into the following Table 1 for convenience of description. Of course, the present invention is not limited thereto, and those skilled in the art can infer other pre-charge voltage settings from the embodiments of the present invention, which are all within the scope of the present invention.
[0036] Table 1
[0037]
[0038]
[0039] From the above Table 1, the applied to the target conductive word line (such as Figure 3A The precharge voltage of the word line WL3) can be the middle reference precharge voltage MV or the low reference precharge voltage LV, and is applied to the non-target conductive word lines (such as Figure 3A The precharge voltage of the word line WL1 or WL2) can be a high reference precharge voltage HV, a medium reference precharge voltage MV or a low reference precharge voltage LV.
[0040] In one embodiment of the present invention, the setting values of the high reference pre-charge voltage HV, the middle reference pre-charge voltage MV and the low reference pre-charge voltage LV are, for example but not limited to, 2-5V, 1-4V and 0-3V.
[0041] FIG. 4A to FIG. 4E The schematic diagram of the operation in the pre-charging stage according to an embodiment of the present invention is shown schematically. Figure 4A As shown, in the precharge stage, for example but not limited to, at least 7 word lines WLN-3 to WLN+3 are turned on, and the remaining word lines are turned off. The precharge voltages applied to the turned-on word lines WLN-3 to WLN+3 are 6V, 6V, 5V, 4V, 3V, 2V and 2V respectively. It should be noted that these voltage values are only used for examples, and the present invention is not limited thereto. Figure 4A As shown, at the junction of the on word line WLN+3 (target on word line) and the next adjacent off word line WLN+4 (i.e., target off word line), the voltage difference is 2V-0=2V. This voltage difference is small, which will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of program disturbance, so that the performance of the memory device is less affected.
[0042] like Figure 4BAs shown, in the precharge stage, for example but not limited to, at least 6 word lines WLN-3 to WLN+2 are turned on, and the remaining word lines are turned off. The precharge voltages applied to the turned-on word lines WLN-3 to WLN+2 are 6V, 6V, 5V, 4V, 3V and 3V respectively. It should be noted that these voltage values are only used for examples, and the present invention is not limited thereto. Figure 4B As shown, at the junction of the turned-on word line WLN+2 (i.e., the target turned-on word line) and the next adjacent turned-off word line WLN+3 (i.e., the target turned-off word line), the voltage difference is 3V-0=3V. This voltage difference is small, which will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of program disturbance, so that the performance of the memory device is less affected.
[0043] like Figure 4C As shown, in the precharge stage, for example but not limited to, at least 4 word lines WLN-3 to WLN are turned on, and the remaining word lines are turned off. The precharge voltages applied to the turned-on word lines WLN-3 to WLN are 6V, 6V, 5V and 4V respectively. It should be noted that these voltage values are only used for example, and the present invention is not limited thereto. Figure 4C As shown, at the junction of the turned-on word line WLN (i.e., the target turned-on word line) and the next adjacent turned-off word line WLN+1 (i.e., the target turned-off word line), the voltage difference is 4V-0=4V. This voltage difference is small, which will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of program disturbance, so that the performance of the memory device is less affected.
[0044] like Figure 4D As shown, in the precharge stage, for example but not limited to, at least 6 word lines WLN-3 to WLN, WLN+2 and WLN+4 are turned on, and the remaining word lines are turned off. The precharge voltages applied to the turned-on word lines WLN-3 to WLN, WLN+2 and WLN+4 are 6V, 6V, 5V, 4V, 3V and 2V respectively. It should be noted that these voltage values are only used for examples, and the present invention is not limited thereto. Figure 4D As shown, at the junction of the turn-on word line WLN (i.e., the target turn-on word line) and the next adjacent turn-off word line WLN+1 (i.e., the target turn-off word line), the voltage difference is 4V-0=4V; at the junction of the turn-on word line WLN+2 (i.e., the target turn-on word line) and the next adjacent turn-off word line WLN+3 (i.e., the target turn-off word line), the voltage difference is 3V-0=3V, and at the junction of the turn-on word line WLN+4 (i.e., the target turn-on word line) and the next adjacent turn-off word line WLN+5 (i.e., the target turn-off word line), the voltage difference is 2V-0=2V. This smaller voltage difference will reduce the occurrence of hot carrier injection effects, thereby reducing the reduction of the read window and the impact of program disturbance, so that the performance of the memory device is less affected. Figure 4D In the embodiment, the turned-on word lines may be interspersed with turned-off word lines, which is also within the scope of the present invention.
[0045] like Figure 4E As shown, in the precharge stage, for example but not limited to, at least 7 word lines WLN-3 to WLN+3 are turned on, and the remaining word lines are turned off. The precharge voltages applied to the turned-on word lines WLN-3 to WLN+3 are 2 to 5V, 2 to 5V, 1 to 4V, 1 to 4V, 0 to 3V, 0 to 3V, and 0 to 3V, respectively. It should be noted that these voltage values are only used for examples, and the present invention is not limited thereto. Figure 4E As shown, at the junction of the on word line WLN+3 (i.e., the target on word line) and the next adjacent off word line WLN+4 (i.e., the target off word line), the voltage difference is (0-3 V)-0=0-3 V. This smaller voltage difference will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of program disturbance, so that the performance of the memory device is less affected.
[0046] From the above, it can be seen that in one embodiment of the present invention, in order to reduce the hot carrier injection effect, in the pre-charging stage, (1) in a given direction, the voltage difference between the next adjacent closed word line from the turned-on word line should be avoided to be too large. Figure 2 , 3A to Figure 3D and FIG. 4A to FIG. 4E From the perspective of FIG. 1 , the predetermined direction refers to the direction from the common source line CSL to the bit line BL. (2) The precharge voltage applied to these conductive word lines can be set in a variety of different ways (not limited to those shown in Table 1).
[0047] Figure 5 Schematically shows a functional block diagram of a memory device according to an embodiment of the present invention. Figure 5 As shown, a memory device 500 according to an embodiment of the present invention includes a memory control circuit 510, a driving circuit 520, and a memory array 530. The memory control circuit 510 is coupled to and controls the driving circuit 520, and the driving circuit 520 is coupled to and drives the memory array 530. Under the control of the memory control circuit 510, in the precharge stage and the programming stage, the driving circuit 520 can output a driving voltage (such as the precharge voltage, programming voltage VPGM, pass voltage VPASS, etc. in the above figure) to drive the memory array 530 for precharge and programming.
[0048] Figure 6A flow chart of a precharging method for a memory device according to an embodiment of the present invention is schematically shown. In step 610, a plurality of independently controlled precharge voltages are applied to a plurality of turn-on word lines, and the precharge voltages are selected from a plurality of reference precharge voltages. In step 620, a plurality of turn-off voltages are applied to a plurality of turn-off word lines, wherein, in a given direction, a target turn-on word line of the turn-on word lines is adjacent to a next adjacent target turn-off word line of the turn-off word lines; and a voltage difference from the target turn-on word line to the next adjacent target turn-off word line is less than a given reference voltage difference.
[0049] The above embodiments of the present invention may be applied to a two-dimensional (2D) memory device or a three-dimensional (3D) memory device. In addition, the above embodiments of the present invention may be applied to a single-cell (SLC) memory device, a multi-bit cell (MLC) memory device, a triple-cell (TLC) memory device, a quad-bit cell (QLC) memory device, etc.
[0050] In the above-mentioned embodiment of the present invention, the pre-charging method can improve program disturbance because a large voltage difference between adjacent word lines is avoided to avoid hot carrier injection effect, thereby obtaining a larger read window.
[0051] In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached claims.
Claims
1. A precharging method for a memory device, comprising: applying a plurality of independently controlled precharge voltages to a plurality of conductive word lines, the precharge voltages being selected from a plurality of reference precharge voltages; as well as applying a plurality of turn-off voltages to a plurality of turn-off word lines, in, In a given direction, a target on word line of the on word lines is adjacent to a next adjacent target off word line of the off word lines; as well as A voltage difference from the target on word line to the next adjacent target off word line is less than a predetermined reference voltage difference.
2. The precharging method of a memory device according to claim 1, wherein: The predetermined direction is from a common source line to a bit line; as well as A voltage of the common source line decreases gradually at a junction of the target on word line and the next adjacent target off word line.
3. The precharging method of the memory device according to claim 1, wherein: The predetermined reference voltage difference is related to a voltage difference between a highest reference pre-charge voltage of the reference pre-charge voltages and a lowest reference pre-charge voltage of the reference pre-charge voltages.
4. The precharging method of a memory device according to claim 1, wherein: The precharge voltage applied to a non-target conduction word line of the conduction word lines is a first reference precharge voltage, a second reference precharge voltage, or a third reference precharge voltage, the first reference precharge voltage is higher than the second reference precharge voltage, and the second reference precharge voltage is higher than the third reference precharge voltage; and The precharge voltage applied to the at least one target turned-on word line is the second reference precharge voltage or the third reference precharge voltage.
5. The precharging method of a memory device according to claim 1, wherein: One of the off word lines is interspersed between the on word lines.
6. A memory device comprising: a memory array; a driving circuit coupled to and driving the memory array; as well as a memory control circuit coupled to and controlling the driving circuit; in, In a pre-charge phase, Under the control of the memory control circuit, the drive circuit applies a plurality of independently controlled precharge voltages to a plurality of conductive word lines of the memory array, the precharge voltages being selected from a plurality of reference precharge voltages; and Under the control of the memory control circuit, the drive circuit applies multiple shutdown voltages to multiple shutdown word lines of the memory array, in, In a given direction, a target on word line of the on word lines is adjacent to a next adjacent target off word line of the off word lines; and a voltage difference from the target on word line to the next adjacent target off word line is less than a given reference voltage difference.
7. The memory device according to claim 6, wherein: The predetermined direction is from a common source line to a bit line; as well as A voltage of the common source line decreases gradually at a junction of the target on word line and the next adjacent target off word line.
8. The memory device according to claim 6, wherein: The predetermined reference voltage difference is related to a voltage difference between a highest reference pre-charge voltage of the reference pre-charge voltages and a lowest reference pre-charge voltage of the reference pre-charge voltages.
9. The memory device according to claim 6, wherein: The precharge voltage applied to a non-target conduction word line of the conduction word lines is a first reference precharge voltage, a second reference precharge voltage, or a third reference precharge voltage of the reference precharge voltages, the first reference precharge voltage is higher than the second reference precharge voltage, and the second reference precharge voltage is higher than the third reference precharge voltage; and The precharge voltage applied to the at least one target turned-on word line is the second reference precharge voltage or the third reference precharge voltage.
10. The memory device according to claim 6, wherein: One of the off word lines is interspersed between the on word lines.