System and method for connecting integrated circuits

Abstract

The present technology relates to systems and methods for connecting integrated circuits. In an embodiment, the present technology provides an apparatus including a first circuit, a second circuit, and a third circuit. The first circuit is coupled to the second circuit and the third circuit through a first interconnect. The third circuit is coupled to a fourth circuit through a second interconnect. The fourth circuit includes a processor circuit. The third circuit may support data transfer at a faster speed than the second circuit may handle, facilitating data transfer between the first circuit and the fourth circuit. Other embodiments are also present.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 514,525, filed on July 19, 2023, entitled “HBM INTERFACE PERFORMANCE, POWER CONSUMPTION AND LATENCY THROUGH 3D CHIPLET,” which is commonly owned and incorporated by reference for all purposes. Technical Field

[0003] The present technology relates to integrated circuits. Background Art

[0004] In the field of semiconductor technology, the demand for faster and more efficient memory solutions has been growing. High bandwidth memory (HBM) has emerged as a revolutionary solution to address the bandwidth requirements of high-performance computing, graphics and networking applications. HBM, a type of stacked dynamic random access memory (DRAM), provides significantly higher bandwidth than traditional memory solutions such as double data rate synchronous dynamic random access memory (DDR SDRAM), while consuming less power. This is achieved by vertically stacking memory dies and connecting them using through silicon vias (TSVs) and microbumps.

[0005] In the past, various methods have been proposed to implement HBM, but they are all inadequate. Improved methods and systems are needed. Summary of the invention

[0006] In one aspect, the present disclosure relates to a device, comprising: a first circuit, which includes a first side, the first side includes a first region and a second region, the first circuit includes a first interconnect; a second circuit, which is coupled to the first region, the second circuit is coupled to the first circuit through the first interconnect; a third circuit, which is coupled to the second region, the third circuit is coupled to the first circuit through the first interconnect; a second interconnect, which is coupled to the third circuit; and a fourth circuit, which is coupled to the third circuit through the second interconnect.

[0007] In another aspect, the present disclosure relates to a device, comprising: a first circuit comprising a first side and a second side, the first side comprising a first region and a second region, the first circuit comprising a first interconnect; a second circuit coupled to the first region, the second circuit coupled to the first circuit through the first interconnect; a third circuit coupled to the second region, the third circuit coupled to the first circuit through the first interconnect; an interposer coupled to the second side; and a fourth circuit coupled to the third circuit through the interposer.

[0008] In other aspects, the present disclosure relates to a device, comprising: a first circuit, which includes a first side, the first side includes a first region and a second region, the first circuit includes a first interconnect; a second circuit, which is coupled to the first region, the second circuit is coupled to the first circuit through the first interconnect; a third circuit, which is coupled to the second region, the third circuit includes a first physical layer circuit; a second interconnect, which is coupled to the third circuit; and a fourth circuit, which includes a second physical layer circuit, the second physical layer circuit is coupled to the first physical layer circuit through the second interconnect. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a simplified block diagram illustrating a system for connecting an HBM to an integrated circuit device in accordance with an embodiment of the present technology.

[0010] Figure 2 is a simplified block diagram illustrating a system for connecting an HBM to an integrated circuit device using a droplet circuit in accordance with an embodiment of the present technology.

[0011] Figure 3 is a simplified block diagram illustrating a droplet circuit according to an embodiment of the present technology. DETAILED DESCRIPTION

[0012] The present technology relates to integrated circuit technology. In an embodiment, the present technology provides a device including a first circuit, a second circuit, and a third circuit. The first circuit is coupled to the second circuit and the third circuit via a first interconnect. The third circuit is coupled to the fourth circuit via a second interconnect. The fourth circuit includes a processor circuit. The third circuit can support data transfer at a faster speed than the second circuit can handle, thereby facilitating data transfer between the first circuit and the fourth circuit. There are other embodiments.

[0013] With the surge in applications requiring high-speed data processing, such as artificial intelligence, real-time graphics rendering, and advanced scientific simulations, the need to bridge the speed gap between HBM and logic boards has become critical. Solutions are needed that optimize the interface between HBM and the logic die to ensure that the system can fully utilize the potential of HBM without being hindered by the limitations of the logic board. For example, artificial intelligence (AI) algorithms, especially deep learning models, require real-time processing of large amounts of data. This requires not only higher memory capacity, but also faster memory access speeds or bandwidth. In addition, as AI is applied in portable devices and edge computing, there is a need to reduce power consumption and minimize latency during memory access.

[0014] High bandwidth memory has emerged as a solution to these memory challenges. The HBM architecture, which involves vertically stacking DRAM dies, allows for significant increases in bandwidth while reducing power consumption. For example, HBM includes a stack of DRAM dies mounted on top of a logic die using TSV 3D. The HBM physical layer (PHY), a key component responsible for data transfer, is located on the logic die. This PHY is then connected to the functional or core die through a silicon interposer. However, as the technology has evolved (e.g., from its initial version to HBM4), certain bottlenecks have become apparent, particularly in the HBM PHY.

[0015] As HBM technology advances to provide higher speeds and capacities, new challenges emerge. The logic die, which is responsible for processing and managing data, has difficulty keeping up with the fast data transfer rates provided by advanced HBM solutions. This speed difference between HBM and HBM PHY on the logic die leads to potential bottlenecks, where the logic die becomes the limiting factor in overall system performance. For example, the silicon technology used to design the HBM PHY on the logic die may not be as advanced as the silicon technology used for the HBM PHY on the processor unit. This can limit the ability of the logic die to handle the high speeds provided by HBM. For example, HBM or processors can be manufactured using a 3nm process, while the logic die can be manufactured using a 14nm process. Upgrading the logic die to match the speed of advanced HBM solutions can be expensive. It also introduces design complexity, especially when trying to maintain compatibility with existing systems. Increasing the speed of the logic die to match HBM can result in a significant increase in cost, making it a major concern for manufacturers. Choosing silicon technology for the logic die is particularly not simple. It is a complex decision affected by many factors. Advanced silicon technology, while providing better performance, is typically more expensive. This makes cost an important factor in the decision-making process. Different components within a chip have different performance requirements. The selected technology must meet the needs of all of these components without compromising overall chip performance. Especially for portable devices, silicon technology must ensure that power consumption is optimized. Often, more mature (and sometimes slower) silicon technology may be preferred due to its proven reliability, even if it is not the latest available.

[0016] It will be appreciated that embodiments of the present technology provide an intermediate chip (e.g., which may be referred to as a droplet chip or droplet circuit) that connects the HBM and the processing unit and bypasses the data rate bottleneck presented by the logic die. As explained above, in some approaches, the logic die, while versatile, may not be optimized for the high-speed data transfer provided by advanced HBM solutions. The droplet chip can efficiently handle high-speed transfers, thereby bypassing the limitations of the logic die. For example, the droplet chip can be used as a high-speed pipeline, ensuring that data from the HBM is fed to the processing unit at an optimal rate, thereby minimizing latency and maximizing bandwidth utilization. It will be appreciated that by simplifying data transfer and reducing the need for multiple data conversions or buffering, the droplet chip can contribute to overall power savings, which is useful for portable and edge devices. Depending on the implementation, the droplet chip can be customized according to a specific use case or application, allowing a modular approach in which different droplet chips can be used based on the specific requirements of the system. By taking over the function of managing high-speed data transfer, the droplet chip can reduce the design complexity of the logic die, allowing it to be optimized for other tasks.

[0017] According to embodiments of the present technology, the use of droplet chips can improve the way systems are designed and integrated. Droplet chips can help manage (e.g., through drivers and gearboxes) high-speed data transfers, ensuring that both the HBM and the processing unit operate at their peak potential, rather than trying to force the logic chip to handle tasks that the logic chip may not be optimized for. For example, the droplet chip acts as a specialized bridge, ensuring that the huge data capacity of the HBM is seamlessly and efficiently fed into the processing unit, allowing the system to be faster, more energy-efficient, and optimized for the needs of modern applications.

[0018] The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it into the context of a particular application. Various modifications for different applications and various uses will be apparent to those skilled in the art, and the general principles defined herein can be applied to a wide range of embodiments. Therefore, the technology is not intended to be limited to the embodiments presented, but should be consistent with the widest scope consistent with the principles and novel features disclosed herein.

[0019] In the following detailed description, many specific details are set forth in order to provide a more thorough understanding of the present technology. However, it will be apparent to those skilled in the art that the present technology can be practiced without being limited to these specific details. In other cases, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the present technology.

[0020] The reader's attention is directed to all papers and documents filed concurrently with this specification, and these papers and documents are open to public inspection together with this specification, and the contents of all these papers and documents are incorporated herein by reference. All features disclosed in this specification (including any attached claims, abstracts and drawings) can be replaced by alternative features for the same, equivalent or similar purposes, unless otherwise expressly specified. Therefore, unless otherwise expressly specified, each feature disclosed is only an example of a general series of equivalent or similar features.

[0021] Furthermore, any element in a claim that does not explicitly recite a "means" for performing a particular function or a "step" for performing a particular function should not be construed as a "means" or "step" clause as specified in 35 U.S.C. § 112, paragraph 6. Specifically, the use of "the step of" or "the act of" in the claims herein is not intended to invoke the provisions of 35 U.S.C. § 112, paragraph 6.

[0022] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in a "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0023] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, between, below, near, or in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element) or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances in which there may be intervening elements.

[0024] Similarly, when an element is referred to herein as being "joined" to another element, it is understood that the element may be directly joined to the other element (without any intervening elements) or that there may be intervening elements between the joined elements. In contrast, when an element is referred to as being "directly joined" to another element, it is understood that there are no intervening elements in the "direct" joining between the elements. However, the presence of direct joining does not exclude other forms of joining in which there may be intervening elements.

[0025] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include intermediate elements present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intermediate elements between the layers. However, the presence of a directly coupled or connected layer does not preclude other connections where intermediate elements may exist.

[0026] In addition, the terms left, right, front, back, up, down, forward, backward, clockwise and counterclockwise are used only for explanation purposes and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0027] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context otherwise dictates, intermediate processes may occur before and / or after any portion of the described process, and further various processes may be reordered, added, and / or omitted according to various embodiments.

[0028] Unless otherwise stated, all numbers used herein to express quantities, dimensions, etc. should be understood to be modified by the term "about" in all instances. In this application, the use of the singular includes the plural unless otherwise specifically stated, and the use of the terms "and" and "or" means "and / or" unless otherwise stated. In addition, the use of the terms "including" and "having" as well as other forms such as "includes", "is included", and "has / have / had" should be considered non-exclusive. In addition, terms such as "element" or "component" cover elements and components comprising one unit as well as elements and components comprising more than one unit, unless otherwise specifically stated.

[0029] As used herein, the phrase "at least one of..." preceding a series of items, and the terms "and" or "or" separating any items, modify the entire list, rather than each member of the list (i.e., each item). The phrase "at least one of..." does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. Where selection of "at least one of each of A, B, and C" or, alternatively, "at least one of A, at least one of B, and at least one of C" is intended, it is expressly described as such.

[0030] One general aspect includes a device comprising a first circuit, the first circuit comprising a first side, the first side comprising a first region and a second region, the first circuit comprising a first interconnect. The device further comprises a second circuit coupled to the first region, the second circuit coupled to the first circuit through the first interconnect. The device further comprises a third circuit coupled to the second region, the third circuit coupled to the first circuit through the first interconnect. The device further comprises a second interconnect coupled to the third circuit. The device further comprises a fourth circuit coupled to the third circuit through the second interconnect.

[0031] Embodiments may include one or more of the following features. The device further includes a first memory coupled to the second circuit, the second circuit including a second memory. The first memory circuit includes a first through silicon via (TSV), and the second memory circuit includes a second TSV, the first TSV coupled to the second TSV by a microbump. The third circuit includes a driver. The device further includes an interposer including the second interconnect. The fourth circuit includes a processor. The first circuit is coupled to the second circuit by a hybrid copper bond. The first circuit is coupled to the third circuit by a hybrid copper bond. The third circuit includes a first physical layer circuit. The fourth circuit includes a second physical layer circuit, the first physical layer circuit is coupled to the second physical layer circuit by the second interconnect. The first side includes a metal layer; and the first circuit further includes a second side, the second side includes a silicon layer. The first interconnect includes a bus operating at a first speed, and the first circuit includes a logic circuit operating at a second speed, the first speed being higher than the second speed. The third circuit includes a gearbox circuit; the fourth circuit operates at a third speed; and the gearbox circuit is configured to match the first speed with the third speed. The device further includes a die coupled to the third circuit.

[0032] According to another embodiment, the present technology provides a device including a first circuit including a first side and a second side, the first side including a first region and a second region, the first circuit including a first interconnect. The device further includes a second circuit coupled to the first region, the second circuit coupled to the first circuit through the first interconnect. The device further includes a third circuit coupled to the second region, the third circuit coupled to the first circuit through the first interconnect. The device further includes an interposer coupled to the second side. The device further includes a fourth circuit coupled to the third circuit through the interposer.

[0033] Embodiments may include one or more of the following features. The first side includes a metal layer, and the second side includes a silicon layer. The third circuit includes a first physical layer circuit, the fourth circuit includes a second physical layer circuit, and the first physical layer circuit is coupled to the second physical layer circuit through the interposer. The first circuit is coupled to the second circuit through a hybrid copper bond.

[0034] According to yet another embodiment, the present technology provides a device including a first circuit including a first side, the first side including a first region and a second region, the first circuit including a first interconnect. The first side includes a second circuit coupled to the first region, the second circuit coupled to the first circuit through the first interconnect. The first side includes a third circuit coupled to the second region, the third circuit including a first physical layer circuit. The first side includes a second interconnect coupled to the third circuit. The first side includes a fourth circuit, the fourth circuit including a second physical layer circuit, the second physical layer circuit coupled to the first physical layer circuit through the second interconnect. In some embodiments, the first interconnect includes a bus operating at a first speed, and the first circuit includes a logic circuit operating at a second speed, the first speed being higher than the second speed.

[0035] Figure 1 1 is a simplified block diagram illustrating a system 100 for connecting HBM to an integrated circuit device according to an embodiment of the present technology. This diagram provides examples only, which should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, substitutions, and modifications.

[0036] As shown, system 100 includes an interposer 102. For example, the term "interposer" refers to an electrical interface that redirects electrical connections between electrical components, which can extend the connections to a wider spacing or reroute the connections to different connections. For example, interposer 102 can include a substrate that uses one or more interconnects to facilitate electrical connections between various components (e.g., processor circuits and memory circuits), thereby allowing high-speed data transfer and compact semiconductor integration.

[0037] As an example, circuit 118 is coupled to interposer 102 and may be coupled to other components through interposer 102. Circuit 118 may include a processor circuit. The term "processor circuit" may refer to an integrated circuit containing logic and arithmetic units for the operations and calculations required to execute a computer program. For example, circuit 118 may include, but is not limited to, an application specific integrated circuit (ASIC), a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), a memory interface, a memory controller, an input / output device, an input / output interface, an auxiliary storage interface, and / or the like. Depending on the application, circuit 118 may be configured to perform computationally intensive tasks and require high-speed data transfer from a memory device. For example, circuit 118 may include an AI accelerator that runs complex machine learning algorithms on large amounts of data. Circuit 118 may need to frequently access a memory device to read and write data, such as weights, activations, gradients, etc. In some cases, circuit 118 may need to communicate with other components, such as sensors, cameras, displays, etc. to receive input and output.

[0038] In various examples, circuit 104 is coupled to interposer 102 via interconnects 108. The term "interconnect" may refer to an electrical path that establishes an electrical path between different components or sections of a semiconductor device, thereby allowing data, signal, and / or power transmission. For example, interconnect 108 may include, but is not limited to, metal traces, vias, microbumps, conductive pads, and / or other conductive materials and structures.

[0039] In some embodiments, circuit 104 is coupled to circuit 106a. For example, circuit 106a includes a first memory circuit. The term "memory circuit" may refer to an electronic chip or integrated circuit configured to store, retain, and facilitate retrieval of data. For example, circuit 106a may include, but is not limited to, high bandwidth memory (HBM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, phase change memory (PCM), magnetoresistive random access memory (MRAM), electrically erasable programmable read-only memory (EEPROM), and / or the like. As an example, circuit 106a includes high bandwidth memory (HBM). The term "high bandwidth memory" or "HBM" may refer to a high-speed random access memory interface designed for high-performance applications such as graphics cards, high-performance computing, machine learning, and / or the like.

[0040] Depending on the implementation, one or more memory circuits may be stacked together to form a 3D package that provides higher memory capacity, bandwidth, and performance than a single memory circuit. For example, circuit 106a may be stacked with one or more circuits (e.g., circuit 106b and / or circuit 106c, etc.), which may be memory circuits of the same or different types. This stacked memory configuration may reduce the power consumption, size, and cost of the memory system. In some examples, stacked memory circuits (e.g., circuits 106a, 106b, 106c, etc.) may be connected using through-silicon vias (TSVs) 110a and / or microbumps 112a, which may establish vertical electrical connections through the circuits, thereby allowing faster and more efficient data transfer between memory circuits. The term "through-silicon via" or "TSV" may refer to an electrical connection through a silicon wafer or die. TSVs are used to connect multiple chips or layers in a 3D package, thereby providing high-density, low-latency, and low-power interconnections between circuits or layers. The term "microbump" may refer to a bonding medium that supports power and signaling between chips or layers in a 3D package such as HBM and logic circuits. A microbump may be a metal bump with a very small diameter (e.g., less than 25um) and pitch (e.g., less than 40um). A microbump may include, but is not limited to, one or more materials such as copper, gold, solder, nickel, and / or the like.

[0041] In various embodiments, circuit 104 may include a logic circuit. Circuit 104 may be coupled to one or more memory circuits (e.g., circuits 106a, 106b, 106c, etc.) via TSV 110b and / or microbump 112b. For example, the term "memory circuit" or "memory" refers to a device or system that can store and retrieve data using electrical or optical signals, including HBM. The term "logic circuit" may refer to a chip or circuit responsible for managing data transfer, error correction, power distribution, or other functions of one or more memory circuits (e.g., circuit 106a). For example, circuit 104 may be configured to connect and control data transmission between one or more memory circuits (e.g., circuit 106a) and a functional die (e.g., circuit 118) in a high-performance system. It serves as a bridge between memory circuits and functional dies to ensure that they can communicate and exchange data efficiently and reliably. Depending on the implementation, circuit 104 can be customized for different applications and requirements, such as graphics, artificial intelligence, high-performance computing, data centers, and / or networking. Circuit 104 may be designed using different silicon technologies and processes depending on the performance, power, cost, and reliability tradeoffs.

[0042] In some embodiments, circuit 104 includes a physical layer (PHY) circuit 114. The term "physical layer" or "physical layer circuit" may refer to a section of a semiconductor chip that handles physical layer and data link layer connections and may provide an electrical and logical interface between a memory circuit (e.g., circuit 106a) and a functional die (e.g., circuit 118). PHY circuit 114 may include various components for facilitating data transfer, such as input / output terminals, phase-locked loops (PLLs), transmitters, receivers, and / or the like. Depending on the application, PHY circuit 114 may be optimized to support various features and standards of HBM, such as data rates, bandwidths, error correction, refresh modes, and / or the like.

[0043] In various implementations, circuit 118 includes PHY circuit 116. PHY circuit 114 may be coupled to PHY circuit 116 via interconnect 120 of interposer 102. PHY circuits 114 and 116 may be configured to facilitate high-speed data transfer between circuit 106a and circuit 118. However, the advancement of HBM's high-speed data transfer capabilities has outpaced the processing and management capabilities of logic circuits, resulting in a potential bottleneck that limits overall system performance. In other words, while HBM can promise high data transfer rates (e.g., greater than 2 Gbps per pin) and high bandwidth (e.g., greater than 400 Gbytes / s), it is difficult for logic circuits to efficiently handle and utilize such fast data streams, resulting in inefficiency and underutilization of HBM's potential. Therefore, it is necessary to bridge this gap to effectively utilize the full potential of HBM's data transfer and bandwidth capabilities.

[0044] Figure 2 2 is a simplified block diagram illustrating a system 200 for connecting an HBM to an integrated circuit device using a droplet circuit according to an embodiment of the present technology. This figure provides examples only, which should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize many variations, substitutions, and modifications. As shown, the system 200 may include an interposer 202, which serves as a substrate for facilitating electrical connections between various components using one or more interconnects, thereby providing an efficient path for signal transmission, reduced latency, and enhanced system integration. For example, a circuit 204 (e.g., the first circuit described in Technical Solution 1) is coupled to the interposer 202 via TSVs 210a and / or microbumps 208a.

[0045] In various implementations, circuit 204 includes a first side and a second side. For example, the first side may include a front side or top of circuit 204, and the second side may include a bottom side or back of circuit 204. In some cases, the first side may include a metal layer, and the second side may include a silicon layer. The first side may include a first region 228 and a second region 230.

[0046] In some examples, the system 200 further includes a circuit 206a (e.g., the second circuit described in technical solution 1). The circuit 206a can be coupled to the circuit 204 via a first interconnect (e.g., the first interconnect described in technical solution 1). For example, the circuit 206a includes a memory circuit. The circuit 206a may include, but is not limited to, a high bandwidth memory (HBM), a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a phase change memory (PCM), a magnetoresistive random access memory (MRAM), an electrically erasable programmable read-only memory (EEPROM), and / or the like. In an example, the circuit 206a includes an HBM, which can be used in high-performance applications such as graphics cards, high-performance computing, machine learning, and / or the like. Depending on the implementation, the circuit 206a may be characterized by a data transfer rate greater than 2 Gbps per pin.

[0047] In some embodiments, one or more memory circuits may be stacked together to form a 3D package that provides higher memory capacity, bandwidth, and performance than a single memory circuit. For example, circuit 206a may be stacked with one or more circuits (e.g., circuit 206b and / or circuit 206c, etc.), which may be memory circuits of the same or different types. In various examples, stacked memory circuits (e.g., circuits 206a, 206b, 206c, etc.) may be connected using through-silicon vias (TSVs) 210b and / or microbumps 208b, which may establish vertical electrical connections through the circuits, thereby allowing faster and more efficient data transfer between memory circuits. For example, the stacked memory circuits may be characterized by a bandwidth greater than 400Gbytes / s. In some examples, circuit 206a includes TSVs 210c, and circuit 206b includes TSVs 210b. TSVs 210c may be coupled to TSVs 210b via microbumps 208b.

[0048] In various implementations, circuit 204 includes logic circuits that may be configured to manage, process, and communicate with one or more memory circuits (e.g., circuits 206a, 206b, 206c, etc.). For example, circuit 206a is coupled to circuit 204 (e.g., first region 228) via a first interconnect. Depending on the implementation, the first interconnect may include, but is not limited to, metal traces, vias, microbumps, conductive pads, and / or other conductive materials and structures. For example, the first interconnect includes a hybrid copper bond (HCB) 212a. The term "hybrid copper bond" or "hybrid copper bond pad" may include a bond between copper or other metals (e.g., gold, etc.) and a dielectric material, which may be organic (e.g., small molecules or monomers, etc.) or inorganic (e.g., silicon oxide, other metal oxides, etc.). HCBs provide a robust and compact bonding solution, thereby enhancing conductivity and mechanical strength between logic circuits and memory circuits, while also optimizing thermal performance and potentially reducing manufacturing costs. To facilitate HCB bonding, circuit 204 may be oriented so that its metal layer faces upward (eg, toward circuit 206a). This orientation ensures direct contact between the metal layers of the two circuits, thereby facilitating efficient HCB bonding and optimizing electrical connectivity between the two.

[0049] According to some embodiments, system 200 further includes circuit 216 (e.g., the third circuit described in technical solution 1). For example, circuit 216 is coupled to circuit 204 (e.g., second region 230) via a first interconnect, which may include HCB 212b. In various implementations, circuit 216 may include PHY circuit 220. PHY circuit 220 may be used as an interface between a memory circuit (e.g., circuit 206a) and a functional die (e.g., circuit 226), and is configured to perform various functions to facilitate data transmission between the two. For example, PHY circuit 220 may be responsible for sending and receiving data, commands, and / or control signals between the memory circuit and the functional die. PHY circuit 220 may be configured to handle tasks such as data serialization and deserialization, link training and calibration, error detection and correction, and / or the like. PHY circuit 220 may include various components for facilitating data transmission, such as input / output terminals, phase-locked loops (PLLs), transmitters, receivers, and / or the like. Depending on the application, the PHY circuit 220 may be optimized to support various features and standards of HBM, such as data rate, bandwidth, error correction, refresh mode, and / or the like.

[0050] In various implementations, circuit 206a may be coupled to PHY circuit 220 via a first interconnect. For example, first interconnect further includes bus 212c, which may be located inside circuit 204. During operation, data signals from circuit 206a may be sent to corresponding HCBs (e.g., HCB 212a) on circuit 204 via one or more TSVs and microbumps (e.g., TSVs 210b and 210c, microbumps 208b, etc.). The HCBs may be connected via bus 212c extending along circuit 204. Bus 212c transmits data from one or more HCBs to PHY 220 via one or more TSVs and / or HCB 212b. PHY circuit 220 may then perform various functions to facilitate data transfer between a memory stack and a functional die (e.g., circuit 226).

[0051] In some cases, bus 212c is configured to operate at a first speed and circuit 204 is configured to operate at a second speed. The first speed may be higher than the second speed. For example, the first speed may be greater than 2 Gbps per pin, allowing high bandwidth and processing power for data transfer between the memory stack and the PHY circuit. The second speed may be lower than the first speed, enabling the logic circuit to dedicate resources to other functions such as memory management, power management, or the like. By separating the data transfer role from the logic circuit, the system can reduce power consumption and heat generation, resulting in enhanced efficiency and reliability.

[0052] As previously mentioned, when docking with logic circuits (e.g., circuit 204), overall system performance has been bottlenecked. The inherent limitations of logic circuits in processing and managing fast data streams often lead to underutilization of the full potential that memory circuits (e.g., HBM) can provide. By decoupling the PHY circuit (e.g., PHY circuit 220) from the logic circuit and incorporating it into a separate circuit (e.g., circuit 216), system 200 provides a dedicated and optimized interface customized for the needs of fast data transfer. This ensures more efficient communication between memory and functional dies, allowing each component to operate at its peak potential. This strategic separation not only eliminates data transfer constraints on logic circuits, but also enables it to focus more efficiently on its core tasks, such as data calculation, management, buffering, testing, or other system-level functions. Depending on the implementation, circuit 216 may be coupled to die 228 to match the height of the memory stack (e.g., one or more circuits 206a, 206b, 206c, etc.).

[0053] In some embodiments, the system 200 further includes a circuit 226 (e.g., the fourth circuit described in technical solution 1), and the circuit 226 may include a processor circuit. For example, the circuit 226 may include, but is not limited to, an application-specific integrated circuit (ASIC), a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), a memory interface, a memory controller, an input / output device, an input / output interface, an auxiliary storage interface, and / or the like. Depending on the application, the circuit 226 may be configured to perform computationally intensive tasks and require high-speed data transmission from a memory device. For example, the circuit 226 may include an AI accelerator that runs complex machine learning algorithms on large amounts of data. The circuit 226 may need to frequently access the memory device to read and write data, such as weights, activations, gradients, etc.

[0054] In various embodiments, circuit 226 includes PHY circuit 222. PHY circuit 222 can be coupled to PHY circuit 220 via interconnect 224. Depending on the application, the PHY circuit can be optimized to support different data transmission modes and speeds. For example, PHY circuits 220 and 222 can support data transfer rates greater than 2Gbps per pin, which provides high bandwidth and processing power for data-intensive applications such as real-time graphics rendering or machine learning calculations. The integration of PHY circuits 220 and 222 in system 200 promotes seamless and fast data exchange between basic components. Their ability to support high-speed data transmission meets the needs of data-centric applications, thereby ensuring optimal performance and efficiency in various operating scenarios. In some cases, circuit 226 is configured to operate at a third speed. Circuit 226 is configured to match the first speed of bus 212c with the third speed of circuit 226 to ensure seamless and fast data flow for various applications.

[0055] Figure 3 3 is a simplified block diagram illustrating a droplet circuit 300 according to an embodiment of the present technology. This diagram provides an example only, which should not unduly limit the scope of the claims. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. In various embodiments, the circuit 300 can be implemented as an intermediate chip (e.g., a semiconductor package) configured to connect memory circuits and functional dies within the semiconductor package. Figure 2 This intermediate configuration ensures optimal communication paths, reduced latency, and the ability to utilize the full potential of both memory and processing resources.

[0056] As shown, circuit 300 may include circuit 302. For example, circuit 302 may include a driver circuit and / or a receiver circuit. The term "driver circuit" may refer to a circuit or component that converts and amplifies an electrical signal from one circuit to another circuit. The term "receiver circuit" may refer to a circuit or component that receives and recovers an electrical signal from another circuit. For example, driver and receiver circuits may be used to facilitate data transfer between various components of a semiconductor device. As an example, driver and receiver circuits may facilitate one or more memory circuits (e.g., Figure 2 circuits 206a, 206b, 206c) and functional die (e.g., Figure 2 In some cases, circuit 302 (e.g., driver and / or receiver circuit) can be implemented by logic circuit (e.g., Figure 2 circuit 204) and one or more memory circuits (e.g., Figure 2 The driver circuits may amplify high-speed data signals from the functional die and transmit them to the memory circuits; the receiver circuits may receive data signals from the high-speed data bus and convert them into a form that can be processed by the functional die. In some cases, the circuit 302 may be coupled to a logic circuit (e.g., Figure 2 Circuit 204).

[0057] In various implementations, the circuit 300 further includes a gearbox circuit 306. The term "gearbox" or "gearbox circuit" may refer to a circuit or component configured to modulate the data rate and format of signals transmitted between different circuits. For example, the gearbox circuit 306 is configured to convert a high-speed data stream from a memory circuit (e.g., HBM) into a format or rate that a functional die can seamlessly handle, or vice versa. For example, a memory circuit (e.g., Figure 2The circuit 206a and / or bus 212c of the PHY circuit 304 can operate at a first speed, and the PHY circuit 304 can operate at a second speed. The gearbox circuit 306 can be configured to match the first speed with the second speed. By facilitating rate matching and format conversion, the gearbox circuit 306 effectively bridges the potential differences in data transfer speeds between the memory circuit and the various functional dies, thereby ensuring smooth and efficient data flow. Depending on the application, the gearbox circuit 306 can perform various functions, such as data alignment, synchronization, and / or the like.

[0058] In some embodiments, circuit 300 includes PHY circuit 304. As previously mentioned, PHY circuit 304 may be used as a memory circuit (e.g., Figure 2 circuit 206a) and a functional die (eg, Figure 2 226) and is configured to perform various functions to facilitate data transmission between the two. For example, the PHY circuit 304 may be responsible for sending and receiving data, commands and / or control signals between the memory circuit and the functional die. The PHY circuit 304 may be configured to handle tasks such as data serialization and deserialization, link training and calibration, error detection and correction, and / or the like. The PHY circuit 304 may include various components for facilitating data transmission, such as input / output terminals, phase-locked loops (PLLs), transmitters, receivers, and / or the like. Depending on the application, the PHY circuit 304 may be optimized to support various features and standards of HBM, such as data rate, bandwidth, error correction, refresh mode, and / or the like. Depending on the implementation, the circuit 300 may further include one or more features 308, such as power management, thermal management, clock generation, testability, security, and / or the like.

[0059] While the above is a complete description of specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present technology as defined by the appended claims.

Claims

1. A device comprising: a first circuit including a first side, the first side including a first region and a second region, the first circuit including a first interconnect; a second circuit coupled to the first region, the second circuit coupled to the first circuit via the first interconnect; a third circuit coupled to the second region, the third circuit coupled to the first circuit via the first interconnect; a second interconnect coupled to the third circuit; and A fourth circuit is coupled to the third circuit through the second interconnect.

2. The device of claim 1, further comprising a first memory coupled to the second circuit, the second circuit comprising a second memory. 3 . The apparatus of claim 2 , wherein the first memory circuit comprises a first through silicon via (TSV) and the second memory circuit comprises a second TSV, the first TSV being coupled to the second TSV through a micro bump. The apparatus of claim 1 , wherein the third circuit comprises a driver.

5. The apparatus of claim 1, further comprising an interposer including the second interconnect. The apparatus of claim 1 , wherein the fourth circuit comprises a processor.

7. The apparatus of claim 1, wherein the first circuit is coupled to the second circuit by a hybrid copper bond.

8. The apparatus of claim 1, wherein the first circuit is coupled to the third circuit by a hybrid copper bond.

9. The apparatus of claim 1, wherein the third circuit comprises a first physical layer circuit.

10. The apparatus of claim 9, wherein the fourth circuit comprises a second physical layer circuit, the first physical layer circuit being coupled to the second physical layer circuit via the second interconnect.

11. The device according to claim 1, wherein: The first side includes a metal layer; and The first circuit further includes a second side including a silicon layer.

12. The apparatus of claim 1, wherein the first interconnect comprises a bus operating at a first speed, and the first circuit comprises a logic circuit operating at a second speed, the first speed being higher than the second speed.

13. The device according to claim 12, wherein: The third circuit includes a gearbox circuit; The fourth circuit operates at a third speed; and The transmission circuit is configured to match the first speed with the third speed.

14. The device of claim 1, further comprising a die coupled to the third circuit.

15. An apparatus comprising: A first circuit includes a first side and a second side, wherein the first side includes a first area and a second area, The first circuit includes a first interconnect; a second circuit coupled to the first region, the second circuit coupled to the first circuit via the first interconnect; a third circuit coupled to the second region, the third circuit coupled to the first circuit via the first interconnect; an interposer coupled to the second side; and A fourth circuit is coupled to the third circuit through the interposer.

16. The device of claim 15, wherein the first side comprises a metal layer and the second side comprises a silicon layer.

17. The apparatus of claim 15, wherein the third circuit comprises a first physical layer circuit, the fourth circuit comprises a second physical layer circuit, and the first physical layer circuit is coupled to the second physical layer circuit through the interposer.

18. The apparatus of claim 15, wherein the first circuit is coupled to the second circuit by a hybrid copper bond.

19. An apparatus comprising: a first circuit including a first side, the first side including a first region and a second region, the first circuit including a first interconnect; a second circuit coupled to the first region, the second circuit coupled to the first circuit via the first interconnect; a third circuit coupled to the second region, the third circuit comprising a first physical layer circuit; a second interconnect coupled to the third circuit; and A fourth circuit includes a second physical layer circuit coupled to the first physical layer circuit via the second interconnect.

20. The apparatus of claim 19, wherein the first interconnect comprises a bus operating at a first speed and the first circuit comprises a logic circuit operating at a second speed, the first speed being higher than the second speed.

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