Packaging structure and manufacturing method thereof

Abstract

The invention provides a packaging structure and a manufacturing method thereof, and the method comprises the steps: providing a device wafer which at least comprises a substrate, a metal layer and a passivation layer, a first through hole is formed in the passivation layer, and the bottom of the side wall of the first through hole is provided with a side digging region; forming a first photoresist layer, filling the side digging region, and covering the side wall and the bottom of the first through hole and the top of the passivation layer; patterning the first photoresist layer to expose a part of the metal layer at the bottom of the first through hole; forming a seed crystal layer, and covering the patterned first photoresist layer and the metal layer; forming a second photoresist layer, filling the first through hole and covering the seed crystal layer; and patterning the second photoresist layer to expose a part of the seed layer at the bottom of the first through hole. According to the invention, the patterned first photoresist layer fills the side digging area and covers the side wall of the first through hole, so that the side digging morphology of the passivation layer is solved, a continuous and uniform seed crystal layer can be formed, the failure of a subsequent copper electroplating process is avoided, and the packaging yield of a chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a packaging structure and a manufacturing method thereof. Background Art

[0002] After the chip foundry completes chip production, the next key step is chip packaging, which not only provides physical protection for the chip, thereby extending its service life, but more importantly, allows the chip to communicate and interact directly with other systems or devices through packaging, thereby realizing various functions.

[0003] The key to completing the chip connection function in the package is the production of its pins. The most common method is to grow copper pillars by electroplating copper. The growth process of copper pillars mainly includes: wafer cleaning, copper seed crystal growth, photoresist patterning, copper electroplating, and removal of copper seed crystal layer.

[0004] However, due to the limitation of the chip foundry's passivation layer etching process, the bottom of the passivation layer will be hollowed out during the etching process, that is, the bottom of the passivation layer will be hollowed out in the incoming material, which directly affects the packaging process and the integrity of the copper pillar. Please refer to Figure 7 As shown, there is a side hollow at the bottom of the passivation layer 12. The side hollow morphology of the passivation layer 12 makes it difficult to grow a continuous seed crystal layer 14 during the sputtering growth of the seed crystal, and then the equipotential cannot be formed in the electroplating process, resulting in incomplete growth of the subsequent copper column or even no growth, which ultimately affects the packaging yield of the chip. Summary of the invention

[0005] The object of the present invention is to provide a packaging structure and a manufacturing method thereof, which can form a continuous and uniform seed layer, is not affected by the side hollowing morphology of the passivation layer and the surface unevenness, thereby avoiding the failure of the copper electroplating process and improving the packaging yield of the chip.

[0006] In order to solve the above technical problem, according to a first aspect of the present invention, a method for manufacturing a packaging structure is provided, comprising the following steps:

[0007] A device wafer is provided, wherein the device wafer comprises a substrate, an epitaxial layer located on the substrate, a device located on the epitaxial layer, an interconnection structure and a passivation layer located on the device, wherein a plurality of first through holes exposing a metal layer located on a top layer in the interconnection structure are formed in the passivation layer, and a sidewall of the first through hole has a side hollowing region at the bottom;

[0008] Forming a first photoresist layer, wherein the first photoresist layer fills the side-cut region and covers the sidewall and the bottom of the first through hole and the top of the passivation layer;

[0009] Patterning the first photoresist layer to expose a portion of the metal layer at the bottom of the first through hole;

[0010] forming a seed layer, wherein the seed layer covers the patterned first photoresist layer and the exposed metal layer;

[0011] forming a second photoresist layer, wherein the second photoresist layer fills the first through hole and covers the seed crystal layer; and

[0012] The second photoresist layer is patterned to expose a portion of the seed crystal layer at the bottom of the first through hole.

[0013] Optionally, the method for patterning the first photoresist layer includes:

[0014] exposing the first photoresist layer using a first mask;

[0015] The first photoresist layer after exposure is developed to form a patterned first photoresist layer.

[0016] Optionally, the method for patterning the second photoresist layer includes:

[0017] exposing the second photoresist layer using a second mask;

[0018] The second photoresist layer after exposure is developed to form a patterned second photoresist layer.

[0019] Optionally, the first mask and the second mask are the same mask.

[0020] Optionally, the seed crystal layer is a copper seed crystal layer.

[0021] Optionally, a method for forming the seed layer includes: a physical vapor deposition process, an atomic layer deposition process or a vacuum evaporation process.

[0022] Optionally, after patterning the second photoresist layer to form a second through hole in the first through hole, the manufacturing method further includes: forming a conductive column in the second through hole.

[0023] Optionally, after forming the conductive pillars, the manufacturing method further includes: removing the patterned second photoresist layer and the patterned first photoresist layer.

[0024] Optionally, the conductive pillar comprises a copper pillar; and the conductive pillar is formed by an electroplating process.

[0025] In order to solve the above technical problem, according to a second aspect of the present invention, a packaging structure is further provided, which is manufactured by the manufacturing method of the packaging structure as described above.

[0026] Compared with the prior art, the technical solution of the present invention has at least the following technical effects:

[0027] The present invention provides a method for manufacturing a packaging structure, wherein a plurality of first through holes exposing a metal layer are formed in a passivation layer of a device wafer, and the bottom of the side wall of the first through hole has a side-recessed area (that is, the passivation layer has a side-recessed morphology). A first photoresist layer is formed on the device wafer, the first photoresist layer fills the side-recessed area and covers the side wall, the bottom and the top of the passivation layer of the first through hole at the same time, and then the first photoresist layer is patterned to expose a portion of the metal layer at the bottom of the first through hole, the side-recessed area is filled by the patterned first photoresist layer, and the side wall (that is, the side wall of the first through hole) and the top of the passivation layer are also covered by the patterned first photoresist layer, so that the side-recessed morphology and surface unevenness of the passivation layer are solved. When a seed layer is subsequently formed, a continuous and uniform seed layer can be formed, thereby reducing the process difficulty when forming the seed layer, effectively avoiding the influence of morphological defects (side-recessed morphology) caused by process bottlenecks on the growth of the seed layer, avoiding the failure of the subsequent copper electroplating process, and finally improving the packaging yield of the chip. At the same time, the present invention adopts a photoresist material to fill the side-cut area and cover the surface of the passivation layer. The processes of forming, patterning and removing the photoresist material are relatively mature and stable, with relatively high stability and reliability, and will not affect the performance of the packaging structure. In addition, the photoresist material is a commonly used material with low cost. The selection of the photoresist material is conducive to reducing the process difficulty and process cost. The processes of forming, patterning and removing the photoresist material are simple and convenient, and will not affect the production efficiency of the packaging structure.

[0028] In addition, in the present invention, the first mask used when patterning the first photoresist layer and the second mask used when patterning the second photoresist layer are the same mask, and no additional mask manufacturing cost is generated. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 6 It is a schematic diagram of the structures of various steps of a method for manufacturing a packaging structure.

[0030] Figure 7 It is a schematic diagram of the structure after the seed layer is formed when the device wafer has a side-cut morphology.

[0031] Figure 8 It is a schematic flow chart of a method for manufacturing a packaging structure provided by an embodiment of the present invention.

[0032] Figures 9 to 15 It is a schematic structural diagram of each step of a method for manufacturing a packaging structure provided by an embodiment of the present invention.

[0033] Description of reference numerals:

[0034] 10-substrate; 11-metal layer; 12-passivation layer; 13-first through hole; 14-seed layer; 15-second photoresist layer; 16-patterned second photoresist layer; 17-second through hole; 18-conductive column; 19-first photoresist layer; 20-patterned first photoresist layer. DETAILED DESCRIPTION

[0035] Figures 1 to 6 This is a schematic diagram of the steps of a packaging structure manufacturing method. First, please refer to Figure 1 As shown, a device wafer is provided, the device wafer comprising a substrate 10, a metal layer 11 and a passivation layer 12 sequentially located on the substrate 10, and a plurality of first through holes 13 exposing the metal layer 11 are formed in the passivation layer 12. In this embodiment, the device wafer is provided by a chip foundry, and the device wafer needs to be cleaned.

[0036] Please refer to Figure 2 As shown, a seed layer 14 is formed, and the seed layer 14 covers the sidewall and the bottom of the first through hole 13 and the top of the passivation layer 12. In this embodiment, the seed layer 14 is a copper seed layer.

[0037] Next, please refer to Figure 3 As shown, a second photoresist layer 15 is formed, and the second photoresist layer 15 fills the first through hole 13 and covers the seed crystal layer 14, that is, the second photoresist layer 15 covers the entire device wafer.

[0038] Then, please refer to Figure 4 As shown, the second photoresist layer 15 is patterned to form a patterned second photoresist layer 16, the patterned second photoresist layer 16 exposes a portion of the bottom of the first through hole 13, and a second through hole 17 is formed in the first through hole 13. In this embodiment, the second through hole 17 exposes a portion of the seed layer 14 at the bottom of the first through hole 13. The second photoresist layer 15 can be patterned by using an exposure and development method. Exemplarily, the second photoresist layer 15 is exposed using a mask, and the exposed second photoresist layer 15 is developed to remove a portion of the second photoresist layer 15, so as to form a patterned second photoresist layer 16 having a second through hole 17.

[0039] Afterwards, please refer to Figure 5 As shown, a conductive column 18 is formed in the second through hole 17. In this embodiment, the conductive column 18 is a copper column, which can be formed by electroplating.

[0040] Next, please refer to Figure 5 and Figure 6As shown, the patterned second photoresist layer 16 is removed, and finally a conductive column 18 is formed in the first through hole 13 and electrically connected to the metal layer 11 .

[0041] However, due to the limitations of the chip foundry's passivation layer 12 etching process, in the process of etching the passivation layer 12 to form the first through hole 13 exposing the metal layer 11, a side hollow will be formed at the bottom of the passivation layer 12, that is, a side hollow area will be formed at the bottom of the side wall of the first through hole 13, and the side wall surface of the first through hole 13 will also be uneven.

[0042] Figure 7 This is a schematic diagram of the structure after the seed layer is formed when the device wafer has a side-cut morphology. Please refer to Figure 7 As shown, there is a side-cut region at the bottom of the side wall of the first through hole 13, which can also be said that the passivation layer 12 has a side-cut morphology. In the process of forming the seed layer 14, due to the existence of the side-cut region, the seed layer 14 will be discontinuous, and since the side wall of the first through hole 13 is uneven, the seed layer 14 formed on the side wall of the first through hole 13 will also be uneven.

[0043] Subsequently, it is necessary to form a conductive column 18 on the seed layer 14 in the second through hole 17 by electroplating. The basic principle of the electroplating process is to deposit a layer of metal on the surface of the metal to be plated by electrolysis. Specifically, during electroplating, a dielectric solution containing plating metal ions is generally used as an electroplating solution, and the metal product to be plated is immersed in the electroplating solution and connected to the negative electrode of the DC power supply as the cathode, and the plating metal is used as the anode. The anode metal dissolves in the solution to become a cation, moves to the cathode and is reduced to metal precipitation on the cathode. This process can be summarized as "anode dissolution, cathode deposition, and unchanged electrolyte". In the process of copper electroplating, the anode is a pure copper plate, which is connected to the positive electrode of the DC power supply, and the cathode is the metal product to be plated, which in this embodiment is a device wafer after the patterned second photoresist layer 16 is formed, and is connected to the negative electrode of the power supply. The electrolyte is usually a copper sulfate solution containing copper ions. After power is turned on, copper ions obtain electrons at the cathode and are reduced to copper ions, and are deposited on the cathode surface to form a coating. In this embodiment, copper ions are deposited on the seed layer 14 exposed by the patterned second photoresist layer 16 to form a conductive column 18. At the same time, the copper plate on the anode loses electrons and becomes copper ions and enters the electrolyte, maintaining the concentration of copper ions in the electrolyte unchanged.

[0044] like Figure 7As shown, due to the discontinuity of the seed layer 14, part of the seed layer 14 cannot be connected to the negative electrode of the power supply. If the seed layer 14 that cannot be connected to the negative electrode of the power supply is exposed at the bottom of the second through hole 17, the conductive pillar 18 cannot be electroplated on the part of the seed layer 14. Therefore, the conductive pillar 18 will not grow completely or even not grow, thereby affecting the chip packaging yield.

[0045] In view of the above problems, the inventor has found through research that, in the case where the bottom of the side wall of the first through hole of the device wafer provided has a side-recessed area, a photoresist layer can be formed first, the photoresist layer fills the side-recessed area and covers the side wall, the bottom and the top of the passivation layer of the first through hole at the same time, and then the photoresist layer is patterned to expose part of the metal layer at the bottom of the first through hole, and then a seed layer is formed. The side-recessed area is filled with the patterned photoresist layer, and the side wall and the top of the passivation layer are also covered by the patterned photoresist layer, so that the side-recessed morphology and surface unevenness of the passivation layer are solved. When the seed layer is subsequently formed, a continuous and uniform seed layer can be formed, thereby reducing the process difficulty when forming the seed layer, effectively avoiding the influence of the morphological defects (side-recessed morphology) caused by the process bottleneck on the growth of the seed layer, avoiding the failure of the subsequent copper electroplating process, and finally improving the packaging yield of the chip.

[0046] After further research, the present invention provides a method for manufacturing a packaging structure, comprising the following steps: providing a device wafer, the device wafer comprising a substrate, an epitaxial layer located on the substrate, a device located on the epitaxial layer, an interconnection structure and a passivation layer located on the device, a plurality of first through holes exposing a metal layer located at the top layer in the interconnection structure are formed in the passivation layer, and the bottom of the side wall of the first through hole has a side-recessed area; forming a first photoresist layer, the first photoresist layer fills the side-recessed area and covers the side wall, the bottom and the top of the passivation layer of the first through hole; patterning the first photoresist layer to expose a portion of the metal layer at the bottom of the first through hole; forming a seed layer, the seed layer covers the patterned first photoresist layer and the exposed metal layer; forming a second photoresist layer, the second photoresist layer fills the first through hole and covers the seed layer; and patterning the second photoresist layer to expose a portion of the copper seed layer at the bottom of the first through hole.

[0047] Correspondingly, the present invention also provides a packaging structure, which is manufactured using the manufacturing method of the packaging structure as described above.

[0048] In the packaging structure and manufacturing method provided by the present invention, a plurality of first through holes exposing a metal layer are formed in the passivation layer of the device wafer, and the bottom of the side wall of the first through hole has a side-recessed area (that is, the passivation layer has a side-recessed morphology). A first photoresist layer is formed on the device wafer, the first photoresist layer fills the side-recessed area and covers the side wall, the bottom and the top of the passivation layer of the first through hole at the same time. Then, the first photoresist layer is patterned to expose part of the metal layer at the bottom of the first through hole. The side-recessed area is filled by the patterned first photoresist layer, and the side wall (that is, the side wall of the first through hole) and the top of the passivation layer are also covered by the patterned first photoresist layer, so that the side-recessed morphology and surface unevenness of the passivation layer are solved. When a seed layer is subsequently formed, a continuous and uniform seed layer can be formed, thereby reducing the process difficulty when forming the seed layer, effectively avoiding the influence of morphological defects (side-recessed morphology) caused by process bottlenecks on the growth of the seed layer, avoiding the failure of the subsequent copper electroplating process, and finally improving the packaging yield of the chip. At the same time, the present invention adopts a photoresist material to fill the side-cut area and cover the surface of the passivation layer. The processes of patterning and removing the photoresist material are relatively mature, with relatively high stability and reliability, and will not affect the performance of the packaging structure. In addition, the photoresist material is a commonly used and low-cost material. The selection of the photoresist material is conducive to reducing the process difficulty and process cost. The processes of forming, patterning and removing the photoresist material are simple and convenient, and will not affect the production efficiency of the packaging structure.

[0049] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0050] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0051] Figure 8 FIG. 1 is a flow chart of a method for manufacturing a packaging structure provided by an embodiment of the present invention. Figure 8 As shown, the method for manufacturing the packaging structure includes the following steps:

[0052] S1: providing a device wafer, wherein the device wafer comprises a substrate, an epitaxial layer located on the substrate, a device located on the epitaxial layer, an interconnection structure and a passivation layer located on the device, wherein a plurality of first through holes exposing a metal layer located on a top layer in the interconnection structure are formed in the passivation layer, and a bottom of a side wall of the first through hole has a side hollowing region;

[0053] S2: forming a first photoresist layer, wherein the first photoresist layer fills the side-cut region and covers the sidewall and the bottom of the first through hole and the top of the passivation layer;

[0054] S3: patterning the first photoresist layer to expose a portion of the metal layer at the bottom of the first through hole;

[0055] S4: forming a seed layer, wherein the seed layer covers the patterned first photoresist layer and the exposed metal layer;

[0056] S5: forming a second photoresist layer, wherein the second photoresist layer fills the first through hole and covers the seed crystal layer; and

[0057] S6: patterning the second photoresist layer to expose a portion of the copper seed crystal layer at the bottom of the first through hole.

[0058] Figures 9 to 15 FIG. 1 is a schematic diagram of the steps of a method for manufacturing a packaging structure according to an embodiment of the present invention. Figure 8 and Figures 9 to 15 The manufacturing method of the packaging structure provided by the embodiment of the present invention is described in detail.

[0059] In step S1, refer to Fig. 9 As shown, a device wafer is provided, which includes a substrate 10, an epitaxial layer located on the substrate, a device located on the epitaxial layer, an interconnection structure and a passivation layer 12 located on the device, wherein a plurality of first through holes 13 exposing a metal layer 11 located on the top layer of the interconnection structure are formed in the passivation layer 12, and the bottom of the side wall of the first through hole 13 has a side hollow area.

[0060] In this embodiment, the material of the substrate 10 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, etc., or silicon on insulator, germanium on insulator; or it can also be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the substrate 10 is a silicon substrate. An epitaxial layer (not shown) is formed on the substrate 10, and a plurality of devices (not shown) are formed on the epitaxial layer. Various devices, such as transistors, capacitors, resistors and similar components, can be formed on the surface of the epitaxial layer by any suitable method. Of course, some devices can also be formed in the epitaxial layer.

[0061] An interconnect structure is formed on the device, and the interconnect structure is used to connect various devices to form a functional circuit. The interconnect structure can be formed by alternating dielectric layers and metal layers, and can be formed by any suitable process (such as deposition, inlay, dual inlay, etc.). The metal layer 11 is the top metal layer in the interconnect structure. Fig. 9 Only the metal layer 11 in the interconnect structure is shown.

[0062] The passivation layer 12 is formed on the metal layer 11, and the passivation layer 12 may include a dielectric material, such as silicon oxide or silicon nitride, or other suitable dielectrics, such as high dielectric constant dielectrics or any combination of these materials. The passivation layer 12 may be formed by any suitable process known to those skilled in the art, such as atomic layer deposition process, chemical vapor deposition process, physical vapor deposition process, etc. In one embodiment of the present invention, the passivation layer 12 includes a silicon oxide layer and a silicon nitride layer, the silicon oxide layer covers the metal layer 11, and the silicon nitride layer covers the silicon oxide layer.

[0063] Afterwards, the passivation layer 12 needs to be etched to form a first through hole 13 exposing the metal layer 11. Exemplarily, a patterned mask layer is formed on the passivation layer 12, and the passivation layer 12 is etched using the patterned mask layer as a mask until the metal layer 11 is exposed, and then the patterned photoresist layer is removed. The patterned mask layer can be a hard mask layer or a photoresist layer.

[0064] However, due to the poor bonding strength between the passivation layer 12 and the metal layer 11, during the process of etching the passivation layer 12 using the patterned mask layer as a mask, the bottom of the first through hole 13 is etched laterally to form a side hollowing area. In addition, due to the characteristics of the passivation layer 12 itself, the side wall of the first through hole 13 will have a relatively high roughness and an uneven surface during the etching process.

[0065] In step S2, please refer to Fig.10 As shown, a first photoresist layer 19 is formed, and the first photoresist layer 19 fills the undercut area and covers the sidewall and bottom of the first through hole 13 and the top of the passivation layer 12 .

[0066] The first photoresist layer 19 fills the undercut area and conformally covers the device wafer. In this embodiment, the first photoresist layer 19 can be formed by a spin coating process.

[0067] In this embodiment, a photoresist material is used to fill the side-cut area and cover the surface of the passivation layer 12 to solve the problem of side-cut morphology and uneven surface of the passivation layer. Although compared with the prior art, the formation of the first photoresist layer 19, and the subsequent patterning of the first photoresist layer 19 and the removal of the patterned first photoresist layer and other process steps are added, however, since the formation, patterning and removal of the photoresist material are relatively mature and stable, with relatively high stability and reliability, on the basis of solving the above technical problems, it will not affect the performance of the packaging structure; in addition, the photoresist material is a commonly used material with low cost in the process, and the selection of the photoresist material is conducive to reducing the process difficulty and process cost, and the formation, patterning and removal of the photoresist material are simple and convenient, and will not affect the production efficiency of the packaging structure.

[0068] In one embodiment of the present invention, the thickness of the first photoresist layer 19 is at least greater than the dimension of the undercut region in a direction parallel to the surface of the device wafer (ie Fig.10 The first photoresist layer 19 has a size in the horizontal direction, so that the first photoresist layer 19 can fill the side-cut area. If the thickness of the first photoresist layer 19 is too thin, the first photoresist layer 19 cannot completely fill the side-cut area. In the subsequent process of forming the seed layer, the seed layer is prone to film discontinuity in the side-cut area. Of course, the thickness of the first photoresist layer 19 cannot be too thick. If the thickness is too thick, it takes too much time and process to form the first photoresist layer 19. The subsequent patterning of the first photoresist layer 19 and removal of the patterned first photoresist layer also take too much process time, resulting in low manufacturing efficiency of the packaging structure.

[0069] In step S3, please refer to Fig.11 As shown, the first photoresist layer 19 is patterned to expose a portion of the metal layer 11 at the bottom of the first through hole 13 .

[0070] Exemplarily, the first photoresist layer 19 is first exposed using a first mask, and then the exposed first photoresist layer 19 is developed to form a patterned first photoresist layer 20. The patterned first photoresist layer 20 exposes a portion of the metal layer 11 at the bottom of the first through hole 13.

[0071] In one embodiment of the present invention, the first mask may be an existing mask, such as Figure 3 and Figure 4 The mask used when patterning the second photoresist layer 15 is used, so patterning the first photoresist layer 19 does not incur additional mask manufacturing costs.

[0072] In one embodiment of the present invention, please refer to Fig.11 As shown, the patterned first photoresist layer 20 fills the side-cut area and covers the sidewall and top of the passivation layer 12 (or covers the sidewall of the first through hole 13 and the top of the passivation layer 12), and the bottom of the first through hole 13 includes the side-cut area, the area covered by the patterned first photoresist layer 20 on the sidewall extending to the bottom, and the central area. In this embodiment, all of the first photoresist layer 19 in the central area can be removed, and the first photoresist layer 19 in part of the central area can also be removed.

[0073] In step S4, please refer to Fig.12 As shown, a seed layer 14 is formed, and the seed layer 14 covers the patterned first photoresist layer 20 and the exposed metal layer 11 .

[0074] The seed layer 14 is formed on the patterned first photoresist layer 20 and the metal layer 11 and is not affected by the undercut area, so that the film layer of the seed layer 14 is continuous and has a flat surface.

[0075] In this embodiment, the seed layer 14 is a copper seed layer. The seed layer 14 can be formed by a physical vapor deposition process. The physical vapor deposition process has the advantages of low deposition temperature, fast deposition speed, controllable composition and structure of the deposition layer, simple operation, high efficiency and low cost, and dense film formation, and the physical vapor deposition process is highly compatible with existing machines and process flows. In other embodiments, the seed layer 14 can also be formed by an atomic layer deposition process or a vacuum evaporation process. The atomic layer deposition process has the advantages of accurately controlling the thickness of the film, improving the uniformity and consistency of the film, enhancing the adhesion between materials, and adapting to low-temperature deposition. The vacuum evaporation process has the advantages of high film purity and good density, simple film formation method, and fast growth rate. The method for forming the seed layer 14 can be determined according to the specific requirements for the seed layer 14 and the actual process conditions. In another embodiment, the material of the seed layer 14 can also include at least one of gold, silver, copper palladium, chromium, molybdenum, titanium, tantalum, tin, tungsten and aluminum.

[0076] In step S5, please refer to Fig.13 As shown, a second photoresist layer 15 is formed, and the second photoresist layer 15 fills the first through hole 13 and covers the seed layer 14 .

[0077] The second photoresist layer 15 may be formed by a spin coating process. The second photoresist layer 15 has a certain thickness and covers the entire device wafer.

[0078] In step S6, please refer to Fig.13 and Fig.14 As shown, the second photoresist layer 15 is patterned to expose a portion of the seed layer 14 at the bottom of the first through hole 13 .

[0079] Exemplarily, the second photoresist layer 15 is first exposed using a second mask, and then the exposed second photoresist layer 15 is developed to form a patterned second photoresist layer 16. The patterned second photoresist layer 16 exposes a portion of the seed layer 14 at the bottom of the first through hole 13, and a second through hole 17 is formed in the first through hole 13.

[0080] In one embodiment of the present invention, the first mask and the second mask are the same mask, and there is no additional mask production cost. If the first mask and the second mask are the same mask, the bottom of the seed layer 14 exposed by the patterned second photoresist layer 16 does not have the first photoresist layer 19 remaining, that is, the area exposed by the patterned first photoresist layer 20 is the same as the area exposed by the patterned second photoresist layer 16.

[0081] In another embodiment of the present invention, the first mask and the second mask may also be different masks, that is, the area exposed by the patterned first photoresist layer 20 is not the same as the area exposed by the patterned second photoresist layer 16, and the area exposed by the patterned first photoresist layer 20 may be larger than the area exposed by the patterned second photoresist layer 16, or may be smaller than the area exposed by the patterned second photoresist layer 16, which can be determined according to actual needs. Of course, the area exposed by the patterned first photoresist layer 20 and the area exposed by the patterned second photoresist layer 16 are both located in the first through hole 13.

[0082] Please refer to Fig.15 As shown, after forming the patterned second photoresist layer 16, the manufacturing method further includes: forming a conductive column 18 in the second through hole 17. In this embodiment, the material of the conductive column 18 includes but is not limited to at least one of gold, silver, copper, palladium, chromium, molybdenum, titanium, tantalum, tin, tungsten and aluminum. The conductive column 18 is the same as the material of the seed layer 14. Exemplarily, the material of the conductive column 18 is copper, and the conductive column 18 can be formed by an electroplating process.

[0083] In the copper electroplating process, the anode is a pure copper plate connected to the positive electrode of the DC power supply, and the cathode is the device wafer after the patterned second photoresist layer 16 is formed. Fig.14 In the structure shown, the seed layer 14 is connected to the negative electrode of the power supply. The electrolyte is a copper sulfate solution containing copper ions. After power is turned on, the copper ions obtain electrons at the cathode and are reduced to copper ions, and are deposited on the seed layer 14 at the bottom of the second through hole 17 to form a conductive column 18. Since the seed layer 14 is continuous and has a flat surface, it can ensure that the conductive column 18 grows completely.

[0084] Please continue to refer to Fig.15 As shown, after the conductive pillar 18 is formed in the second through hole 17, the manufacturing method further includes: removing the patterned second photoresist layer 16 and the patterned first photoresist layer 20. Exemplarily, any suitable process such as an ashing process or a wet etching process can be used to remove the patterned second photoresist layer 16 and the patterned first photoresist layer 20. Of course, the seed layer 14 not covered by the conductive pillar 18 is also removed.

[0085] The present invention provides a method for manufacturing a packaging structure, wherein a plurality of first through holes 13 exposing a metal layer 11 are formed in a passivation layer 12 of a device wafer, and the bottom of the side wall of the first through hole 13 has a side-recessed area (that is, the passivation layer has a side-recessed morphology), and a first photoresist layer 19 is formed on the device wafer, the first photoresist layer 19 fills the side-recessed area and covers the side wall, the bottom and the top of the passivation layer 12 of the first through hole 13, and then the first photoresist layer 19 is patterned to expose a portion of the metal layer 11 at the bottom of the first through hole 13, and the side-recessed area The domain is filled with the patterned first photoresist layer 20, and the side walls (i.e., the side walls of the first through hole) and the top of the passivation layer 12 are also covered by the patterned first photoresist layer 20, so that the side-concave morphology and surface unevenness of the passivation layer 12 are solved. When the seed layer 14 is subsequently formed, a continuous and uniform seed layer 14 can be formed, thereby reducing the process difficulty when forming the seed layer 14, effectively avoiding the influence of morphological defects (side-concave morphology) caused by process bottlenecks on the growth of the seed layer 14, avoiding the failure of the subsequent copper electroplating process, and ultimately improving the packaging yield of the chip. At the same time, the present invention uses a photoresist material to fill the side-cut area and cover the surface of the passivation layer 12. The processes of forming, patterning and removing the photoresist material are relatively mature and stable, with relatively high stability and reliability, and will not affect the performance of the packaging structure. In addition, the photoresist material is a commonly used and low-cost material. The selection of the photoresist material is conducive to reducing the process difficulty and process cost. The processes of forming, patterning and removing the photoresist material are simple and convenient, and will not affect the production efficiency of the packaging structure.

[0086] In addition, in the present invention, the first mask used when patterning the first photoresist layer 19 and the second mask used when patterning the second photoresist layer 15 are the same mask, and there is no additional mask manufacturing cost.

[0087] Correspondingly, the present invention also provides a packaging structure, which is manufactured using the manufacturing method of the packaging structure as described above.

[0088] Please refer to Fig.15 As shown, the packaging structure includes:

[0089] A substrate 10, an epitaxial layer (not shown) located on the substrate, a device (not shown) located on the epitaxial layer, an interconnection structure and a passivation layer 12 located on the device, wherein the passivation layer 12 is formed with a plurality of first through holes 13 exposing a metal layer 11 located at a top layer in the interconnection structure, and the bottom of the side wall of the first through hole 13 has a side hollowing area;

[0090] The conductive column 18 is located in the first through hole 13 and is electrically connected to the metal layer 11 .

[0091] In one embodiment of the present invention, the material of the conductive pillar 18 includes but is not limited to at least one of gold, silver, copper, palladium, chromium, molybdenum, titanium, tantalum, tin, tungsten and aluminum. Exemplarily, the material of the conductive pillar 18 is copper.

[0092] In summary, in the packaging structure and the manufacturing method thereof provided by the present invention, a plurality of first through holes exposing the metal layer are formed in the passivation layer of the device wafer, and the bottom of the side wall of the first through hole has a side-recessed area (that is, the passivation layer has a side-recessed morphology), and a first photoresist layer is formed on the device wafer, the first photoresist layer fills the side-recessed area and covers the side wall, the bottom and the top of the passivation layer of the first through hole at the same time, and then the first photoresist layer is patterned to expose part of the metal layer at the bottom of the first through hole, and the side-recessed area is formed on the device wafer. The area is filled with the patterned first photoresist layer, and the sidewalls (i.e., the sidewalls of the first through hole) and the top of the passivation layer are also covered by the patterned first photoresist layer, so that the side-cut morphology and surface unevenness of the passivation layer are solved. When the seed layer is subsequently formed, a continuous and uniform seed layer can be formed, thereby reducing the process difficulty when forming the seed layer, effectively avoiding the influence of the morphological defects (side-cut morphology) caused by the process bottleneck on the growth seed layer, avoiding the failure of the subsequent copper electroplating process, and finally improving the chip packaging yield. At the same time, the present invention adopts a photoresist material to fill the side-cut area and cover the surface of the passivation layer. The formation, patterning and removal of the photoresist material are relatively mature and stable, with relatively high stability and reliability, and will not affect the performance of the packaging structure; in addition, the photoresist material is a commonly used material with low cost in the process. The selection of the photoresist material is conducive to reducing the process difficulty and process cost. The formation, patterning and removal of the photoresist material are simple and convenient, and will not affect the production efficiency of the packaging structure.

[0093] In addition, in the present invention, the first mask used when patterning the first photoresist layer and the second mask used when patterning the second photoresist layer are the same mask, and no additional mask manufacturing cost is generated.

[0094] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a packaging structure, characterized in that: The following steps are involved: A device wafer is provided, wherein the device wafer comprises a substrate, an epitaxial layer located on the substrate, a device located on the epitaxial layer, an interconnection structure and a passivation layer located on the device, wherein a plurality of first through holes exposing a metal layer located on a top layer in the interconnection structure are formed in the passivation layer, and a sidewall of the first through hole has a side hollowing region at the bottom; Forming a first photoresist layer, wherein the first photoresist layer fills the side-cut region and covers the sidewall and the bottom of the first through hole and the top of the passivation layer; Patterning the first photoresist layer to expose a portion of the metal layer at the bottom of the first through hole; forming a seed layer, wherein the seed layer covers the patterned first photoresist layer and the exposed metal layer; forming a second photoresist layer, wherein the second photoresist layer fills the first through hole and covers the seed crystal layer; as well as The second photoresist layer is patterned to expose a portion of the seed crystal layer at the bottom of the first through hole.

2. The method for manufacturing a packaging structure according to claim 1, characterized in that: The method for patterning the first photoresist layer includes: exposing the first photoresist layer using a first mask; The first photoresist layer after exposure is developed to form a patterned first photoresist layer.

3. The method for manufacturing a packaging structure according to claim 2, characterized in that: The method for patterning the second photoresist layer includes: exposing the second photoresist layer using a second mask; The second photoresist layer after exposure is developed to form a patterned second photoresist layer.

4. The method for manufacturing a packaging structure according to claim 3, characterized in that: The first mask and the second mask are the same mask.

5. The method for manufacturing a packaging structure according to claim 1, characterized in that: The seed crystal layer is a copper seed crystal layer.

6. The method for manufacturing a packaging structure according to claim 5, characterized in that: The method of forming the seed layer includes: physical vapor deposition process, atomic layer deposition process or vacuum evaporation process.

7. The method for manufacturing a packaging structure according to any one of claims 1 to 6, characterized in that: After patterning the second photoresist layer to form a second through hole in the first through hole, the manufacturing method further includes: forming a conductive column in the second through hole.

8. The method for manufacturing a packaging structure according to claim 7, characterized in that: After forming the conductive pillars, the manufacturing method further includes: removing the patterned second photoresist layer and the patterned first photoresist layer.

9. The method for manufacturing a packaging structure according to claim 7, characterized in that: The conductive pillars include copper pillars; and the conductive pillars are formed by an electroplating process.

10. A packaging structure, characterized in that: The packaging structure is manufactured by the manufacturing method of any one of claims 1 to 9.

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