Wafer level packaging method for filling supporting material before bonding and chip structure

Abstract

The invention discloses a wafer-level packaging method for filling a supporting material before bonding and a chip structure, and the method comprises the steps: providing a first wafer and a second wafer, the first wafer is provided with a plurality of chip modules, and at least a part of the chip modules are provided with a sealing function region exposed on the first surface of the first wafer; connecting parts surrounding at least part of the periphery of the sealing function area are formed on the first surface, and a cutting channel cavity is formed between every two adjacent connecting parts; the cutting channel cavity is filled with a supporting material; the wafer-level packaging structure formed by bonding the connecting part and the second wafer is not easy to crack and damage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging and testing, and in particular to a wafer-level packaging method for filling supporting materials before bonding and a chip structure. Background Art

[0002] Traditional chip packaging is to fix the pre-processed and divided single chip in the packaging tube shell, connect the contacts on the chip with the electrical pins on the packaging tube shell through wire bonding technology, and finally fill it with insulating packaging materials or add a cover plate to seal it. With the development of semiconductor manufacturing technology, wafer level packaging (WLP) has been developed to improve integration and reduce chip manufacturing costs. This technology is a technology that packages and tests the entire wafer and then cuts it to obtain a single finished chip.

[0003] Wafer-level packaging technology includes wafer bonding technology. More and more semiconductor devices are beginning to use bonding to achieve the purpose of pre-bonding protection of devices, functional device stacking, etc., and bonding is often no longer 100% flat bonding, but through pre-processing of the bonding surface, a cavity structure is formed. From a simple metal bonding layer cavity of a few microns to a silicon cavity of tens or hundreds of microns, the cutting path area forms a pipeline cavity structure that runs horizontally and vertically.

[0004] The existence of such cut-way cavities has a great impact on subsequent packaging. For chip-level packaging, cutting is generally performed first, followed by chip-level packaging. In this case, only the impact of cutting needs to be considered, such as the risk of breakage and cracks in the bonding layer. For wafer-level packaging, the existence of cut-way cavities will bring more problems and troubles:

[0005] Grinding thinning and cracking: This risk mainly exists at the edge of the wafer. Since grinding is a grinding process with great pressure, the edge, which has no support structure, is very likely to cause wafer fracture.

[0006] Cutting line corrosion: Due to the existence of the pipeline cavity, the liquid of the wet process flows into the pipeline cavity, which will cause cutting line corrosion, destroy the bonding layer structure and the internal circuit of the chip, and eventually lead to serious problems such as wafer cavity explosion and chip function damage.

[0007] Cutting abnormality: When discussing the use of a wafer knife to cut Si and other materials, in order to achieve a better back collapse effect, it is necessary to select a suitable tape to adhere and support the back of the material to reduce the vibration during the cutting process and the force of pulling the cutting interface material. However, the state of the cutting cavity is exactly zero support, and the rigidity of the material is completely relied on to resist the pulling and vibration of the blade. Therefore, the size of the back collapse will be very difficult to control, and may even cause the entire material layer to break during the cutting process, or cause the crack to extend to the inside of the circuit, causing the chip to fail.

[0008] In the prior art, after wafer bonding, the glue is added to the edge to make the glue flow into the cutting path cavity to achieve the purpose of support. However, it is difficult to control the extent to which the glue is added into the cutting path. Considering that the glue cannot produce obvious volatile gas, the material usually selected will not have good fluidity, so the distance it can penetrate from the edge to the inside is limited, and most of the middle area cannot be filled with glue, so the support effect is limited. Summary of the invention

[0009] One of the purposes of the present invention is to provide a wafer-level packaging method for filling a supporting material before bonding, so as to solve the technical problem of poor support effect of the saw path cavity in the prior art.

[0010] One of the objectives of the present invention is to provide a chip structure.

[0011] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a wafer-level packaging method for filling a supporting material before bonding, comprising the following steps:

[0012] Providing a first wafer and a second wafer, wherein the first wafer is provided with a plurality of chip modules, and at least some of the chip modules have a sealing functional area exposed to a first surface of the first wafer;

[0013] A connection portion is formed on the first surface and is arranged around at least a portion of the outer periphery of the sealing functional area, and a cutting path cavity is formed between adjacent connection portions;

[0014] Filling the cutting path cavity with support material;

[0015] The connecting portion and the second wafer are bonded to form a wafer-level packaging structure.

[0016] As a further improvement of an embodiment of the present invention, along a thickness direction of the wafer-level packaging structure, the filling portion connects the first wafer and the second wafer.

[0017] As a further improvement of an embodiment of the present invention, the supporting material is at least one of photoresist, epoxy resin glue, and UV glue.

[0018] As a further improvement of an embodiment of the present invention, the supporting material is a photoresist, and “filling the cutting path cavity with the supporting material” comprises the steps of:

[0019] Applying photoresist on the first surface of the first wafer;

[0020] Expose and develop to form a photoresist protrusion protruding out of the connecting portion in the cutting path cavity;

[0021] The photoresist protrusions are ground so that they do not protrude from the connecting portion.

[0022] As a further improvement of one embodiment of the present invention, the supporting material is epoxy resin glue or UV glue, and "filling the cutting path cavity with supporting material" includes the steps of: filling the cutting path cavity with epoxy resin glue or UV glue by dispensing.

[0023] As a further improvement of an embodiment of the present invention, the dicing street cavities in all regions of the first wafer are filled with supporting materials.

[0024] As a further improvement of an embodiment of the present invention, the step includes: cutting the corresponding cutting path cavities to form a plurality of independent chip structures.

[0025] As a further improvement of one embodiment of the present invention, the cutting road cavity includes a plurality of transverse cutting roads that penetrate horizontally and a plurality of longitudinal cutting roads that penetrate longitudinally, wherein the transverse and longitudinal directions are horizontal and perpendicular to each other; a plurality of the transverse cutting roads are arranged along the longitudinal direction, and a plurality of the longitudinal cutting roads are arranged along the transverse direction, and the transverse cutting roads and the longitudinal cutting roads are cross-connected.

[0026] As a further improvement of an embodiment of the present invention, the width of the transverse cutting road and / or the longitudinal cutting road is in the range of 40 mm to 200 mm.

[0027] As a further improvement of one embodiment of the present invention, the first wafer is provided with the chip module and the connecting part, the second wafer has a substrate and a circuit layer arranged on the substrate, the surface of the circuit layer is bonded to the connecting part, and the cutting path cavity corresponds to the non-functional area of ​​the circuit layer.

[0028] As a further improvement of an embodiment of the present invention, “bonding the connection portion to the second wafer” comprises the steps of:

[0029] The connection portion and the second wafer are connected by dielectric bonding or non-dielectric bonding, and the wafer-level packaging structure includes a bonding layer arranged between the connection portion and the second wafer.

[0030] To achieve one of the above-mentioned objects of the invention, an embodiment of the present invention provides a chip structure, using a wafer-level packaging method of filling supporting materials before bonding as described in any of the above items, wherein the chip structure is formed by cutting the cutting path cavity of the wafer-level packaging structure.

[0031] Compared with the prior art, the present invention provides a wafer-level packaging method for filling supporting materials before bonding, wherein the supporting material is first filled in the cutting line cavity, which has good supporting properties, and then the first wafer and the second wafer are bonded and connected. The formed wafer-level packaging structure is not easily damaged during the cutting process. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1-2 The present invention relates to a wafer-level packaging method for forming a chip structure in one embodiment of the present invention.

[0033] Figure 3 FIG. 4 is a schematic plan view of a first wafer in one embodiment of the present invention.

[0034] Figure 4 1 is a plan view of a wafer-level packaging structure in one embodiment of the present invention.

[0035] Figure 5 4 is a schematic cross-sectional view of a wafer-level packaging structure in one embodiment of the present invention.

[0036] Figure 6 Schematic diagram of a chip structure in one embodiment of the present invention.

[0037] Figure 7 It is a cross-sectional schematic diagram of a chip structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0039] It should be noted that the term "comprises" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In addition, the terms "first", "second", "third", "fourth", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0040] The terms "connected", "connected to" or any other variants are intended to cover various relative positions in a connection relationship, so as to include direct connection or indirect connection. Among them, the direct connection can be formed by a gas pipeline, the indirect connection can be a connection relationship established by a device such as a valve body, a sensor, etc., can be a connection relationship established by a gas circuit component such as a brake control unit, or can be a connection relationship established by any other medium such as air.

[0041] See also Figure 1-2 , a wafer-level packaging method for filling a supporting material before bonding provided by an embodiment of the present invention comprises the steps of:

[0042] S1: providing a first wafer 100 and a second wafer 200 , wherein the first wafer 100 is provided with a plurality of chip modules 30 , and at least part of the chip modules 30 has a sealing functional area 310 exposed to a first surface 110 of the first wafer 100 .

[0043] The second wafer 200 has a substrate and a circuit layer 210 disposed on the substrate. The circuit layer 210 includes a functional area and a non-functional area.

[0044] The first wafer 100 can be made by semiconductor manufacturing technology, for example, forming N-type metal oxide semiconductor devices and P-type metal oxide semiconductor devices on a semiconductor substrate by deposition, etching and other processes, and forming a dielectric layer, a metal interconnection structure and a pad electrically connected to the metal interconnection on the device. The first wafer 100 can be made of third-generation semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium nitride or indium gallium.

[0045] The second wafer 200 can be made by semiconductor manufacturing technology, for example, forming N-type metal oxide semiconductor devices and P-type metal oxide semiconductor devices on a semiconductor substrate by deposition, etching and other processes, and forming a dielectric layer, a metal interconnection structure and a pad electrically connected to the metal interconnection junction on the device. The second wafer 200 can be: lithium tantalate (LiTaO3), lithium niobate (LiNbO3), silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-side polished silicon wafers (Double Side Polished Wafers, DSP).

[0046] The chip module 30 includes at least one chip, and the multiple chips can be chips with the same function; or, the multiple chips include at least two chips with different functions. The chip includes at least one of a logic chip, a memory chip, a central processing unit chip, a microprocessor chip, and an analog-to-digital conversion chip, or the chip includes at least one MEMS chip of a microphone, a pressure sensor, a speed sensor, an acceleration sensor, and a filter, a sensor chip that senses one of a radio frequency signal, an infrared radiation signal, a visible light signal, an acoustic wave signal, and an electromagnetic wave signal, etc.

[0047] The chip module 300 can be only set on the first wafer 100, the first wafer 100 is a functional wafer, and the second wafer 200 is a cover wafer; or only set on the second wafer 200, the second wafer 200 is a functional wafer, and the first wafer 100 is a cover wafer; or set on the first wafer 100 and the second wafer 200 at the same time, the first wafer 100 and the second wafer 200 are both functional wafers, and form each other's cover wafers; in actual applications, it can be adjusted according to process requirements.

[0048] Combination Figure 3 As shown, in a specific embodiment, the first wafer 100 is provided with the chip module 30 to be a functional wafer, and the second wafer 200 may not be provided with the chip module 300 to be formed as a cover wafer.

[0049] S2: forming a connection portion 320 on the first surface 110 and surrounding at least a portion of the outer periphery of the sealing functional area 310 , and forming a cutting path cavity 330 between adjacent connection portions 320 .

[0050] Combination Figure 4-5 As shown, the first wafer 100 is provided with a chip module 30, and the connecting portion 320 is formed on the first wafer 100, and can also be formed on the first surface 110 by etching or deposition, or can be bonded to the first surface 110 by a bonding layer. The saw path cavity 330 can be formed when the first wafer 100 is formed, or can be formed by subsequent etching.

[0051] The connecting portion 320 is an annular structure, the cutting path cavities 330 are crisscrossed, and the outer ends of the cutting path cavities 330 are connected to the outside, which is convenient for subsequent filling of supporting materials.

[0052] In a preferred embodiment, the cutting road cavity 330 includes a plurality of transverse cutting roads 331 that penetrate horizontally, and a plurality of longitudinal cutting roads 332 that penetrate longitudinally, wherein the transverse and longitudinal directions are horizontal and perpendicular to each other; a plurality of the transverse cutting roads 331 are arranged along the longitudinal direction, and a plurality of the longitudinal cutting roads 332 are arranged along the transverse direction, and the transverse cutting roads 331 and the longitudinal cutting roads 332 are cross-connected to facilitate the flow of supporting materials.

[0053] The outer ends of the cutting road cavity 330 are connected to the outside, including the two ends of the transverse cutting road 331 are connected to the outside, and the two ends of the longitudinal cutting road 332 are connected to the outside.

[0054] In a preferred embodiment, the width of the transverse cutting road 331 and / or the longitudinal cutting road 332 ranges from 40 mm to 200 mm. Theoretically, for the first wafer 100, the second wafer 200 and the chip module 30 of different sizes, the smaller the width of the cutting road cavity 330, the better, so as to reserve more space for the chip module 30. In actual packaging applications, due to the limited process level, the width of the cutting road cavity 330 cannot be made particularly small. Common widths of the cutting road cavity 330 are 80 mm and 120 mm, which ensure the appropriate width of the cutting road cavity 330 without taking up too much space of the first wafer 100.

[0055] In a preferred embodiment, the scribe line cavity 330 further includes transverse scribe lines and longitudinal scribe lines located at the periphery of the chip module 30 in the edge region.

[0056] S3 : filling the scribe line cavity 330 with a supporting material to form a filling portion 400 .

[0057] In a preferred embodiment, the supporting material is at least one of photoresist, epoxy resin glue, and UV glue. The flowing colloid is convenient for filling and has viscosity.

[0058] The supporting material is gradually solidified in the scribe line cavity 330 to form a filling portion 400 .

[0059] The cutting path cavities 330 in all areas of the first wafer 100 are filled with supporting materials. In other words, filling portions 400 are formed in all transverse cutting paths 331 and longitudinal cutting paths 332 to strengthen support. Compared with the prior art in which filling portions 400 are formed only in the cutting path cavities 330 in the edge areas, the stability and uniformity of support in this case are improved.

[0060] In a preferred embodiment, when the supporting material is photoresist, “filling the cutting path cavity 330 with the supporting material” comprises the following steps:

[0061] S31: Apply photoresist to the first surface 110 of the first wafer 100. The first wafer 100 is provided with the chip module 30 and the connecting portion 320, and the first surface 110 is formed with a sealing functional area 31. When the first surface 110 is coated with photoresist, it can be understood that the sealing functional area 31 and the cutting path cavity 330 will be filled with photoresist.

[0062] S32: Expose and develop to form a photoresist protrusion protruding from the connection part 320 in the cutting path cavity 330. Photoresist is a photolithographic material that can be removed and retained by photolithography. Specifically, when using a mask for exposure and development, a suitable mask image is made so that the photoresist on the surface of the corresponding connection part 320 and the sealing functional area 31 is removed, and only the photoresist at the cutting path cavity 330 is retained, thereby forming a photoresist protruding from the connection part 320.

[0063] S33: grinding the photoresist protrusions so that they do not protrude from the connecting portion 320, otherwise it will affect the subsequent bonding of the first wafer 100 and the second wafer 200.

[0064] In this way, in the present case, the scribe line cavity 330 is filled before the first wafer 100 and the second wafer 200 are bonded.

[0065] In a preferred embodiment, the support material is epoxy resin glue or UV glue, and "filling the support material into the cutting path cavity" includes the steps of: filling the cutting path cavity 330 with epoxy resin glue or UV glue by dispensing. Epoxy resin glue or UV glue cannot be easily removed, so it can only be directly dispensed into the cutting path cavity 330 using a dispensing machine to form a filling portion 400.

[0066] Similarly, the filling of the scribe line cavity 330 can be completed before the first wafer 100 and the second wafer 200 are bonded.

[0067] The wafer-level packaging method of filling supporting material before bonding has a simple process and is easy to operate. It can accurately control the degree to which the supporting material fills the cutting path cavity 330, such as controlling the amount and position of the filled glue to ensure good support during cutting without causing glue overflow.

[0068] S4: Bonding the connection part 320 and the second wafer 200 to form a wafer-level packaging structure 2000. Specifically, the surface of the circuit layer 210 of the second wafer 200 is bonded to the connection part 320, and the cutting path cavity 330 corresponds to the non-functional area of ​​the circuit layer 210. In this way, the functional area of ​​the circuit layer 210 is not affected.

[0069] In one embodiment, “bonding the connection portion 320 and the second wafer 200” comprises the following steps:

[0070] S41 : connecting the connection portion 320 and the second wafer 200 by dielectric bonding or dielectric-free bonding, wherein the wafer-level packaging structure 2000 includes a bonding layer disposed between the connection portion 320 and the second wafer 200 .

[0071] The connecting portion 320 is formed on the first wafer 100 by etching or deposition. The end of the connecting portion 320 close to the second wafer 200 can be bonded to the surface of the circuit layer 210 of the second wafer 200 without a medium, or can be bonded to the surface of the circuit layer 210 of the second wafer 200 by a medium, such as organic adhesive bonding or metal bonding. In this way, the first wafer 100 and the second wafer 200 are connected. In actual applications, during the bonding connection, the first wafer 100 and the second wafer 200 are in a high temperature and high pressure environment.

[0072] In a specific embodiment, the bonding layer may be a bonding adhesive, comprising the steps of: applying the bonding adhesive corresponding to the connecting portion 320. The bonding adhesive may be applied at the connecting portion 320, or may be applied on the circuit layer surface of the second wafer 200. The first wafer 100 is provided with the chip module 30 and the connecting portion 320, the connecting portion 320 is formed on the first wafer 100, and the bonding adhesive is connected between the connecting portion 320 and the second wafer 200.

[0073] In one embodiment, along the thickness direction of the wafer-level packaging structure 2000, the filling portion 400 connects the first wafer 100 and the second wafer 200. The filling portion 400 is filled in the saw path cavity 330 of the first wafer 100 and is also connected to the second wafer 200; further, during the bonding process, if a high temperature environment is entered, the filling portion 400 becomes a fluid colloid and further adheres to the second wafer 200.

[0074] The cutting path cavity 330 is the position where the first wafer 100 and the second wafer 200 are cut to form the chip structure 1000 after the first wafer 100 and the second wafer 200 are bonded. The cutting path cavity 330 achieves the effect of dividing several chip modules 30 from each other, realizes wafer-level packaging, simplifies the process flow, and improves packaging efficiency.

[0075] It is understandable that the wafer-level packaging structure 2000 may be subjected to a thinning process before being cut to form the chip structure 1000. The back side of the first wafer 100 and / or the second wafer 200 may be subjected to a thinning process to be thinned to a suitable thickness to ensure the performance of the chip module 30 in the first wafer 100 and to reduce the packaging thickness.

[0076] S5: Cutting the corresponding cutting path cavities 330 to form a plurality of independent chip structures 1000. When cutting the cutting path cavities 330, since the filling parts 400 are formed in all the cutting path cavities 330, they have good support. On the one hand, cracks and damages of the wafer-level packaging structure 2000 can be prevented during the thinning process and the cutting process; on the other hand, when the wafer-level packaging structure 2000 is subjected to a wet process, the presence of the filling parts 400 can prevent liquid from flowing into the cutting path cavities, which would cause corrosion of the cutting path cavities.

[0077] Combination Figure 6-7 As shown, the chip structure 1000 includes a first substrate 10, a second substrate 20, a connection layer 32, and a chip module 30 disposed on the first substrate 10. The connection layer 32 connects the first substrate 10 and the second substrate 20, and the connection layer 32 is disposed around the periphery of the sealing functional area 31. The chip structure 1000 also includes a filling structure 40 disposed around the periphery of the connection layer 32 for protecting the chip module.

[0078] The chip structure 1000 is formed by cutting the entire wafer-level packaging structure 2000, wherein the first layer substrate 10 is formed by cutting the first wafer 100, the second layer substrate 20 is formed by cutting the second wafer 200, the filling structure 40 is formed by cutting the filling part 400, and the connecting layer 32 is formed by cutting the connecting part 320. The structure of the chip module 30 itself will not be affected, and the chip structure 1000 formed by cutting includes at least one chip module 30.

[0079] The outer circumference of the filling structure 40 is located in the same plane as the outer circumferences of the first substrate 10 and the second substrate 20. In other words, the filling structure 40 constitutes part of the outer wall of the chip structure 1000 to protect the internal structure.

[0080] A filling groove 33 is formed on the first surface 301, which is equivalent to a cutting path cavity 330 formed by cutting. The filling structure 40 is filled in the filling groove 33. The connecting layer 32 and the filling structure 40 are ring-shaped. The connecting layer 32 is arranged around the periphery of the sealing functional area 31. The filling structure 40 is further arranged around the periphery of the connecting layer 32. The connecting layer 32 serves to separate the sealing functional area 31 and the filling structure 40.

[0081] The bonding layer is bonded to the connection layer 32 and the second substrate 20 , and is further sealed between the filling groove 33 and the sealing functional area 31 , thereby further preventing the filling structure 40 from entering the sealing functional area 31 and affecting the function of the chip.

[0082] The non-functional area of ​​the circuit layer 21 of the second substrate 20 is at least partially connected to the filling structure 40 . The filling structure 40 does not need to realize any function, and thus corresponds to the non-functional area of ​​the circuit layer 21 .

[0083] The beneficial effects of the present invention are: the wafer-level packaging method of filling supporting materials before bonding has a simple process and is easy to operate. It can accurately control the degree to which the supporting materials are filled into the cutting path cavity 330, such as controlling the amount and position of the filled glue to ensure good support during cutting without causing glue overflow, etc.; the cutting path cavities 330 are all filled with supporting materials, and the wafer-level packaging structure 2000 is not easily damaged or broken during the cutting or thinning process.

[0084] It can be formed by referring to any of the technical solutions provided above, and will not be described in detail here.

[0085] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0086] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A wafer-level packaging method for filling supporting materials before bonding, characterized in that: The following steps are involved: Providing a first wafer and a second wafer, wherein the first wafer is provided with a plurality of chip modules, and at least some of the chip modules have a sealing functional area exposed to a first surface of the first wafer; A connection portion is formed on the first surface and is arranged around at least a portion of the outer periphery of the sealing functional area, and a cutting path cavity is formed between adjacent connection portions; Filling the cutting path cavity with support material; The connecting portion and the second wafer are bonded to form a wafer-level packaging structure.

2. The wafer-level packaging method of filling supporting material before bonding according to claim 1, characterized in that: Along the thickness direction of the wafer-level packaging structure, the filling portion connects the first wafer and the second wafer.

3. The wafer-level packaging method of filling supporting material before bonding according to claim 1, characterized in that: The supporting material is at least one of photoresist, epoxy resin glue and UV glue.

4. The wafer-level packaging method of filling supporting material before bonding according to claim 1, characterized in that: The supporting material is photoresist, and "filling the cutting path cavity with the supporting material" comprises the steps of: Applying photoresist on the first surface of the first wafer; Expose and develop to form a photoresist protrusion protruding out of the connecting portion in the cutting path cavity; The photoresist protrusions are ground so that they do not protrude from the connecting portion.

5. The wafer-level packaging method of filling supporting material before bonding according to claim 1, characterized in that: The supporting material is epoxy resin glue or UV glue, and "filling the cutting path cavity with supporting material" includes the steps of: filling the cutting path cavity with epoxy resin glue or UV glue by dispensing.

6. The wafer-level packaging method of filling supporting material before bonding according to claim 1, characterized in that: The scribe line cavities in all regions of the first wafer are filled with supporting material.

7. The wafer-level packaging method of filling supporting material before bonding according to claim 1, characterized in that: The method comprises the steps of: cutting the corresponding cutting path cavities to form a plurality of independent chip structures.

8. The wafer-level packaging method of filling supporting material before bonding according to claim 1, characterized in that: The cutting path cavity includes a plurality of transverse cutting paths penetrating transversely and a plurality of longitudinal cutting paths penetrating longitudinally, wherein the transverse and longitudinal directions are horizontal and perpendicular to each other; a plurality of the transverse cutting paths are arranged longitudinally, a plurality of the longitudinal cutting paths are arranged transversely, and the transverse cutting paths and the longitudinal cutting paths are cross-connected.

9. The wafer-level packaging method of filling supporting material before bonding according to claim 8, characterized in that: The width of the transverse cutting line and / or the longitudinal cutting line is in the range of 40 mm to 200 mm.

10. The wafer-level packaging method of filling supporting material before bonding according to claim 1, characterized in that: The first wafer is provided with the chip module and the connecting part, the second wafer has a substrate and a circuit layer provided on the substrate, the surface of the circuit layer is bonded to the connecting part, and the cutting path cavity corresponds to the non-functional area of ​​the circuit layer.

11. The wafer-level packaging method of filling supporting material before bonding according to claim 1, characterized in that: “Bonding the connection portion and the second wafer” comprises the steps of: The connection portion and the second wafer are connected by dielectric bonding or non-dielectric bonding, and the wafer-level packaging structure includes a bonding layer arranged between the connection portion and the second wafer.

12. A chip structure, using the wafer-level packaging method of filling the supporting material before bonding as claimed in any one of claims 1 to 11, characterized in that: The chip structure is formed by cutting the scribe line cavity through the wafer-level packaging structure.

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