Semiconductor device and method of forming semiconductor device

Abstract

The invention relates to a semiconductor device and a method of forming a semiconductor device. A method of forming a semiconductor device includes forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the through hole; selectively forming a cap layer over an upper surface of the via, where the cap layer has a curved upper surface extending over a first upper surface of the first dielectric layer remote from the substrate; after forming the cap layer, forming a barrier layer in the opening over the cap layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming a conductive material over the barrier layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor device technology, and more particularly to low contact resistance vias in back-end-of-line interconnect structures. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric layers, conductive layers, and semiconducting layers over a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. As the size of electronic components continues to shrink in semiconductor manufacturing, challenges arise that require new solutions. Summary of the invention

[0004] According to one aspect of the present application, a method for forming a semiconductor device is provided, the method comprising: forming a through hole in a first dielectric layer disposed above a substrate; forming a second dielectric layer above the first dielectric layer; forming an opening in the second dielectric layer, wherein the opening exposes an upper surface of the through hole; selectively forming a cap layer above the upper surface of the through hole, wherein the cap layer has a curved upper surface extending above a first upper surface of the first dielectric layer away from the substrate; after forming the cap layer, forming a barrier layer in the opening above the cap layer and along a sidewall of the second dielectric layer exposed by the opening; and filling the opening by forming a conductive material above the barrier layer.

[0005] In some implementations, an upper surface of the via is flush with the first upper surface of the first dielectric layer, wherein the curved upper surface of the cap layer is a convex upper surface.

[0006] In some implementations, the capping layer is formed of the same material as the vias.

[0007] In some implementations, the conductive material is different than the material of the vias.

[0008] In some implementations, the method further includes forming a transistor over the substrate before forming the via, wherein the via is formed over the transistor and is formed to be electrically coupled to a conductive region of the transistor.

[0009] In some implementations, the first dielectric layer and the second dielectric layer are formed in a middle-of-line (MEOL) process and a back-end-of-line (BEOL) process, respectively, of a semiconductor device.

[0010] In some implementations, the method further includes: after selectively forming the capping layer and before forming the barrier layer, selectively forming an inhibitor layer over the capping layer, wherein the inhibitor layer reduces a deposition rate of the barrier layer.

[0011] In some implementations, after forming the barrier layer, a first portion of the barrier layer disposed on the cap layer has a first thickness, and a second portion of the barrier layer disposed along a sidewall of the second dielectric layer has a second thickness, the first thickness being less than the second thickness.

[0012] In some embodiments, the method further includes: after forming the barrier layer and before filling the opening, forming a lining layer over the barrier layer in the opening, wherein a first portion of the lining layer disposed over the cap layer has a third thickness, and a second portion of the lining layer disposed along a sidewall of the second dielectric layer has a fourth thickness, and the third thickness is less than the fourth thickness.

[0013] In some implementations, the method further includes removing the inhibitor layer after forming the barrier layer and before filling the opening.

[0014] In some implementations, removing the inhibitor layer includes performing a plasma treatment process, wherein the plasma treatment process removes the inhibitor layer without removing the barrier layer.

[0015] According to another aspect of the present application, a method for forming a semiconductor device is provided, the method comprising: forming an opening in a second dielectric layer disposed above a first dielectric layer, wherein the first dielectric layer is disposed above a substrate, wherein the opening exposes an upper surface of a through hole embedded in the first dielectric layer; selectively forming a cap layer on the upper surface of the through hole; selectively forming an inhibitor layer on the cap layer; after selectively forming the inhibitor layer, lining the sidewalls and bottom of the opening with a barrier layer, wherein the barrier layer is formed as a non-conformal layer; and filling the opening by forming a conductive material in the opening above the barrier layer.

[0016] In some implementations, the method further includes removing the inhibitor layer by performing a plasma treatment process after the lining and before the filling, wherein the plasma treatment process removes the inhibitor layer without removing the barrier layer.

[0017] In some implementations, the barrier layer has a first portion on the capping layer and has a second portion along a sidewall of the second dielectric layer, wherein the first portion of the barrier layer is thinner than the second portion of the barrier layer.

[0018] In some embodiments, the method further includes: forming a liner layer on the barrier layer after the lining and before the filling, wherein the liner layer is formed as a non-conformal layer, wherein a first portion of the liner layer disposed above the cap layer is thinner than a second portion of the liner layer disposed along a sidewall of the second dielectric layer.

[0019] In some implementations, an upper surface of the via is flush with an upper surface of the first dielectric layer away from the substrate, wherein the upper surface of the capping layer is a raised upper surface and extends farther from the substrate than the upper surface of the first dielectric layer.

[0020] According to another aspect of the present application, a semiconductor device is provided, comprising: a substrate; a transistor on the substrate; a first dielectric layer on the substrate and the transistor; a through-hole embedded in the first dielectric layer and electrically coupled to a conductive region of the transistor; a cap layer on an upper surface of the through-hole, wherein a lower surface of the cap layer facing the substrate is a flat surface, and an upper surface of the cap layer facing away from the substrate is a convex surface; a second dielectric layer on the first dielectric layer, wherein an upper surface of the cap layer extends farther from the substrate than a lower surface of the second dielectric layer facing the substrate; and a wire embedded in the second dielectric layer and on the cap layer, wherein the wire is electrically coupled to the through-hole through the cap layer.

[0021] In some implementations, the semiconductor device further includes a barrier layer extending along a sidewall and a bottom of the conductive line, wherein the barrier layer has a non-uniform thickness.

[0022] In some implementations, a first portion of the barrier layer along the upper surface of the capping layer has a first thickness, and a second portion of the barrier layer along the sidewall of the conductive line has a second thickness greater than the first thickness.

[0023] In some implementations, the via and the capping layer are a first conductive material, wherein the conductive line is a second conductive material different from the first conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood through the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0025] Figures 1 to 9B Cross-sectional views of a semiconductor device at various fabrication stages are shown in accordance with an embodiment.

[0026] Fig.10 and Fig.11 Cross-sectional views of a semiconductor device at various fabrication stages according to another embodiment are shown.

[0027] Fig.12 A flow chart of a method of forming a semiconductor device according to an embodiment is shown. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples for realizing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. Throughout the discussion herein, unless otherwise described, the same or similar reference numerals in different drawings represent the same or similar components formed by the same or similar formation method, using (one or more) the same or similar materials.

[0029] Additionally, spatially relative terms (e.g., "below," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in a figure relative to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0030] In some embodiments, during the back-end of line (BEOL) processing of a semiconductor device, a cap layer is selectively formed on a via below. The cap layer has a curved upper surface to increase the surface area of ​​the interface between the via and a subsequently formed wire overlying the via. The increased surface area reduces the contact resistance of the via. In some embodiments, an inhibitor layer is selectively formed on the cap layer. The inhibitor layer hinders the subsequent formation of a barrier layer and a liner layer on the cap layer. Therefore, the barrier layer and liner layer formed subsequently have uneven thicknesses. For example, a portion of the barrier layer / liner layer formed on the cap layer has a smaller thickness, while a portion of the barrier layer / liner layer formed on the dielectric layer has a larger thickness. The barrier layer / liner layer of smaller thickness helps to further reduce the contact resistance, while the barrier layer / liner layer of larger thickness provides better protection to prevent the outward diffusion of the material (e.g., copper) of the wire.

[0031] Figure 1 9 show cross-sectional views of a semiconductor device 100 at various stages of manufacture according to an embodiment. The semiconductor device 100 may be, for example, a fin field effect transistor (FinFET) device.

[0032] like Figure 1 As shown, semiconductor device 100 includes substrate 101. Substrate 101 can be a bulk substrate (e.g., a doped or undoped silicon substrate), or an active layer of a semiconductor on insulator (SOI) substrate. Substrate 101 can include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations of the foregoing. Other substrates, such as multilayer substrates or gradient substrates, can also be used.

[0033] In the front end of line (FEOL) process of the semiconductor device, electrical components such as transistors, resistors, capacitors, inductors, or diodes are formed in or on the substrate 101. Figure 1 In the example of , semiconductor fins 103 (also referred to as fins) are formed to protrude above the substrate 101. Isolation regions 105 such as shallow trench isolation (STI) regions are formed between or around the semiconductor fins 103. A gate electrode 109 and a gate dielectric layer 113 are formed over the semiconductor fins 103. Gate spacers 111 are formed along sidewalls of the gate electrode 109. Source / drain regions 107 (e.g., epitaxial source / drain regions) are formed over the semiconductor fins 103 and on opposite sides of the gate electrode 109. FEOL processes for forming electrical components such as FinFETs are known in the art, and therefore the details are not discussed herein.

[0034] Next, contacts 115 and 117 (eg, source / drain contacts and gate contacts) are formed in a middle of line (MEOL) process to electrically couple to corresponding underlying conductive features (eg, gate electrode 109 or source / drain regions 107).

[0035] exist Figure 1 In the embodiment, a first interlayer dielectric (ILD) layer 121 is formed around the gate electrode 109 over the substrate 101. The first ILD layer 121 may be formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and may be deposited by any suitable method such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD). A planarization process such as a chemical mechanical planarization (CMP) process may be performed to planarize the top surface of the first ILD layer 121 so that the top surface of the first ILD layer 121 is flush with the top surface of the gate electrode 109.

[0036] Contacts 115 (also referred to as source / drain contacts) are formed in the first ILD layer 121, for example, the contacts 115 are formed over and electrically coupled to the corresponding underlying source / drain regions 107. The contacts 115 may be formed by forming openings in the first ILD layer 121 (for example, using photolithography and etching techniques) to expose the underlying source / drain regions 107, and filling the openings with a conductive material (for example, tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), copper (Cu), etc.).

[0037] Next, an etch stop layer (ESL) 123 (e.g., silicon nitride, silicon carbide, silicon oxynitride, etc.) is formed over the first ILD layer 121, and a second ILD layer 125 is formed over the ESL 123. In some embodiments, the second ILD layer 125 is formed of the same or similar material as the first ILD layer 121. A contact 117 is formed to extend through the second ILD layer 125 and the ESL 123 to electrically couple to a conductive feature below, such as a gate electrode 109 or a contact 115. The contact 117 electrically coupled to the corresponding gate electrode 109 below is also referred to as a gate contact. The contact 117 may be formed by forming an opening in the second ILD layer 125 and filling the opening with a conductive material (e.g., W, Mo, Co, Ru, or Cu). A planarization process (e.g., CMP) is performed to remove excess portions of the conductive material from the upper surface of the second ILD layer 125 and achieve a flat upper surface between the contact 117 and the second ILD layer 125. It should be noted that Figure 1 The structures shown are illustrative rather than limiting, variations are possible and are fully intended to be included within the scope of the present disclosure.

[0038] The following discussion focuses on the back-end-of-line (BEOL) processing of the semiconductor device 100, wherein Figure 1 An interconnect structure is formed on top of the structure shown. The interconnect structure includes multiple dielectric layers and conductive features (eg, vias, wires) formed in the multiple dielectric layers. The interconnect structure interconnects underlying electrical components (eg, transistors) to form a functional circuit.

[0039] To facilitate the following discussion, Figure 1 The structure shown is referred to as device layer 50. In addition, the subsequent figures (see, e.g. Figure 2) and is shown as including a substrate 101, a transistor 106 (e.g., a FinFET) formed on the substrate 101, an ESL 123, a second ILD layer 125, and a contact 117 (also referred to as a via 117) extending through the second ILD layer 125 and the ESL 123 to be electrically coupled to a conductive region (e.g., a source / drain region 107 or a gate electrode 109) of the transistor 106. It should be understood that the detailed structure of the device layer 50 is similar to that of FIG. Figure 1 The detailed structures are the same or similar.

[0040] Next reference Figure 2 , an ESL 131, a low-K dielectric layer 133, and a dielectric layer 135 are sequentially formed over the second ILD layer 125 and the via 117. In an embodiment, the ESL 131 is formed of aluminum oxide, but other suitable materials may also be used, such as silicon nitride, silicon carbide, silicon oxynitride, a combination of the foregoing, etc. The ESL 131 may be formed using a suitable formation method, such as plasma enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), etc.

[0041] The low-K dielectric layer 133 is formed of a material having a dielectric constant value (K value) less than that of silicon oxide. In an embodiment, the low-K dielectric layer 133 is formed of carbon-doped silicon oxide (e.g., SiOC) using a suitable formation method (e.g., CVD, PECVD, etc.). The dielectric layer 135 is formed of a dielectric material different from the dielectric material of the low-K dielectric layer 133 to provide etching selectivity for subsequent processing. The dielectric layer 135 can be formed of, for example, silicon oxide or other suitable materials using any suitable formation method.

[0042] Next, an opening 139 is formed in the dielectric layer 135, the low-K dielectric layer 133, and the ESL 131 to expose the upper surface of the through hole 117. In order to form the opening 139, a hard mask layer 137 is formed on the dielectric layer 135. The hard mask layer 137 is formed of a suitable material (e.g., tungsten carbide (WC)) using a suitable formation method (e.g., CVD, PECVD, etc.). The hard mask layer 137 is then patterned using, for example, photolithography and etching techniques to form a patterned hard mask layer 137. Next, an etching process (e.g., an anisotropic etching process) is performed using the patterned hard mask layer 137 as an etching mask to form the opening 139 and expose the through hole 117.

[0043] exist Figure 2In the example of FIG. 1 , the upper portion 117U of the via 117 is oxidized, for example, by oxygen in the ambient air, and forms an oxide (e.g., tungsten oxide) of the material (e.g., tungsten) of the via 117. Therefore, the upper portion 117U may also be referred to as an oxidized upper portion 117U of the via 117. The thickness of the oxidized upper portion 117U may be, for example, between about 2.5 nm and about 3.5 nm.

[0044] Next, in Figure 3 In some embodiments, the pre-cleaning process 140 is performed to reduce the thickness of the oxidized upper portion 117U of the through hole 117. In some embodiments, the pre-cleaning process 140 is a plasma cleaning process performed using a remote plasma (e.g., a plasma generated in a processing chamber different from the chamber having the semiconductor device 100). The remote plasma can be generated using a gas source (e.g., a gas mixture) of hydrogen (e.g., H2) and a carrier gas (e.g., argon (Ar)). In some embodiments, the volume percentage of H2 in the gas source is between about 5% and about 25%, and the flow rate of the gas source is between about 200 standard cubic centimeters per minute (sccm) and about 500 sccm. In some embodiments, the power of the radio frequency (RF) source used to generate the remote plasma is between about 100W and about 500W. As an example, the pre-cleaning process can last for a time between about 25 seconds and about 50 seconds at a temperature between about 300°C and about 350°C.

[0045] In some embodiments, the hydrogen plasma used in the pre-cleaning process 140 reacts with the oxide in the oxidized upper portion 117U of the via 117 and converts (e.g., reduces) the oxide into the material of the via 117 (e.g., tungsten) through a chemical reaction process called a reduction process. As a result, the thickness of the oxidized upper portion 117U of the via 117 is reduced to, for example, a thickness between about 1.5 nm and about 2.5 nm. Figure 3 , the remaining portion of the oxidized upper portion 117U is shown at the top of the via 117. In some embodiments, depending on, for example, the duration of the pre-cleaning process 140, the thickness of the original oxidized upper portion 117U, and / or the parameters of the pre-cleaning process 140, the oxidized upper portion 117U may be completely reduced (e.g., converted) to the material of the via 117. In some embodiments, the reduction process (e.g., the pre-cleaning process 140) does not change the position of the upper surface of the via 117, and therefore, after the pre-cleaning process 140, the upper surface of the via 117 (which may correspond to the upper surface of the oxidized upper portion 117U if the oxidized upper portion 117U is not completely reduced to the material of the via 117) is still flush with the upper surface of the second ILD layer 125 away from the substrate 101. Since the oxidized upper portion 117U of the via 117 may increase the resistance of the via 117, by reducing the thickness of the oxidized upper portion 117U, the electrical performance of the formed device is improved.

[0046] Next, in Figure 4 In the embodiment, a capping layer 141 is selectively formed on the through hole 117. In some embodiments, the capping layer 141 is formed of the same material as the through hole 117. For example, the through hole 117 can be formed of tungsten, and the capping layer 141 is also formed of tungsten. In the embodiment in which the through hole 117 is formed of tungsten, the capping layer 141 is formed using a tungsten-containing precursor (e.g., WCl5, WF6) by a suitable formation method (e.g., CVD, atomic layer deposition (ALD)), etc.). A mixture of a tungsten-containing precursor (e.g., WCl5, WF6) and hydrogen can be used in the selective deposition process for the capping layer 141. In the embodiment in which the through hole 117 is formed of molybdenum (Mo), a molybdenum-containing precursor (e.g., MoCl5) can be used to selectively form the capping layer 141.

[0047] exist Figure 4 In the example of , the capping layer 141 (e.g., W) is also selectively formed on the hard mask layer 137. In other words, the capping layer 141 is formed on the exposed upper surface of the through hole 117 and the exposed surface of the hard mask layer 137, and the capping layer 141 is not formed on other surfaces of the semiconductor device 100. In the illustrated embodiment, the capping layer 141 is selectively formed on the hard mask layer 137 because the hard mask layer 137 is formed of a tungsten-containing material (e.g., tungsten carbide (WC)). In the context of the deposition process of the capping layer 141, the material properties of the hard mask layer 137 (e.g., tungsten or tungsten oxide) are similar to the material properties of the through hole 117 (e.g., including tungsten or tungsten oxide), and since tungsten tends to grow on tungsten-containing materials, the capping layer 141 is selectively formed on the hard mask layer 137. Figure 4 In the example of FIG. 1 , the capping layer 141 is selectively formed on the via 117 and the hard mask layer 137 .

[0048] In some embodiments, the deposition rate of the material of the capping layer 141 (e.g., tungsten) on the via 117 and on the hard mask layer 137 is higher (e.g., two times, five times, or ten times higher) than the deposition rate on the other layers (e.g., 131, 133, and 135) of the semiconductor device 100. Therefore, one or more etching processes performed using an etchant selective to the material of the capping layer 141 can be performed after the deposition process of the capping layer 141, or alternately performed with the deposition cycle of the deposition process (e.g., ALD process), so that after the deposition process of the capping layer 141 is completed, the surfaces of the other layers (e.g., 131, 133, and 135) of the semiconductor device 100 are free of the capping layer 141.

[0049] like Figure 4As shown, the cap layer 141 on the via 117 has a lower surface in contact with the via 117 (e.g., in physical contact with the remaining oxidized upper portion 117U of the via 117), and has an upper surface facing away from the via 117. The lower surface of the cap layer 141 is a flat surface, and the upper surface of the cap layer 141 is a curved upper surface (e.g., a convex upper surface). The curved upper surface of the cap layer 141 extends upward away from the substrate 101, and may extend farther from the substrate 101 than the lower surface of the low-K dielectric layer 133. The curved upper surface of the cap layer 141 on the via 117 increases the contact surface area between the cap layer 141 and the subsequently formed conductive line 149 (see, e.g., Fig. 8A ), and thus the contact resistance of the through hole 117 is advantageously reduced.

[0050] In some embodiments, the cap layer 141 is not formed of the same material as the via 117 (e.g., tungsten), but is formed of a conductive material having the same or similar lattice constant, crystal phase, and / or physical / chemical properties as the material of the via 117, wherein the physical / chemical properties refer to thermal stability, melting temperature, electron affinity, chemical reactivity (e.g., with materials or chemicals used in subsequent processing (e.g., C, N, O, F, Cl, etc.)), combinations of the foregoing, etc. The material of the cap layer 141 selected based on the above criteria may still allow for the following: Figure 4 The selective growth of the cap layer 141 is shown, while allowing a variety of materials to be used for the cap layer 141. As examples, potential benefits of a wider selection of cap layers 141 may include, for example, lower cost, higher throughput, better device performance (e.g., lower contact resistance), better compatibility with subsequent BEOL processing, and easier integration with existing process flows.

[0051] Next, in Figure 5 In the embodiment, an inhibitor layer 143 is selectively formed on the cap layer 141. The inhibitor layer 143 is formed of an inhibitor, which hinders the barrier layer 145 and the liner layer 147 (see Figure 6 ) is formed on the inhibitor layer 143 (e.g., reduces the deposition rate).

[0052] In some embodiments, the inhibitor used to form the inhibitor layer 143 meets the following criteria. First, adsorption of the inhibitor should occur at the surface of the through hole 117 (e.g., W) and not at the surface of the dielectric layer (e.g., 131, 133, 135, and 125). Second, the inhibitor should be able to withstand subsequent processing conditions and maintain its barrier capability (e.g., the ability to hinder the formation of the barrier layer and the liner layer) during the subsequent deposition of the barrier layer 145 and the liner layer 147. For example, if the deposition of the barrier layer 145 or the liner layer 147 is performed at high temperature or using plasma treatment, the inhibitor should not be removed at high temperature or by plasma treatment. Finally, and very importantly, the inhibitor should be able to be completely removed from the metal surface (e.g., the surface of the through hole 117) by a subsequent deblocking process without leaving contamination or causing damage to other layers of the semiconductor device 100.

[0053] In some embodiments, by, for example, Figure 4 The semiconductor device 100 is immersed in an inhibitor (e.g., symmetrical internal alkyne (SA-03), linear terminal alkyne (SA-02), or linear alkyl silane (SFS-1)) to form an inhibitor layer 143. The inhibitor is attached to the exposed metal surface of the cap layer 141 through covalent bonds and forms a hydrophobic monolayer (e.g., inhibitor layer 143), which prevents or hinders the subsequent deposition of the barrier layer 145 and the liner layer 147. In some embodiments, the intrinsic electron affinity and orbital state of the metal surface of the cap layer 141 significantly determine the adsorption of the inhibitor. For example, a metal with an empty orbital attracts the inhibitor and forms a covalent bond with the inhibitor. On the other hand, most dielectric films do not have an empty orbital that attracts the inhibitor. Therefore, the inhibitor layer 143 is selectively formed on the exposed surface of the cap layer 141.

[0054] Next, in Figure 6 in Figure 5 A barrier layer 145 and a liner layer 147 are successively formed on the semiconductor device 100. The barrier layer 145 may be formed of, for example, tantalum nitride (TaN), tantalum (Ta), etc., and the liner layer 147 may be formed of, for example, ruthenium (Ru), cobalt (Co), etc. Each of the barrier layer 145 and the liner layer 147 may be formed using a suitable deposition method (e.g., CVD, PECVD, ALD, etc.).

[0055] like Figure 6As shown, since the inhibitor layer 143 hinders the formation of the barrier layer 145 and the liner layer 147, the barrier layer 145 and the liner layer 147 are non-conformal layers. In other words, the barrier layer 145 and the liner layer 147 each have a non-uniform thickness. Specifically, the portion of the barrier layer 145 (or liner layer 147) formed on the inhibitor layer 143 is thinner (e.g., has a smaller thickness) than the portion of the barrier layer 145 (or liner layer 147) formed on the dielectric layer (e.g., 125, 131, 133, and 135). Figure 8B and Figure 8C The barrier layer 145 and the liner layer 147 are discussed in more detail.

[0056] In some embodiments, because barrier layer 145 and liner layer 147 have a higher resistance than the conductive material (e.g., copper) of subsequently formed conductive line 149 and the conductive material (e.g., tungsten) of cap layer 141, reducing the thickness of barrier layer 145 and liner layer 147 advantageously reduces the resistance at the interface between conductive line 149 and through hole 117.

[0057] Next, in Figure 7 In some embodiments, the deblocking process 148 is a plasma treatment process performed using hydrogen plasma, and therefore, the deblocking process 148 is also referred to as a hydrogen plasma treatment process. In some embodiments, a gas source (e.g., a gas mixture) including hydrogen (H2) and a carrier gas (e.g., Ar) is ignited into a plasma using a capacitively coupled plasma (CCP) system. The flow rate of the gas source is between about 2000 sccm and about 5000 sccm, and the volume percentage of hydrogen in the gas mixture is between about 75% and about 100%. The RF power of the CCP system can be between about 200W and about 600W. As an example, the hydrogen plasma treatment process can be performed at a pressure between about 1 Torr and about 10 Torr and a temperature between about 200°C and about 300°C.

[0058] In some embodiments, the hydrogen plasma reacts with the inhibitor and decomposes the inhibitor into smaller volatile fragments, which are then removed. Therefore, after the hydrogen plasma treatment is completed, the inhibitor layer 143 is removed (e.g., completely removed) from the semiconductor device 100. In some embodiments, the hydrogen plasma treatment process removes the inhibitor layer 143 without damaging the barrier layer 145 and the liner layer 147 when performed using the above-described process parameters.

[0059] Next, in Fig. 8AIn the process, a conductive material is formed over the liner layer 147 to fill the opening 139. The conductive material may be, for example, copper, titanium, tungsten, aluminum, etc., formed by a suitable formation method, such as PVD, plating (e.g., electroplating or electroless plating), etc. In an embodiment, the conductive material is copper and is different from the material of the through hole 117 (e.g., W). Next, a planarization process (e.g., CMP) is performed to remove the hard mask layer 137, the portion of the cap layer 141 disposed on the hard mask layer 137, the dielectric layer 135, the portion of the barrier layer 145 / liner layer 147 disposed over the low-K dielectric layer 133, and the portion of the conductive material disposed over the low-K dielectric layer 133. The remaining portion of the conductive material in the opening 139 forms a conductive line 149. After the planarization process, the conductive line 149, the low-K dielectric layer 133, and the barrier layer 145 / liner layer 147 have a coplanar upper surface.

[0060] Figure 8B Shows Fig. 8A An enlarged view of area 150 is shown. Figure 8B As shown, the portion of the barrier layer 145 (or liner layer 147) disposed along the upper surface of the cap layer 141 has a smaller thickness than the portion of the barrier layer 145 (or liner layer 147) disposed along the surface of the dielectric layer (e.g., 125, 131, and 133). In some embodiments, the total thickness T1 of the portion of the barrier layer 145 and the liner layer 147 along the upper surface of the cap layer 141 (referred to as the inhibited barrier layer 145 / liner layer 147) is less than the total thickness T2 of the portion of the barrier layer 145 and the liner layer 14 along the surface of the dielectric layer (e.g., 125, 131, and 133) (referred to as the uninhibited barrier layer 145 / liner layer 147). For example, the thickness T1 may be between 0.8 nm and about 1.8 nm, and the thickness T2 may be between 2.0 nm and 3.0 nm. In some embodiments, because the inhibitor layer 143 hinders the formation of the barrier layer 145 and the liner layer 147, the thickness T1 is between about 40% and about 60% of the thickness T2. It should be noted that without the influence of the inhibitor layer 143, the barrier layer 145 and the liner layer 147 can both be formed as conformal layers (e.g., having a substantially uniform thickness), with the thickness of each layer varying within a small percentage of the target thickness, such as between 5% and about 10%. In contrast, the inhibitor layer 143 in the present disclosure results in a significant reduction in the thickness of the inhibited barrier layer 145 / liner layer 147 compared to the thickness of the uninhibited barrier layer 145 / liner layer 147.

[0061] In some embodiments, the thickness T3 of the capping layer 141 on the through hole 117 is between about 2.0 nm and about 5.0 nm. The width D1 of the interface between the capping layer 141 and the barrier layer 145 is between about 10.0 nm and about 15.0 nm. The angle α measured between the lower surface of the barrier layer 145 and the tangent line of the capping layer 141 contacting the edge of the upper surface of the capping layer 141 is between about 120 degrees and about 160 degrees.

[0062] In some embodiments, the thickness T3 of the cap layer 141 indicates an increase in contact area and a decrease in contact resistance, and the range of the thickness T3 should be appropriately selected for both performance and yield. For example, if the thickness T3 is too small (e.g., less than about 2.0 nm), the reduction in contact resistance may not be significant enough. If the thickness T3 is too large (e.g., greater than about 5.0 nm), it may become difficult for the conductive material to fill the bottom of the opening 139, and the conductive line 149 may not be properly formed, which may result in yield loss. In some embodiments, the ratio between the thickness T1 of the suppressed barrier layer 145 / liner layer 147 and the thickness T2 of the unsuppressed barrier layer 145 / liner layer 147 is associated with the benefit of reduced contact resistance, and therefore, smaller values ​​and ranges (e.g., between 40% and 60%) may indicate better performance. In some embodiments, the thickness T3 of the capping layer 141 is greater than the thickness T1 of the inhibited barrier layer 145 / liner layer 147 , which may be advantageous because the capping layer 141 is more conductive than the barrier layer 145 / liner layer 147 .

[0063] exist Figure 8B In the example shown in FIG. 1 , the conductive line 149 is wider than the cap layer 141 and the via 117 . Figure 8C An example is shown in which the conductive line 149 is narrower than the cap layer 141 and the via 117. Figure 8C , the thickness T1 of the suppressed barrier layer 145 / liner layer 147 is between about 0.5 nm and about 1.5 nm, while the thickness T2 of the unsuppressed barrier layer 145 / liner layer 147 is between about 1.5 nm and about 2.5 nm. Figure 8C The ratio between the thickness T1 and the thickness T2 in is between about 30% and about 60%. The thickness T3 is between about 2.0 nm and about 5.0 nm. The width D1 is between about 9.0 nm and about 12.0 nm. It should be noted that in Figure 8C , the angle α is measured between the sidewall of the barrier layer 145 and a tangent line of the cap layer 141 that contacts the edge of the upper surface of the cap layer 141. The angle α is between about 110 degrees and about 150 degrees.

[0064] Next, in Fig.9A, ESL 151 and low-K dielectric layer 153 are formed over low-K dielectric layer 133 and conductive line 149, and via 155 is formed to extend through low-K dielectric layer 153 and ESL 151 to be electrically coupled to conductive line 149. ESL 151, low-K dielectric layer 153, and via 155 may be formed of the same or similar materials using the same or similar formation methods as ESL 131, low-K dielectric layer 133, and via 117, respectively, and thus the details are not repeated here. Fig.9A An oxidized upper portion 155U of the via 155 is also shown.

[0065] exist Fig.9A In the illustrated embodiment, unlike via 117, cap layer 141 is not formed on via 155, and inhibitor layer 143 is not formed on cap layer 141 (and is subsequently removed). This may be because the contact resistance of via 117 dominates the resistance of the interconnect structure of semiconductor device 100, and therefore, cap layer 141 and inhibitor layer 143 are used to reduce the contact resistance of via 117. For vias in the interconnect structure (e.g., vias formed in BEOL processing) such as via 155, cap layer 141 and inhibitor layer 143 are not used in order to save production costs and increase throughput. In other embodiments, via 155 is processed using the same processing steps as via 117, such as using cap layer 141 and inhibitor layer 143 to further reduce the resistance of the interconnect structure, in which case via 155 will have cap layer 141 formed on top, similar to cap layer 141 on via 117. These and other variations are fully intended to be included within the scope of the present disclosure.

[0066] Next, ESL 159 and low K dielectric layer 161 are formed over low K dielectric layer 153. Openings are formed in ESL 159 and low K dielectric layer 161 to expose via 155. Barrier layer 163 and liner layer 165 are formed in the openings, and a conductive material is formed in the openings to form conductive lines 167. The materials and processing steps of ESL 159, low K dielectric layer 161, conductive lines 167, barrier layer 163, and liner layer 165 are the same or similar to those discussed above, so the details will not be repeated. It should be noted that in Fig.9A In the example of FIG. 1 , since the capping layer 141 and the inhibitor layer 143 are not formed on the through hole 155 , the barrier layer 163 and the liner layer 165 are conformal layers (eg, both have substantially uniform thickness).

[0067] exist Fig.9A In the embodiment, the via 155 and the conductive line 167 can be formed by two separate single damascene processes. Of course, this is only a non-limiting example. Fig. 9BAs shown, other suitable methods (eg, a dual damascene process) may also be used to form vias 155 and conductive lines 167 after forming ESL 159 and low-K dielectric layer 161. These and other variations are fully intended to be included within the scope of the present disclosure.

[0068] As will be readily appreciated by those skilled in the art, additional processing may be performed to complete the fabrication of semiconductor device 100. For example, additional layers of dielectric layers and conductive features (e.g., vias, conductive lines) may be formed over conductive lines 167. An under-bump metal (UBM) structure may be formed over the top metal layer of the interconnect structure, and external connectors (e.g., conductive bumps, copper pillars, etc.) may be formed on the UBM structure to allow semiconductor device 100 to be electrically connected to other external devices. The details are not discussed here.

[0069] Fig.10 and Fig.11 A cross-sectional view of a semiconductor device 100A at various stages of fabrication is shown according to another embodiment. The semiconductor device 100A is formed by following similar processing steps as the semiconductor device 100 , but without the processing steps of forming the inhibitor layer 143 and without the deblocking process 148 of removing the inhibitor layer 143 . Fig.10 The processing steps shown in Figure 4 In other words, Figures 1 to 4 , Fig.10 and Fig.11 Various processing steps to form semiconductor device 100A are shown.

[0070] exist Fig.10 in Figure 4 Barrier layer 145 and liner layer 147 are formed over the structure shown. Note that since inhibitor layer 143 is not formed on cap layer 141 prior to deposition of barrier layer 145 and liner layer 147, barrier layer 145 and liner layer 147 are formed as conformal layers (eg, having substantially uniform thickness).

[0071] Next, in Fig.11 In the embodiment, by filling the opening 139 with a conductive material and performing a planarization process (e.g., CMP), a conductive line 149 is formed in the opening 139. Subsequent processing steps for the via 155, conductive line 167, barrier layer 163, liner layer 165, and various dielectric layers (e.g., 151, 153, 159, 161) are the same or similar to the processing steps described above for the semiconductor device 100, and therefore the details are not repeated.

[0072] Fig.12 1 is a flow chart of a method 1000 for forming a semiconductor device according to an embodiment. It should be understood that Fig.12The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, or repeated: Fig.12 The various steps shown.

[0073] refer to Fig.12 At block 1010, a through hole is formed in a first dielectric layer disposed above a substrate. At block 1020, a second dielectric layer is formed above the first dielectric layer. At block 1030, an opening is formed in the second dielectric layer, wherein the opening exposes an upper surface of the through hole. At block 1040, a capping layer is selectively formed above the upper surface of the through hole, wherein the capping layer has a curved upper surface extending above a first upper surface of the first dielectric layer away from the substrate. At block 1050, after forming the capping layer, a barrier layer is formed in the opening above the capping layer and along a sidewall of the second dielectric layer exposed by the opening. At block 1060, the opening is filled by forming a conductive material over the barrier layer.

[0074] The disclosed embodiments achieve various advantages. For example, the capping layer increases the contact area of ​​the via, thereby reducing the contact resistance. The inhibitor layer causes the barrier layer and the liner layer to have a smaller thickness at the interface between the wire and the via, and a larger thickness along the sidewalls of the dielectric layer. The smaller thickness of the barrier layer and the liner layer helps to further reduce the contact resistance, while the larger thickness helps to prevent the material of the wire (e.g., copper) from diffusing outward into the dielectric layer. The disclosed method can be easily integrated into existing BEOL processing to achieve improved performance of the formed device.

[0075] In an embodiment, a method of forming a semiconductor device includes: forming a through hole in a first dielectric layer disposed on a substrate; forming a second dielectric layer on the first dielectric layer; forming an opening in the second dielectric layer, wherein the opening exposes an upper surface of the through hole; selectively forming a cap layer on the upper surface of the through hole, wherein the cap layer has a curved upper surface extending above a first upper surface of the first dielectric layer away from the substrate; after forming the cap layer, forming a barrier layer in the opening on the cap layer and along the sidewall of the second dielectric layer exposed by the opening; and filling the opening by forming a conductive material on the barrier layer. In an embodiment, the upper surface of the through hole is flush with the first upper surface of the first dielectric layer, wherein the curved upper surface of the cap layer is a convex upper surface. In an embodiment, the cap layer is formed of the same material as the through hole. In an embodiment, the conductive material is different from the material of the through hole. In an embodiment, the method further includes: before forming the through hole, forming a transistor on the substrate, wherein the through hole is formed on the transistor and is formed to be electrically coupled to a conductive region of the transistor. In an embodiment, the first dielectric layer and the second dielectric layer are formed in a middle-of-line (MEOL) process and a back-end-of-line (BEOL) process of the semiconductor device, respectively. In an embodiment, the method further comprises: selectively forming an inhibitor layer on the cap layer after selectively forming the cap layer and before forming the barrier layer, wherein the inhibitor layer reduces a deposition rate of the barrier layer. In an embodiment, after forming the barrier layer, a first portion of the barrier layer disposed on the cap layer has a first thickness, and a second portion of the barrier layer disposed along a sidewall of the second dielectric layer has a second thickness, and the first thickness is less than the second thickness. In an embodiment, the method further comprises: after forming the barrier layer and before filling the opening, forming a liner layer on the barrier layer in the opening, wherein a first portion of the liner layer disposed on the cap layer has a third thickness, and a second portion of the liner layer disposed along a sidewall of the second dielectric layer has a fourth thickness, and the third thickness is less than the fourth thickness. In an embodiment, the method further comprises: after forming the barrier layer and before filling the opening, removing the inhibitor layer. In an embodiment, removing the inhibitor layer comprises: performing a plasma treatment process, wherein the plasma treatment process removes the inhibitor layer without removing the barrier layer.

[0076] In an embodiment, a method of forming a semiconductor device includes: forming an opening in a second dielectric layer disposed over a first dielectric layer, wherein the first dielectric layer is disposed over a substrate, wherein the opening exposes an upper surface of a via embedded in the first dielectric layer; selectively forming a cap layer over the upper surface of the via; selectively forming an inhibitor layer over the cap layer; lining the sidewalls and bottom of the opening with a barrier layer after selectively forming the inhibitor layer, wherein the barrier layer is formed as a non-conformal layer; and filling the opening by forming a conductive material over the barrier layer in the opening. In an embodiment, the method further includes: removing the inhibitor layer by performing a plasma treatment process after lining and before filling, wherein the plasma treatment process removes the inhibitor layer without removing the barrier layer. In an embodiment, the barrier layer has a first portion on the cap layer and has a second portion along the sidewalls of the second dielectric layer, wherein the first portion of the barrier layer is thinner than the second portion of the barrier layer. In an embodiment, the method further comprises: forming a liner layer on the barrier layer after the lining and before the filling, wherein the liner layer is formed as a non-conformal layer, wherein a first portion of the liner layer disposed above the cap layer is thinner than a second portion of the liner layer disposed along a sidewall of the second dielectric layer. In an embodiment, an upper surface of the through hole is flush with an upper surface of the first dielectric layer away from the substrate, wherein an upper surface of the cap layer is a raised upper surface and extends farther from the substrate than an upper surface of the first dielectric layer.

[0077] In an embodiment, a semiconductor device includes: a substrate; a transistor on the substrate; a first dielectric layer on the substrate and the transistor; a via embedded in the first dielectric layer and electrically coupled to a conductive region of the transistor; a cap layer on an upper surface of the via, wherein a lower surface of the cap layer facing the substrate is a flat surface, and an upper surface of the cap layer facing away from the substrate is a convex surface; a second dielectric layer on the first dielectric layer, wherein an upper surface of the cap layer extends farther from the substrate than a lower surface of the second dielectric layer facing the substrate; and a wire embedded in the second dielectric layer and on the cap layer, wherein the wire is electrically coupled to the via through the cap layer. In an embodiment, the semiconductor device further includes a barrier layer extending along a sidewall and a bottom of the wire, wherein the barrier layer has a non-uniform thickness. In an embodiment, a first portion of the barrier layer along the upper surface of the cap layer has a first thickness, and a second portion of the barrier layer along the sidewall of the wire has a second thickness greater than the first thickness. In an embodiment, the via and the cap layer are a first conductive material, wherein the wire is a second conductive material different from the first conductive material.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer on the first dielectric layer; forming an opening in the second dielectric layer, wherein the opening exposes an upper surface of the through hole; selectively forming a capping layer over an upper surface of the through hole, wherein the capping layer has a curved upper surface extending over a first upper surface of the first dielectric layer away from the substrate; After forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and The opening is filled by forming a conductive material over the barrier layer.

2. The method according to claim 1, wherein: An upper surface of the through hole is flush with a first upper surface of the first dielectric layer, wherein the curved upper surface of the cap layer is a convex upper surface.

3. The method according to claim 1, wherein: The capping layer is formed of the same material as that of the through hole.

4. The method according to claim 3, wherein: The conductive material is different from a material of the through-hole.

5. The method according to claim 1, further comprising: A transistor is formed over the substrate before forming the via, wherein the via is formed over the transistor and is formed to be electrically coupled to a conductive region of the transistor.

6. The method according to claim 1, wherein: The first dielectric layer and the second dielectric layer are formed in a middle-of-line (MEOL) process and a back-end-of-line (BEOL) process of the semiconductor device, respectively.

7. The method according to claim 1, further comprising: After selectively forming the capping layer and before forming the barrier layer, An inhibitor layer is selectively formed over the cap layer, wherein the inhibitor layer reduces a deposition rate of the barrier layer.

8. The method according to claim 7, wherein: After forming the barrier layer, a first portion of the barrier layer disposed on the cap layer has a first thickness, and a second portion of the barrier layer disposed along a sidewall of the second dielectric layer has a second thickness, the first thickness being smaller than the second thickness.

9. A method for forming a semiconductor device, the method comprising: forming an opening in a second dielectric layer disposed over a first dielectric layer, wherein the first dielectric layer is disposed over a substrate, wherein the opening exposes an upper surface of a via embedded in the first dielectric layer; selectively forming a capping layer on an upper surface of the through hole; selectively forming an inhibitor layer on the cap layer; After selectively forming the inhibitor layer, lining the sidewalls and bottom of the opening with a barrier layer, wherein the barrier layer is formed as a non-conformal layer; and The opening is filled by forming a conductive material in the opening over the barrier layer.

10. A semiconductor device comprising: substrate; a transistor on the substrate; a first dielectric layer over the substrate and the transistor; a via embedded in the first dielectric layer and electrically coupled to a conductive region of the transistor; a cap layer on the upper surface of the through hole, wherein a lower surface of the cap layer facing the substrate is a flat surface, and an upper surface of the cap layer facing away from the substrate is a convex surface; a second dielectric layer on the first dielectric layer, wherein an upper surface of the cap layer extends further from the substrate than a lower surface of the second dielectric layer toward the substrate; and A conductive line is embedded in the second dielectric layer and above the cap layer, wherein the conductive line is electrically coupled to the via through the cap layer.

Images