Novel packaged integrated circuit structure and preparation method thereof

Abstract

The invention belongs to the technical field of integrated circuits, and provides a novel packaged integrated circuit structure and a preparation method thereof.The novel packaged integrated circuit structure comprises a carrier plate and a packaging structure, the packaging structure is installed in the carrier plate, the packaging structure comprises a chip installation groove formed in the front end of the carrier plate, and an IC chip is installed at one end in the chip installation groove through an adhesive layer; the front end of the IC chip is provided with stress buffer glue, the stress buffer glue is filled in the gap between the IC chip and the chip installation groove, the front end of the stress buffer glue is flush with the front end of the chip installation groove, and the front end of the stress buffer glue and the front end of the carrier plate are provided with plastic packaging layers. The front end of the carrier plate is provided with the chip mounting groove, the IC chip is mounted in the chip mounting groove, the heat dissipation holes and the heat dissipation fins are used for heat dissipation, the heat conduction efficiency is remarkably improved, meanwhile, due to the fact that the thickness of the plastic package layer is reduced, heat resistance is reduced, heat generated during work of the integrated power device can be transmitted to the external environment more quickly, and the service life of the integrated power device is prolonged. Therefore, the overall heat dissipation effect is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a novel packaged integrated circuit structure and a preparation method thereof. Background Art

[0002] As a whole, an integrated circuit device integrates multiple IC chips and other electronic components, and realizes complex circuit functions and system applications through specific connection methods and layouts. IC chips are the core components of integrated circuit devices.

[0003] At present, when installing an IC chip, the IC chip is usually installed on the front end of an integrated circuit carrier. Then, a large amount of plastic encapsulation material is needed to encapsulate the IC chip and the front end of the carrier during plastic encapsulation. The thickness of the plastic encapsulation layer needs to be greater than the thickness of the IC chip. Therefore, when the plastic encapsulation layer is thicker, the heat dissipation resistance will increase, thereby reducing the overall heat dissipation performance of the packaged product, thereby affecting the performance and reliability of the product. In addition, a thicker plastic encapsulation layer will increase the total volume of the package body. At the same time, when the plastic encapsulation layer is thicker, more plastic encapsulation material will be used. As part of the production cost, the increase in the amount of plastic encapsulation material will directly lead to an increase in the overall production cost. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a novel packaged integrated circuit structure and a preparation method thereof to solve the above problems.

[0005] A novel packaged integrated circuit device, comprising:

[0006] Carrier board;

[0007] A packaging structure is installed inside a carrier board, the packaging structure includes a chip mounting groove opened at the front end of the carrier board, an IC chip is installed at one end of the chip mounting groove through an adhesive layer, a stress buffer glue is arranged at the front end of the IC chip, the stress buffer glue is filled in the gap between the IC chip and the chip mounting groove, the front end of the stress buffer glue is flush with the front end of the chip mounting groove, and a plastic sealing layer is arranged at the front end of the stress buffer glue and the front end of the carrier board.

[0008] Preferably, the front end and the rear end of the carrier board are coated with solder resist ink.

[0009] Preferably, a plurality of conducting holes are opened at the front end of the carrier board, and a plurality of electrical connection circuits are arranged at the front end of the carrier board.

[0010] Preferably, a plurality of SMT pads and a plurality of electroplated connecting wires are provided at the rear end of the carrier board, and the SMT pads, the plurality of electroplated connecting wires and the plurality of electrical connecting lines are electrically connected through vias.

[0011] Preferably, a plurality of bonding pads are provided at the front end of the carrier board, and a plurality of electrical connection lines are electrically connected to the plurality of bonding pads respectively; a plurality of chip electrodes are provided at the front end of the IC chip, and a plurality of bonding wires are welded to the plurality of bonding pads respectively; the IC chip is electrically connected to the SMT pads, a plurality of electroplating connection wires and a plurality of electrical connection lines through a plurality of bonding wires.

[0012] Preferably, a heat sink is provided at the rear end of the carrier board, a plurality of heat dissipation holes are provided on the IC chip, the chip mounting slot and the heat sink, and a direction mark is provided at the rear end of the carrier board.

[0013] A novel method for manufacturing an integrated circuit package includes the following steps:

[0014] S1. Preparation of the carrier: First, a chip mounting slot is opened on the front of the carrier using a laser processing process, and then a via hole and a wire tray are opened on the carrier and an electrical connection line is laid. Then, an SMT pad and an electroplated connection line are set at the rear end of the carrier and electrically connected to the electrical connection line through the via hole, and then solder resist ink is applied to the front and rear ends of the carrier;

[0015] S2, IC chip mounting: Then, adhesive is applied to the rear end of the IC chip and one end of the chip mounting groove, and then the IC chip is mounted into the chip mounting groove using the adhesive, and then the adhesive is cured in a curing furnace to form an adhesive layer;

[0016] S3, electrical connection: Use metal wire as bonding wire, weld one end of the bonding wire to the chip electrode, and weld the other end of the bonding wire to the bonding wire plate;

[0017] S4. Packaging: First, fill the gap between the IC chip and the chip mounting groove with stress buffer glue, and fill the stress buffer glue to the front end of the IC chip, so that the stress buffer glue fills and covers the open end of the chip mounting groove. Then, install the mounted carrier board into the mold of the plastic packaging machine, and then inject the molten plastic packaging material into the mold cavity through the injection molding component. The plastic packaging material covers the front end of the carrier board and the IC chip, and then the plastic packaging material is cooled and fixed to form a plastic packaging layer.

[0018] Preferably, the carrier board in S1 is made of ceramic, glass or BT substrate.

[0019] Preferably, the adhesive in S2 is epoxy resin.

[0020] Preferably, the stress buffer glue and the plastic sealing layer in S4 are both made of opaque materials.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] The present invention significantly improves the heat conduction efficiency by opening a chip mounting groove at the front end of the carrier board, mounting the IC chip in the chip mounting groove, and using heat dissipation holes and heat sinks for heat dissipation. At the same time, due to the reduction in the thickness of the plastic sealing layer, the thermal resistance is reduced, so that the heat generated by the operation of the integrated power device can be transferred to the external environment more quickly, thereby improving the overall heat dissipation effect, extending the service life of the product, and effectively improving the product quality. It can also further save the amount of plastic sealing materials and reduce the production cost of integrated circuits. Secondly, the use of stress buffer glue enhances the reliability of the product in many aspects. It fills the gap between the IC chip and the chip mounting groove, as well as the space between the front end of the IC chip and the carrier board, effectively alleviating the damage to the IC chip and the connecting circuits caused by thermal stress generated by heat. Finally, under the dual protection of the plastic sealing layer and the stress buffer glue, the IC chip is firmly wrapped in the chip mounting groove of the carrier board, preventing the influence of external impact and vibration on the chip, and further improving the reliability and performance of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the structure of the present invention from a first viewing angle;

[0024] Figure 2 It is a schematic diagram of the structure of the second viewing angle of the present invention;

[0025] Figure 3 It is a schematic diagram of the internal structure of the present invention;

[0026] Figure 4 It is a schematic diagram of the internal structure of the present invention;

[0027] Figure 5 It is a cross-sectional structural schematic diagram of the present invention;

[0028] Figure 6 It is a flow chart of the manufacturing method of the present invention.

[0029] In the figure:

[0030] 1. Carrier board; 2. Through hole; 3. Electrical connection line; 4. Wire tray; 5. SMT pad; 6. Electroplating connection line; 7. Heat sink; 8. Direction mark; 9. Packaging structure; 91. Chip mounting slot; 92. IC chip; 93. Adhesive layer; 94. Stress buffer glue; 95. Plastic sealing layer; 10. Chip electrode; 11. Bonding wire; 12. Heat dissipation hole. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. It should be pointed out that the drawings are schematic and not drawn to scale. For the sake of clarity and convenience in the figures, the relative sizes and proportions of the parts shown in the figures are exaggerated or reduced in size, and any size is only exemplary and not restrictive.

[0032] As attached Figure 1 To Attachment Figure 6 As shown:

[0033] Embodiment 1: The present invention provides a novel packaged integrated circuit device, comprising:

[0034] Carrier board 1;

[0035] The packaging structure 9 is installed inside the carrier 1. The packaging structure 9 includes a chip mounting groove 91 opened at the front end of the carrier 1. An IC chip 92 is installed at one end of the chip mounting groove 91 through an adhesive layer 93. A stress buffer glue 94 is arranged at the front end of the IC chip 92. The stress buffer glue 94 fills the gap between the IC chip 92 and the chip mounting groove 91. The front end of the stress buffer glue 94 is flush with the front end of the chip mounting groove 91. A plastic sealing layer 95 is arranged at the front end of the stress buffer glue 94 and the front end of the carrier 1.

[0036] The front end and the rear end of the carrier board 1 are coated with solder resist ink.

[0037] A plurality of conducting holes 2 are formed at the front end of the carrier board 1 , and a plurality of electrical connection circuits 3 are arranged at the front end of the carrier board 1 .

[0038] A plurality of SMT pads 5 and a plurality of electroplated connecting wires 6 are disposed at the rear end of the carrier board 1 . The SMT pads 5 , the plurality of electroplated connecting wires 6 and the plurality of electrical connecting lines 3 are electrically connected through the vias 2 .

[0039] A plurality of bonding pads 4 are provided at the front end of the carrier board 1, and a plurality of electrical connection lines 3 are electrically connected to the plurality of bonding pads 4 respectively. A plurality of chip electrodes 10 are provided at the front end of the IC chip 92, and a plurality of bonding wires 11 are welded to the plurality of bonding pads 4 respectively. The IC chip 92 is electrically connected to the SMT pads 5, a plurality of electroplating connection wires 6 and a plurality of electrical connection lines 3 through a plurality of bonding wires 11.

[0040] A heat sink 7 is disposed at the rear end of the carrier board 1 . The IC chip 92 , the chip mounting slot 91 and the heat sink 7 are all provided with a plurality of heat dissipation holes 12 . A direction mark 8 is disposed at the rear end of the carrier board 1 .

[0041] As can be seen from the above, the IC chip 92 is installed in the chip mounting groove 91 at the front end of the carrier board 1 through the adhesive layer 93, and the IC chip 92 is electrically connected to the SMT pad 5, a plurality of electroplated connecting wires 6 and a plurality of electrical connecting lines 3 by welding the bonding wire 11, the chip electrode 10 and the bonding wire plate 4, and then the stress buffer glue 94 is used to fill the gap between the IC chip 92 and the chip mounting groove 91 and the stress buffer glue 94 is used to fill the front end of the IC chip 92 flush with the carrier board 1, and then the carrier board 1 and the IC chip 92 are plastic-sealed with the plastic sealing layer 95.

[0042] By opening a chip mounting groove 91 at the front end of the carrier board 1, installing the IC chip 92 in the chip mounting groove 91, and using the heat dissipation holes 12 and the heat sink 7 for heat dissipation, the heat conduction efficiency is significantly improved. At the same time, due to the reduction in the thickness of the plastic sealing layer 95, the thermal resistance is reduced, so that the heat generated by the operation of the integrated circuit device can be transferred to the external environment more quickly, thereby improving the overall heat dissipation effect, extending the service life of the product, and effectively improving the product quality. It can also further save the amount of plastic sealing materials and reduce the production cost of integrated circuits. Secondly, the use of stress buffer glue 94 enhances the reliability of the product in many aspects. It fills the gap between the IC chip 92 and the chip mounting groove 91, as well as the space between the front end of the IC chip 92 and the carrier board 1, effectively reducing the damage to the IC chip 92 and the connecting circuit caused by the thermal stress generated by the heat. Finally, under the dual protection of the plastic sealing layer 95 and the stress buffer glue 94, the IC chip 92 is firmly encapsulated in the chip mounting groove 91 of the carrier board 1, preventing the influence of external impact and vibration on the chip, and further improving the reliability and performance of the product.

[0043] Embodiment 2: The present invention provides a novel method for manufacturing an integrated circuit package, which specifically comprises the following steps:

[0044] S1. Preparation of carrier board 1: firstly, a chip mounting groove 91 is opened on the front of carrier board 1 by laser processing, then a via hole 2 and a wire pad 4 are opened on carrier board 1 and an electrical connection line 3 is laid, then an SMT pad 5 and an electroplated connection line 6 are arranged at the rear end of carrier board 1, and electrically connected to the electrical connection line 3 through the via hole 2, and then solder resist ink is coated on the front and rear ends of carrier board 1;

[0045] S2, mounting the IC chip 92: Then, adhesive is applied to the rear end of the IC chip 92 and one end of the chip mounting groove 91, and then the IC chip 92 is mounted in the chip mounting groove 91 by using the adhesive, and then the adhesive is cured in a curing furnace to form an adhesive layer 93;

[0046] S3, electrical connection: Use a metal lead as a bonding wire 11, then weld one end of the bonding wire 11 to the chip electrode 10, and then weld the other end of the bonding wire 11 to the bonding wire plate 4;

[0047] S4, packaging: first, fill the stress buffer glue 94 in the gap between the IC chip 92 and the chip mounting groove 91, and fill the stress buffer glue 94 to the front end of the IC chip 92, so that the stress buffer glue 94 fills and covers the open end of the chip mounting groove 91, and then install the mounted carrier board 1 into the mold of the plastic packaging machine, and then inject the molten plastic packaging material into the mold cavity through the injection molding component. The plastic packaging material covers the front end of the carrier board 1 and the IC chip 92, and then the plastic packaging material is cooled and fixed to form a plastic packaging layer 95.

[0048] The material of the carrier board 1 in S1 is ceramic, glass or BT substrate.

[0049] The adhesive in S2 is epoxy resin.

[0050] The stress buffer glue 94 and the plastic sealing layer 95 in S4 are both made of opaque materials.

[0051] As can be seen from the above, each step of manufacturing the integrated circuit through methods S1, S2, S3 and S4 is optimized to ensure the performance and quality of the final product. In particular, by opening a chip mounting groove 91 at the front end of the carrier board 1 and installing the IC chip 92 into the chip mounting groove 91, the thickness of the plastic layer 95 is effectively reduced, the heat dissipation effect of the integrated circuit device is further improved, and the amount of plastic material used in the plastic layer 95 can be reduced to reduce the production cost.

[0052] Embodiment 3

[0053] In combination with Example 1 and Example 2, the device and the method are applied to actual scenarios. At present, the installation of the IC chip 92 in the integrated circuit is to directly install the IC chip 92 on the front end of the carrier 1, so that the rear end of the IC chip 92 is located at the front end of the carrier 1, so that the thickness of the plastic layer 95 needs to be greater than the IC chip 92 during plastic sealing. By using the device, the IC chip 92 is embedded and installed inside the carrier 1, and the plastic layer 95 only needs to be sealed at the front end of the carrier 1, thereby effectively reducing the thickness of the plastic layer 95, further reducing the resistance to heat transfer, effectively improving the heat dissipation effect of the integrated circuit, and reducing the amount of plastic sealing material used, further reducing the production cost of the integrated circuit.

[0054] The standard parts used in the present invention can all be purchased from the market, and the special-shaped parts can be customized according to the description and the drawings. The specific connection methods of each part adopt conventional means such as mature bolts, rivets, welding, etc. in the prior art. The machinery, parts and equipment all adopt conventional models in the prior art, and the circuit connection adopts the conventional connection method in the prior art, which will not be described in detail here. The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in this field.

[0055] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. "Multiple" means two or more, unless otherwise clearly and specifically defined.

[0056] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0057] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0058] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0059] In the drawings of the embodiments disclosed in the present invention, only the structures related to the embodiments disclosed in the present invention are involved, and other structures can refer to the general design. In the absence of conflict, the same embodiment and different embodiments of the present invention can be combined with each other.

[0060] Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A novel packaged integrated circuit device, characterized in that: include: Carrier board (1); A packaging structure (9) is installed inside a carrier board (1), the packaging structure (9) comprising a chip mounting groove (91) opened at the front end of the carrier board (1), an IC chip (92) being mounted at one end inside the chip mounting groove (91) via an adhesive layer (93), a stress buffer glue (94) being arranged at the front end of the IC chip (92), the stress buffer glue (94) being filled in the gap between the IC chip (92) and the chip mounting groove (91), the front end of the stress buffer glue (94) being flush with the front end of the chip mounting groove (91), and a plastic sealing layer (95) being arranged at the front end of the stress buffer glue (94) and the front end of the carrier board (1).

2. A novel packaged integrated circuit device as claimed in claim 1, characterized in that: The front end and the rear end of the carrier board (1) are both coated with solder resist ink.

3. A novel packaged integrated circuit device as claimed in claim 1, characterized in that: A plurality of conducting holes (2) are provided at the front end of the carrier board (1), and a plurality of electrical connection circuits (3) are provided at the front end of the carrier board (1).

4. A novel packaged integrated circuit device as claimed in claim 3, characterized in that: The rear end of the carrier board (1) is provided with a plurality of SMT pads (5) and a plurality of electroplated connecting wires (6); the SMT pads (5), the plurality of electroplated connecting wires (6) and the plurality of electrical connecting lines (3) are electrically connected via the through holes (2).

5. A novel packaged integrated circuit device as claimed in claim 4, characterized in that: The front end of the carrier board (1) is provided with a plurality of wire bonding pads (4), and the plurality of electrical connection lines (3) are respectively electrically connected to the plurality of wire bonding pads (4). The front end of the IC chip (92) is provided with a plurality of chip electrodes (10), and the plurality of chip electrodes (10) are all welded with a plurality of bonding wires (11), and the plurality of bonding wires (11) are respectively welded to the plurality of wire bonding pads (4). The IC chip (92) is electrically connected to the SMT pad (5), the plurality of electroplating connection wires (6), and the plurality of electrical connection lines (3) through the plurality of bonding wires (11).

6. A novel packaged integrated circuit device as claimed in claim 5, characterized in that: The rear end of the carrier board (1) is provided with a heat sink (7); the IC chip (92), the chip mounting groove (91) and the heat sink (7) are all provided with a plurality of heat dissipation holes (12); and the rear end of the carrier board (1) is provided with a direction mark (8).

7. A novel packaged integrated circuit device as claimed in any one of claims 1 to 6, further comprising a novel packaged integrated circuit manufacturing method, characterized in that: The specific steps include: S1. Preparation of the carrier (1): firstly, a chip mounting groove (91) is opened on the front of the carrier (1) by using a laser processing process, then a via hole (2) and a soldering wire tray (4) are opened on the carrier (1) and an electrical connection line (3) is laid, then an SMT pad (5) and an electroplated connection line (6) are arranged at the rear end of the carrier (1), and are electrically connected to the electrical connection line (3) through the via hole (2), and then solder resist ink is coated on the front and rear ends of the carrier (1); S2, mounting the IC chip (92): Then, an adhesive is applied to the rear end of the IC chip (92) and one end inside the chip mounting groove (91), and then the IC chip (92) is mounted in the chip mounting groove (91) using the adhesive, and then the adhesive is cured in a curing furnace to form an adhesive layer (93); S3, electrical connection: using a metal lead as a bonding wire (11), welding one end of the bonding wire (11) to the chip electrode (10), and then welding the other end of the bonding wire (11) to the bonding wire plate (4); S4, packaging: first, fill the stress buffer glue (94) in the gap between the IC chip (92) and the chip mounting groove (91), and fill the stress buffer glue (94) to the front end of the IC chip (92), so that the stress buffer glue (94) fills and covers the open end of the chip mounting groove (91), then install the mounted carrier board (1) into the mold of the plastic packaging machine, and then inject the molten plastic packaging material into the mold cavity through the injection molding component, the plastic packaging material covers the front end of the carrier board (1) and the IC chip (92), and then cool and fix the plastic packaging material to form a plastic packaging layer (95).

8. A method for manufacturing a novel packaged integrated circuit as claimed in claim 7, characterized in that: The carrier board (1) in S1 is made of ceramic, glass or BT substrate.

9. A method for manufacturing a novel packaged integrated circuit as claimed in claim 7, characterized in that: The adhesive in S2 is epoxy resin.

10. A method for manufacturing a novel packaged integrated circuit as claimed in claim 7, characterized in that: The stress buffer glue (94) and the plastic sealing layer (95) in S4 are both made of opaque materials.

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